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[edk2-devel] [PATCH v2 0/6] RISC-V MMU support

Tuan Phan posted 6 patches 1 year ago
Failed in applying to current master (apply log)
MdePkg/Include/Library/BaseLib.h              |   5 +
MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
.../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
.../VirtNorFlashStaticLib.c                   |   3 +-
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
16 files changed, 776 insertions(+), 31 deletions(-)
create mode 100644 MdePkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
[edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Posted by Tuan Phan 1 year ago 
RISC-V: Add MMU support

This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.

There are three parts:
1. Add MMU base library. MMU will be enabled during
CpuDxe initialization.
2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base
address to GCD if already done.
3. Fix all resources should be populated in HOB
or added to GCD by driver before accessing when MMU enabled.

Changes in v2:
  - Move MMU core to a library.
  - Setup SATP mode as highest possible that HW supports.

Tuan Phan (6):
  MdePkg/BaseLib: RISC-V: Support getting satp register value
  MdePkg/Register: RISC-V: Add satp mode bits shift definition
  UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
  OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
  OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
  OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
    devices

 MdePkg/Include/Library/BaseLib.h              |   5 +
 MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
 .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++
 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
 .../VirtNorFlashStaticLib.c                   |   3 +-
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
 OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
 OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
 OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
 OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
 UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
 16 files changed, 776 insertions(+), 31 deletions(-)
 create mode 100644 MdePkg/Include/Library/BaseRiscVMmuLib.h
 create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
 create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
 create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S

-- 
2.25.1



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Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Posted by Andrei Warkentin 1 year ago 
Hi Tuan,

Do you mind sharing the GitHub branch as well? It would help with the review immensely.

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Friday, April 14, 2023 1:58 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <andrei.warkentin@intel.com>; Tuan Phan <tphan@ventanamicro.com>
> Subject: [PATCH v2 0/6] RISC-V MMU support
> 
> RISC-V: Add MMU support
> 
> This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> supported and tested. The MMU is required to support setting page
> attribute which is the first basic step to support security booting on RISC-V.
> 
> There are three parts:
> 1. Add MMU base library. MMU will be enabled during CpuDxe initialization.
> 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD
> if already done.
> 3. Fix all resources should be populated in HOB or added to GCD by driver
> before accessing when MMU enabled.
> 
> Changes in v2:
>   - Move MMU core to a library.
>   - Setup SATP mode as highest possible that HW supports.
> 
> Tuan Phan (6):
>   MdePkg/BaseLib: RISC-V: Support getting satp register value
>   MdePkg/Register: RISC-V: Add satp mode bits shift definition
>   UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>   OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
>   OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
>   OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
>     devices
> 
>  MdePkg/Include/Library/BaseLib.h              |   5 +
>  MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
>  .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
>  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> ++++++++++++++++++
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
>  MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
>  .../VirtNorFlashStaticLib.c                   |   3 +-
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
>  OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
>  OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
>  OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
>  OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
>  16 files changed, 776 insertions(+), 31 deletions(-)  create mode 100644
> MdePkg/Include/Library/BaseRiscVMmuLib.h
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>  create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> 
> --
> 2.25.1



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Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Posted by Tuan Phan 1 year ago 
Hi Andrei,
Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu
Will put the link in the cover letter next round.

From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Andrei Warkentin <andrei.warkentin@intel.com>
Date: Tuesday, April 18, 2023 at 9:04 AM
To: Tuan Phan <tphan@ventanamicro.com>, devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>, Gao, Liming <gaoliming@byosoft.com.cn>, Liu, Zhiguang <zhiguang.liu@intel.com>, sunilvl@ventanamicro.com <sunilvl@ventanamicro.com>, git@danielschaefer.me <git@danielschaefer.me>
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Hi Tuan,

Do you mind sharing the GitHub branch as well? It would help with the review immensely.

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Friday, April 14, 2023 1:58 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <andrei.warkentin@intel.com>; Tuan Phan <tphan@ventanamicro.com>
> Subject: [PATCH v2 0/6] RISC-V MMU support
>
> RISC-V: Add MMU support
>
> This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> supported and tested. The MMU is required to support setting page
> attribute which is the first basic step to support security booting on RISC-V.
>
> There are three parts:
> 1. Add MMU base library. MMU will be enabled during CpuDxe initialization.
> 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD
> if already done.
> 3. Fix all resources should be populated in HOB or added to GCD by driver
> before accessing when MMU enabled.
>
> Changes in v2:
>   - Move MMU core to a library.
>   - Setup SATP mode as highest possible that HW supports.
>
> Tuan Phan (6):
>   MdePkg/BaseLib: RISC-V: Support getting satp register value
>   MdePkg/Register: RISC-V: Add satp mode bits shift definition
>   UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>   OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
>   OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
>   OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
>     devices
>
>  MdePkg/Include/Library/BaseLib.h              |   5 +
>  MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
>  .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
>  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> ++++++++++++++++++
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
>  MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
>  .../VirtNorFlashStaticLib.c                   |   3 +-
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
>  OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
>  OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
>  OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
>  OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
>  16 files changed, 776 insertions(+), 31 deletions(-)  create mode 100644
> MdePkg/Include/Library/BaseRiscVMmuLib.h
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>  create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
>
> --
> 2.25.1







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Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Posted by Andrei Warkentin 12 months ago 
Apologies for the late review. I added my comments on GH. Aside from a request for more context for https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d20087ab7414#comments, I think this patch set from a functionality standpoint looks good enough to be submitted.

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Tuan Phan
Sent: Wednesday, April 19, 2023 5:37 PM
To: devel@edk2.groups.io; Warkentin, Andrei <andrei.warkentin@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; sunilvl@ventanamicro.com; git@danielschaefer.me
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support

Hi Andrei,
Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu
Will put the link in the cover letter next round.

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> on behalf of Andrei Warkentin <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>
Date: Tuesday, April 18, 2023 at 9:04 AM
To: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>, devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>, Gao, Liming <gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>>, Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>, sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com> <sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>>, git@danielschaefer.me<mailto:git@danielschaefer.me> <git@danielschaefer.me<mailto:git@danielschaefer.me>>
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Hi Tuan,

Do you mind sharing the GitHub branch as well? It would help with the review immensely.

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Sent: Friday, April 14, 2023 1:58 PM
> To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Gao, Liming
> <gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>>; Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>;
> sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>; git@danielschaefer.me<mailto:git@danielschaefer.me>; Warkentin, Andrei
> <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>; Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Subject: [PATCH v2 0/6] RISC-V MMU support
>
> RISC-V: Add MMU support
>
> This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> supported and tested. The MMU is required to support setting page
> attribute which is the first basic step to support security booting on RISC-V.
>
> There are three parts:
> 1. Add MMU base library. MMU will be enabled during CpuDxe initialization.
> 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD
> if already done.
> 3. Fix all resources should be populated in HOB or added to GCD by driver
> before accessing when MMU enabled.
>
> Changes in v2:
>   - Move MMU core to a library.
>   - Setup SATP mode as highest possible that HW supports.
>
> Tuan Phan (6):
>   MdePkg/BaseLib: RISC-V: Support getting satp register value
>   MdePkg/Register: RISC-V: Add satp mode bits shift definition
>   UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>   OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
>   OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
>   OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
>     devices
>
>  MdePkg/Include/Library/BaseLib.h              |   5 +
>  MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
>  .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
>  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> ++++++++++++++++++
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
>  MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
>  .../VirtNorFlashStaticLib.c                   |   3 +-
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
>  OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
>  OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
>  OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
>  OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
>  16 files changed, 776 insertions(+), 31 deletions(-)  create mode 100644
> MdePkg/Include/Library/BaseRiscVMmuLib.h
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>  create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
>
> --
> 2.25.1







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Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Posted by Tuan Phan 11 months, 2 weeks ago 
Thanks Andrei,
Sunil, any comments or it is good to go. As this patchset spans across
MdePkg, UefiCpuPkg and OvmfPkg, do I need to separate it so each package
maintainer can merge independently?

On Mon, May 8, 2023 at 10:19 AM Warkentin, Andrei <
andrei.warkentin@intel.com> wrote:

> Apologies for the late review. I added my comments on GH. Aside from a
> request for more context for
> https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d20087ab7414#comments,
> I think this patch set from a functionality standpoint looks good enough to
> be submitted.
>
>
>
> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
>
>
>
> *From:* devel@edk2.groups.io <devel@edk2.groups.io> *On Behalf Of *Tuan
> Phan
> *Sent:* Wednesday, April 19, 2023 5:37 PM
> *To:* devel@edk2.groups.io; Warkentin, Andrei <andrei.warkentin@intel.com>
> *Cc:* Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <
> gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me
> *Subject:* Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
>
>
>
> Hi Andrei,
>
> Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu
>
> Will put the link in the cover letter next round.
>
>
>
> *From: *devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Andrei
> Warkentin <andrei.warkentin@intel.com>
> *Date: *Tuesday, April 18, 2023 at 9:04 AM
> *To: *Tuan Phan <tphan@ventanamicro.com>, devel@edk2.groups.io <
> devel@edk2.groups.io>
> *Cc: *Kinney, Michael D <michael.d.kinney@intel.com>, Gao, Liming <
> gaoliming@byosoft.com.cn>, Liu, Zhiguang <zhiguang.liu@intel.com>,
> sunilvl@ventanamicro.com <sunilvl@ventanamicro.com>, git@danielschaefer.me
> <git@danielschaefer.me>
> *Subject: *Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
>
> Hi Tuan,
>
> Do you mind sharing the GitHub branch as well? It would help with the
> review immensely.
>
> A
>
> > -----Original Message-----
> > From: Tuan Phan <tphan@ventanamicro.com>
> > Sent: Friday, April 14, 2023 1:58 PM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> > sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> > <andrei.warkentin@intel.com>; Tuan Phan <tphan@ventanamicro.com>
> > Subject: [PATCH v2 0/6] RISC-V MMU support
> >
> > RISC-V: Add MMU support
> >
> > This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> > supported and tested. The MMU is required to support setting page
> > attribute which is the first basic step to support security booting on
> RISC-V.
> >
> > There are three parts:
> > 1. Add MMU base library. MMU will be enabled during CpuDxe
> initialization.
> > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to
> GCD
> > if already done.
> > 3. Fix all resources should be populated in HOB or added to GCD by driver
> > before accessing when MMU enabled.
> >
> > Changes in v2:
> >   - Move MMU core to a library.
> >   - Setup SATP mode as highest possible that HW supports.
> >
> > Tuan Phan (6):
> >   MdePkg/BaseLib: RISC-V: Support getting satp register value
> >   MdePkg/Register: RISC-V: Add satp mode bits shift definition
> >   UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
> >   OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
> >   OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
> >   OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
> >     devices
> >
> >  MdePkg/Include/Library/BaseLib.h              |   5 +
> >  MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
> >  .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
> >  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
> >  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> > ++++++++++++++++++
> >  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
> >  MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
> >  .../VirtNorFlashStaticLib.c                   |   3 +-
> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
> >  OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
> >  OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
> >  OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
> >  OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
> >  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
> >  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
> >  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
> >  16 files changed, 776 insertions(+), 31 deletions(-)  create mode 100644
> > MdePkg/Include/Library/BaseRiscVMmuLib.h
> >  create mode 100644
> > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> >  create mode 100644
> > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> >  create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> >
> > --
> > 2.25.1
>
>
>
>
> 
>


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Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Posted by Sunil V L 11 months, 2 weeks ago 
On Tue, May 23, 2023 at 02:59:50PM -0700, Tuan Phan wrote:
> Thanks Andrei,
> Sunil, any comments or it is good to go. As this patchset spans across
> MdePkg, UefiCpuPkg and OvmfPkg, do I need to separate it so each package
> maintainer can merge independently?
> 
Hi Tuan,

I don't see an issue when a patch set spans across multiple modules as
long as corresponding maintainers review/ack. However, it is better if
the change in single patch is restricted to one module/package. In your
series, PATCH 3/6 is spread across 3 different modules. Could you
separate the change for each package?

Also, while all other patches affects RISC-V only, PATCH 5/6 in your
series is a generic change which affects other architectures. Ard
is the maintainer for this and he should to agree for the change. Did I
miss a response to his question for this patch?

Thanks!
Sunil


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