From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102876+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102876+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289771; cv=none; d=zohomail.com; s=zohoarc; b=bmZSgUb7PvQizGgTJLIOFxwT7BIhtB0Or1KVpnRupzvrqgCuZH76RgChUd7maow+e0PjCx+V4U9mFOUZLWN5xk8lB6O6uTDENBzuBRi6SesUELay03gZ/HCFSQPiYObJDRk8FgKzmQ7+MViqsPD8a4l2Qi5rwfT0ZelE6iGcJGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289771; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=I+vBBCzdA2B6XC1HITlImMS6ljt+GRjvuEwVZZl8k68=; b=UezagyagzQSVg8y0gUHw/mIlUkegRzmtNZHnXkb/+LyjlfSSbl0flKb0OvORc8C0YpIA/ktx88tVwyYL0fS2oXrn5o+blzE1Xz1TSkHoJwFa+Y1vdHcGb44VjfZtQhqgjQ/mJnHTmVqEziGlqhma9tLBH+jfYVzejYwBkR6XSVE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102876+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 168128977111955.93550713074046; Wed, 12 Apr 2023 01:56:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id D7WyYY1788612xgeuQ5FiZkX; Wed, 12 Apr 2023 01:56:10 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.38067.1681289770279775325 for ; Wed, 12 Apr 2023 01:56:10 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126742" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126742" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:55:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262041" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262041" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:55:52 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Ray Ni Subject: [edk2-devel] [Patch V2 1/8] OvmfPkg: Add CpuPageTableLib required by PiSmmCpuDxe Date: Wed, 12 Apr 2023 16:53:36 +0800 Message-Id: <20230412085343.1077-2-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Z8gXUucW61rre0lIhuZGTbTrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289770; bh=O9ZFUogLv1fOP6C8vf9rUomR90nCZQSWi+n0Ew3RfFs=; h=Cc:Date:From:Reply-To:Subject:To; b=LSwjAvBsLykgEUlOdEyDvQywKRjWpsZBwrKJqKFlEjL2JysfDj7c9Ic0jpOZRid2csE AaS7sNDSsgrBzq/yCK+Hibqlki7Qlxq6aDUmv+Oaj3kgwE+nuzMj31G+iu4eOCKYgv15f lhikCJf+xRp6zeiHHNg+Pj9FeILmOLzlaws= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289772022100003 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib instance required by PiSmmCpuDxe in corresponding DSC files of OvmfPkg. Signed-off-by: Dun Tan Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Ray Ni Acked-by: Gerd Hoffmann --- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 3 ++- OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index cc2dd925bc..8a2fb8049f 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -190,6 +190,7 @@ MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLi= b.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif @@ -399,7 +400,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 86177bb948..77f10e2c86 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -193,6 +193,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 065b544506..156d6c1434 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -197,6 +197,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif @@ -409,7 +410,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 3d405cd4ad..35bb011212 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -210,6 +210,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf @@ -430,7 +431,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102876): https://edk2.groups.io/g/devel/message/102876 Mute This Topic: https://groups.io/mt/98215422/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102877+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102877+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289773; cv=none; d=zohomail.com; s=zohoarc; b=CCoscze5zCYnGkSKDFXSMEtckUWuGAEUXI6x19w4+ul4HmZOJK56vgkJI/xTDk20uN7Jp8NlM9fPainwV+U9gWeJIBIGd4kWTJ0VZ0DiAr7x62qHZTCaQ8504GVThhrT97XDTX+1M/5+qSBdjkA+jTei8yBJ627HQYZa0Rrgayc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5sP1sGJTDt5ah7irGcwGKYicHQfAblKxlnZw/LEOmMs=; b=GEg1yg6fCRKdE61OU8LxL5x5G9ZbrTrjOIBCgJ+B/NTr0ETHqkOzjGFXeDjscvmtBAJEBVRWMUvHvjcSdXEVtcpkuz872Zsk0FREwx3Lkl+5Vq7N8y648na3dvg1fK3rv7MbdnFsdTYZWskZ4LbEdrXldfCSVG3uhsOpzEeAiPA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102877+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1681289773168890.9706124159192; Wed, 12 Apr 2023 01:56:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mpggYY1788612xt2g3YzLybx; Wed, 12 Apr 2023 01:56:12 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.38067.1681289770279775325 for ; Wed, 12 Apr 2023 01:56:12 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126763" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126763" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:55:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262070" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262070" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:55:56 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [Patch V2 2/8] UefiPayloadPkg: Add CpuPageTableLib required by PiSmmCpuDxe Date: Wed, 12 Apr 2023 16:53:37 +0800 Message-Id: <20230412085343.1077-3-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: wmY20N8Ivy5dvFWd2v6Rr7ngx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289772; bh=CprawwtExrWbPgcDX8oMoeqnE5gsp46uBxy/Pxg5r1g=; h=Cc:Date:From:Reply-To:Subject:To; b=RuTeshq5Taw4Zwmx5qScnsa1IQPFoqv7EcetH7uRGAxVKoZUIyL0UDNzUxHfHAu4xFt YCZqQ1aEcugvo+tLqatwVuoV+DNFLm30Ddxe7c7zv4dr5fhj7w/hVMqfUWA0SDy4GpraR ElNM1Rw4z6CoqUSLF6eumTDW/XZAm7EC+Mk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289774580100009 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by PiSmmCpuDxeSmm in UefiPayloadPkg.dsc. Signed-off-by: Dun Tan Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo --- UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index bca5d3f335..eeee8bb090 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -207,6 +207,7 @@ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf HobLib|UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 # # UEFI & PI @@ -339,7 +340,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf !if $(PERFORMANCE_MEASUREMENT_ENABLE) PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102877): https://edk2.groups.io/g/devel/message/102877 Mute This Topic: https://groups.io/mt/98215423/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102878+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102878+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289773; cv=none; d=zohomail.com; s=zohoarc; b=DmIAnlkSmey2JQIL//vZwxYietCEE6UPuMk4XzQz7fg/9B1TewicckgGeyGZ4PMk/ZT5oZYmpV27NutmZmc/cZd8IAJjQcX4XVPWPY85QCYg1FChU5v+G5GMeZFQahckOfuJgg7MGj/L7006Wu67QNZgkPJQ1ULxEGrlDe8Veb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6xR1uIPHF40FwiGnb6/7D0RTTlbSTz3eyCAPUfT1/PY=; b=TkHilOp5b+73S5hsKZmvYfqGBoZP41yr/nPHRnbhdw1d4k8iEZzHoV0+EG9HsdXoJC6xDAOSNkb4+AWCSBiWWUXr2eKon+3EytsM2jdGdk78k/KG4Tim8JM7of36Q0FInhTFiq9Mn9Mq729fkY0oWNeVymz8+aFcrrjsAF3BU58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102878+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 168128977358545.89328460857291; Wed, 12 Apr 2023 01:56:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mJMIYY1788612xcVqZAdDAeD; Wed, 12 Apr 2023 01:56:13 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.38067.1681289770279775325 for ; Wed, 12 Apr 2023 01:56:12 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126774" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126774" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262083" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262083" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:55:59 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 3/8] UefiCpuPkg: Use CpuPageTableLib to convert SMM paging attribute. Date: Wed, 12 Apr 2023 16:53:38 +0800 Message-Id: <20230412085343.1077-4-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: wDfspKyGqKfMlreEVbMYxxVYx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289773; bh=KVL35glTJibzN78S+qvg8Qi2LkZwO6z3+UjMoAvSgVY=; h=Cc:Date:From:Reply-To:Subject:To; b=vWPTlqqBiX80uqlL8lFQdDxx8uWeVW7q2Snnn0uufr45chbKwhQPzd/58zpJnoApGF3 gIH3oUyXtNDV+DfrGr5szliK/K5N7fTrWQFseYNu+ESFUTKDetyHpDF3dNTutB8led77q lXtDzai0U7LE5keM277JtotECKX8XbyHOmo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289774031100007 Content-Type: text/plain; charset="utf-8" Simplify the ConvertMemoryPageAttributes API to convert paging attribute by CpuPageTableLib. In the new API, it calls PageTableMap() to update the page attributes of a memory range. With the PageTableMap() API in CpuPageTableLib, we can remove the complicated page table manipulating code. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 3 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 28 +++++++++++++----= ----------- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 403 +++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +++++++-- 5 files changed, 114 insertions(+), 330 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpu= DxeSmm/Ia32/PageTbl.c index 34bf6e1a25..9c8107080a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -1,7 +1,7 @@ /** @file Page table manipulation functions for IA-32 processors =20 -Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -31,6 +31,7 @@ SmmInitPageTable ( InitializeSpinLock (mPFLock); =20 mPhysicalAddressBits =3D 32; + mPagingMode =3D PagingPae; =20 if (FeaturePcdGet (PcdCpuSmmProfileEnable) || HEAP_GUARD_NONSTOP_MODE || diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index a5c2bdd971..ba341cadc6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -50,6 +50,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include @@ -260,6 +261,7 @@ extern UINTN mNumberOfCpus; extern EFI_SMM_CPU_PROTOCOL mSmmCpu; extern EFI_MM_MP_PROTOCOL mSmmMp; extern BOOLEAN m5LevelPagingNeeded; +extern PAGING_MODE mPagingMode; =20 /// /// The mode of the CPU at the time an SMI occurs @@ -1008,11 +1010,10 @@ SetPageTableAttributes ( Length from their current attributes to the attributes specified by Attr= ibutes. =20 @param[in] PageTableBase The page table base. - @param[in] EnablePML5Paging If PML5 paging is enabled. + @param[in] PagingMode The paging mode. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to set for the = memory region. - @param[out] IsSplitted TRUE means page table splitted. FALSE mean= s page table not splitted. =20 @retval EFI_SUCCESS The attributes were set for the memory reg= ion. @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by @@ -1030,12 +1031,11 @@ SetPageTableAttributes ( **/ EFI_STATUS SmmSetMemoryAttributesEx ( - IN UINTN PageTableBase, - IN BOOLEAN EnablePML5Paging, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN UINTN PageTableBase, + IN PAGING_MODE PagingMode, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes ); =20 /** @@ -1043,34 +1043,32 @@ SmmSetMemoryAttributesEx ( Length from their current attributes to the attributes specified by Attr= ibutes. =20 @param[in] PageTableBase The page table base. - @param[in] EnablePML5Paging If PML5 paging is enabled. + @param[in] PagingMode The paging mode. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to clear for th= e memory region. - @param[out] IsSplitted TRUE means page table splitted. FALSE mean= s page table not splitted. =20 @retval EFI_SUCCESS The attributes were cleared for the memory= region. @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by BaseAddress and Length cannot be modified. @retval EFI_INVALID_PARAMETER Length is zero. Attributes specified an illegal combinatio= n of attributes that - cannot be set together. + cannot be cleared together. @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of the memory resource range. @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory resource range specified by BaseAddress an= d Length. - The bit mask of attributes is not support = for the memory resource + The bit mask of attributes is not supporte= d for the memory resource range specified by BaseAddress and Length. =20 **/ EFI_STATUS SmmClearMemoryAttributesEx ( IN UINTN PageTableBase, - IN BOOLEAN EnablePML5Paging, + IN PAGING_MODE PagingMode, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN UINT64 Attributes ); =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index 158e05e264..38d4e950a4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -97,6 +97,7 @@ ReportStatusCodeLib SmmCpuFeaturesLib PeCoffGetEntryPointLib + CpuPageTableLib =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## CONSUMES diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 834a756061..deb5895d83 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -26,14 +26,9 @@ UINTN mGcdMemNumberOfDesc =3D= 0; =20 EFI_MEMORY_ATTRIBUTES_TABLE *mUefiMemoryAttributesTable =3D NULL; =20 -PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { - { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 }, - { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 }, - { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 }, -}; - -BOOLEAN mIsShadowStack =3D FALSE; -BOOLEAN m5LevelPagingNeeded =3D FALSE; +BOOLEAN mIsShadowStack =3D FALSE; +BOOLEAN m5LevelPagingNeeded =3D FALSE; +PAGING_MODE mPagingMode =3D PagingModeMax; =20 // // Global variable to keep track current available memory used as page tab= le. @@ -185,52 +180,6 @@ AllocatePageTableMemory ( return Buffer; } =20 -/** - Return length according to page attributes. - - @param[in] PageAttributes The page attribute of the page entry. - - @return The length of page entry. -**/ -UINTN -PageAttributeToLength ( - IN PAGE_ATTRIBUTE PageAttribute - ) -{ - UINTN Index; - - for (Index =3D 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttr= ibuteTable[0]); Index++) { - if (PageAttribute =3D=3D mPageAttributeTable[Index].Attribute) { - return (UINTN)mPageAttributeTable[Index].Length; - } - } - - return 0; -} - -/** - Return address mask according to page attributes. - - @param[in] PageAttributes The page attribute of the page entry. - - @return The address mask of page entry. -**/ -UINTN -PageAttributeToMask ( - IN PAGE_ATTRIBUTE PageAttribute - ) -{ - UINTN Index; - - for (Index =3D 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttr= ibuteTable[0]); Index++) { - if (PageAttribute =3D=3D mPageAttributeTable[Index].Attribute) { - return (UINTN)mPageAttributeTable[Index].AddressMask; - } - } - - return 0; -} - /** Return page table entry to match the address. =20 @@ -353,181 +302,6 @@ GetAttributesFromPageEntry ( return Attributes; } =20 -/** - Modify memory attributes of page entry. - - @param[in] PageEntry The page entry. - @param[in] Attributes The bit mask of attributes to modify for t= he memory region. - @param[in] IsSet TRUE means to set attributes. FALSE means = to clear attributes. - @param[out] IsModified TRUE means page table modified. FALSE mean= s page table not modified. -**/ -VOID -ConvertPageEntryAttribute ( - IN UINT64 *PageEntry, - IN UINT64 Attributes, - IN BOOLEAN IsSet, - OUT BOOLEAN *IsModified - ) -{ - UINT64 CurrentPageEntry; - UINT64 NewPageEntry; - - CurrentPageEntry =3D *PageEntry; - NewPageEntry =3D CurrentPageEntry; - if ((Attributes & EFI_MEMORY_RP) !=3D 0) { - if (IsSet) { - NewPageEntry &=3D ~(UINT64)IA32_PG_P; - } else { - NewPageEntry |=3D IA32_PG_P; - } - } - - if ((Attributes & EFI_MEMORY_RO) !=3D 0) { - if (IsSet) { - NewPageEntry &=3D ~(UINT64)IA32_PG_RW; - if (mIsShadowStack) { - // Environment setup - // ReadOnly page need set Dirty bit for shadow stack - NewPageEntry |=3D IA32_PG_D; - // Clear user bit for supervisor shadow stack - NewPageEntry &=3D ~(UINT64)IA32_PG_U; - } else { - // Runtime update - // Clear dirty bit for non shadow stack, to protect RO page. - NewPageEntry &=3D ~(UINT64)IA32_PG_D; - } - } else { - NewPageEntry |=3D IA32_PG_RW; - } - } - - if ((Attributes & EFI_MEMORY_XP) !=3D 0) { - if (mXdSupported) { - if (IsSet) { - NewPageEntry |=3D IA32_PG_NX; - } else { - NewPageEntry &=3D ~IA32_PG_NX; - } - } - } - - *PageEntry =3D NewPageEntry; - if (CurrentPageEntry !=3D NewPageEntry) { - *IsModified =3D TRUE; - DEBUG ((DEBUG_VERBOSE, "ConvertPageEntryAttribute 0x%lx", CurrentPageE= ntry)); - DEBUG ((DEBUG_VERBOSE, "->0x%lx\n", NewPageEntry)); - } else { - *IsModified =3D FALSE; - } -} - -/** - This function returns if there is need to split page entry. - - @param[in] BaseAddress The base address to be checked. - @param[in] Length The length to be checked. - @param[in] PageEntry The page entry to be checked. - @param[in] PageAttribute The page attribute of the page entry. - - @retval SplitAttributes on if there is need to split page entry. -**/ -PAGE_ATTRIBUTE -NeedSplitPage ( - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute - ) -{ - UINT64 PageEntryLength; - - PageEntryLength =3D PageAttributeToLength (PageAttribute); - - if (((BaseAddress & (PageEntryLength - 1)) =3D=3D 0) && (Length >=3D Pag= eEntryLength)) { - return PageNone; - } - - if (((BaseAddress & PAGING_2M_MASK) !=3D 0) || (Length < SIZE_2MB)) { - return Page4K; - } - - return Page2M; -} - -/** - This function splits one page entry to small page entries. - - @param[in] PageEntry The page entry to be splitted. - @param[in] PageAttribute The page attribute of the page entry. - @param[in] SplitAttribute How to split the page entry. - - @retval RETURN_SUCCESS The page entry is splitted. - @retval RETURN_UNSUPPORTED The page entry does not support to be = splitted. - @retval RETURN_OUT_OF_RESOURCES No resource to split page entry. -**/ -RETURN_STATUS -SplitPage ( - IN UINT64 *PageEntry, - IN PAGE_ATTRIBUTE PageAttribute, - IN PAGE_ATTRIBUTE SplitAttribute - ) -{ - UINT64 BaseAddress; - UINT64 *NewPageEntry; - UINTN Index; - - ASSERT (PageAttribute =3D=3D Page2M || PageAttribute =3D=3D Page1G); - - if (PageAttribute =3D=3D Page2M) { - // - // Split 2M to 4K - // - ASSERT (SplitAttribute =3D=3D Page4K); - if (SplitAttribute =3D=3D Page4K) { - NewPageEntry =3D AllocatePageTableMemory (1); - DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); - if (NewPageEntry =3D=3D NULL) { - return RETURN_OUT_OF_RESOURCES; - } - - BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; - for (Index =3D 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { - NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) | mAddres= sEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); - } - - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAG= E_ATTRIBUTE_BITS; - return RETURN_SUCCESS; - } else { - return RETURN_UNSUPPORTED; - } - } else if (PageAttribute =3D=3D Page1G) { - // - // Split 1G to 2M - // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K = to get more compact page table. - // - ASSERT (SplitAttribute =3D=3D Page2M || SplitAttribute =3D=3D Page4K); - if (((SplitAttribute =3D=3D Page2M) || (SplitAttribute =3D=3D Page4K))= ) { - NewPageEntry =3D AllocatePageTableMemory (1); - DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); - if (NewPageEntry =3D=3D NULL) { - return RETURN_OUT_OF_RESOURCES; - } - - BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; - for (Index =3D 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { - NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) | mAddres= sEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); - } - - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAG= E_ATTRIBUTE_BITS; - return RETURN_SUCCESS; - } else { - return RETURN_UNSUPPORTED; - } - } else { - return RETURN_UNSUPPORTED; - } -} - /** This function modifies the page attributes for the memory region specifi= ed by BaseAddress and Length from their current attributes to the attributes specified by Attr= ibutes. @@ -535,12 +309,11 @@ SplitPage ( Caller should make sure BaseAddress and Length is at page boundary. =20 @param[in] PageTableBase The page table base. - @param[in] EnablePML5Paging If PML5 paging is enabled. + @param[in] PagingMode The paging mode. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to modify for t= he memory region. @param[in] IsSet TRUE means to set attributes. FALSE means = to clear attributes. - @param[out] IsSplitted TRUE means page table splitted. FALSE mean= s page table not splitted. @param[out] IsModified TRUE means page table modified. FALSE mean= s page table not modified. =20 @retval RETURN_SUCCESS The attributes were modified for the me= mory region. @@ -559,21 +332,19 @@ SplitPage ( RETURN_STATUS ConvertMemoryPageAttributes ( IN UINTN PageTableBase, - IN BOOLEAN EnablePML5Paging, + IN PAGING_MODE PagingMode, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, IN BOOLEAN IsSet, - OUT BOOLEAN *IsSplitted OPTIONAL, OUT BOOLEAN *IsModified OPTIONAL ) { - UINT64 *PageEntry; - PAGE_ATTRIBUTE PageAttribute; - UINTN PageEntryLength; - PAGE_ATTRIBUTE SplitAttribute; RETURN_STATUS Status; - BOOLEAN IsEntryModified; + IA32_MAP_ATTRIBUTE PagingAttribute; + IA32_MAP_ATTRIBUTE PagingAttrMask; + UINTN PageTableBufferSize; + VOID *PageTableBuffer; EFI_PHYSICAL_ADDRESS MaximumSupportMemAddress; =20 ASSERT (Attributes !=3D 0); @@ -581,6 +352,7 @@ ConvertMemoryPageAttributes ( =20 ASSERT ((BaseAddress & (SIZE_4KB - 1)) =3D=3D 0); ASSERT ((Length & (SIZE_4KB - 1)) =3D=3D 0); + ASSERT (PageTableBase !=3D 0); =20 if (Length =3D=3D 0) { return RETURN_INVALID_PARAMETER; @@ -599,61 +371,80 @@ ConvertMemoryPageAttributes ( return RETURN_UNSUPPORTED; } =20 - // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016= lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); - - if (IsSplitted !=3D NULL) { - *IsSplitted =3D FALSE; - } + PagingAttribute.Uint64 =3D 0; + PagingAttribute.Uint64 =3D mAddressEncMask | BaseAddress; + PagingAttrMask.Uint64 =3D 0; =20 - if (IsModified !=3D NULL) { - *IsModified =3D FALSE; + if ((Attributes & EFI_MEMORY_RO) !=3D 0) { + PagingAttrMask.Bits.ReadWrite =3D 1; + if (IsSet) { + PagingAttribute.Bits.ReadWrite =3D 0; + PagingAttrMask.Bits.Dirty =3D 1; + if (mIsShadowStack) { + // Environment setup + // ReadOnly page need set Dirty bit for shadow stack + PagingAttribute.Bits.Dirty =3D 1; + // Clear user bit for supervisor shadow stack + PagingAttribute.Bits.UserSupervisor =3D 0; + PagingAttrMask.Bits.UserSupervisor =3D 1; + } else { + // Runtime update + // Clear dirty bit for non shadow stack, to protect RO page. + PagingAttribute.Bits.Dirty =3D 0; + } + } else { + PagingAttribute.Bits.ReadWrite =3D 1; + } } =20 - // - // Below logic is to check 2M/4K page to make sure we do not waste memor= y. - // - while (Length !=3D 0) { - PageEntry =3D GetPageTableEntry (PageTableBase, EnablePML5Paging, Base= Address, &PageAttribute); - if (PageEntry =3D=3D NULL) { - return RETURN_UNSUPPORTED; + if ((Attributes & EFI_MEMORY_XP) !=3D 0) { + if (mXdSupported) { + PagingAttribute.Bits.Nx =3D IsSet ? 1 : 0; + PagingAttrMask.Bits.Nx =3D 1; } + } =20 - PageEntryLength =3D PageAttributeToLength (PageAttribute); - SplitAttribute =3D NeedSplitPage (BaseAddress, Length, PageEntry, Pag= eAttribute); - if (SplitAttribute =3D=3D PageNone) { - ConvertPageEntryAttribute (PageEntry, Attributes, IsSet, &IsEntryMod= ified); - if (IsEntryModified) { - if (IsModified !=3D NULL) { - *IsModified =3D TRUE; - } - } - + if ((Attributes & EFI_MEMORY_RP) !=3D 0) { + if (IsSet) { + PagingAttribute.Bits.Present =3D 0; // - // Convert success, move to next + // When map a range to non-present, all attributes except Present sh= ould not be provided. // - BaseAddress +=3D PageEntryLength; - Length -=3D PageEntryLength; + PagingAttrMask.Uint64 =3D 0; + PagingAttrMask.Bits.Present =3D 1; } else { - Status =3D SplitPage (PageEntry, PageAttribute, SplitAttribute); - if (RETURN_ERROR (Status)) { - return RETURN_UNSUPPORTED; - } - - if (IsSplitted !=3D NULL) { - *IsSplitted =3D TRUE; - } - - if (IsModified !=3D NULL) { - *IsModified =3D TRUE; - } - // - // Just split current page - // Convert success in next around + // When map range to present range, provide all attributes. // + PagingAttribute.Bits.Present =3D 1; + PagingAttrMask.Uint64 =3D MAX_UINT64; } } =20 + if (PagingAttrMask.Uint64 =3D=3D 0) { + return RETURN_SUCCESS; + } + + PageTableBufferSize =3D 0; + Status =3D PageTableMap (&PageTableBase, PagingMode, NULL, = &PageTableBufferSize, BaseAddress, Length, &PagingAttribute, &PagingAttrMas= k, IsModified); + + if (Status =3D=3D RETURN_INVALID_PARAMETER) { + // + // The only reason that PageTableMap returns RETURN_INVALID_PARAMETER = here is to modify other attributes + // of non-present range but remains the non-present range still as non= -present. + // + DEBUG ((DEBUG_ERROR, "SMM ConvertMemoryPageAttributes: Non-present ran= ge in [0x%lx, 0x%lx] needs to be removed\n", BaseAddress, BaseAddress + Len= gth)); + } + + if (Status =3D=3D RETURN_BUFFER_TOO_SMALL) { + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTa= bleBufferSize)); + ASSERT (PageTableBuffer !=3D NULL); + Status =3D PageTableMap (&PageTableBase, PagingMode, PageTableBuffer, = &PageTableBufferSize, BaseAddress, Length, &PagingAttribute, &PagingAttrMas= k, IsModified); + } + + ASSERT_RETURN_ERROR (Status); + ASSERT (PageTableBufferSize =3D=3D 0); + return RETURN_SUCCESS; } =20 @@ -697,11 +488,10 @@ FlushTlbForAll ( Length from their current attributes to the attributes specified by Attr= ibutes. =20 @param[in] PageTableBase The page table base. - @param[in] EnablePML5Paging If PML5 paging is enabled. + @param[in] PagingMode The paging mode. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to set for the = memory region. - @param[out] IsSplitted TRUE means page table splitted. FALSE mean= s page table not splitted. =20 @retval EFI_SUCCESS The attributes were set for the memory reg= ion. @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by @@ -720,17 +510,16 @@ FlushTlbForAll ( EFI_STATUS SmmSetMemoryAttributesEx ( IN UINTN PageTableBase, - IN BOOLEAN EnablePML5Paging, + IN PAGING_MODE PagingMode, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN UINT64 Attributes ) { EFI_STATUS Status; BOOLEAN IsModified; =20 - Status =3D ConvertMemoryPageAttributes (PageTableBase, EnablePML5Paging,= BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified); + Status =3D ConvertMemoryPageAttributes (PageTableBase, PagingMode, BaseA= ddress, Length, Attributes, TRUE, &IsModified); if (!EFI_ERROR (Status)) { if (IsModified) { // @@ -748,11 +537,10 @@ SmmSetMemoryAttributesEx ( Length from their current attributes to the attributes specified by Attr= ibutes. =20 @param[in] PageTableBase The page table base. - @param[in] EnablePML5Paging If PML5 paging is enabled. + @param[in] PagingMode The paging mode. @param[in] BaseAddress The physical address that is the start add= ress of a memory region. @param[in] Length The size in bytes of the memory region. @param[in] Attributes The bit mask of attributes to clear for th= e memory region. - @param[out] IsSplitted TRUE means page table splitted. FALSE mean= s page table not splitted. =20 @retval EFI_SUCCESS The attributes were cleared for the memory= region. @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by @@ -771,17 +559,16 @@ SmmSetMemoryAttributesEx ( EFI_STATUS SmmClearMemoryAttributesEx ( IN UINTN PageTableBase, - IN BOOLEAN EnablePML5Paging, + IN PAGING_MODE PagingMode, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, - IN UINT64 Attributes, - OUT BOOLEAN *IsSplitted OPTIONAL + IN UINT64 Attributes ) { EFI_STATUS Status; BOOLEAN IsModified; =20 - Status =3D ConvertMemoryPageAttributes (PageTableBase, EnablePML5Paging,= BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified); + Status =3D ConvertMemoryPageAttributes (PageTableBase, PagingMode, BaseA= ddress, Length, Attributes, FALSE, &IsModified); if (!EFI_ERROR (Status)) { if (IsModified) { // @@ -823,14 +610,10 @@ SmmSetMemoryAttributes ( IN UINT64 Attributes ) { - IA32_CR4 Cr4; - UINTN PageTableBase; - BOOLEAN Enable5LevelPaging; - - PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; - Cr4.UintN =3D AsmReadCr4 (); - Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); - return SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, Base= Address, Length, Attributes, NULL); + UINTN PageTableBase; + + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + return SmmSetMemoryAttributesEx (PageTableBase, mPagingMode, BaseAddress= , Length, Attributes); } =20 /** @@ -862,14 +645,10 @@ SmmClearMemoryAttributes ( IN UINT64 Attributes ) { - IA32_CR4 Cr4; - UINTN PageTableBase; - BOOLEAN Enable5LevelPaging; - - PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; - Cr4.UintN =3D AsmReadCr4 (); - Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); - return SmmClearMemoryAttributesEx (PageTableBase, Enable5LevelPaging, Ba= seAddress, Length, Attributes, NULL); + UINTN PageTableBase; + + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + return SmmClearMemoryAttributesEx (PageTableBase, mPagingMode, BaseAddre= ss, Length, Attributes); } =20 /** @@ -891,7 +670,7 @@ SetShadowStack ( EFI_STATUS Status; =20 mIsShadowStack =3D TRUE; - Status =3D SmmSetMemoryAttributesEx (Cr3, m5LevelPagingNeeded, B= aseAddress, Length, EFI_MEMORY_RO, NULL); + Status =3D SmmSetMemoryAttributesEx (Cr3, mPagingMode, BaseAddre= ss, Length, EFI_MEMORY_RO); mIsShadowStack =3D FALSE; =20 return Status; @@ -915,7 +694,7 @@ SetNotPresentPage ( { EFI_STATUS Status; =20 - Status =3D SmmSetMemoryAttributesEx (Cr3, m5LevelPagingNeeded, BaseAddre= ss, Length, EFI_MEMORY_RP, NULL); + Status =3D SmmSetMemoryAttributesEx (Cr3, mPagingMode, BaseAddress, Leng= th, EFI_MEMORY_RP); return Status; } =20 @@ -1799,7 +1578,7 @@ EnablePageTableProtection ( // // Set entire pool including header, used-memory and left free-memory = as ReadOnly in SMM page table. // - ConvertMemoryPageAttributes (PageTableBase, m5LevelPagingNeeded, Addre= ss, PoolSize, EFI_MEMORY_RO, TRUE, NULL, NULL); + ConvertMemoryPageAttributes (PageTableBase, mPagingMode, Address, Pool= Size, EFI_MEMORY_RO, TRUE, NULL); Pool =3D Pool->NextPool; } while (Pool !=3D HeadPool); } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 3deb1ffd67..a25a96f68c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -1,7 +1,7 @@ /** @file Page Fault (#PF) handler for X64 processors =20 -Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -353,7 +353,12 @@ SmmInitPageTable ( m1GPageTableSupport =3D Is1GPageSupport (); m5LevelPagingNeeded =3D Is5LevelPagingNeeded (); mPhysicalAddressBits =3D CalculateMaximumSupportAddress (); - PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); + if (m5LevelPagingNeeded) { + mPagingMode =3D m1GPageTableSupport ? Paging5Level1GB : Paging5Level; + PatchInstructionX86 (gPatch5LevelPagingNeeded, TRUE, 1); + } else { + mPagingMode =3D m1GPageTableSupport ? Paging4Level1GB : Paging4Level; + } DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPag= ingNeeded)); DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTab= leSupport)); DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRes= trictedMemoryAccess)); --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102878): https://edk2.groups.io/g/devel/message/102878 Mute This Topic: https://groups.io/mt/98215424/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102879+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102879+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289775; cv=none; d=zohomail.com; s=zohoarc; b=nQePNZvuTQjtO6voNuFMa2eucIevoq7I2w26QZPXV+hyuY0V3nLWRAoDrbGpR8NouhSqYFRKwMGKnHaZVHXuG4CwGfvJ/kC4+/MzVQBSjd5xAySNIHma0yTm9/3sygKB3zjOjW/d9QEVpINykWYqH4ZsOeN/YHUTdy2xv8v5VC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289775; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=r9ldKTyW3tR0CbZVVtoPqJ6mvBfQBpeGXOtPK6FhcYg=; b=dQzWfL3fA6Pn0dszG4mlBk1VVz8Zuyw3S+a/Ccdhbm9ujeHFJpGeDlT9H80k01SjK84BTWtikn1jyDAtCZxykze9zGrlVtgwAWIjN1F8RNHzpOcObsPCt1lJWnvAym8aCJu3afDUu9XoLb5ONns5AlGeMUaWrIT2E8ZfjlPy6Tw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102879+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1681289775517952.2166641141467; Wed, 12 Apr 2023 01:56:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6lyMYY1788612xf0b9Rpk9Ur; Wed, 12 Apr 2023 01:56:14 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.38106.1681289773082554342 for ; Wed, 12 Apr 2023 01:56:13 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126787" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126787" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262093" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262093" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:02 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 4/8] UefiCpuPkg/PiSmmCpuDxeSmm: Avoid setting non-present range to RO/NX Date: Wed, 12 Apr 2023 16:53:39 +0800 Message-Id: <20230412085343.1077-5-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 9qJa31wTgsv7AJfmj8V56sV6x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289774; bh=qHhth8cisaEUvfgCaHQWW/f7y+PLfn2atkmD5Z1BOqw=; h=Cc:Date:From:Reply-To:Subject:To; b=KmXCF6C7RFsaLLHLhn5GX+KDTqrS57578pkO/eiiCF1cYa1onrna5GoNrkIZpraak73 LMkz74iPpXpxIkSrwHEasIyAiRLl0gvmXtiAN+EsZA7l1u5vMAZ2DXvoH1sqVbh9IxKuw WsXeBi54d/onUj3Zdyzp0Ghxz7+QkUnrXHU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289776894100016 Content-Type: text/plain; charset="utf-8" In PiSmmCpuDxeSmm code, SetMemMapAttributes() marks memory ranges in SmmMemoryAttributesTable to RO/NX. There may exist non-present range in these memory ranges. Set other attributes for a non-present range is not permitted in CpuPageTableMapLib. So add code to handle this case. Only map the present ranges in SmmMemoryAttributesTable to RO or NX. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 141 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++---------------------- 1 file changed, 119 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index deb5895d83..89040d386e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -858,6 +858,89 @@ PatchGdtIdtMap ( ); } =20 +/** + This function remove the non-present range in [MemMapStart, MemMapLimit]= and + set [MemMapStart, NonPresentRangeStart] as MemoryAttribute in page table. + + @param MemMapStart Pointer to the start address of range. + @param MemMapLimit Limit address of range. + @param NonPresentRangeStart Start address of non-present range. + @param NonPresentRangeLimit Limit address of non-present range. + @param MemoryAttribute The bit mask of attributes to modify = for the memory region. + +**/ +VOID +RemoveNonPresentRange ( + UINT64 *MemMapStart, + UINT64 MemMapLimit, + UINT64 NonPresentRangeStart, + UINT64 NonPresentRangeLimit, + UINT64 MemoryAttribute + ) +{ + if (*MemMapStart < NonPresentRangeStart) { + SmmSetMemoryAttributes ( + *MemMapStart, + NonPresentRangeStart - *MemMapStart, + MemoryAttribute + ); + } + + *MemMapStart =3D NonPresentRangeLimit; +} + +/** + This function set [MemMapStart, MemMapLimit] to the input MemoryAttribut= e. + + @param MemMapStart Start address of range. + @param MemMapLimit Limit address of range. + @param Map Pointer to the array of Cr3 IA32_MAP_ENTRY. + @param Count Count of IA32_MAP_ENTRY in Map. + @param MemoryAttribute The bit mask of attributes to modify for the= memory region. + +**/ +VOID +SetMemMapWithNonPresentRange ( + UINT64 MemMapStart, + UINT64 MemMapLimit, + IA32_MAP_ENTRY *Map, + UINTN Count, + UINT64 MemoryAttribute + ) +{ + UINTN Index; + UINT64 NonPresentRangeStart; + + NonPresentRangeStart =3D 0; + + for (Index =3D 0; Index < Count; Index++) { + if ((Map[Index].LinearAddress > NonPresentRangeStart) && + (MemMapStart < Map[Index].LinearAddress) && (MemMapLimit > NonPres= entRangeStart)) + { + // + // [NonPresentRangeStart, Map[Index].LinearAddress] is non-present. + // + RemoveNonPresentRange (&MemMapStart, MemMapLimit, NonPresentRangeSta= rt, Map[Index].LinearAddress, MemoryAttribute); + } + + NonPresentRangeStart =3D Map[Index].LinearAddress + Map[Index].Length; + if (NonPresentRangeStart >=3D MemMapLimit) { + break; + } + } + + // + // There is no non-present in current [MemMapStart, MemMapLimit] anymore. + // + if (MemMapStart < MemMapLimit) { + SmmSetMemoryAttributes ( + MemMapStart, + MemMapLimit - MemMapStart, + MemoryAttribute + ); + } +} + /** This function sets memory attribute according to MemoryAttributesTable. **/ @@ -872,6 +955,21 @@ SetMemMapAttributes ( UINTN DescriptorSize; UINTN Index; EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable; + UINTN PageTable; + EFI_STATUS Status; + IA32_MAP_ENTRY *Map; + UINTN Count; + UINT64 MemoryAttribute; + + Count =3D 0; + Map =3D NULL; + PageTable =3D AsmReadCr3 (); + Status =3D PageTableParse (PageTable, mPagingMode, NULL, &Count); + ASSERT (Status =3D=3D RETURN_BUFFER_TOO_SMALL); + Map =3D AllocatePool (Count * sizeof (IA32_MAP_ENTRY)); + ASSERT (Map !=3D NULL); + Status =3D PageTableParse (PageTable, mPagingMode, Map, &Count); + ASSERT_RETURN_ERROR (Status); =20 SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (= VOID **)&MemoryAttributesTable); if (MemoryAttributesTable =3D=3D NULL) { @@ -901,33 +999,32 @@ SetMemMapAttributes ( MemoryMap =3D MemoryMapStart; for (Index =3D 0; Index < MemoryMapEntryCount; Index++) { DEBUG ((DEBUG_VERBOSE, "SetAttribute: Memory Entry - 0x%lx, 0x%x\n", M= emoryMap->PhysicalStart, MemoryMap->NumberOfPages)); - switch (MemoryMap->Type) { - case EfiRuntimeServicesCode: - SmmSetMemoryAttributes ( - MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), - EFI_MEMORY_RO - ); - break; - case EfiRuntimeServicesData: - SmmSetMemoryAttributes ( - MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), - EFI_MEMORY_XP - ); - break; - default: - SmmSetMemoryAttributes ( - MemoryMap->PhysicalStart, - EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages), - EFI_MEMORY_XP - ); - break; + if (MemoryMap->Type =3D=3D EfiRuntimeServicesCode) { + MemoryAttribute =3D EFI_MEMORY_RO; + } else { + // + // Set other type memory as NX. + // + MemoryAttribute =3D EFI_MEMORY_XP; } =20 + // + // There may exist non-present range overlaps with the MemoryMap range. + // Do not change other attributes of non-present range while still rem= aining it as non-present + // + SetMemMapWithNonPresentRange ( + MemoryMap->PhysicalStart, + MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->Numb= erOfPages), + Map, + Count, + MemoryAttribute + ); + MemoryMap =3D NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize); } =20 + FreePool (Map); + PatchSmmSaveStateMap (); PatchGdtIdtMap (); =20 --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102879): https://edk2.groups.io/g/devel/message/102879 Mute This Topic: https://groups.io/mt/98215425/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102880+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102880+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289775; cv=none; d=zohomail.com; s=zohoarc; b=i+b4v7cqfndGSv/Y/ROJratxvads6W1WbTzZMyq+rjiaLntqVtStshKGL2DGnBCwA6b7pmrYGTlduZGl77p3uVEmM+BKDyhK5KUuPLylPCoQoU5gqkNl/Ivd0npghDMqxZLBGnDHMB823RzcUHjpa9TGTJkgXf1zdTr9U4B8Wh4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289775; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=u/zFPNiCHw0/2q4KH6uFaoMlpsLUciNXzelqWEucQ9k=; b=O+ARdmUve0Yq08OQZczd/3bKiTKE5s1nPPAvciFghNhRsiGFwESygIs3LTfUDrdrb06jS5gSHFAcWuXMskStUeYt0Cm9EK4uJPa8xxV4KAlC8CA/Ol8AY0FzRqZ9SgWDjUR+Yr9rynJY1tUzjp7PV8m+rCq8RRZK9vsqGqfq+ek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102880+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1681289775929354.6214461779474; Wed, 12 Apr 2023 01:56:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id piibYY1788612xRft23yWg2f; Wed, 12 Apr 2023 01:56:15 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.38106.1681289773082554342 for ; Wed, 12 Apr 2023 01:56:13 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126799" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126799" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262100" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262100" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:07 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 5/8] UefiCpuPkg: Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h Date: Wed, 12 Apr 2023 16:53:40 +0800 Message-Id: <20230412085343.1077-6-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: mwrXojIEbdskxF30lXS8wzShx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289775; bh=O2VtR1sXkthzH4qXftzDkd3DCMC95pL30RwZuWN2am8=; h=Cc:Date:From:Reply-To:Subject:To; b=peu81q86Fpv8SSwjKYWg0FroFnUQBoSktRzzKLPiHBpHodGw7w8i65IhyEKVtIvQgDs opOkPYQTLRN8TTUq7N26g9gA3DVVHCX05RNv1Q5r43gq3gvfTb+3mFhB7AIDgbsIUJbXO zkT3N11b+R6TUIixWkvSX1QPKwidh8XUpqM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289776887100015 Content-Type: text/plain; charset="utf-8" Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove extern for mSmmShadowStackSize in c files to simplify code. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 3 +-- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 + UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 3 +-- 5 files changed, 3 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiS= mmCpuDxeSmm/Ia32/SmmFuncsArch.c index 6c48a53f67..636dc8d92f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c @@ -1,7 +1,7 @@ /** @file SMM CPU misc functions for Ia32 arch specific. =20 -Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -14,7 +14,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer; UINTN mGdtBufferSize; =20 extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; =20 X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index baf827cf9d..1878252eac 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -29,8 +29,6 @@ MM_COMPLETION mSmmStartupThisApToken; // UINT32 *mPackageFirstThreadIndex =3D NULL; =20 -extern UINTN mSmmShadowStackSize; - /** Performs an atomic compare exchange operation to get semaphore. The compare exchange operation must be performed using diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index ba341cadc6..a155e09200 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -262,6 +262,7 @@ extern EFI_SMM_CPU_PROTOCOL mSmmCpu; extern EFI_MM_MP_PROTOCOL mSmmMp; extern BOOLEAN m5LevelPagingNeeded; extern PAGING_MODE mPagingMode; +extern UINTN mSmmShadowStackSize; =20 /// /// The mode of the CPU at the time an SMI occurs diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index a25a96f68c..25ced50955 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define PAGE_TABLE_PAGES 8 #define ACC_MAX_BIT BIT3 =20 -extern UINTN mSmmShadowStackSize; - LIST_ENTRY mPagePool =3D INITIALIZE_LIST_HEAD_VAR= IABLE (mPagePool); BOOLEAN m1GPageTableSupport =3D FALSE; BOOLEAN mCpuSmmRestrictedMemoryAccess; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSm= mCpuDxeSmm/X64/SmmFuncsArch.c index 00a284c369..c4f21e2155 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -1,7 +1,7 @@ /** @file SMM CPU misc functions for x64 arch specific. =20 -Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -12,7 +12,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer; UINTN mGdtBufferSize; =20 extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; =20 X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102880): https://edk2.groups.io/g/devel/message/102880 Mute This Topic: https://groups.io/mt/98215426/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102881+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102881+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289777; cv=none; d=zohomail.com; s=zohoarc; b=OwaElYFSTwCIwCj8Oj5NpshPBtxugQaMNUQcJDtZFdwf+rcoMeefIDuLd/cfdJ71URruuUN07X4mtdK0NkQL0F2+1gjlKX2Naxyqq0igBeqyEqhAQiIusXRPmBhaADW3UD1YlChKyg/hLPJEpMMkdeEWyGojc3k4kyIjOeoCF3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289777; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/KY0/LTzHT1Sp7N38Q/2rzYo3V5e2McHVs+fDq3/n1Q=; b=NrNwZjAgMsx5gKJSlfHJZTHYsnyB1Zy9uhfTID3/QXVhg98zPWgOtAMG8s3KaW5s2zzx0tCtSmqzWESkcPtCIZ6kn0gXjRuYJc0ijmm+16bkWxdUZC4vNntywsarzVVdmtpbxPFBQi+VqWCVAXQgIxch8Kt8kg6TDYaO86PVQV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102881+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1681289777349344.99736055544736; Wed, 12 Apr 2023 01:56:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ebJfYY1788612xWXD6Vs6OTp; Wed, 12 Apr 2023 01:56:17 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.38106.1681289773082554342 for ; Wed, 12 Apr 2023 01:56:15 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126826" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126826" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262110" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262110" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:10 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 6/8] UefiCpuPkg: Refinement to current smm page table generation code Date: Wed, 12 Apr 2023 16:53:41 +0800 Message-Id: <20230412085343.1077-7-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: KXBuceMwvFK2RBn4tKsy5aeKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289777; bh=Qvb0RcgIIcbGhtv9cm+8ZBlQwrIsxH6DKNNQ3d73bjg=; h=Cc:Date:From:Reply-To:Subject:To; b=DNJePqTR46mxvgKrJS0lGG0ICYcLyAQLSBGFwziGFSaiYnWM9AtCr2KiMeeZiAbPeF1 q8rrqR7tXjNJ53COG8np7432kt3tQRU7DbJFOyHWOYhs9bi7qPdhSQr7uCVZop5nXcfNS WncyTKoqmaSgKWumGAXe+Yf3ccO9p6fMN6A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289778651100021 Content-Type: text/plain; charset="utf-8" This commit is code refinement to current smm pagetable generation code. Add a new GenSmmPageTable() API to create page table for smm based on the PageTableMap() API in CpuPageTableLib. Caller only needs to specify the paging mode and the PhysicalAddressBits to map. This function can be used to create both IA32 pae paging and X64 5level, 4level paging. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 130 -----------------= ---------------------------------------------------------------------------= -------------------------------------- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 15 +++++++++------ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 65 +++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 218 +++++++++++++++++= ++++++---------------------------------------------------------------------= ---------------------------------------------------------------------------= --------------------------------------------------- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 19 ++---------------= -- 7 files changed, 101 insertions(+), 350 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpu= DxeSmm/Ia32/PageTbl.c index 9c8107080a..b11264ce4a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -63,7 +63,7 @@ SmmInitPageTable ( InitializeIDTSmmStackGuard (); } =20 - return Gen4GPageTable (TRUE); + return GenSmmPageTable (PagingPae, mPhysicalAddressBits); } =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c b/UefiCpuPkg/P= iSmmCpuDxeSmm/Ia32/SmmProfileArch.c index bba4a6f058..650090e534 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c @@ -18,7 +18,7 @@ InitSmmS3Cr3 ( VOID ) { - mSmmS3ResumeState->SmmS3Cr3 =3D Gen4GPageTable (TRUE); + mSmmS3ResumeState->SmmS3Cr3 =3D GenSmmPageTable (PagingPae, mPhysicalAdd= ressBits); =20 return; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 1878252eac..f8b81fc96e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -999,136 +999,6 @@ APHandler ( ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 -/** - Create 4G PageTable in SMRAM. - - @param[in] Is32BitPageTable Whether the page table is 32-bit PAE - @return PageTable Address - -**/ -UINT32 -Gen4GPageTable ( - IN BOOLEAN Is32BitPageTable - ) -{ - VOID *PageTable; - UINTN Index; - UINT64 *Pte; - UINTN PagesNeeded; - UINTN Low2MBoundary; - UINTN High2MBoundary; - UINTN Pages; - UINTN GuardPage; - UINT64 *Pdpte; - UINTN PageIndex; - UINTN PageAddress; - - Low2MBoundary =3D 0; - High2MBoundary =3D 0; - PagesNeeded =3D 0; - if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - // - // Add one more page for known good stack, then find the lower 2MB ali= gned address. - // - Low2MBoundary =3D (mSmmStackArrayBase + EFI_PAGE_SIZE) & ~(SIZE_2MB-1); - // - // Add two more pages for known good stack and stack guard page, - // then find the lower 2MB aligned address. - // - High2MBoundary =3D (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStac= kSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1); - PagesNeeded =3D ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1; - } - - // - // Allocate the page table - // - PageTable =3D AllocatePageTableMemory (5 + PagesNeeded); - ASSERT (PageTable !=3D NULL); - - PageTable =3D (VOID *)((UINTN)PageTable); - Pte =3D (UINT64 *)PageTable; - - // - // Zero out all page table entries first - // - ZeroMem (Pte, EFI_PAGES_TO_SIZE (1)); - - // - // Set Page Directory Pointers - // - for (Index =3D 0; Index < 4; Index++) { - Pte[Index] =3D ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAdd= ressEncMask | - (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_= ATTRIBUTE_BITS); - } - - Pte +=3D EFI_PAGE_SIZE / sizeof (*Pte); - - // - // Fill in Page Directory Entries - // - for (Index =3D 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) { - Pte[Index] =3D (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATT= RIBUTE_BITS; - } - - Pdpte =3D (UINT64 *)PageTable; - if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - Pages =3D (UINTN)PageTable + EFI_PAGES_TO_SIZE (5); - GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE; - for (PageIndex =3D Low2MBoundary; PageIndex <=3D High2MBoundary; PageI= ndex +=3D SIZE_2MB) { - Pte =3D (UINT64 *)(UINTN= )(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(= EFI_PAGE_SIZE - 1)); - Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] =3D (UINT64)Pages | = mAddressEncMask | PAGE_ATTRIBUTE_BITS; - // - // Fill in Page Table Entries - // - Pte =3D (UINT64 *)Pages; - PageAddress =3D PageIndex; - for (Index =3D 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) { - if (PageAddress =3D=3D GuardPage) { - // - // Mark the guard page as non-present - // - Pte[Index] =3D PageAddress | mAddressEncMask; - GuardPage +=3D (mSmmStackSize + mSmmShadowStackSize); - if (GuardPage > mSmmStackArrayEnd) { - GuardPage =3D 0; - } - } else { - Pte[Index] =3D PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BI= TS; - } - - PageAddress +=3D EFI_PAGE_SIZE; - } - - Pages +=3D EFI_PAGE_SIZE; - } - } - - if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) !=3D 0) { - Pte =3D (UINT64 *)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZ= E - 1)); - if ((Pte[0] & IA32_PG_PS) =3D=3D 0) { - // 4K-page entries are already mapped. Just hide the first one anywa= y. - Pte =3D (UINT64 *)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE= _SIZE - 1)); - Pte[0] &=3D ~(UINT64)IA32_PG_P; // Hide page 0 - } else { - // Create 4K-page entries - Pages =3D (UINTN)AllocatePageTableMemory (1); - ASSERT (Pages !=3D 0); - - Pte[0] =3D (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS); - - Pte =3D (UINT64 *)Pages; - PageAddress =3D 0; - Pte[0] =3D PageAddress | mAddressEncMask; // Hide page 0 but pr= esent left - for (Index =3D 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) { - PageAddress +=3D EFI_PAGE_SIZE; - Pte[Index] =3D PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BI= TS; - } - } - } - - return (UINT32)(UINTN)PageTable; -} - /** Checks whether the input token is the current used token. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index a155e09200..b72c883fc5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -542,15 +542,18 @@ extern UINT8 mPhysicalAddress= Bits; extern UINT64 mAddressEncMask; =20 /** - Create 4G PageTable in SMRAM. + Create page table based on input PagingMode and PhysicalAddressBits in s= mm. =20 - @param[in] Is32BitPageTable Whether the page table is 32-bit PAE - @return PageTable Address + @param[in] PagingMode The paging mode. + @param[in] PhysicalAddressBits The bits of physical address to map. + + @retval PageTable Address =20 **/ -UINT32 -Gen4GPageTable ( - IN BOOLEAN Is32BitPageTable +UINTN +GenSmmPageTable ( + IN PAGING_MODE PagingMode, + IN UINT8 PhysicalAddressBits ); =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 89040d386e..5b970157c6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1549,6 +1549,71 @@ EdkiiSmmClearMemoryAttributes ( return SmmClearMemoryAttributes (BaseAddress, Length, Attributes); } =20 +/** + Create page table based on input PagingMode and PhysicalAddressBits in s= mm. + + @param[in] PagingMode The paging mode. + @param[in] PhysicalAddressBits The bits of physical address to map. + + @retval PageTable Address + +**/ +UINTN +GenSmmPageTable ( + IN PAGING_MODE PagingMode, + IN UINT8 PhysicalAddressBits + ) +{ + UINTN PageTableBufferSize; + UINTN PageTable; + VOID *PageTableBuffer; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + RETURN_STATUS Status; + UINTN GuardPage; + UINTN Index; + UINT64 Length; + + Length =3D LShiftU64 (1, PhysicalAddressBits); + PageTable =3D 0; + PageTableBufferSize =3D 0; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Uint64 =3D mAddressEncMask; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + MapAttribute.Bits.UserSupervisor =3D 1; + MapAttribute.Bits.Accessed =3D 1; + MapAttribute.Bits.Dirty =3D 1; + + Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBufferS= ize, 0, Length, &MapAttribute, &MapMask, NULL); + ASSERT (Status =3D=3D RETURN_BUFFER_TOO_SMALL); + DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial SMM = page table\n", PageTableBufferSize)); + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTabl= eBufferSize)); + ASSERT (PageTableBuffer !=3D NULL); + Status =3D PageTableMap (&PageTable, PagingMode, PageTableBuffer, &PageT= ableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); + ASSERT (Status =3D=3D RETURN_SUCCESS); + ASSERT (PageTableBufferSize =3D=3D 0); + + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { + // + // Mark the guard page at the bottom of smm stack as non-present + // + for (Index =3D 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOf= Cpus; Index++) { + GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE + Index * (mSmmStac= kSize + mSmmShadowStackSize); + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, Gu= ardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); + } + } + + if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) !=3D 0) { + // + // Mark [0, 4k] as non-present + // + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, 0, SIZE= _4KB, EFI_MEMORY_RP, TRUE, NULL); + } + + return (UINTN)PageTable; +} + /** This function retrieves the attributes of the memory region specified by BaseAddress and Length. If different attributes are got from different p= art diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 25ced50955..cdbf52ae77 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -167,160 +167,6 @@ CalculateMaximumSupportAddress ( return PhysicalAddressBits; } =20 -/** - Set static page table. - - @param[in] PageTable Address of page table. - @param[in] PhysicalAddressBits The maximum physical address bits supp= orted. -**/ -VOID -SetStaticPageTable ( - IN UINTN PageTable, - IN UINT8 PhysicalAddressBits - ) -{ - UINT64 PageAddress; - UINTN NumberOfPml5EntriesNeeded; - UINTN NumberOfPml4EntriesNeeded; - UINTN NumberOfPdpEntriesNeeded; - UINTN IndexOfPml5Entries; - UINTN IndexOfPml4Entries; - UINTN IndexOfPdpEntries; - UINTN IndexOfPageDirectoryEntries; - UINT64 *PageMapLevel5Entry; - UINT64 *PageMapLevel4Entry; - UINT64 *PageMap; - UINT64 *PageDirectoryPointerEntry; - UINT64 *PageDirectory1GEntry; - UINT64 *PageDirectoryEntry; - - // - // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses - // when 5-Level Paging is disabled. - // - ASSERT (PhysicalAddressBits <=3D 52); - if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) { - PhysicalAddressBits =3D 48; - } - - NumberOfPml5EntriesNeeded =3D 1; - if (PhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits= - 48); - PhysicalAddressBits =3D 48; - } - - NumberOfPml4EntriesNeeded =3D 1; - if (PhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits= - 39); - PhysicalAddressBits =3D 39; - } - - NumberOfPdpEntriesNeeded =3D 1; - ASSERT (PhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits - = 30); - - // - // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. - // - PageMap =3D (VOID *)PageTable; - - PageMapLevel4Entry =3D PageMap; - PageMapLevel5Entry =3D NULL; - if (m5LevelPagingNeeded) { - // - // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it. - // - PageMapLevel5Entry =3D PageMap; - } - - PageAddress =3D 0; - - for ( IndexOfPml5Entries =3D 0 - ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded - ; IndexOfPml5Entries++, PageMapLevel5Entry++) - { - // - // Each PML5 entry points to a page of PML4 entires. - // So lets allocate space for them and fill them in in the IndexOfPml4= Entries loop. - // When 5-Level Paging is disabled, below allocation happens only once. - // - if (m5LevelPagingNeeded) { - PageMapLevel4Entry =3D (UINT64 *)((*PageMapLevel5Entry) & ~mAddressE= ncMask & gPhyMask); - if (PageMapLevel4Entry =3D=3D NULL) { - PageMapLevel4Entry =3D AllocatePageTableMemory (1); - ASSERT (PageMapLevel4Entry !=3D NULL); - ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1)); - - *PageMapLevel5Entry =3D (UINT64)(UINTN)PageMapLevel4Entry | mAddre= ssEncMask | PAGE_ATTRIBUTE_BITS; - } - } - - for (IndexOfPml4Entries =3D 0; IndexOfPml4Entries < (NumberOfPml5Entri= esNeeded =3D=3D 1 ? NumberOfPml4EntriesNeeded : 512); IndexOfPml4Entries++,= PageMapLevel4Entry++) { - // - // Each PML4 entry points to a page of Page Directory Pointer entrie= s. - // - PageDirectoryPointerEntry =3D (UINT64 *)((*PageMapLevel4Entry) & ~mA= ddressEncMask & gPhyMask); - if (PageDirectoryPointerEntry =3D=3D NULL) { - PageDirectoryPointerEntry =3D AllocatePageTableMemory (1); - ASSERT (PageDirectoryPointerEntry !=3D NULL); - ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1)); - - *PageMapLevel4Entry =3D (UINT64)(UINTN)PageDirectoryPointerEntry |= mAddressEncMask | PAGE_ATTRIBUTE_BITS; - } - - if (m1GPageTableSupport) { - PageDirectory1GEntry =3D PageDirectoryPointerEntry; - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress= +=3D SIZE_1GB) { - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPageDirectoryEntrie= s < 4)) { - // - // Skip the < 4G entries - // - continue; - } - - // - // Fill in the Page Directory entries - // - *PageDirectory1GEntry =3D PageAddress | mAddressEncMask | IA32_P= G_PS | PAGE_ATTRIBUTE_BITS; - } - } else { - PageAddress =3D BASE_4GB; - for (IndexOfPdpEntries =3D 0; IndexOfPdpEntries < (NumberOfPml4Ent= riesNeeded =3D=3D 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++,= PageDirectoryPointerEntry++) { - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPdpEntries < 4)) { - // - // Skip the < 4G entries - // - continue; - } - - // - // Each Directory Pointer entries points to a page of Page Direc= tory entires. - // So allocate space for them and fill them in in the IndexOfPag= eDirectoryEntries loop. - // - PageDirectoryEntry =3D (UINT64 *)((*PageDirectoryPointerEntry) &= ~mAddressEncMask & gPhyMask); - if (PageDirectoryEntry =3D=3D NULL) { - PageDirectoryEntry =3D AllocatePageTableMemory (1); - ASSERT (PageDirectoryEntry !=3D NULL); - ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1)); - - // - // Fill in a Page Directory Pointer Entries - // - *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirectoryEnt= ry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; - } - - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress= +=3D SIZE_2MB) { - // - // Fill in the Page Directory entries - // - *PageDirectoryEntry =3D PageAddress | mAddressEncMask | IA32_P= G_PS | PAGE_ATTRIBUTE_BITS; - } - } - } - } - } -} - /** Create PageTable for SMM use. =20 @@ -332,15 +178,16 @@ SmmInitPageTable ( VOID ) { - EFI_PHYSICAL_ADDRESS Pages; - UINT64 *PTEntry; + UINTN PageTable; LIST_ENTRY *FreePage; UINTN Index; UINTN PageFaultHandlerHookAddress; IA32_IDT_GATE_DESCRIPTOR *IdtEntry; EFI_STATUS Status; + UINT64 *Pml3Entry; UINT64 *Pml4Entry; UINT64 *Pml5Entry; + UINT8 PhysicalAddressBits; =20 // // Initialize spin lock @@ -357,59 +204,40 @@ SmmInitPageTable ( } else { mPagingMode =3D m1GPageTableSupport ? Paging4Level1GB : Paging4Level; } + DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPag= ingNeeded)); DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTab= leSupport)); DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRes= trictedMemoryAccess)); DEBUG ((DEBUG_INFO, "PhysicalAddressBits - %d\n", mPhysicalA= ddressBits)); - // - // Generate PAE page table for the first 4GB memory space - // - Pages =3D Gen4GPageTable (FALSE); =20 // - // Set IA32_PG_PMNT bit to mask this entry + // Generate initial SMM page table // - PTEntry =3D (UINT64 *)(UINTN)Pages; - for (Index =3D 0; Index < 4; Index++) { - PTEntry[Index] |=3D IA32_PG_PMNT; - } + PhysicalAddressBits =3D mCpuSmmRestrictedMemoryAccess ? mPhysicalAddress= Bits : 32; + PageTable =3D GenSmmPageTable (mPagingMode, PhysicalAddressBit= s); =20 - // - // Fill Page-Table-Level4 (PML4) entry - // - Pml4Entry =3D (UINT64 *)AllocatePageTableMemory (1); - ASSERT (Pml4Entry !=3D NULL); - *Pml4Entry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; - ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry)); + if (m5LevelPagingNeeded) { + Pml5Entry =3D (UINT64 *)PageTable; + SetSubEntriesNum (Pml5Entry, 1); + Pml4Entry =3D (UINT64 *)((*Pml5Entry) & ~mAddressEncMask & gPhyMask); + } else { + Pml4Entry =3D (UINT64 *)PageTable; + } =20 // - // Set sub-entries number + // Set IA32_PG_PMNT bit to mask first 4 Pml3Entry entry // - SetSubEntriesNum (Pml4Entry, 3); - PTEntry =3D Pml4Entry; - - if (m5LevelPagingNeeded) { - // - // Fill PML5 entry - // - Pml5Entry =3D (UINT64 *)AllocatePageTableMemory (1); - ASSERT (Pml5Entry !=3D NULL); - *Pml5Entry =3D (UINTN)Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BIT= S; - ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry)); - // - // Set sub-entries number - // - SetSubEntriesNum (Pml5Entry, 1); - PTEntry =3D Pml5Entry; + Pml3Entry =3D (UINT64 *)((*Pml4Entry) & ~mAddressEncMask & gPhyMask); + for (Index =3D 0; Index < 4; Index++) { + Pml3Entry[Index] |=3D IA32_PG_PMNT; } =20 - if (mCpuSmmRestrictedMemoryAccess) { + if (!mCpuSmmRestrictedMemoryAccess) { // - // When access to non-SMRAM memory is restricted, create page table - // that covers all memory space. + // Set Pml4Entry sub-entries number // - SetStaticPageTable ((UINTN)PTEntry, mPhysicalAddressBits); - } else { + SetSubEntriesNum (Pml4Entry, 3); + // // Add pages to page pool // @@ -466,7 +294,7 @@ SmmInitPageTable ( // // Return the address of PML4/PML5 (to set CR3) // - return (UINT32)(UINTN)PTEntry; + return (UINT32)PageTable; } =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/Pi= SmmCpuDxeSmm/X64/SmmProfileArch.c index cb7a691745..0805b2e780 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c @@ -35,26 +35,11 @@ InitSmmS3Cr3 ( VOID ) { - EFI_PHYSICAL_ADDRESS Pages; - UINT64 *PTEntry; - - // - // Generate PAE page table for the first 4GB memory space - // - Pages =3D Gen4GPageTable (FALSE); - - // - // Fill Page-Table-Level4 (PML4) entry - // - PTEntry =3D (UINT64 *)AllocatePageTableMemory (1); - ASSERT (PTEntry !=3D NULL); - *PTEntry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; - ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); - // + // Generate level4 page table for the first 4GB memory space // Return the address of PML4 (to set CR3) // - mSmmS3ResumeState->SmmS3Cr3 =3D (UINT32)(UINTN)PTEntry; + mSmmS3ResumeState->SmmS3Cr3 =3D (UINT32)GenSmmPageTable (Paging4Level, 3= 2); =20 return; } --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102881): https://edk2.groups.io/g/devel/message/102881 Mute This Topic: https://groups.io/mt/98215428/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102882+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102882+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289780; cv=none; d=zohomail.com; s=zohoarc; b=OmgiXnERUV13F0yBFuL5+z2t2DdFK19tWCGlu6V0d+dUrARRIGWzEFHSJHAZ6yEfx2TAc/kwGPvuqg+Tmw0GqSoz1/SGHoUxarLmCT1VZhp+Xx3YRywztQDIwCshLFM/fyhlbEv3pNI9DC5iONMtgNsJfclLoiXsk6ZxV6F6zts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289780; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3bcvuSXc2B4QIkA9jrohAFM4EBRL0ZUKFPm+a82PRa4=; b=EainpwnrgjmEKRSq6M8rTRQ6GIIzfnyvhu5En2BKNcwBcA7zX1S2ZhDNAIiyQIUpl+ixs1EcX7nx4MjzSuLood136qRWWP/xWsoN0SffE5aXwpkvVjbFJ+CUaidfItkvMMAKw1JaXG1NDlxOpcddPPal8FGsMyRwa40vp7+/RKM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102882+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1681289780238666.9469738012621; Wed, 12 Apr 2023 01:56:20 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jaVMYY1788612xnW5oXMq3t2; Wed, 12 Apr 2023 01:56:19 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.38106.1681289773082554342 for ; Wed, 12 Apr 2023 01:56:19 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126877" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126877" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262115" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262115" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:13 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 7/8] UefiCpuPkg: Refinement to code about updating smm page table Date: Wed, 12 Apr 2023 16:53:42 +0800 Message-Id: <20230412085343.1077-8-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: UhUyhRxbvXPbK7prcSSD9AgHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289779; bh=hQDrpGkAKpLMHO30VYFXZlpPgn616jImGO8ZWAkHJko=; h=Cc:Date:From:Reply-To:Subject:To; b=lC0jgXJZ30VdjsLuIcmlM+BA5OPOJ+3Nv3n6SU7NBCDaiwkWBOwbsi084MyzYVPeB8H jPBg/5vO0PsAB0uNOoyBfIeXNkkAMKkira9TmAP/gJkExpXmPEyf41RiJKak/ci1MJkMK VoUJQNH+cRicP5VRxmEKBWsQD1dh7HfHxRc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289780645100025 Content-Type: text/plain; charset="utf-8" This commit is code refinement to current smm runtime pagetable update code. In InitPaging() function, sort mProtectionMemRange or mSmmCpuSmramRanges at first. If PcdCpuSmmProfileEnable is TRUE, use ConvertMemoryPageAttributes() API to map the range in mProtectionMemRange to the attrbute recorded in the attribute field of mProtectionMemRange, map the range outside mProtectionMemRange as non-present. If PcdCpuSmmProfileEnable is FALSE, set the ranges not in mSmmCpuSmramRanges as NX. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 37 +++++++++++++++++++++++++= ++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 348 +++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++--------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- 2 files changed, 162 insertions(+), 223 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index b72c883fc5..7603076bda 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -713,6 +713,43 @@ SmmBlockingStartupThisAp ( IN OUT VOID *ProcArguments OPTIONAL ); =20 +/** + This function modifies the page attributes for the memory region specifi= ed by BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + Caller should make sure BaseAddress and Length is at page boundary. + + @param[in] PageTableBase The page table base. + @param[in] BaseAddress The physical address that is the start add= ress of a memory region. + @param[in] Length The size in bytes of the memory region. + @param[in] Attributes The bit mask of attributes to modify for t= he memory region. + @param[in] IsSet TRUE means to set attributes. FALSE means = to clear attributes. + @param[out] IsModified TRUE means page table modified. FALSE mean= s page table not modified. + + @retval RETURN_SUCCESS The attributes were modified for the me= mory region. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource = range specified by + BaseAddress and Length cannot be modifi= ed. + @retval RETURN_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combina= tion of attributes that + cannot be set together. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources t= o modify the attributes of + the memory resource range. + @retval RETURN_UNSUPPORTED The processor does not support one or m= ore bytes of the memory + resource range specified by BaseAddress= and Length. + The bit mask of attributes is not suppo= rt for the memory resource + range specified by BaseAddress and Leng= th. +**/ +RETURN_STATUS +ConvertMemoryPageAttributes ( + IN UINTN PageTableBase, + IN PAGING_MODE PagingMode, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes, + IN BOOLEAN IsSet, + OUT BOOLEAN *IsModified OPTIONAL + ); + /** This function sets the attributes for the memory region specified by Bas= eAddress and Length from their current attributes to the attributes specified by Attr= ibutes. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index 1b0b6673e1..fabdbb4186 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -546,259 +546,161 @@ InitProtectedMemRange ( } =20 /** - Update page table according to protected memory ranges and the 4KB-page = mapped memory ranges. + Function to compare 2 MEMORY_PROTECTION_RANGE based on range base. + + @param[in] Buffer1 pointer to Device Path poiner to compare + @param[in] Buffer2 pointer to second DevicePath pointer to co= mpare =20 + @retval 0 Buffer1 equal to Buffer2 + @retval <0 Buffer1 is less than Buffer2 + @retval >0 Buffer1 is greater than Buffer2 **/ -VOID -InitPaging ( - VOID +INTN +EFIAPI +ProtectionRangeCompare ( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 ) { - UINT64 Pml5Entry; - UINT64 Pml4Entry; - UINT64 *Pml5; - UINT64 *Pml4; - UINT64 *Pdpt; - UINT64 *Pd; - UINT64 *Pt; - UINTN Address; - UINTN Pml5Index; - UINTN Pml4Index; - UINTN PdptIndex; - UINTN PdIndex; - UINTN PtIndex; - UINTN NumberOfPdptEntries; - UINTN NumberOfPml4Entries; - UINTN NumberOfPml5Entries; - UINTN SizeOfMemorySpace; - BOOLEAN Nx; - IA32_CR4 Cr4; - BOOLEAN Enable5LevelPaging; + if (((MEMORY_PROTECTION_RANGE *)Buffer1)->Range.Base > ((MEMORY_PROTECTI= ON_RANGE *)Buffer2)->Range.Base) { + return 1; + } else if (((MEMORY_PROTECTION_RANGE *)Buffer1)->Range.Base < ((MEMORY_P= ROTECTION_RANGE *)Buffer2)->Range.Base) { + return -1; + } =20 - Cr4.UintN =3D AsmReadCr4 (); - Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); + return 0; +} =20 - if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { - if (!Enable5LevelPaging) { - Pml5Entry =3D (UINTN)mSmmProfileCr3 | IA32_PG_P; - Pml5 =3D &Pml5Entry; - } else { - Pml5 =3D (UINT64 *)(UINTN)mSmmProfileCr3; - } +/** + Function to compare 2 EFI_SMRAM_DESCRIPTOR based on CpuStart. =20 - SizeOfMemorySpace =3D HighBitSet64 (gPhyMask) + 1; - ASSERT (SizeOfMemorySpace <=3D 52); + @param[in] Buffer1 pointer to Device Path poiner to compare + @param[in] Buffer2 pointer to second DevicePath pointer to co= mpare =20 - // - // Calculate the table entries of PML5E, PML4E and PDPTE. - // - NumberOfPml5Entries =3D 1; - if (SizeOfMemorySpace > 48) { - if (Enable5LevelPaging) { - NumberOfPml5Entries =3D (UINTN)LShiftU64 (1, SizeOfMemorySpace - 4= 8); - } + @retval 0 Buffer1 equal to Buffer2 + @retval <0 Buffer1 is less than Buffer2 + @retval >0 Buffer1 is greater than Buffer2 +**/ +INTN +EFIAPI +CpuSmramRangeCompare ( + IN CONST VOID *Buffer1, + IN CONST VOID *Buffer2 + ) +{ + if (((EFI_SMRAM_DESCRIPTOR *)Buffer1)->CpuStart > ((EFI_SMRAM_DESCRIPTOR= *)Buffer2)->CpuStart) { + return 1; + } else if (((EFI_SMRAM_DESCRIPTOR *)Buffer1)->CpuStart < ((EFI_SMRAM_DES= CRIPTOR *)Buffer2)->CpuStart) { + return -1; + } =20 - SizeOfMemorySpace =3D 48; - } + return 0; +} =20 - NumberOfPml4Entries =3D 1; - if (SizeOfMemorySpace > 39) { - NumberOfPml4Entries =3D (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39); - SizeOfMemorySpace =3D 39; - } +/** + Update page table according to protected memory ranges and the 4KB-page = mapped memory ranges. =20 - NumberOfPdptEntries =3D 1; - ASSERT (SizeOfMemorySpace > 30); - NumberOfPdptEntries =3D (UINTN)LShiftU64 (1, SizeOfMemorySpace - 30); +**/ +VOID +InitPaging ( + VOID + ) +{ + RETURN_STATUS Status; + UINTN Index; + UINTN PageTable; + UINT64 Base; + UINT64 Length; + UINT64 Limit; + UINT64 PreviousAddress; + UINT64 MemoryAttrMask; + VOID *Buffer; + + PageTable =3D AsmReadCr3 (); + if (sizeof (UINTN) =3D=3D sizeof (UINT32)) { + Limit =3D BASE_4GB; } else { - Pml4Entry =3D (UINTN)mSmmProfileCr3 | IA32_PG_P; - Pml4 =3D &Pml4Entry; - Pml5Entry =3D (UINTN)Pml4 | IA32_PG_P; - Pml5 =3D &Pml5Entry; - NumberOfPml5Entries =3D 1; - NumberOfPml4Entries =3D 1; - NumberOfPdptEntries =3D 4; + Limit =3D (IsRestrictedMemoryAccess ()) ? LShiftU64 (1, mPhysicalAddre= ssBits) : BASE_4GB; } =20 // - // Go through page table and change 2MB-page into 4KB-page. + // [0, 4k] may be non-present. // - for (Pml5Index =3D 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) { - if ((Pml5[Pml5Index] & IA32_PG_P) =3D=3D 0) { - // - // If PML5 entry does not exist, skip it - // - continue; - } + PreviousAddress =3D ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BI= T1) !=3D 0) ? BASE_4KB : 0; =20 - Pml4 =3D (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK); - for (Pml4Index =3D 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { - if ((Pml4[Pml4Index] & IA32_PG_P) =3D=3D 0) { - // - // If PML4 entry does not exist, skip it - // - continue; + DEBUG ((DEBUG_INFO, "Patch page table start ...\n")); + if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { + // + // Sort the mProtectionMemRange + // + Buffer =3D AllocateZeroPool (sizeof (MEMORY_PROTECTION_RANGE)); + ASSERT (Buffer !=3D NULL); + QuickSort (mProtectionMemRange, mProtectionMemRangeCount, sizeof (MEMO= RY_PROTECTION_RANGE), (BASE_SORT_COMPARE)ProtectionRangeCompare, Buffer); + for (Index =3D 0; Index < mProtectionMemRangeCount; Index++) { + MemoryAttrMask =3D 0; + if ((mProtectionMemRange[Index].Nx =3D=3D 1) && mXdSupported) { + MemoryAttrMask |=3D EFI_MEMORY_XP; } =20 - Pdpt =3D (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYS= ICAL_ADDRESS_MASK); - for (PdptIndex =3D 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, = Pdpt++) { - if ((*Pdpt & IA32_PG_P) =3D=3D 0) { - // - // If PDPT entry does not exist, skip it - // - continue; - } - - if ((*Pdpt & IA32_PG_PS) !=3D 0) { - // - // This is 1G entry, skip it - // - continue; - } - - Pd =3D (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRE= SS_MASK); - if (Pd =3D=3D 0) { - continue; - } - - for (PdIndex =3D 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, = Pd++) { - if ((*Pd & IA32_PG_P) =3D=3D 0) { - // - // If PD entry does not exist, skip it - // - continue; - } - - Address =3D (UINTN)LShiftU64 ( - LShiftU64 ( - LShiftU64 ((Pml5Index << 9) + Pml4Index, 9)= + PdptIndex, - 9 - ) + PdIndex, - 21 - ); - - // - // If it is 2M page, check IsAddressSplit() - // - if (((*Pd & IA32_PG_PS) !=3D 0) && IsAddressSplit (Address)) { - // - // Based on current page table, create 4KB page table for spli= t area. - // - ASSERT (Address =3D=3D (*Pd & PHYSICAL_ADDRESS_MASK)); - - Pt =3D AllocatePageTableMemory (1); - ASSERT (Pt !=3D NULL); + if (mProtectionMemRange[Index].Present =3D=3D 0) { + MemoryAttrMask =3D EFI_MEMORY_RP; + } =20 - // Split it - for (PtIndex =3D 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex= ++) { - Pt[PtIndex] =3D Address + ((PtIndex << 12) | mAddressEncMask= | PAGE_ATTRIBUTE_BITS); - } // end for PT + Base =3D mProtectionMemRange[Index].Range.Base; + Length =3D mProtectionMemRange[Index].Range.Top - Base; + if (MemoryAttrMask !=3D 0) { + Status =3D ConvertMemoryPageAttributes (PageTable, mPagingMode, Ba= se, Length, MemoryAttrMask, TRUE, NULL); + ASSERT_RETURN_ERROR (Status); + } =20 - *Pd =3D (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_B= ITS; - } // end if IsAddressSplit - } // end for PD - } // end for PDPT - } // end for PML4 - } // end for PML5 + if (Base > PreviousAddress) { + // + // Mark the ranges not in mProtectionMemRange as non-present. + // + MemoryAttrMask =3D EFI_MEMORY_RP; + Status =3D ConvertMemoryPageAttributes (PageTable, mPaging= Mode, PreviousAddress, Base - PreviousAddress, MemoryAttrMask, TRUE, NULL); + ASSERT_RETURN_ERROR (Status); + } =20 - // - // Go through page table and set several page table entries to absent or= execute-disable. - // - DEBUG ((DEBUG_INFO, "Patch page table start ...\n")); - for (Pml5Index =3D 0; Pml5Index < NumberOfPml5Entries; Pml5Index++) { - if ((Pml5[Pml5Index] & IA32_PG_P) =3D=3D 0) { - // - // If PML5 entry does not exist, skip it - // - continue; + PreviousAddress =3D Base + Length; } =20 - Pml4 =3D (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK); - for (Pml4Index =3D 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { - if ((Pml4[Pml4Index] & IA32_PG_P) =3D=3D 0) { + // + // This assignment is for setting the last remaining range + // + MemoryAttrMask =3D EFI_MEMORY_RP; + } else { + // + // Sort the mSmmCpuSmramRanges + // + Buffer =3D AllocateZeroPool (sizeof (EFI_SMRAM_DESCRIPTOR)); + ASSERT (Buffer !=3D NULL); + QuickSort (mSmmCpuSmramRanges, mSmmCpuSmramRangeCount, sizeof (EFI_SMR= AM_DESCRIPTOR), (BASE_SORT_COMPARE)CpuSmramRangeCompare, Buffer); + MemoryAttrMask =3D EFI_MEMORY_XP; + for (Index =3D 0; Index < mSmmCpuSmramRangeCount; Index++) { + Base =3D mSmmCpuSmramRanges[Index].CpuStart; + if ((Base > PreviousAddress) && mXdSupported) { // - // If PML4 entry does not exist, skip it + // Mark the ranges not in mSmmCpuSmramRanges as NX. // - continue; + Status =3D ConvertMemoryPageAttributes (PageTable, mPagingMode, Pr= eviousAddress, Base - PreviousAddress, MemoryAttrMask, TRUE, NULL); + ASSERT_RETURN_ERROR (Status); } =20 - Pdpt =3D (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYS= ICAL_ADDRESS_MASK); - for (PdptIndex =3D 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, = Pdpt++) { - if ((*Pdpt & IA32_PG_P) =3D=3D 0) { - // - // If PDPT entry does not exist, skip it - // - continue; - } - - if ((*Pdpt & IA32_PG_PS) !=3D 0) { - // - // This is 1G entry, set NX bit and skip it - // - if (mXdSupported) { - *Pdpt =3D *Pdpt | IA32_PG_NX; - } - - continue; - } + PreviousAddress =3D mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmra= mRanges[Index].PhysicalSize; + } + } =20 - Pd =3D (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRE= SS_MASK); - if (Pd =3D=3D 0) { - continue; - } + FreePool (Buffer); =20 - for (PdIndex =3D 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, = Pd++) { - if ((*Pd & IA32_PG_P) =3D=3D 0) { - // - // If PD entry does not exist, skip it - // - continue; - } - - Address =3D (UINTN)LShiftU64 ( - LShiftU64 ( - LShiftU64 ((Pml5Index << 9) + Pml4Index, 9)= + PdptIndex, - 9 - ) + PdIndex, - 21 - ); - - if ((*Pd & IA32_PG_PS) !=3D 0) { - // 2MB page - - if (!IsAddressValid (Address, &Nx)) { - // - // Patch to remove Present flag and RW flag - // - *Pd =3D *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); - } - - if (Nx && mXdSupported) { - *Pd =3D *Pd | IA32_PG_NX; - } - } else { - // 4KB page - Pt =3D (UINT64 *)(UINTN)(*Pd & ~mAddressEncMask & PHYSICAL_ADD= RESS_MASK); - if (Pt =3D=3D 0) { - continue; - } - - for (PtIndex =3D 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex= ++, Pt++) { - if (!IsAddressValid (Address, &Nx)) { - *Pt =3D *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); - } - - if (Nx && mXdSupported) { - *Pt =3D *Pt | IA32_PG_NX; - } - - Address +=3D SIZE_4KB; - } // end for PT - } // end if PS - } // end for PD - } // end for PDPT - } // end for PML4 - } // end for PML5 + if (PreviousAddress < Limit) { + // + // Set the last remaining range to EFI_MEMORY_RP/EFI_MEMORY_XP. + // This path applies to both SmmProfile enable/disable case. + // + Status =3D ConvertMemoryPageAttributes (PageTable, mPagingMode, Previo= usAddress, Limit - PreviousAddress, MemoryAttrMask, TRUE, NULL); + ASSERT_RETURN_ERROR (Status); + } =20 // // Flush TLB --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102882): https://edk2.groups.io/g/devel/message/102882 Mute This Topic: https://groups.io/mt/98215429/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 17:57:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102883+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102883+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1681289781; cv=none; d=zohomail.com; s=zohoarc; b=D9lL8tqVbqrrIlb9FKcRER4GJvDsV8EWaBtAu43JIdODCE9jpj52lp1HFq4CW06g9KmDOOlLKWgeKVKbMw78jzdFybRVKtqBYbNKTA1nSOxXJ+rH4b+h0mAe8mIL/yotvoMxBmAX4u1NdVKB4Qx8KBPztSzKiyAPOy8SaTh0fcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681289781; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=IAh+W+7vgtYkJyWWi9EXFJWXtJBH8w4p7iW4KMNQtRo=; b=A9RTW7Xh/b+9BYR3P9siGD8AuEPSnLVR9AvjvOate3bZtiRT6KiEgRqkjaXz8AX4XnafJPtsnev0EVt923+fFkHBrdTxxXZMhGrAAi6jQV6MFwjnzaSubIgISd6o+d/k690LY4GxK2YrNHBsBaSQu9wBsDasJfMFqScXxqDTOZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102883+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1681289781563518.5517711077507; Wed, 12 Apr 2023 01:56:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KboFYY1788612xQCfhPYTL28; Wed, 12 Apr 2023 01:56:21 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.38106.1681289773082554342 for ; Wed, 12 Apr 2023 01:56:20 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="430126915" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="430126915" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="666262119" X-IronPort-AV: E=Sophos;i="5.98,338,1673942400"; d="scan'208";a="666262119" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2023 01:56:16 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V2 8/8] UefiCpuPkg/PiSmmCpuDxeSmm: Remove unnecessary function Date: Wed, 12 Apr 2023 16:53:43 +0800 Message-Id: <20230412085343.1077-9-dun.tan@intel.com> In-Reply-To: <20230412085343.1077-1-dun.tan@intel.com> References: <20230412085343.1077-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: Fk8HN7ioDWP0IECREJnthM4Qx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681289781; bh=7C6OH7V5e8TJuLXwlNu0nQlEyDRnJ5QxJensNKb4vS0=; h=Cc:Date:From:Reply-To:Subject:To; b=Awlt0S+4M82K326/32P/iK0R9SNo3sDMR4QCA0oeSJcBA87K9E0jHkpmZYz+GDxCeys d7spcPMbX3/0vm+4j2ma6LVr0D/QPCBM2D7ypexpFjMNAm71XtzKOa6vcwSslUdpmJzZa D4WDqRdB0pZfzyk3v8wEzK/PGSkHqTnbXYI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681289783487100030 Content-Type: text/plain; charset="utf-8" Remove unnecessary function SetNotPresentPage(). We can directly use ConvertMemoryPageAttributes to set a range to non-present. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 8 ++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 16 ---------------- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 22 ------------------= ---- 3 files changed, 6 insertions(+), 40 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index c0e368ea94..5316ba7b5a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1074,10 +1074,14 @@ PiCpuSmmEntry ( mSmmShadowStackSize ); if (FeaturePcdGet (PcdCpuSmmStackGuard)) { - SetNotPresentPage ( + ConvertMemoryPageAttributes ( Cr3, + mPagingMode, (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_= TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index, - EFI_PAGES_TO_SIZE (1) + EFI_PAGES_TO_SIZE (1), + EFI_MEMORY_RP, + TRUE, + NULL ); } } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 7603076bda..470d566ef1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1235,22 +1235,6 @@ SetShadowStack ( IN UINT64 Length ); =20 -/** - Set not present memory. - - @param[in] Cr3 The page table base address. - @param[in] BaseAddress The physical address that is the start addr= ess of a memory region. - @param[in] Length The size in bytes of the memory region. - - @retval EFI_SUCCESS The not present memory is set. -**/ -EFI_STATUS -SetNotPresentPage ( - IN UINTN Cr3, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ); - /** Initialize the shadow stack related data structure. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 5b970157c6..968a15919f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -676,28 +676,6 @@ SetShadowStack ( return Status; } =20 -/** - Set not present memory. - - @param[in] Cr3 The page table base address. - @param[in] BaseAddress The physical address that is the start addr= ess of a memory region. - @param[in] Length The size in bytes of the memory region. - - @retval EFI_SUCCESS The not present memory is set. -**/ -EFI_STATUS -SetNotPresentPage ( - IN UINTN Cr3, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length - ) -{ - EFI_STATUS Status; - - Status =3D SmmSetMemoryAttributesEx (Cr3, mPagingMode, BaseAddress, Leng= th, EFI_MEMORY_RP); - return Status; -} - /** Retrieves a pointer to the system configuration table from the SMM Syste= m Table based on a specified GUID. --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102883): https://edk2.groups.io/g/devel/message/102883 Mute This Topic: https://groups.io/mt/98215432/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-