From nobody Tue May 14 16:34:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102694+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102694+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680871667; cv=none; d=zohomail.com; s=zohoarc; b=MLjaYsYRdVCgZcABv/p4Lw6P2H3mGz5FPYQGgY4Zbgwt7qe9IayvnjFxTwTewZ6r9h16VjtDYrIgK9ZeIpvbI6j77/Ol+E+llB2QVOb6Bd20DOK4/IrO2Y6GJ53txSvlNFE3oCgZMUdk0A5SpbMF+H+dfdBY3qnUqVgbdSRjVC0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680871667; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=czETrHWOy94Pm4kmXYiO70jtqQ6OwNR0Ct6imfDxrxQ=; b=F7Ev/cmKiWhqVWO+O/Cow55S7eBdeAUJzWiEN1zF0eVkV0pXn32lO2LNWza8uFcFY0ziaxl4cCbgeDt24fgKMGWmyFbA0+LTSi4rGvQvBu2m9NRhwnZdU7MYLyvcSh33JJuzIx8CT0kc7YVjdtcOTpe9Jbo/vhpI6fD9XIu54g0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102694+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680871667824862.9101265495808; Fri, 7 Apr 2023 05:47:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id TpzvYY1788612xkObDg90QIu; Fri, 07 Apr 2023 05:47:47 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web11.6909.1680871666149173397 for ; Fri, 07 Apr 2023 05:47:46 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 4C05E260FDE; Fri, 7 Apr 2023 14:47:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bR2QOLL4lZgp; Fri, 7 Apr 2023 14:47:40 +0200 (CEST) X-Received: from applejack.lan (83.11.21.111.ipv4.supernova.orange.pl [83.11.21.111]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id 5282326069C; Fri, 7 Apr 2023 14:47:38 +0200 (CEST) From: "Marcin Juszkiewicz" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Rebecca Cran , Marcin Juszkiewicz Subject: [edk2-devel] [PATCH v3] add ArmCpuInfo EFI application Date: Fri, 7 Apr 2023 14:47:31 +0200 Message-Id: <20230407124731.121236-1-marcin.juszkiewicz@linaro.org> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org X-Gm-Message-State: wM7C6SvJfvtMkJgP0aSpnwlSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680871667; bh=Xe0frf7iQ86ekl08X6I54PlSDcKKkn6GPt0l3Rip8Wg=; h=Cc:Date:From:Reply-To:Subject:To; b=g+c7HOS+xiJsuhWNgQdrnc2GLgvP0l9NO7/cHXbariZKSUxj9eEEr3g+exe8sBD9/nZ hQ4Yem3Ii9L/QLwlMoqVxcPzCj3/hHLNnJ7SlZXGLQUVifkqLE6Mfm/6UcaHuwkwTR0wW dpnT1OcWRlG2nbg6p62xBEfXwTeGaM+Fd/M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680871668421100003 Content-Type: text/plain; charset="utf-8" App goes through ID_AA64*_EL1 system registers and decode their values. Signed-off-by: Marcin Juszkiewicz --- ArmPkg/ArmPkg.dsc | 1 + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 38 + ArmPkg/Application/ArmCpuInfo/readargs.h | 12 + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2317 ++++++++++++++++++++ ArmPkg/Application/ArmCpuInfo/readregs.s | 49 + 5 files changed, 2417 insertions(+) diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc index 3fb95d1951a9..6b938ce8b671 100644 --- a/ArmPkg/ArmPkg.dsc +++ b/ArmPkg/ArmPkg.dsc @@ -166,6 +166,7 @@ [Components.AARCH64] ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf =20 [Components.AARCH64, Components.ARM] ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf b/ArmPkg/Applicat= ion/ArmCpuInfo/ArmCpuInfo.inf new file mode 100644 index 000000000000..158f86a4740c --- /dev/null +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf @@ -0,0 +1,38 @@ +## @file +# +# Attempt to have AArch64 cpu information. +# +# Based on HelloWorld: +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved. +# Copyright (c) 2023 Marcin Juszkiewicz +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmCpuInfo + FILE_GUID =3D b3134491-6502-4faf-a9da-007184e32163 + MODULE_TYPE =3D UEFI_APPLICATION + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UefiMain + +# +# This flag specifies whether HII resource section is generated into PE i= mage. +# + UEFI_HII_RESOURCE_SECTION =3D TRUE + +[Sources] + ArmCpuInfo.c + readregs.s + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + UefiApplicationEntryPoint + UefiLib diff --git a/ArmPkg/Application/ArmCpuInfo/readargs.h b/ArmPkg/Application/= ArmCpuInfo/readargs.h new file mode 100644 index 000000000000..eaa52cf16145 --- /dev/null +++ b/ArmPkg/Application/ArmCpuInfo/readargs.h @@ -0,0 +1,12 @@ +UINT64 read_aa64pfr0_el1(void); +UINT64 read_aa64pfr1_el1(void); +UINT64 read_aa64dfr0_el1(void); +UINT64 read_aa64dfr1_el1(void); +UINT64 read_aa64isar0_el1(void); +UINT64 read_aa64isar1_el1(void); +UINT64 read_aa64isar2_el1(void); +UINT64 read_aa64mmfr0_el1(void); +UINT64 read_aa64mmfr1_el1(void); +UINT64 read_aa64mmfr2_el1(void); +UINT64 read_aa64smfr0_el1(void); +UINT64 read_aa64zfr0_el1(void); diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c b/ArmPkg/Applicatio= n/ArmCpuInfo/ArmCpuInfo.c new file mode 100644 index 000000000000..6c31ad4dbcb9 --- /dev/null +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c @@ -0,0 +1,2317 @@ +/** @file + + Copyright (c) 2023 Marcin Juszkiewicz + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include "readargs.h" + +void +print_text ( + const char *field, + const char *bits, + const char *value, + const char *description + ) +{ + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, bits, value, description= ); +} + +void +print_values ( + const char *field, + const char *bits, + const int value, + const char *description + ) +{ + STATIC CONST CHAR8 binaries[][5] =3D { + "0000", "0001", "0010", "0011", + "0100", "0101", "0110", "0111","1000", "1001", "1010", "1011", + "1100", "1101", "1110", "1111" + }; + + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, bits, binaries[value & 0= xf], description); +} + +void +print_spacer ( + void + ) +{ + AsciiPrint ("------------------|-------|-------|------------------------= ----------------------\n"); +} + +void +handle_aa64mmfr0_el1 ( + const UINT64 aa64mmfr0_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR0_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D aa64mmfr0_el1 & 0xf; + switch (value) { + case 0b0000: + description =3D "32 bits (4GB) of physical address range supported.= "; + break; + case 0b0001: + description =3D "36 bits (64GB) of physical address range supported= ."; + break; + case 0b0010: + description =3D "40 bits (1TB) of physical address range supported.= "; + break; + case 0b0011: + description =3D "42 bits (4TB) of physical address range supported.= "; + break; + case 0b0100: + description =3D "44 bits (16TB) of physical address range supported= ."; + break; + case 0b0101: + description =3D "48 bits (256TB) of physical address range supporte= d."; + break; + case 0b0110: + description =3D "52 bits (4PB) of physical address range supported.= "; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + if (value =3D=3D 0b0110) { + print_text ("", "", "", "FEAT_LPA implemented."); + } + + bits =3D "7:4 "; + value =3D (aa64mmfr0_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "ASID: 8 bits"; + break; + case 0b0010: + description =3D "ASID: 16 bits"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64mmfr0_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "No mixed-endian support."; + break; + case 0b0001: + description =3D "Mixed-endian support."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // only valid for BigEnd !=3D 0b0000 + if (((aa64mmfr0_el1 >> 8) & 0xf) !=3D 0b0000 ) { + if (((aa64mmfr0_el1 >> 16) & 0xf) =3D=3D 0b0000 ) { + print_values ("ID_AA64MMFR0_EL1", "19:16", 0b0000, "No mixed-endian = support at EL0."); + } + + if (((aa64mmfr0_el1 >> 16) & 0xf) =3D=3D 0b0001 ) { + print_values ("ID_AA64MMFR0_EL1", "19:16", 0b0001, "Mixed-endian sup= port at EL0."); + } + } + + bits =3D "15:12"; + value =3D (aa64mmfr0_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "No support for a distinction between Secure and Non= -Secure Memory."; + break; + case 0b0001: + description =3D "Supports a distinction between Secure and Non-Secur= e Memory."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "31:28"; + value =3D (aa64mmfr0_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D " 4KB granule supported."; + break; + case 0b1111: + description =3D " 4KB granule not supported."; + break; + case 0b0001: // add FEAT_LPA2 check + description =3D " 4KB granule supported for 52-bit address."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64mmfr0_el1 >> 40) & 0xf; + switch (value) { + case 0b0001: + description =3D " 4KB granule not supported at stage 2."; + break; + case 0b0010: + description =3D " 4KB granule supported at stage 2."; + break; + case 0b0011: + description =3D " 4KB granule supported at stage 2 for 52-bit addres= s."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64mmfr0_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "16KB granule not supported."; + break; + case 0b0001: + description =3D "16KB granule supported."; + break; + case 0b0010: // add FEAT_LPA2 check + description =3D "16KB granule supported for 52-bit address."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64mmfr0_el1 >> 32) & 0xf; + switch (value) { + case 0b0001: + description =3D "16KB granule not supported at stage 2."; + break; + case 0b0010: + description =3D "16KB granule supported at stage 2."; + break; + case 0b0011: + description =3D "16KB granule supported at stage 2 for 52-bit addres= s."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "27:24"; + value =3D (aa64mmfr0_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "64KB granule supported."; + break; + case 0b1111: + description =3D "64KB granule not supported."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64mmfr0_el1 >> 36) & 0xf; + switch (value) { + case 0b0001: + description =3D "64KB granule not supported at stage 2."; + break; + case 0b0010: + description =3D "64KB granule supported at stage 2."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "47:44"; + value =3D (aa64mmfr0_el1 >> 44) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_ExS not implemented."; + break; + case 0b0001: + description =3D "FEAT_ExS implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 55:48 reserved + + bits =3D "59:56"; + value =3D (aa64mmfr0_el1 >> 56) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_FGT not implemented."; + break; + case 0b0001: + description =3D "FEAT_FGT implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "63:60"; + value =3D (aa64mmfr0_el1 >> 60) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_ECV not implemented."; + break; + case 0b0001: + description =3D "FEAT_ECV implemented."; + break; + case 0b0010: + description =3D "FEAT_ECV implemented with extras."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); +} + +void +handle_aa64mmfr1_el1 ( + const UINT64 aa64mmfr1_el1, + const UINT64 aa64pfr0_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR1_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D aa64mmfr1_el1 & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_HAFDBS not implemented."; + break; + case 0b0001: + description =3D "FEAT_HAFDBS implemented without dirty status suppor= t."; + break; + case 0b0010: + description =3D "FEAT_HAFDBS implemented with dirty status support."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64mmfr1_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_VMID16 not implemented."; + break; + case 0b0010: + description =3D "FEAT_VMID16 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64mmfr1_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_VHE not implemented."; + break; + case 0b0001: + description =3D "FEAT_VHE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "15:12"; + value =3D (aa64mmfr1_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_HPDS not implemented."; + break; + case 0b0001: + description =3D "FEAT_HPDS implemented."; + break; + case 0b0010: + description =3D "FEAT_HPDS2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "19:16"; + value =3D (aa64mmfr1_el1 >> 16) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LOR not implemented."; + break; + case 0b0001: + description =3D "FEAT_LOR implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64mmfr1_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_PAN not implemented."; + break; + case 0b0001: + description =3D "FEAT_PAN implemented."; + break; + case 0b0010: + description =3D "FEAT_PAN2 implemented."; + break; + case 0b0011: + description =3D "FEAT_PAN3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // when FEAT_RAS implemented + if ((((aa64pfr0_el1 >> 28) & 0xf) =3D=3D 0b0001) || + (((aa64pfr0_el1 >> 28) & 0xf) =3D=3D 0b0010)) + { + if (((aa64mmfr1_el1 >> 24) & 0xf) =3D=3D 0b0000 ) { + print_values ("ID_AA64MMFR1_EL1", "27:24", 0b0000, "The PE never gen= erates an SError interrupt due to"); + print_text ("", "", "", "an External abort on a speculative read."); + } + + if (((aa64mmfr1_el1 >> 24) & 0xf) =3D=3D 0b0001 ) { + print_values ("ID_AA64MMFR1_EL1", "27:24", 0b0001, "The PE might gen= erate an SError interrupt due to"); + print_text ("", "", "", "an External abort on a speculative read."); + } + } + + bits =3D "31:28"; + value =3D (aa64mmfr1_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_XNX not implemented."; + break; + case 0b0001: + description =3D "FEAT_XNX implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64mmfr1_el1 >> 32) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TWED not implemented."; + break; + case 0b0001: + description =3D "FEAT_TWED implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64mmfr1_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_ETS not implemented."; + break; + case 0b0001: + description =3D "FEAT_ETS implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64mmfr1_el1 >> 40) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_HCX not implemented."; + break; + case 0b0001: + description =3D "FEAT_HCX implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "47:44"; + value =3D (aa64mmfr1_el1 >> 44) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_AFP not implemented."; + break; + case 0b0001: + description =3D "FEAT_AFP implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "51:48"; + value =3D (aa64mmfr1_el1 >> 48) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_nTLBPA not implemented."; + break; + case 0b0001: + description =3D "FEAT_nTLBPA implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "55:52"; + value =3D (aa64mmfr1_el1 >> 52) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TIDCP1 not implemented"; + break; + case 0b0001: + description =3D "FEAT_TIDCP1 implemented"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "59:56"; + value =3D (aa64mmfr1_el1 >> 56) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_CMOW not implemented."; + break; + case 0b0001: + description =3D "FEAT_CMOW implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 63:60 reserved +} + +void +handle_aa64mmfr2_el1 ( + const UINT64 aa64mmfr2_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR2_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D (aa64mmfr2_el1) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TTCNP not implemented."; + break; + case 0b0001: + description =3D "FEAT_TTCNP implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64mmfr2_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_UAO not implemented."; + break; + case 0b0001: + description =3D "FEAT_UAO implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64mmfr2_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LSMAOC not implemented."; + break; + case 0b0001: + description =3D "FEAT_LSMAOC implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "15:12"; + value =3D (aa64mmfr2_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_IESB not implemented."; + break; + case 0b0001: + description =3D "FEAT_IESB implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "19:16"; + value =3D (aa64mmfr2_el1 >> 16) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LVA not implemented."; + break; + case 0b0001: + description =3D "FEAT_LVA implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64mmfr2_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_CCIDX not implemented."; + break; + case 0b0001: + description =3D "FEAT_CCIDX implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "27:24"; + value =3D (aa64mmfr2_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_NV not implemented."; + break; + case 0b0001: + description =3D "FEAT_NV implemented."; + break; + case 0b0010: + description =3D "FEAT_NV2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "31:28"; + value =3D (aa64mmfr2_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TTST not implemented."; + break; + case 0b0001: + description =3D "FEAT_TTST implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64mmfr2_el1 >> 32) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LSE2 not implemented."; + break; + case 0b0001: + description =3D "FEAT_LSE2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64mmfr2_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_IDST not implemented."; + break; + case 0b0001: + description =3D "FEAT_IDST implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64mmfr2_el1 >> 40) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_S2FWB not implemented."; + break; + case 0b0001: + description =3D "FEAT_S2FWB implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 47:44 reserved + + bits =3D "51:48"; + value =3D (aa64mmfr2_el1 >> 48) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TTL not implemented."; + break; + case 0b0001: + description =3D "FEAT_TTL implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "55:52"; + value =3D (aa64mmfr2_el1 >> 52) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_BBM: Level 0 support for changing block size i= s supported."; + break; + case 0b0001: + description =3D "FEAT_BBM: Level 1 support for changing block size i= s supported."; + break; + case 0b0010: + description =3D "FEAT_BBM: Level 2 support for changing block size i= s supported."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "59:56"; + value =3D (aa64mmfr2_el1 >> 56) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_EVT not implemented."; + break; + case 0b0001: + description =3D "FEAT_EVT: HCR_EL2.{TOCU, TICAB, TID4} traps are sup= ported."; + break; + case 0b0010: + description =3D "FEAT_EVT: HCR_EL2.{TTLBOS, TTLSBIS, TOCU, TICAB, TI= D4} traps are supported."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "63:60"; + value =3D (aa64mmfr2_el1 >> 60) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_E0PD not implemented."; + break; + case 0b0001: + description =3D "FEAT_E0PD implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); +} + +void +handle_aa64pfr0_el1 ( + const UINT64 aa64pfr0_el1, + const UINT64 aa64pfr1_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64PFR0_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D (aa64pfr0_el1) & 0xf; + switch (value) { + case 0b0001: + description =3D "EL0 in AArch64 only"; + break; + case 0b0010: + description =3D "EL0 in AArch64 and AArch32"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64pfr0_el1 >> 4) & 0xf; + switch (value) { + case 0b0001: + description =3D "EL1 in AArch64 only"; + break; + case 0b0010: + description =3D "EL1 in AArch64 and AArch32"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64pfr0_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "EL2 not implemented."; + break; + case 0b0001: + description =3D "EL2 in AArch64 only"; + break; + case 0b0010: + description =3D "EL2 in AArch64 and AArch32"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "15:12"; + value =3D (aa64pfr0_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "EL3 not implemented."; + break; + case 0b0001: + description =3D "EL3 in AArch64 only"; + break; + case 0b0010: + description =3D "EL3 in AArch64 and AArch32"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "19:16"; + value =3D (aa64pfr0_el1 >> 16) & 0xf; + switch (value) { + case 0b0000: + description =3D "Floating-point implemented."; + break; + case 0b0001: + description =3D "Floating-point with half-precision support (FEAT_F= P16)."; + break; + case 0b1111: + description =3D "Floating-point not implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64pfr0_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "Advanced SIMD implemented."; + break; + case 0b0001: + description =3D "Advanced SIMD with half precision support (FEAT_FP= 16)."; + break; + case 0b1111: + description =3D "Advanced SIMD not implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "27:24"; + value =3D (aa64pfr0_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "System registers of GIC CPU not implemented."; + break; + case 0b0001: + description =3D "System registers to versions 3.0/4.0 of GIC CPU imp= lemented."; + break; + case 0b0011: + description =3D "System registers to versions 4.1 of GIC CPU impleme= nted."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "31:28"; + value =3D (aa64pfr0_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_RAS not implemented."; + break; + case 0b0001: + description =3D "FEAT_RAS implemented."; + break; + case 0b0010: + description =3D "FEAT_RASv1p1 implemented."; + // 0b0010 FEAT_RASv1p1 implemented and, if EL3 is implemented, FEAT_= DoubleFault implemented. + if ((((aa64pfr0_el1 >> 12) & 0xf) =3D=3D 0b0001) || + (((aa64pfr0_el1 >> 12) & 0xf) =3D=3D 0b0010)) + { + description =3D "FEAT_RASv1p1 implemented. FEAT_DoubleFault implem= ented."; + } + + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64pfr0_el1 >> 32) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SVE not implemented."; + break; + case 0b0001: + description =3D "FEAT_SVE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64pfr0_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "Secure EL2 not implemented."; + break; + case 0b0001: + description =3D "Secure EL2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64pfr0_el1 >> 40) & 0xf; + switch (value) { + case 0b0000: + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0000 ) { + description =3D "FEAT_MPAM not implemented."; + } + + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0001 ) { + description =3D "FEAT_MPAM v0.1 implemented."; + } + + break; + case 0b0001: + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0000 ) { + description =3D "FEAT_MPAM v1.0 implemented."; + } + + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0001 ) { + description =3D "FEAT_MPAM v1.1 implemented."; + } + + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "47:44"; + value =3D (aa64pfr0_el1 >> 44) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_AMU not implemented."; + break; + case 0b0001: + description =3D "FEAT_AMUv1 implemented."; + break; + case 0b0010: + description =3D "FEAT_AMUv1p1 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "51:48"; + value =3D (aa64pfr0_el1 >> 48) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_DIT not implemented."; + break; + case 0b0001: + description =3D "FEAT_DIT implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "55:52"; + value =3D (aa64pfr0_el1 >> 52) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_RME not implemented"; + break; + case 0b0001: + description =3D "FEAT_RME implemented"; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "59:56"; + value =3D (aa64pfr0_el1 >> 56) & 0xf; + switch (value) { + case 0b0000: + description =3D "no info is FEAT_CSV2 implemented."; + break; + case 0b0001: + description =3D "FEAT_CSV2 implemented."; + break; + case 0b0010: + description =3D "FEAT_CSV2_2 implemented."; + break; + case 0b0011: + description =3D "FEAT_CSV2_3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + if (value =3D=3D 0b0001) { + if (((aa64pfr1_el1 >> 32) & 0xf) =3D=3D 0b0001 ) { + print_values ("ID_AA64PRF1_EL1", "35:32", 0b0001, "FEAT_CSV2_1p1 imp= lemented."); + } + + if (((aa64pfr1_el1 >> 32) & 0xf) =3D=3D 0b0010 ) { + print_values ("ID_AA64PRF1_EL1", "35:32", 0b0010, "FEAT_CSV2_1p2 imp= lemented."); + } + } + + bits =3D "63:60"; + value =3D (aa64pfr0_el1 >> 60) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_CSV3 not implemented."; + break; + case 0b0001: + description =3D "FEAT_CSV3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); +} + +void +handle_aa64pfr1_el1 ( + const UINT64 aa64pfr1_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64PFR1_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D aa64pfr1_el1 & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_BTI not implemented."; + break; + case 0b0001: + description =3D "FEAT_BTI implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64pfr1_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SSBS not implemented."; + break; + case 0b0001: + description =3D "FEAT_SSBS implemented."; + break; + case 0b0010: + description =3D "FEAT_SSBS2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64pfr1_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_MTE not implemented."; + break; + case 0b0001: + description =3D "FEAT_MTE implemented."; + break; + case 0b0010: + description =3D "FEAT_MTE2 implemented."; + break; + case 0b0011: + description =3D "FEAT_MTE3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 15:12 is RAS_frac + // 19:16 is MPAM_frac + // 23:20 is reserved + + bits =3D "27:24"; + value =3D (aa64pfr1_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SME not implemented."; + break; + case 0b0001: + description =3D "FEAT_SME implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "31:28"; + value =3D (aa64pfr1_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_RNG_TRAP not implemented."; + break; + case 0b0001: + description =3D "FEAT_RNG_TRAP implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 35:32 is CSV2_frac + + bits =3D "39:36"; + value =3D (aa64pfr1_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_NMI not implemented."; + break; + case 0b0001: + description =3D "FEAT_NMI implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 63:40 are reserved +} + +void +handle_aa64isar0_el1 ( + const UINT64 aa64isar0_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR0_EL1"; + char *description; + char *bits; + + // 3:0 reserved + + bits =3D "7:4 "; + value =3D (aa64isar0_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_AES, FEAT_PMULL not implemented."; + break; + case 0b0001: + description =3D "FEAT_AES implemented."; + break; + case 0b0010: + description =3D "FEAT_AES and FEAT_PMULL implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64isar0_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SHA1 not implemented."; + break; + case 0b0001: + description =3D "FEAT_SHA1 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "15:12"; + value =3D (aa64isar0_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SHA256, FEAT_SHA512 not implemented."; + break; + case 0b0001: + description =3D "FEAT_SHA256 implemented."; + break; + case 0b0010: + description =3D "FEAT_SHA512 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "19:16"; + value =3D (aa64isar0_el1 >> 16) & 0xf; + switch (value) { + case 0b0000: + description =3D "CRC32 not implemented."; + break; + case 0b0001: + description =3D "CRC32 instructions implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64isar0_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LSE not implemented."; + break; + case 0b0010: + description =3D "FEAT_LSE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "27:24"; + value =3D (aa64isar0_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "TME instructions not implemented."; + break; + case 0b0001: + description =3D "TME instructions implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "31:28"; + value =3D (aa64isar0_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_RDM not implemented."; + break; + case 0b0001: + description =3D "FEAT_RDM implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64isar0_el1 >> 32) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SHA3 not implemented."; + break; + case 0b0001: + description =3D "FEAT_SHA3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64isar0_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SM3 not implemented."; + break; + case 0b0001: + description =3D "FEAT_SM3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64isar0_el1 >> 40) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SM4 not implemented."; + break; + case 0b0001: + description =3D "FEAT_SM4 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "47:44"; + value =3D (aa64isar0_el1 >> 44) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_DotProd not implemented."; + break; + case 0b0001: + description =3D "FEAT_DotProd implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "51:48"; + value =3D (aa64isar0_el1 >> 48) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_FHM not implemented."; + break; + case 0b0001: + description =3D "FEAT_FHM implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "55:52"; + value =3D (aa64isar0_el1 >> 52) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_FlagM/FEAT_FlagM2 not implemented."; + break; + case 0b0001: + description =3D "FEAT_FlagM implemented."; + break; + case 0b0010: + description =3D "FEAT_FlagM2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "59:56"; + value =3D (aa64isar0_el1 >> 56) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TLBIOS/FEAT_TLBIRANGE not implemented."; + break; + case 0b0001: + description =3D "FEAT_TLBIOS implemented."; + break; + case 0b0010: + description =3D "FEAT_TLBIRANGE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "63:60"; + value =3D (aa64isar0_el1 >> 60) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_RNG not implemented."; + break; + case 0b0001: + description =3D "FEAT_RNG implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); +} + +void +handle_aa64isar1_el1 ( + const UINT64 aa64isar1_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR1_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D (aa64isar1_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "DC CVAP not implemented."; + break; + case 0b0001: + description =3D "FEAT_DPB implemented."; + break; + case 0b0010: + description =3D "FEAT_DPB2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64isar1_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "Address Authentication (APA) not implemented."; + break; + case 0b0001: + description =3D "FEAT_PAuth implemented."; + break; + case 0b0010: + description =3D "FEAT_EPAC implemented."; + break; + case 0b0011: + description =3D "FEAT_PAuth2 implemented."; + break; + case 0b0100: + description =3D "FEAT_FPAC implemented."; + break; + case 0b0101: + description =3D "FEAT_FPACCOMBINE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + if (value > 0) { + print_text ("", "", "", "FEAT_PACQARMA5 implemented."); + } + + bits =3D "11:8 "; + value =3D (aa64isar1_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "Address Authentication (API) not implemented."; + break; + case 0b0001: + description =3D "FEAT_PAuth implemented."; + break; + case 0b0010: + description =3D "FEAT_EPAC implemented."; + break; + case 0b0011: + description =3D "FEAT_PAuth2 implemented."; + break; + case 0b0100: + description =3D "FEAT_FPAC implemented."; + break; + case 0b0101: + description =3D "FEAT_FPACCOMBINE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + if (value > 0) { + print_text ("", "", "", "FEAT_PACIMP implemented."); + } + + bits =3D "15:12"; + value =3D (aa64isar1_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_JSCVT not implemented."; + break; + case 0b0001: + description =3D "FEAT_JSCVT implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "19:16"; + value =3D (aa64isar1_el1 >> 16) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_FCMA not implemented."; + break; + case 0b0001: + description =3D "FEAT_FCMA implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64isar1_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LRCPC (2) not implemented."; + break; + case 0b0001: + description =3D "FEAT_LRCPC implemented."; + break; + case 0b0010: + description =3D "FEAT_LRCPC2 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "27:24"; + value =3D (aa64isar1_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_PACQARMA5 not implemented."; + break; + case 0b0001: + description =3D "FEAT_PACQARMA5 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "31:28"; + value =3D (aa64isar1_el1 >> 28) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_PACIMP not implemented."; + break; + case 0b0001: + description =3D "FEAT_PACIMP implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64isar1_el1 >> 32) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_FRINTTS not implemented."; + break; + case 0b0001: + description =3D "FEAT_FRINTTS implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64isar1_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SB not implemented."; + break; + case 0b0001: + description =3D "FEAT_SB implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64isar1_el1 >> 40) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SPECRES not implemented."; + break; + case 0b0001: + description =3D "FEAT_SPECRES implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "47:44"; + value =3D (aa64isar1_el1 >> 44) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_BF16 not implemented."; + break; + case 0b0001: + description =3D "FEAT_BF16 implemented."; + break; + case 0b0010: + description =3D "FEAT_EBF16 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "51:48"; + value =3D (aa64isar1_el1 >> 48) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_DGH not implemented."; + break; + case 0b0001: + description =3D "FEAT_DGH implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "55:52"; + value =3D (aa64isar1_el1 >> 52) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_I8MM not implemented."; + break; + case 0b0001: + description =3D "FEAT_I8MM implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "59:56"; + value =3D (aa64isar1_el1 >> 56) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_XS not implemented."; + break; + case 0b0001: + description =3D "FEAT_XS implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "63:60"; + value =3D (aa64isar1_el1 >> 60) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_LS64 not implemented."; + break; + case 0b0001: + description =3D "FEAT_LS64 implemented."; + break; + case 0b0010: + description =3D "FEAT_LS64_V implemented."; + break; + case 0b0011: + description =3D "FEAT_LS64_ACCDATA implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); +} + +void +handle_aa64isar2_el1 ( + const UINT64 aa64isar2_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR2_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D (aa64isar2_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_WFxT not implemented."; + break; + case 0b0010: + description =3D "FEAT_WFxT implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64isar2_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_RPRES not implemented."; + break; + case 0b0001: + description =3D "FEAT_RPRES implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64isar2_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_PACQARMA3 not implemented."; + break; + case 0b0001: + description =3D "FEAT_PACQARMA3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "15:12"; + value =3D (aa64isar2_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "Address Authentication (APA3) not implemented."; + break; + case 0b0001: + description =3D "FEAT_PAuth implemented."; + break; + case 0b0010: + description =3D "FEAT_EPAC implemented."; + break; + case 0b0011: + description =3D "FEAT_PAuth2 implemented."; + break; + case 0b0100: + description =3D "FEAT_FPAC implemented."; + break; + case 0b0101: + description =3D "FEAT_FPACCOMBINE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "19:16"; + value =3D (aa64isar2_el1 >> 16) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_MOPS not implemented."; + break; + case 0b0001: + description =3D "FEAT_MOPS implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "23:20"; + value =3D (aa64isar2_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_HBC not implemented."; + break; + case 0b0001: + description =3D "FEAT_HBC implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "27:24"; + value =3D (aa64isar2_el1 >> 24) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_CONSTPACFIELD not implemented."; + break; + case 0b0001: + description =3D "FEAT_CONSTPACFIELD implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 63:28 reserved +} + +void +handle_aa64dfr0_el1 ( + const UINT64 aa64dfr0_el1 + ) +{ + UINT64 value; + STATIC CONST CHAR8 RegName[] =3D "ID_AA64DFR0_EL1"; + char *description; + char *bits; + + bits =3D "3:0 "; + value =3D (aa64dfr0_el1 >> 4) & 0xf; + switch (value) { + case 0b0110: + description =3D "Armv8 debug architecture"; + break; + case 0b0111: + description =3D "Armv8 debug architecture with VHE"; + break; + case 0b1000: + description =3D "FEAT_Debugv8p2 implemented."; + break; + case 0b1001: + description =3D "FEAT_Debugv8p4 implemented."; + break; + case 0b1010: + description =3D "FEAT_Debugv8p8 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "7:4 "; + value =3D (aa64dfr0_el1 >> 4) & 0xf; + switch (value) { + case 0b0000: + description =3D "Trace unit System registers not implemented."; + break; + case 0b0001: + description =3D "Trace unit System registers implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "11:8 "; + value =3D (aa64dfr0_el1 >> 8) & 0xf; + switch (value) { + case 0b0000: + description =3D "Performance Monitors Extension not implemented."; + break; + case 0b0001: + description =3D "FEAT_PMUv3 implemented."; + break; + case 0b0100: + description =3D "FEAT_PMUv3p1 implemented."; + break; + case 0b0101: + description =3D "FEAT_PMUv3p4 implemented."; + break; + case 0b0110: + description =3D "FEAT_PMUv3p5 implemented."; + break; + case 0b0111: + description =3D "FEAT_PMUv3p7 implemented."; + break; + case 0b1000: + description =3D "FEAT_PMUv3p8 implemented."; + break; + case 0b1111: + description =3D "IMPLEMENTATION DEFINED form of performance monitors= supported."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "15:12"; + value =3D (aa64dfr0_el1 >> 12) & 0xf; + switch (value) { + case 0b0000: + description =3D "reserved"; + break; + default: + description =3D "Number of breakpoints, minus 1."; + break; + } + + print_values (RegName, bits, value, description); + + // 19:16 reserved + + bits =3D "23:20"; + value =3D (aa64dfr0_el1 >> 20) & 0xf; + switch (value) { + case 0b0000: + description =3D "reserved"; + break; + default: + description =3D "Number of watchpoints, minus 1."; + break; + } + + print_values (RegName, bits, value, description); + + // 27:24 reserved + + bits =3D "31:28"; + value =3D (aa64dfr0_el1 >> 28) & 0xf; + switch (value) { + default: + description =3D "Number of breakpoints that are context-aware, minus= 1."; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "35:32"; + value =3D (aa64dfr0_el1 >> 32) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_SPE not implemented."; + break; + case 0b0001: + description =3D "FEAT_SPE implemented."; + break; + case 0b0010: + description =3D "FEAT_SPEv1p1 implemented."; + break; + case 0b0011: + description =3D "FEAT_SPEv1p2 implemented."; + break; + case 0b0100: + description =3D "FEAT_SPEv1p3 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "39:36"; + value =3D (aa64dfr0_el1 >> 36) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_DoubleLock implemented."; + break; + case 0b1111: + description =3D "FEAT_DoubleLock not implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "43:40"; + value =3D (aa64dfr0_el1 >> 40) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TRF not implemented."; + break; + case 0b0001: + description =3D "FEAT_TRF implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "47:44"; + value =3D (aa64dfr0_el1 >> 44) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_TRBE not implemented."; + break; + case 0b0001: + description =3D "FEAT_TRBE implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "51:48"; + value =3D (aa64dfr0_el1 >> 48) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_MTPMU not implemented."; + break; + case 0b0001: + description =3D "FEAT_MTPMU and FEAT_PMUv3 implemented."; + break; + case 0b1111: + description =3D "FEAT_MTPMU not implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + bits =3D "55:52"; + value =3D (aa64dfr0_el1 >> 52) & 0xf; + switch (value) { + case 0b0000: + description =3D "FEAT_BRBE not implemented."; + break; + case 0b0001: + description =3D "FEAT_BRBE implemented."; + break; + case 0b0010: + description =3D "FEAT_BRBEv1p1 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); + + // 59:56 reserved + + bits =3D "63:60"; + value =3D (aa64dfr0_el1 >> 60) & 0xf; + switch (value) { + case 0b0000: + description =3D "Setting MDCR_EL2.HPMN to zero has CONSTRAINED UNPRE= DICTABLE behavior."; + break; + case 0b0001: + description =3D "FEAT_HPMN0 implemented."; + break; + default: + description =3D "unknown"; + break; + } + + print_values (RegName, bits, value, description); +} + +EFI_STATUS +EFIAPI +UefiMain ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT64 aa64dfr0_el1 =3D read_aa64dfr0_el1 (); + UINT64 aa64dfr1_el1 =3D read_aa64dfr1_el1 (); + UINT64 aa64isar0_el1 =3D read_aa64isar0_el1 (); + UINT64 aa64isar1_el1 =3D read_aa64isar1_el1 (); + UINT64 aa64isar2_el1 =3D read_aa64isar2_el1 (); + UINT64 aa64mmfr0_el1 =3D read_aa64mmfr0_el1 (); + UINT64 aa64mmfr1_el1 =3D read_aa64mmfr1_el1 (); + UINT64 aa64mmfr2_el1 =3D read_aa64mmfr2_el1 (); + UINT64 aa64pfr0_el1 =3D read_aa64pfr0_el1 (); + UINT64 aa64pfr1_el1 =3D read_aa64pfr1_el1 (); + + /* UINT64 aa64smfr0_el1 =3D read_aa64smfr0_el1 ();*/ + /* UINT64 aa64zfr0_el1 =3D read_aa64zfr0_el1 ();*/ + + AsciiPrint ("ID_AA64MMFR0_EL1 =3D 0x%016lx\n", aa64mmfr0_el1); + AsciiPrint ("ID_AA64MMFR1_EL1 =3D 0x%016lx\n", aa64mmfr1_el1); + AsciiPrint ("ID_AA64MMFR2_EL1 =3D 0x%016lx\n", aa64mmfr2_el1); + AsciiPrint ("ID_AA64PFR0_EL1 =3D 0x%016lx\n", aa64pfr0_el1); + AsciiPrint ("ID_AA64PFR1_EL1 =3D 0x%016lx\n", aa64pfr1_el1); + AsciiPrint ("ID_AA64ISAR0_EL1 =3D 0x%016lx\n", aa64isar0_el1); + AsciiPrint ("ID_AA64ISAR1_EL1 =3D 0x%016lx\n", aa64isar1_el1); + AsciiPrint ("ID_AA64ISAR2_EL1 =3D 0x%016lx\n", aa64isar2_el1); + AsciiPrint ("ID_AA64DFR0_EL1 =3D 0x%016lx\n", aa64dfr0_el1); + AsciiPrint ("ID_AA64DFR1_EL1 =3D 0x%016lx\n", aa64dfr1_el1); = // ignore + /* AsciiPrint ("ID_AA64SMFR0_EL1 =3D 0x%016lx\n", aa64smfr0_el1);*/ + /* AsciiPrint ("ID_AA64ZFR0_EL1 =3D 0x%016lx\n", aa64zfr0_el1);*/ + + AsciiPrint ("\n"); + print_text ("Register", "Bits", "Value", "Feature"); + print_spacer (); + + handle_aa64mmfr0_el1 (aa64mmfr0_el1); + print_spacer (); + handle_aa64mmfr1_el1 (aa64mmfr1_el1, aa64pfr0_el1); + print_spacer (); + handle_aa64mmfr2_el1 (aa64mmfr2_el1); + + print_spacer (); + handle_aa64pfr0_el1 (aa64pfr0_el1, aa64pfr1_el1); + print_spacer (); + handle_aa64pfr1_el1 (aa64pfr1_el1); + + print_spacer (); + handle_aa64isar0_el1 (aa64isar0_el1); + print_spacer (); + handle_aa64isar1_el1 (aa64isar1_el1); + print_spacer (); + handle_aa64isar2_el1 (aa64isar2_el1); + + print_spacer (); + handle_aa64dfr0_el1 (aa64dfr0_el1); + + return EFI_SUCCESS; +} diff --git a/ArmPkg/Application/ArmCpuInfo/readregs.s b/ArmPkg/Application/= ArmCpuInfo/readregs.s new file mode 100644 index 000000000000..052834b3c3f2 --- /dev/null +++ b/ArmPkg/Application/ArmCpuInfo/readregs.s @@ -0,0 +1,49 @@ +#include + +ASM_FUNC(read_aa64pfr0_el1) + mrs x0, ID_AA64PFR0_EL1; + ret; + +ASM_FUNC(read_aa64pfr1_el1) + mrs x0, ID_AA64PFR1_EL1; + ret; + +ASM_FUNC(read_aa64dfr0_el1) + mrs x0, ID_AA64DFR0_EL1; + ret; + +ASM_FUNC(read_aa64dfr1_el1) + mrs x0, ID_AA64DFR1_EL1; + ret; + +ASM_FUNC(read_aa64isar0_el1) + mrs x0, ID_AA64ISAR0_EL1; + ret; + +ASM_FUNC(read_aa64isar1_el1) + mrs x0, ID_AA64ISAR1_EL1; + ret; + +ASM_FUNC(read_aa64isar2_el1) + mrs x0, ID_AA64ISAR2_EL1; + ret; + +ASM_FUNC(read_aa64mmfr0_el1) + mrs x0, ID_AA64MMFR0_EL1; + ret; + +ASM_FUNC(read_aa64mmfr1_el1) + mrs x0, ID_AA64MMFR1_EL1; + ret; + +ASM_FUNC(read_aa64mmfr2_el1) + mrs x0, ID_AA64MMFR2_EL1; + ret; + +# ASM_FUNC(read_aa64zfr0_el1) +# mrs x0, ID_AA64ZFR0_EL1; +# ret; + +# ASM_FUNC(read_aa64smfr0_el1) +# mrs x0, ID_AA64SMFR0_EL1; +# ret; --=20 2.40.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102694): https://edk2.groups.io/g/devel/message/102694 Mute This Topic: https://groups.io/mt/98123579/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-