From nobody Wed May 15 14:37:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102436+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102436+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1680546859; cv=none; d=zohomail.com; s=zohoarc; b=PuD0FAA7S8SUsRMsgprQjvUlvPZ/rgz20WJiCQ6x2mOSMu29fe98hN1TLmMWghF7zlJwPAD7yC/z01UXGLIs9SNZ7OnCFoZa84Qt+QjnCOP5stc0rWG7brv0C3j3Az1sKQlcmSVG+vu4iq3xGxAzE6YjhcRwclPOJ9HjSH4/qR4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680546859; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=+0ifNUvHjAuDlVQXZ0KZ/p5ZA93iAxcADoJouuIiMPk=; b=AmFgIOgyBvzT1wLiF6DfrsLKxfMz9QAgT1D5VoaBZNxMm8vJx5P3qdbX6uZ6CMCfBTCML2uUnIdgrMwrHBRy4cSlL8V+MsUlfEqa/JmBw/BDAsJ8I7kirRc/BkxKm73ol20bY+sAmqjHOLdLVAxZDUd2rPeDh8t5ESTKHLXQHRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102436+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680546859432933.161894148388; Mon, 3 Apr 2023 11:34:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id GycUYY1788612x1iEKIxktKu; Mon, 03 Apr 2023 11:34:19 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.79706.1680546858373903365 for ; Mon, 03 Apr 2023 11:34:18 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="404740505" X-IronPort-AV: E=Sophos;i="5.98,315,1673942400"; d="scan'208";a="404740505" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 11:34:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10669"; a="1015820786" X-IronPort-AV: E=Sophos;i="5.98,315,1673942400"; d="scan'208";a="1015820786" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.251.25.144]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2023 11:34:17 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni , Ted Kuo Subject: [edk2-devel] [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay. Date: Mon, 3 Apr 2023 11:34:05 -0700 Message-Id: <20230403183405.1689-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: bMvudjnZqSd4p92RxmREg20ox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680546859; bh=RA10VfR0cdxpAHmqlzz6jJCP1wB9GQGvSeZF/Ib5o/g=; h=Cc:Date:From:Reply-To:Subject:To; b=VaJQZowcRrNFkKYM1g7xqMBKqhHT5WtsuPeA4C0UkQzZv1A3jqC5yxNTMf64m6trvku DZ2Pe56R6Lrl+sAge/ztlgtrgYOGZ4guoxo+Uu8VbidL8RHhrnbqgTN91y0tX3aoqq5Hv kDMbtOpaPbFU8wuDE0wx6DJQZu9a2JQbNHE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680546861285100005 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. This patch also removed unnecessary LoadCheck code after supporting CPU microcode already loaded scenario. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu Reviewed-by: Ted Kuo Reviewed-by: Nate DeSimone Reviewed-by: Ray Ni --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 46 ++++++++++++++++++++++= ++---------------------- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 45 ++++++++++++++++++++++= ++--------------------- 2 files changed, 48 insertions(+), 43 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..900126b93b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): cmp esp, 0 jz ParamError =20 + ; + ; If microcode already loaded before this function, exit this function = with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -330,7 +346,7 @@ CheckMainHeader: cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] jne LoadMicrocodeDefault1 test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] - jnz LoadCheck ; Jif signature and platform ID match + jnz LoadMicrocode ; Jif signature and platform ID match =20 LoadMicrocodeDefault1: ; Check if extended header exists @@ -363,7 +379,7 @@ CheckExtSig: cmp dword [edi + ExtSig.ExtSigProcessor], ebx jne LoadMicrocodeDefault2 test dword [edi + ExtSig.ExtSigFlags], edx - jnz LoadCheck ; Jif signature and platform ID match + jnz LoadMicrocode ; Jif signature and platform ID match LoadMicrocodeDefault2: ; Check if any more extended signatures exist add edi, ExtSig.size @@ -435,23 +451,7 @@ LoadMicrocodeDefault4: ; Is valid Microcode start point ? cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh jz Done - -LoadCheck: - ; Get the revision of the current microcode update loaded - mov ecx, MSR_IA32_BIOS_SIGN_ID - xor eax, eax ; Clear EAX - xor edx, edx ; Clear EDX - wrmsr ; Load 0 to MSR at 8Bh - - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature - - ; Verify this microcode update is not already loaded - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - je Continue - + jmp CheckMainHeader LoadMicrocode: ; EAX contains the linear address of the start of the Update Data ; EDX contains zero @@ -465,10 +465,12 @@ LoadMicrocode: mov eax, 1 cpuid =20 -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index b32fa32a89..698bb063a7 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError mov rsp, rcx =20 + ; + ; If microcode already loaded before this function, exit this function = with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -198,7 +214,7 @@ CheckMainHeader: cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] jne LoadMicrocodeDefault1 test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] - jnz LoadCheck ; Jif signature and platform ID match + jnz LoadMicrocode ; Jif signature and platform ID match =20 LoadMicrocodeDefault1: ; Check if extended header exists @@ -231,7 +247,7 @@ CheckExtSig: cmp dword [edi + ExtSig.ExtSigProcessor], ebx jne LoadMicrocodeDefault2 test dword [edi + ExtSig.ExtSigFlags], edx - jnz LoadCheck ; Jif signature and platform ID match + jnz LoadMicrocode ; Jif signature and platform ID match LoadMicrocodeDefault2: ; Check if any more extended signatures exist add edi, ExtSig.size @@ -276,22 +292,7 @@ LoadMicrocodeDefault4: ; Is valid Microcode start point ? cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh jz Done - -LoadCheck: - ; Get the revision of the current microcode update loaded - mov ecx, MSR_IA32_BIOS_SIGN_ID - xor eax, eax ; Clear EAX - xor edx, edx ; Clear EDX - wrmsr ; Load 0 to MSR at 8Bh - - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature - - ; Verify this microcode update is not already loaded - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - je Continue + jmp CheckMainHeader =20 LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -306,10 +307,12 @@ LoadMicrocode: mov eax, 1 cpuid =20 -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102436): https://edk2.groups.io/g/devel/message/102436 Mute This Topic: https://groups.io/mt/98042607/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-