From nobody Tue May 14 23:11:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102334+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102334+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1680303416; cv=none; d=zohomail.com; s=zohoarc; b=MjL5O6bmmO3vPvlPkKLUSya/O80r7/IsM0g0WS9X2s8HWfJGYSVpuFxmLfb0UokEwmK+4NTq/KnxaxT7aLfYLLFUmqmZKsC+EQDKBier08l3nhuL96YLg7ubViH5P+P153zI3eWujIuA82TX3mdMvKVMGex60P64NSFiguuP8Os= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680303416; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=kRogmTw9XmYJrH4kGZt5+du+mM4m+kqXdBbEPOokl4E=; b=lvbramyiHDm/y6brrNH9MA7Hx2U4v/kOlGAVqxfJpI1hGqLeFLyZ2KLrpjp8vfJQKv5pMoIBiLMQJFGUpvm8pqngmRKGf8bkHS3l0t1oo6hfAeeiqzGS4bjTpEXGH1waGfY2bMiNdN3VcOLwN3BYYNXDI6++ao6SIw8ugcfzs8s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102334+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680303416784909.8115416219159; Fri, 31 Mar 2023 15:56:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PZcZYY1788612xmJgD54mmtE; Fri, 31 Mar 2023 15:56:48 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.9659.1680303407349844522 for ; Fri, 31 Mar 2023 15:56:47 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10666"; a="404307034" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="404307034" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2023 15:56:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10666"; a="809190278" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="809190278" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.252.130.169]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2023 15:56:46 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [edk2-devel] [PATCH v3] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay. Date: Fri, 31 Mar 2023 15:56:35 -0700 Message-Id: <20230331225635.1356-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: vjyPeURCTOf35bIAU3ZR1AWbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680303408; bh=TFhVXqvzTFbka7K9UlwRvbaSVPnn1AHGUMV7k3r23i0=; h=Cc:Date:From:Reply-To:Subject:To; b=emFnekR/huzVH8CevLoFRYGTE79x5I4NIoil0LgOLjdWbXjCAmfpijZekdISI7RTe38 zRJw1ssb5/wKcqbLGfNCewvM76P/JkDWFJnl2Hd9ITMCeWF+2mWmos1YP2/uQoxoTuPJZ 4LanA6F5IuTqKTu762UtCnEDm0rCcfkv1QM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680303417296100001 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 26 ++++++++++++++++++++++= ---- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 ++++++++++++++++++++++= ---- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..79f2a20a2c 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): cmp esp, 0 jz ParamError =20 + ; + ; If microcode already loaded before this function, exit this function = with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -450,7 +466,7 @@ LoadCheck: =20 ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - je Continue + je Done ; if already one version microcode loaded, go to done =20 LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -465,10 +481,12 @@ LoadMicrocode: mov eax, 1 cpuid =20 -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index b32fa32a89..3e40678f47 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError mov rsp, rcx =20 + ; + ; If microcode already loaded before this function, exit this function = with SUCCESS. + ; + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -291,7 +307,7 @@ LoadCheck: =20 ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - je Continue + je Done ; if already one version microcode loaded, go to done =20 LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -306,10 +322,12 @@ LoadMicrocode: mov eax, 1 cpuid =20 -Continue: - jmp NextMicrocode - Done: + mov ecx, MSR_IA32_BIOS_SIGN_ID + xor eax, eax ; Clear EAX + xor edx, edx ; Clear EDX + wrmsr ; Load 0 to MSR at 8Bh + mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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