From nobody Fri May 17 00:12:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+102124+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102124+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1680104649; cv=none; d=zohomail.com; s=zohoarc; b=F5i2Bcx6KLyEddcr+cLdgBqyVqyDTed6jVq3QTfy4ikf+DCqET5MtABZO2ddwDuAR0PKat1iBo/Z5hACt3GVloHd99rE9T+ZgFgSr92RYZq2K+h5R6WznPIKeoummo4GQjZtBEcFXn//pD8paMxMl+MLBu57FUBt/iH8VoZ2RWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680104649; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=4W8Vghtph+N7xvcwtd5pOfF5VGHcPjWSydv5eMCBR7g=; b=S5yJpKUZvUohLBHYivJSVX81h9XM306xEuINIYMugTgSC6gy//5PhVvDE1W5kKAoEGhGGIsD1yjw/yDFifFHeBGF5tH+ACW9B5wGX21fkujDMBK6arhkOqsJFf08LXPZhP7LkY7nNZyRMSJnJEDve1IsWYrUgZYSKImRVxniFbk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+102124+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1680104649863544.5289726756708; Wed, 29 Mar 2023 08:44:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id YPeyYY1788612xpaYLPrybIa; Wed, 29 Mar 2023 08:44:08 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.1391.1680104646902406984 for ; Wed, 29 Mar 2023 08:44:07 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10664"; a="342514523" X-IronPort-AV: E=Sophos;i="5.98,301,1673942400"; d="scan'208";a="342514523" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2023 08:44:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10664"; a="677814576" X-IronPort-AV: E=Sophos;i="5.98,301,1673942400"; d="scan'208";a="677814576" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.251.1.231]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2023 08:44:06 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay. Date: Wed, 29 Mar 2023 08:43:52 -0700 Message-Id: <20230329154352.1092-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: Ad6FNJTAJOCOor2ABVqXttObx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1680104648; bh=FtMIkfYu/neb1M6kvSaVXLOPuTdBayIxwoZryFqoXnU=; h=Cc:Date:From:Reply-To:Subject:To; b=JpaC72fC2pGfEIx4dImI1RcJscVqoiVkyefJyWE+7kEgFQExLdcqBeexKSsfyZL03+6 YNwRUMmJNuqybF62VZ18aeE/e1z0ZWjWxcjyAURGeuJMl8sXk+kwf3eHoIPFYqGa/a+5A mg6lMuT9sTfwpFCthC+YiLe+jmAAdXlq4OE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1680104650940100003 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu Reviewed-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 18 ++++++++++++++---- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 16 ++++++++++++---- 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..b902d017ee 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,19 @@ ASM_PFX(LoadMicrocodeDefault): cmp esp, 0 jz ParamError =20 + ; + ; If microcode already loaded before this function, exit this function = with SUCCESS. + ; + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor eax, eax + test edx, edx + jnz Exit2 + + + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -450,7 +463,7 @@ LoadCheck: =20 ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - je Continue + je Done ; if already one version microcode loaded, go to done =20 LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -465,9 +478,6 @@ LoadMicrocode: mov eax, 1 cpuid =20 -Continue: - jmp NextMicrocode - Done: mov eax, 1 cpuid diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index b32fa32a89..2a23c33c9b 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,17 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamError mov rsp, rcx =20 + ; + ; If microcode already loaded before this function, exit this function = with SUCCESS. + ; + mov eax, 1 + cpuid + mov ecx, MSR_IA32_BIOS_SIGN_ID + rdmsr ; Get current microcode signature + xor rax, rax + test edx, edx + jnz Exit2 + ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k ; first check UPD header revision @@ -291,7 +302,7 @@ LoadCheck: =20 ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx - je Continue + je Done ; if already one version microcode loaded, go to done =20 LoadMicrocode: ; EAX contains the linear address of the start of the Update Data @@ -306,9 +317,6 @@ LoadMicrocode: mov eax, 1 cpuid =20 -Continue: - jmp NextMicrocode - Done: mov eax, 1 cpuid --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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