From nobody Fri May 17 13:39:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99738+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99738+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675777802; cv=none; d=zohomail.com; s=zohoarc; b=BLN7UlXfOHZMA/d4IC3SFtBZooIZHyQP9ZoKfy1AKoOFjhh/Cd/t95SfS5qVyj82KNhtQcqgqNota7iFAGGQAnnK33YirEeOF21uQdKwxu/bECfTHwemeCS01L+Gs3HBNw6wGTO858jPb2iOIb9VqSEBtsfTU7GlHXFL0kAdACY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675777802; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Wvp+mKkNeKfO8YdtlxQ4m+Cr5jjP9yJOwvXoJCPgsjs=; b=YkH+MNZlh0ZhHUPyfM3tunjRWueEMF/3P2HPZDpTGZk9F0ZPjOhAfq6CvShNB3Ryr891te+hOtJNYyUrt/lC+YRkY0cAGYOiM8RUk0XYrxpjVwdSoQSDkTyltsvEItVKf61h1klB31GbSeoALtuPqCUacMTB2KFb2gkgpXesAAw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99738+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1675777802097710.5561925473787; Tue, 7 Feb 2023 05:50:02 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id T9XnYY1788612xB29We0Nv0o; Tue, 07 Feb 2023 05:50:01 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.83549.1675777797372123216 for ; Tue, 07 Feb 2023 05:50:01 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="329524593" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="329524593" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:01 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="660234260" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="660234260" X-Received: from xieyuanh-mobl.ccr.corp.intel.com ([10.255.31.127]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:49:58 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [PATCH 1/5] UefiCpuPkg: Duplicate RelocateApLoop for Amd x64 processors. Date: Tue, 7 Feb 2023 21:49:35 +0800 Message-Id: <20230207134939.273-2-yuanhao.xie@intel.com> In-Reply-To: <20230207134939.273-1-yuanhao.xie@intel.com> References: <20230207134939.273-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: RPrFAcnx48iIpFEUxoe89o6Bx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675777801; bh=9/xPluu7y0BRF4/0j12skibqsJWUCEVVmOARCflq1Do=; h=Cc:Date:From:Reply-To:Subject:To; b=l5slaIL9brNQ0qJ1PyMda8gBp1a9bKHwColCNbXVti3KodzCPy1CEI4oB5qBkjbQ8xO Js6LUjPgAn6QeB8p/lat38+f8liiigAJUKMcQpPyk8Hp5zR0dCaDrSYtLfrI/ItiByFNf a/Xh3kOa2Ebplr1l/JK06AaPLmHpOkIZ1/c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675777804291100001 Content-Type: text/plain; charset="utf-8" The duplicated variant is to ensure 64-bit Amd processors can follow the logic of current existing design to avoid crash may caused by the untested modification. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 70 +++++--- UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 20 ++- UefiCpuPkg/Library/MpInitLib/MpLib.h | 28 +++ UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 169 ++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 3 + 5 files changed, 256 insertions(+), 34 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index a84e9e33ba..fd94652e5b 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -1,7 +1,7 @@ /** @file MP initialize support functions for DXE phase. =20 - Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -378,32 +378,44 @@ RelocateApLoop ( IN OUT VOID *Buffer ) { - CPU_MP_DATA *CpuMpData; - BOOLEAN MwaitSupport; - ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; - UINTN ProcessorNumber; - UINTN StackStart; + CPU_MP_DATA *CpuMpData; + BOOLEAN MwaitSupport; + ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; + ASM_RELOCATE_AP_LOOP_AMD64 AsmRelocateApLoopFuncAmd64; + UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); - if (CpuMpData->UseSevEsAPMethod) { - StackStart =3D CpuMpData->SevEsAPResetStackStart; + if (StandardSignatureIsAuthenticAMD () && (sizeof (UINTN) =3D=3D sizeof = (UINT64))) { + StackStart =3D CpuMpData->UseSevEsAPMethod ? CpuMpData->SevEsAPResetSt= ackStart : mReservedTopOfApStack; + AsmRelocateApLoopFuncAmd64 =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedA= pLoopFunc; + AsmRelocateApLoopFuncAmd64 ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } else { - StackStart =3D mReservedTopOfApStack; + StackStart =3D mReservedTopOfApStack; + AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoop= Func; + AsmRelocateApLoopFunc ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } =20 - AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFu= nc; - AsmRelocateApLoopFunc ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); // // It should never reach here // @@ -582,11 +594,19 @@ InitMpGlobalData ( =20 mReservedTopOfApStack =3D (UINTN)Address + ApSafeBufferSize; ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddress, - CpuMpData->AddressMap.RelocateApLoopFuncSize - ); + if (StandardSignatureIsAuthenticAMD () && (sizeof (UINTN) =3D=3D sizeof = (UINT64))) { + CopyMem ( + mReservedApLoopFunc, + CpuMpData->AddressMap.RelocateApLoopFuncAddress, + CpuMpData->AddressMap.RelocateApLoopFuncSize + ); + } else { + CopyMem ( + mReservedApLoopFunc, + CpuMpData->AddressMap.RelocateApLoopFuncAddressAmd64, + CpuMpData->AddressMap.RelocateApLoopFuncSizeAmd64 + ); + } =20 Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/Mp= InitLib/MpEqu.inc index ebadcc6fb3..4d0933d352 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -21,15 +21,17 @@ CPU_SWITCH_STATE_LOADED equ 2 ; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP ; struc MP_ASSEMBLY_ADDRESS_MAP - .RendezvousFunnelAddress CTYPE_UINTN 1 - .ModeEntryOffset CTYPE_UINTN 1 - .RendezvousFunnelSize CTYPE_UINTN 1 - .RelocateApLoopFuncAddress CTYPE_UINTN 1 - .RelocateApLoopFuncSize CTYPE_UINTN 1 - .ModeTransitionOffset CTYPE_UINTN 1 - .SwitchToRealNoNxOffset CTYPE_UINTN 1 - .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 - .SwitchToRealPM16ModeSize CTYPE_UINTN 1 + .RendezvousFunnelAddress CTYPE_UINTN 1 + .ModeEntryOffset CTYPE_UINTN 1 + .RendezvousFunnelSize CTYPE_UINTN 1 + .RelocateApLoopFuncAddress CTYPE_UINTN 1 + .RelocateApLoopFuncSize CTYPE_UINTN 1 + .RelocateApLoopFuncAddressAmd64 CTYPE_UINTN 1 + .RelocateApLoopFuncSizeAmd64 CTYPE_UINTN 1 + .ModeTransitionOffset CTYPE_UINTN 1 + .SwitchToRealNoNxOffset CTYPE_UINTN 1 + .SwitchToRealPM16ModeOffset CTYPE_UINTN 1 + .SwitchToRealPM16ModeSize CTYPE_UINTN 1 endstruc =20 ; diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index f5086e497e..4f6146e30d 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -179,6 +179,8 @@ typedef struct { UINTN RendezvousFunnelSize; UINT8 *RelocateApLoopFuncAddress; UINTN RelocateApLoopFuncSize; + UINT8 *RelocateApLoopFuncAddressAmd64; + UINTN RelocateApLoopFuncSizeAmd64; UINTN ModeTransitionOffset; UINTN SwitchToRealNoNxOffset; UINTN SwitchToRealPM16ModeOffset; @@ -373,6 +375,32 @@ typedef IN UINTN WakeupBuffer ); =20 +/** + Assembly code to place AP into safe loop mode for Amd X64 processors. + Place AP into targeted C-State if MONITOR is supported, otherwise + place AP into hlt state. + Place AP in protected mode if the current is long mode. Due to AP maybe + wakeup by some hardware event. It could avoid accessing page table that + may not available during booting to OS. + + @param[in] MwaitSupport TRUE indicates MONITOR is supported. + FALSE indicates MONITOR is not supported. + @param[in] ApTargetCState Target C-State value. + @param[in] PmCodeSegment Protected mode code segment value. +**/ +typedef + VOID +(EFIAPI *ASM_RELOCATE_AP_LOOP_AMD64)( + IN BOOLEAN MwaitSupport, + IN UINTN ApTargetCState, + IN UINTN PmCodeSegment, + IN UINTN TopOfApStack, + IN UINTN NumberToFinish, + IN UINTN Pm16CodeSegment, + IN UINTN SevEsAPJumpTable, + IN UINTN WakeupBuffer + ); + /** Assembly code to get starting address and size of the rendezvous entry f= or APs. Information for fixing a jump instruction in the code is also returned. diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Libr= ary/MpInitLib/X64/AmdSev.nasm index 7c2469f9c5..b3021bc6ea 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm @@ -346,3 +346,172 @@ PM16Mode: iret =20 SwitchToRealProcEnd: +;-------------------------------------------------------------------------= ------------ +; AsmRelocateApLoopAmd64 (MwaitSupport, ApTargetCState, PmCodeSegment, To= pOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +;-------------------------------------------------------------------------= ------------ + +AsmRelocateApLoopStartAmd64: +BITS 64 + cmp qword [rsp + 56], 0 ; SevEsAPJumpTable + je NoSevEsAmd64 + + ; + ; Perform some SEV-ES related setup before leaving 64-bit mode + ; + push rcx + push rdx + + ; + ; Get the RDX reset value using CPUID + ; + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for RDX + + ; + ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call + ; - Must be done while in 64-bit long mode so that writes to + ; the GHCB memory will be unencrypted. + ; - No NAE events can be generated once this is set otherwise + ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. + ; + mov rcx, 0xc0010130 + rdmsr ; Retrieve current GHCB address + shl rdx, 32 + or rdx, rax + + mov rdi, rdx + xor rax, rax + mov rcx, 0x800 + shr rcx, 3 + rep stosq ; Clear the GHCB + + mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD + mov [rdx + 0x390], rax + mov rax, 114 ; Set SwExitCode valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo1 valid bit + bts [rdx + 0x3f0], rax + inc rax ; Set SwExitInfo2 valid bit + bts [rdx + 0x3f0], rax + + pop rdx + pop rcx + +NoSevEsAmd64: + cli ; Disable interrupt before switching to 3= 2-bit mode + mov rax, [rsp + 40] ; CountTofinish + lock dec dword [rax] ; (*CountTofinish)-- + + mov r10, [rsp + 48] ; Pm16CodeSegment + mov rax, [rsp + 56] ; SevEsAPJumpTable + mov rbx, [rsp + 64] ; WakeupBuffer + mov rsp, r9 ; TopOfApStack + + push rax ; Save SevEsAPJumpTable + push rbx ; Save WakeupBuffer + push r10 ; Save Pm16CodeSegment + push rcx ; Save MwaitSupport + push rdx ; Save ApTargetCState + + lea rax, [PmEntryAmd64] ; rax <- The start address of transi= tion code + + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; +o64 retf + +BITS 32 +PmEntryAmd64: + mov eax, cr0 + btr eax, 31 ; Clear CR0.PG + mov cr0, eax ; Disable paging and caches + + mov ecx, 0xc0000080 + rdmsr + and ah, ~ 1 ; Clear LME + wrmsr + mov eax, cr4 + and al, ~ (1 << 5) ; Clear PAE + mov cr4, eax + + pop edx + add esp, 4 + pop ecx, + add esp, 4 + +MwaitCheckAmd64: + cmp cl, 1 ; Check mwait-monitor support + jnz HltLoopAmd64 + mov ebx, edx ; Save C-State to ebx +MwaitLoopAmd64: + cli + mov eax, esp ; Set Monitor Address + xor ecx, ecx ; ecx =3D 0 + xor edx, edx ; edx =3D 0 + monitor + mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] + shl eax, 4 + mwait + jmp MwaitLoopAmd64 + +HltLoopAmd64: + pop edx ; PM16CodeSegment + add esp, 4 + pop ebx ; WakeupBuffer + add esp, 4 + pop eax ; SevEsAPJumpTable + add esp, 4 + cmp eax, 0 ; Check for SEV-ES + je DoHltAmd64 + + cli + ; + ; SEV-ES is enabled, use VMGEXIT (GHCB information already + ; set by caller) + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Back from VMGEXIT AP_HLT_LOOP + ; Push the FLAGS/CS/IP values to use + ; + push word 0x0002 ; EFLAGS + xor ecx, ecx + mov cx, [eax + 2] ; CS + push cx + mov cx, [eax] ; IP + push cx + push word 0x0000 ; For alignment, will be discarded + + push edx + push ebx + + mov edx, esi ; Restore RDX reset value + + retf + +DoHltAmd64: + cli + hlt + jmp DoHltAmd64 + +BITS 64 +AsmRelocateApLoopEndAmd64: diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 5d71995bf8..cd40099ae4 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -459,6 +459,9 @@ ASM_PFX(AsmGetAddressMap): lea rax, [AsmRelocateApLoopStart] mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], rax mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart + lea rax, [AsmRelocateApLoopStartAmd64] + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= essAmd64], rax + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= Amd64], AsmRelocateApLoopEndAmd64 - AsmRelocateApLoopStartAmd64 mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], PM16Mode - RendezvousFunnelProcStart --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99738): https://edk2.groups.io/g/devel/message/99738 Mute This Topic: https://groups.io/mt/96807118/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 13:39:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99739+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99739+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675777806; cv=none; d=zohomail.com; s=zohoarc; b=h5c3jvuzALiwbEhqXWPHi2Ha3Btrhny+hwg0qnswLqzUJHkuVaysXsTek51dT8zrEUIeJQ7Q5JPQxjFwPwR+0U5sLALfAV4nisbpVh2tGBou6CTiDtJNXvp8wX3Ee+llHGDm5f6eBnnXDXnpJKiyP4r+YlRcwDkKLjtEZaYhTss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675777806; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=UvvqNwgSs9JCv5pjOBgrWg1S9LrT14k9BXMLiYqAfX8=; b=hPlleBATySFO7pmfbIWnmM2gL4g7UnIVqU7lk1WR9GiYkIqKBLhOwvMKxMysypfiM4SaeZ43C6sb26rWIuiwsscw1iyPZBd/tUvmYj6P5gLLYn4AuEtkviyDZ4WZDQEEn3y9cSm90rF27Y2T/H7DccpV1NqY9NzRyEU2WaWx018= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99739+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1675777806414759.0848975224492; Tue, 7 Feb 2023 05:50:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8UZMYY1788612xXAZOnLBDNo; Tue, 07 Feb 2023 05:50:06 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.83549.1675777797372123216 for ; Tue, 07 Feb 2023 05:50:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="329524629" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="329524629" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:05 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="660234278" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="660234278" X-Received: from xieyuanh-mobl.ccr.corp.intel.com ([10.255.31.127]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:03 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [PATCH 2/5] UefiCpuPkg: Contiguous memory allocation and code clean-up. Date: Tue, 7 Feb 2023 21:49:36 +0800 Message-Id: <20230207134939.273-3-yuanhao.xie@intel.com> In-Reply-To: <20230207134939.273-1-yuanhao.xie@intel.com> References: <20230207134939.273-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: jaD0vORELCJpOViTVyJwrfIfx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675777806; bh=FXm5Im888zj+l6SwL9cIDXniBKF4w9jAM4Kw7yESFUg=; h=Cc:Date:From:Reply-To:Subject:To; b=kUo/gbFSKPVGAbh0G343SgKD+IK+Y36Q7V2V8Eba4QeIeXX7j1Z7Ap+VL2Kns/1hryR tPqr1QvinT44narOy/G787qiZeGUMtamVbcCE6CuTbI8MQuiA06mRw2PqzGOhI0wkeiQB qOB4P9y6s4P2gzE1STh6N7uHn56WAPUzxrg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675777808353100001 Content-Type: text/plain; charset="utf-8" Contiguous memory allocation and This patch includes the code refactoring to eliminate the duplication, non-descriptive variable, etc. The memory is calculated taking into account the size difference of RelocateApLoopFunc under different cases. Allocate the memory for stacks and AP loop at contiguous address. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 157 ++++++++++++------------ UefiCpuPkg/Library/MpInitLib/MpLib.h | 9 ++ 2 files changed, 85 insertions(+), 81 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index fd94652e5b..7b51c5c7f7 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -20,14 +20,14 @@ =20 #define AP_SAFE_STACK_SIZE 128 =20 -CPU_MP_DATA *mCpuMpData =3D NULL; -EFI_EVENT mCheckAllApsEvent =3D NULL; -EFI_EVENT mMpInitExitBootServicesEvent =3D NULL; -EFI_EVENT mLegacyBootEvent =3D NULL; -volatile BOOLEAN mStopCheckAllApsStatus =3D TRUE; -VOID *mReservedApLoopFunc =3D NULL; -UINTN mReservedTopOfApStack; -volatile UINT32 mNumberToFinish =3D 0; +CPU_MP_DATA *mCpuMpData =3D NULL; +EFI_EVENT mCheckAllApsEvent =3D NULL; +EFI_EVENT mMpInitExitBootServicesEvent =3D NULL; +EFI_EVENT mLegacyBootEvent =3D NULL; +volatile BOOLEAN mStopCheckAllApsStatus =3D TRUE; +UINTN mReservedTopOfApStack; +volatile UINT32 mNumberToFinish =3D 0; +RELOCATE_AP_LOOP_ENTRY mReservedApLoop; =20 // // Begin wakeup buffer allocation below 0x88000 @@ -380,8 +380,6 @@ RelocateApLoop ( { CPU_MP_DATA *CpuMpData; BOOLEAN MwaitSupport; - ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; - ASM_RELOCATE_AP_LOOP_AMD64 AsmRelocateApLoopFuncAmd64; UINTN ProcessorNumber; UINTN StackStart; =20 @@ -390,30 +388,28 @@ RelocateApLoop ( MwaitSupport =3D IsMwaitSupport (); if (StandardSignatureIsAuthenticAMD () && (sizeof (UINTN) =3D=3D sizeof = (UINT64))) { StackStart =3D CpuMpData->UseSevEsAPMethod ? CpuMpData->SevEsAPResetSt= ackStart : mReservedTopOfApStack; - AsmRelocateApLoopFuncAmd64 =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedA= pLoopFunc; - AsmRelocateApLoopFuncAmd64 ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); + mReservedApLoop.Amd64Entry ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } else { - StackStart =3D mReservedTopOfApStack; - AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoop= Func; - AsmRelocateApLoopFunc ( - MwaitSupport, - CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, - StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer - ); + StackStart =3D mReservedTopOfApStack; + mReservedApLoop.GenericEntry ( + MwaitSupport, + CpuMpData->ApTargetCState, + CpuMpData->PmCodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN)&mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer + ); } =20 // @@ -477,12 +473,15 @@ InitMpGlobalData ( ) { EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Address; - UINTN ApSafeBufferSize; + MP_ASSEMBLY_ADDRESS_MAP *AddressMap; + UINTN AllocSize; UINTN Index; EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc; UINTN StackBase; CPU_INFO_IN_HOB *CpuInfoInHob; + EFI_PHYSICAL_ADDRESS Address; + UINT8 *ApLoopFuncData; + UINTN ApLoopFuncSize; =20 SaveCpuMpData (CpuMpData); =20 @@ -537,6 +536,21 @@ InitMpGlobalData ( } } =20 + AddressMap =3D &CpuMpData->AddressMap; + if (StandardSignatureIsAuthenticAMD () && (sizeof (UINTN) =3D=3D sizeof = (UINT64))) { + // + // 64-bit AMD Processor + // + ApLoopFuncData =3D AddressMap->RelocateApLoopFuncAddressAmd64; + ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSizeAmd64; + } else { + // + // Intel Processor (32-bit or 64-bit), or 32-bit AMD Processor + // + ApLoopFuncData =3D AddressMap->RelocateApLoopFuncAddress; + ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSize; + } + // // Avoid APs access invalid buffer data which allocated by BootServices, // so we will allocate reserved data for AP loop code. We also need to @@ -545,26 +559,32 @@ InitMpGlobalData ( // Allocating it in advance since memory services are not available in // Exit Boot Services callback function. // - ApSafeBufferSize =3D EFI_PAGES_TO_SIZE ( - EFI_SIZE_TO_PAGES ( - CpuMpData->AddressMap.RelocateApLoopFuncSize - ) - ); + // +------------+ + // | Ap Loop | + // +------------+ + // | Stack * N | + // +------------+ (low address) + // Address =3D BASE_4GB - 1; - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiReservedMemoryType, - EFI_SIZE_TO_PAGES (ApSafeBufferSize), - &Address - ); + STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) =3D=3D 0= , "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT"); + AllocSize =3D EFI_PAGES_TO_SIZE ( + EFI_SIZE_TO_PAGES ( + CpuMpData->CpuCount * AP_SAFE_STACK_SIZE + ApLoopFuncSize + ) + ); + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (AllocSize), + &Address + ); ASSERT_EFI_ERROR (Status); - - mReservedApLoopFunc =3D (VOID *)(UINTN)Address; - ASSERT (mReservedApLoopFunc !=3D NULL); - + // If a memory range has the EFI_MEMORY_XP attribute, OS loader + // may set the IA32_EFER.NXE (No-eXecution Enable) bit in IA32_EFER MSR, + // then set the XD (eXecution Disable) bit in the CPU PAE page table. // - // Make sure that the buffer memory is executable if NX protection is en= abled - // for EfiReservedMemoryType. + // Here is to make sure that the memory is executable if NX protection is + // enabled for EfiReservedMemoryType. // // TODO: Check EFI_MEMORY_XP bit set or not once it's available in DXE G= CD // service. @@ -573,40 +593,15 @@ InitMpGlobalData ( if (!EFI_ERROR (Status)) { gDS->SetMemorySpaceAttributes ( Address, - ApSafeBufferSize, + ApLoopFuncSize, MemDesc.Attributes & (~EFI_MEMORY_XP) ); } =20 - ApSafeBufferSize =3D EFI_PAGES_TO_SIZE ( - EFI_SIZE_TO_PAGES ( - CpuMpData->CpuCount * AP_SAFE_STACK_SIZE - ) - ); - Address =3D BASE_4GB - 1; - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiReservedMemoryType, - EFI_SIZE_TO_PAGES (ApSafeBufferSize), - &Address - ); - ASSERT_EFI_ERROR (Status); - - mReservedTopOfApStack =3D (UINTN)Address + ApSafeBufferSize; + mReservedTopOfApStack =3D ((UINTN)Address + CpuMpData->CpuCount * AP_SAF= E_STACK_SIZE); ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); - if (StandardSignatureIsAuthenticAMD () && (sizeof (UINTN) =3D=3D sizeof = (UINT64))) { - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddress, - CpuMpData->AddressMap.RelocateApLoopFuncSize - ); - } else { - CopyMem ( - mReservedApLoopFunc, - CpuMpData->AddressMap.RelocateApLoopFuncAddressAmd64, - CpuMpData->AddressMap.RelocateApLoopFuncSizeAmd64 - ); - } + mReservedApLoop.Data =3D (VOID *)mReservedTopOfApStack; + CopyMem (mReservedApLoop.Data, ApLoopFuncData, ApLoopFuncSize); =20 Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 4f6146e30d..f1b9063e78 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -401,6 +401,15 @@ typedef IN UINTN WakeupBuffer ); =20 +// +// Union holds the relocate APs loop entries for different cases +// +typedef union { + VOID *Data; + ASM_RELOCATE_AP_LOOP_AMD64 Amd64Entry; // 64-bit AMD Processor + ASM_RELOCATE_AP_LOOP GenericEntry; // Intel Processor (32-bit o= r 64-bit), or 32-bit AMD Processor +} RELOCATE_AP_LOOP_ENTRY; + /** Assembly code to get starting address and size of the rendezvous entry f= or APs. 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View/Reply Online (#99739): https://edk2.groups.io/g/devel/message/99739 Mute This Topic: https://groups.io/mt/96807120/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 13:39:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99740+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99740+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675777809; cv=none; d=zohomail.com; s=zohoarc; b=S9JEzSPQ6h6wbne5BEAQqW5IFolfz9z1vZwCHd8pzRBjX3xv9ATmPw6jaJ9zmTmXvMGP6AwDKRtohkawEkVs70+Fn6XB43nD7NNZgdjn1yzlsuPLgZR6vQJdke5pZIom2N/59HgBVDRZpabYz62nsrHxrbY7YODZnBhippjo5qY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675777809; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vrTRUYHgpoa6NJ/syQ3Vfbwakzrdv+DCCFuyRK4Hazs=; b=MNNGQe4jU6HqH/WXuLi97IYYq29BfwDZEq5uN8+FdSiwL855K+fJ0AGHxQ6PDZ710iuhO/5U5H4w12el+pAmO7CKAu2ebT6B6v7iMpUEVE4tXeEMtOlmpIujzdz9imhITs7tXA0K1HRdrFGQspdbgL4RJ5DYUsutw7voKOFJGYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99740+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1675777809904325.4007897766726; Tue, 7 Feb 2023 05:50:09 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9On5YY1788612x4KtZFlH4nW; Tue, 07 Feb 2023 05:50:09 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.83549.1675777797372123216 for ; Tue, 07 Feb 2023 05:50:09 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="329524652" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="329524652" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:08 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="660234281" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="660234281" X-Received: from xieyuanh-mobl.ccr.corp.intel.com ([10.255.31.127]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:07 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann Subject: [edk2-devel] [PATCH 3/5] OvmfPkg: Add CpuPageTableLib required by MpInitLib. Date: Tue, 7 Feb 2023 21:49:37 +0800 Message-Id: <20230207134939.273-4-yuanhao.xie@intel.com> In-Reply-To: <20230207134939.273-1-yuanhao.xie@intel.com> References: <20230207134939.273-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: pNc6WWMnM6yDRtmAJtAoJQevx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675777809; bh=znRhp9aXOvs/4hORSk3wIsqODR4jUq2/2Pp4uJaxNh8=; h=Cc:Date:From:Reply-To:Subject:To; b=ONmHoFCEjkDB+Ev1NC1jKHbrQcW4y1BSGxVZP5Muiv5F3q2LbOywfhoo/PM+H4TuQU0 kWNuh+xuEsfMMCpzhpqgKA7MuXfIcp+ebiI5KsinMolvS5tEFl5CTJdqpvzxzCu4kgtkV W68qPoiXye05Mvr8HdPYp77FZLMlXO3KJrQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675777810320100005 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by MpInitLib in OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Signed-off-by: Yuanhao Xie Acked-by: Gerd Hoffmann Reviewed-by: Ard Biesheuvel --- OvmfPkg/AmdSev/AmdSevX64.dsc | 3 ++- OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/IntelTdx/IntelTdxX64.dsc | 4 +++- OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 2 ++ OvmfPkg/OvmfXen.dsc | 3 ++- 7 files changed, 12 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 36100f5fdc..1cafe0d5b3 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -3,7 +3,7 @@ # virtual machine remote attestation and secret injection # # Copyright (c) 2020 James Bottomley, IBM Corporation. -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -353,6 +353,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 7326417eab..36fb9bf2a2 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -404,6 +404,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX6= 4.dsc index 81511e3556..0a9b7f54d3 100644 --- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc +++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -313,6 +313,7 @@ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxDxeLib.inf PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf @@ -582,6 +583,7 @@ # Directly use DxeMpInitLib. It depends on DxeMpInitLibMpDepLib which # checks the Protocol of gEfiMpInitLibMpDepProtocolGuid. # + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.i= nf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NULL|OvmfPkg/Library/MpInitLibDepLib/DxeMpInitLibMpDepLib.inf } diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 2d53b5c295..b7fad2607f 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -403,6 +403,7 @@ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a9d422bd91..f21b78299f 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -414,6 +414,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 3f970a79a0..055bc72e57 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -434,6 +434,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf @@ -818,6 +819,7 @@ # Directly use DxeMpInitLib. It depends on DxeMpInitLibMpDepLib which # checks the Protocol of gEfiMpInitLibMpDepProtocolGuid. # + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.i= nf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NULL|OvmfPkg/Library/MpInitLibDepLib/DxeMpInitLibMpDepLib.inf } diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index c328987e84..bfa08c08e3 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) 2019, Citrix Systems, Inc. # Copyright (c) Microsoft Corporation. @@ -339,6 +339,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99740): https://edk2.groups.io/g/devel/message/99740 Mute This Topic: https://groups.io/mt/96807123/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 13:39:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99741+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99741+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675777813; cv=none; d=zohomail.com; s=zohoarc; b=lL4qrQtRHJCSi5jAiJstz6Iylus7Pd70BqGQMmWHCQMZQjlQ2thM//MiZ/5LwPl7yE1/4MZLO4ZLcYwORkvmAGM0xwiSUiOfuNi6IPZoYHbYaBfS+jjIUeA7VBRO9GhnGkxrnrTpBIk8XHpH1ZpCRTA9cWMZ8TDPGYvpiG0kewE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675777813; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=mTwxq+mIJhq7cPdAFG4wvXnu+4+WYvbTJV4dZAvwjAA=; b=Ga0j7HEwwKlwXMkG/Qc/AeMSZ73OONqboFuiZTZXK3eGHA4sG3cbpJL65KEsv/5+zsvf9B3OJxMD40ewDYDmzVnE1hr9QlrPEXwbMGbU07CYRz9Zo++1HFxGm4GnnV10V3b2+q9XSRqTSaRMxOKLZWS09krudsZ21gVEyz5jVLo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99741+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1675777813661985.7977999076436; Tue, 7 Feb 2023 05:50:13 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bp1LYY1788612x8kPghXW2Uz; Tue, 07 Feb 2023 05:50:13 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.83549.1675777797372123216 for ; Tue, 07 Feb 2023 05:50:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="329524684" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="329524684" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="660234285" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="660234285" X-Received: from xieyuanh-mobl.ccr.corp.intel.com ([10.255.31.127]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:10 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [PATCH 4/5] UefiPayloadPkg: Add CpuPageTableLib required by MpInitLib Date: Tue, 7 Feb 2023 21:49:38 +0800 Message-Id: <20230207134939.273-5-yuanhao.xie@intel.com> In-Reply-To: <20230207134939.273-1-yuanhao.xie@intel.com> References: <20230207134939.273-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: g528ONnqqfcZwWHdaDQPdLYNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675777813; bh=YqAYxkAHfHJHtOWhjwzvaaGlyuwr+6Ozt0COKo/1IYc=; h=Cc:Date:From:Reply-To:Subject:To; b=MyVczgX3XlUqtIAp6vZavuqHgUGo8hopxsRy6b6OXe1G33JqjvwIaiaoAUPCpq7lOZd qkznm9Kwmb21J0n7NnfqzBD9PYAhXALoZa7a7iST4mb641tj2DZLoAeXE8xxGjrdil3uY Jt94Or1j6k4mVwgzr/zikIeaKzeJniUJLB4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675777814317100002 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by MpInitLib in UefiPayloadPkg. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie Reviewed-by: Gua Guo =20 Reviewed-by: Guo Dong --- UefiPayloadPkg/UefiPayloadPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index 2dbd875f37..a1a3c74290 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -340,6 +340,7 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf !if $(PERFORMANCE_MEASUREMENT_ENABLE) PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#99741): https://edk2.groups.io/g/devel/message/99741 Mute This Topic: https://groups.io/mt/96807125/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 13:39:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+99742+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99742+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1675777817; cv=none; d=zohomail.com; s=zohoarc; b=eYaeLZczjPxZwNqSzmEJJI8ZqkgMeekBOd2BjC41f06ruIrHJKcnmgVk08i4e8AaF2joUwRe03eEvuT9WpDmRiDb1c3dxoP69oUms1hOUcZX73BSJT5W2RBzR38QMOvmzdjeR4B6GjTzvoAckmdbBo4NyPHEZ4fr8xV94ybIjO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675777817; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Q4VNKaT14HfaOLdLpR5sBCQXBLsxGDhq2GSq1R9Ap0Y=; b=XdiHds0hgkzf70WJ5dB4nUf8fIiGtcibTUjtY+eIcFmI+2AeSUBs6eNCAftQ6fDDr/9wuq9pfdjKaalEAQus/y3CV1wPo59uN4pAz0ORS4ClWAYtjKmmZpGTmVrwOXG+y/9yRVxDvMOSQJmUnw1PmKefffN9vlGqmhi3MwT+Gvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+99742+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 167577781719917.026786601765366; Tue, 7 Feb 2023 05:50:17 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6FmBYY1788612xU0SmRgG22h; Tue, 07 Feb 2023 05:50:16 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.83549.1675777797372123216 for ; Tue, 07 Feb 2023 05:50:16 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="329524699" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="329524699" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:16 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10614"; a="660234289" X-IronPort-AV: E=Sophos;i="5.97,278,1669104000"; d="scan'208";a="660234289" X-Received: from xieyuanh-mobl.ccr.corp.intel.com ([10.255.31.127]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2023 05:50:14 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [PATCH 5/5] UefiCpuPkg: Put APs in 64 bit mode before handoff to OS. Date: Tue, 7 Feb 2023 21:49:39 +0800 Message-Id: <20230207134939.273-6-yuanhao.xie@intel.com> In-Reply-To: <20230207134939.273-1-yuanhao.xie@intel.com> References: <20230207134939.273-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: SZjTHlwK87YsG7PpmgGNa1GUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1675777816; bh=/TA30yAPEFoYGfKB8epDTL1BXL46Ijahu0UIHeizJKE=; h=Cc:Date:From:Reply-To:Subject:To; b=T5SBBzjGT17iAIiRLMf9EVwEmFSQ7A96rGKS4+yL4oPBtiIZc3bdYsBXA+dFHbhQRJR F1CB0lE4I6QlC/hudY9EYmVkM7nwSPlhV+b7zwVyHY1OdAqKI9Ct2bt7yygAy/CFu44KQ pspOJBz2Xv3/pxh36PreVQ4nV9Oh5M19850= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1675777818389100002 Content-Type: text/plain; charset="utf-8" Only keep 4GB limitation of memory allocation for the case APs still need to be transferred to 32-bit mode before OS. Remove the unused arguments of AsmRelocateApLoopStart, updated the stack offset. Create PageTable for the allocated reserved memory. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 7 +- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 61 +++--- .../Library/MpInitLib/Ia32/CreatePageTable.c | 23 +++ .../Library/MpInitLib/Ia32/MpFuncs.nasm | 9 +- UefiCpuPkg/Library/MpInitLib/MpLib.h | 18 +- .../Library/MpInitLib/X64/CreatePageTable.c | 82 +++++++++ UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 173 +++--------------- UefiCpuPkg/UefiCpuPkg.dsc | 1 + 8 files changed, 193 insertions(+), 181 deletions(-) create mode 100644 UefiCpuPkg/Library/MpInitLib/Ia32/CreatePageTable.c create mode 100644 UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index cd07de3a3c..5507472379 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -1,7 +1,7 @@ ## @file # MP Initialize Library instance for DXE driver. # -# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -24,10 +24,12 @@ [Sources.IA32] Ia32/AmdSev.c Ia32/MpFuncs.nasm + Ia32/CreatePageTable.c =20 [Sources.X64] X64/AmdSev.c X64/MpFuncs.nasm + X64/CreatePageTable.c =20 [Sources.common] AmdSev.c @@ -57,6 +59,9 @@ CcExitLib MicrocodeLib =20 +[LibraryClasses.X64] + CpuPageTableLib + [Protocols] gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES =20 diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 7b51c5c7f7..92b6df7f68 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -28,6 +28,7 @@ volatile BOOLEAN mStopCheckAllApsStatus =3D = TRUE; UINTN mReservedTopOfApStack; volatile UINT32 mNumberToFinish =3D 0; RELOCATE_AP_LOOP_ENTRY mReservedApLoop; +UINTN mApPageTable; =20 // // Begin wakeup buffer allocation below 0x88000 @@ -378,10 +379,10 @@ RelocateApLoop ( IN OUT VOID *Buffer ) { - CPU_MP_DATA *CpuMpData; - BOOLEAN MwaitSupport; - UINTN ProcessorNumber; - UINTN StackStart; + CPU_MP_DATA *CpuMpData; + BOOLEAN MwaitSupport; + UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); @@ -403,12 +404,9 @@ RelocateApLoop ( mReservedApLoop.GenericEntry ( MwaitSupport, CpuMpData->ApTargetCState, - CpuMpData->PmCodeSegment, StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, (UINTN)&mNumberToFinish, - CpuMpData->Pm16CodeSegment, - CpuMpData->SevEsAPBuffer, - CpuMpData->WakeupBuffer + mApPageTable ); } =20 @@ -480,7 +478,7 @@ InitMpGlobalData ( UINTN StackBase; CPU_INFO_IN_HOB *CpuInfoInHob; EFI_PHYSICAL_ADDRESS Address; - UINT8 *ApLoopFuncData; + UINT8 *ApLoopFunc; UINTN ApLoopFuncSize; =20 SaveCpuMpData (CpuMpData); @@ -541,13 +539,15 @@ InitMpGlobalData ( // // 64-bit AMD Processor // - ApLoopFuncData =3D AddressMap->RelocateApLoopFuncAddressAmd64; + Address =3D BASE_4GB - 1; + ApLoopFunc =3D AddressMap->RelocateApLoopFuncAddressAmd64; ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSizeAmd64; } else { // // Intel Processor (32-bit or 64-bit), or 32-bit AMD Processor // - ApLoopFuncData =3D AddressMap->RelocateApLoopFuncAddress; + Address =3D MAX_ADDRESS; + ApLoopFunc =3D AddressMap->RelocateApLoopFuncAddress; ApLoopFuncSize =3D AddressMap->RelocateApLoopFuncSize; } =20 @@ -559,17 +559,17 @@ InitMpGlobalData ( // Allocating it in advance since memory services are not available in // Exit Boot Services callback function. // + // +------------+ (TopOfApStack) + // | Stack * N | // +------------+ - // | Ap Loop | + // | Padding | // +------------+ - // | Stack * N | - // +------------+ (low address) + // | Ap Loop | + // +------------+ (low address ) // - Address =3D BASE_4GB - 1; - STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) =3D=3D 0= , "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT"); AllocSize =3D EFI_PAGES_TO_SIZE ( EFI_SIZE_TO_PAGES ( - CpuMpData->CpuCount * AP_SAFE_STACK_SIZE + ApLoopFuncSize + CpuMpData->CpuCount * AP_SAFE_STACK_SIZE + ALIGN_VALUE (= ApLoopFuncSize, EFI_PAGE_SIZE) ) ); Status =3D gBS->AllocatePages ( @@ -591,17 +591,28 @@ InitMpGlobalData ( // Status =3D gDS->GetMemorySpaceDescriptor (Address, &MemDesc); if (!EFI_ERROR (Status)) { - gDS->SetMemorySpaceAttributes ( - Address, - ApLoopFuncSize, - MemDesc.Attributes & (~EFI_MEMORY_XP) - ); + Status =3D gDS->SetMemorySpaceAttributes ( + Address, + ALIGN_VALUE (ApLoopFuncSize, EFI_PAGE_SIZE), + MemDesc.Attributes & (~EFI_MEMORY_XP) + ); + ASSERT_EFI_ERROR (Status); } =20 - mReservedTopOfApStack =3D ((UINTN)Address + CpuMpData->CpuCount * AP_SAF= E_STACK_SIZE); + mReservedTopOfApStack =3D (UINTN)Address + AllocSize; ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) =3D= =3D 0); - mReservedApLoop.Data =3D (VOID *)mReservedTopOfApStack; - CopyMem (mReservedApLoop.Data, ApLoopFuncData, ApLoopFuncSize); + mReservedApLoop.Data =3D (VOID *)(UINTN)Address; + CopyMem (mReservedApLoop.Data, ApLoopFunc, ApLoopFuncSize); + + if (!StandardSignatureIsAuthenticAMD () && (sizeof (UINTN) =3D=3D sizeof= (UINT64))) { + // + // 64-bit Intel Processor + // + mApPageTable =3D CreatePageTable ( + (UINTN)Address, + AllocSize + ); + } =20 Status =3D gBS->CreateEvent ( EVT_TIMER | EVT_NOTIFY_SIGNAL, diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/CreatePageTable.c b/UefiCpuP= kg/Library/MpInitLib/Ia32/CreatePageTable.c new file mode 100644 index 0000000000..76328c38f1 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/CreatePageTable.c @@ -0,0 +1,23 @@ +/** @file + Function to create page talbe. + Only create page table for x64, and leave the CreatePageTable empty for = Ia32. + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Only create page table for x64, and leave the CreatePageTable empty for = Ia32. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @return The page table to be created. +**/ +UINTN +CreatePageTable ( + IN UINTN Address, + IN UINTN Length + ) +{ + return 0; +} diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index bfcdbd31c1..5cffa632ab 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -219,20 +219,17 @@ SwitchToRealProcEnd: RendezvousFunnelProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); -; -; The last three parameters (Pm16CodeSegment, SevEsAPJumpTable and Wakeup= Buffer) are -; specific to SEV-ES support and are not applicable on IA32. +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, TopOfApStack, CountTof= inish, Cr3); ;-------------------------------------------------------------------------= ------------ AsmRelocateApLoopStart: mov eax, esp - mov esp, [eax + 16] ; TopOfApStack + mov esp, [eax + 12] ; TopOfApStack push dword [eax] ; push return address for stack trace push ebp mov ebp, esp mov ebx, [eax + 8] ; ApTargetCState mov ecx, [eax + 4] ; MwaitSupport - mov eax, [eax + 20] ; CountTofinish + mov eax, [eax + 16] ; CountTofinish lock dec dword [eax] ; (*CountTofinish)-- cmp cl, 1 ; Check mwait-monitor support jnz HltLoop diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index f1b9063e78..b0acf82ab1 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -313,6 +313,7 @@ typedef struct { =20 #define AP_SAFE_STACK_SIZE 128 #define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE +STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) =3D=3D 0, = "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT"); =20 #pragma pack(1) =20 @@ -367,12 +368,9 @@ typedef (EFIAPI *ASM_RELOCATE_AP_LOOP)( IN BOOLEAN MwaitSupport, IN UINTN ApTargetCState, - IN UINTN PmCodeSegment, IN UINTN TopOfApStack, IN UINTN NumberToFinish, - IN UINTN Pm16CodeSegment, - IN UINTN SevEsAPJumpTable, - IN UINTN WakeupBuffer + IN UINTN Cr3 ); =20 /** @@ -501,6 +499,18 @@ GetSevEsAPMemory ( VOID ); =20 +/** + Create 1:1 mapping page table in reserved memory to map the specified ad= dress range. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @return The page table to be created. +**/ +UINTN +CreatePageTable ( + IN UINTN Address, + IN UINTN Length + ); + /** This function will be called by BSP to wakeup AP. =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c b/UefiCpuPk= g/Library/MpInitLib/X64/CreatePageTable.c new file mode 100644 index 0000000000..1341477e52 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c @@ -0,0 +1,82 @@ +/** @file + Function to create page talbe. + Only create page table for x64, and leave the CreatePageTable empty for = Ia32. + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include +#include +#include +#include +#include + +/** + Create 1:1 mapping page table in reserved memory to map the specified ad= dress range. + @param[in] LinearAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @return The page table to be created. +**/ +UINTN +CreatePageTable ( + IN UINTN Address, + IN UINTN Length + ) +{ + EFI_STATUS Status; + VOID *PageTableBuffer; + UINTN PageTableBufferSize; + UINTN PageTable; + PAGING_MODE PagingMode; + IA32_CR4 Cr4; + + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + + MapAttribute.Uint64 =3D Address; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + + MapMask.Bits.PageTableBaseAddress =3D 1; + MapMask.Bits.Present =3D 1; + MapMask.Bits.ReadWrite =3D 1; + + PageTable =3D 0; + PageTableBufferSize =3D 0; + + Cr4.UintN =3D AsmReadCr4 (); + + if (Cr4.Bits.LA57 =3D=3D 1) { + PagingMode =3D Paging5Level; + } else { + PagingMode =3D Paging4Level; + } + + Status =3D PageTableMap ( + &PageTable, + PagingMode, + NULL, + &PageTableBufferSize, + Address, + Length, + &MapAttribute, + &MapMask + ); + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", PageTableBuffe= rSize)); + + PageTableBuffer =3D AllocateReservedPages (EFI_SIZE_TO_PAGES (PageTableB= ufferSize)); + ASSERT (PageTableBuffer !=3D NULL); + Status =3D PageTableMap ( + &PageTable, + PagingMode, + PageTableBuffer, + &PageTableBufferSize, + Address, + Length, + &MapAttribute, + &MapMask + ); + ASSERT_EFI_ERROR (Status); + return PageTable; +} diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index cd40099ae4..4ba6a62e4a 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -279,172 +279,55 @@ CProcedureInvoke: RendezvousFunnelProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, TopOfApStack, CountTof= inish, Cr3); +; This function is called during the finalizaiton of Mp initialization be= fore booting +; to OS, and aim to put Aps either in Mwait or HLT. ;-------------------------------------------------------------------------= ------------ -AsmRelocateApLoopStart: -BITS 64 - cmp qword [rsp + 56], 0 ; SevEsAPJumpTable - je NoSevEs - - ; - ; Perform some SEV-ES related setup before leaving 64-bit mode - ; - push rcx - push rdx - - ; - ; Get the RDX reset value using CPUID - ; - mov rax, 1 - cpuid - mov rsi, rax ; Save off the reset value for RDX - - ; - ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call - ; - Must be done while in 64-bit long mode so that writes to - ; the GHCB memory will be unencrypted. - ; - No NAE events can be generated once this is set otherwise - ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. - ; - mov rcx, 0xc0010130 - rdmsr ; Retrieve current GHCB address - shl rdx, 32 - or rdx, rax - - mov rdi, rdx - xor rax, rax - mov rcx, 0x800 - shr rcx, 3 - rep stosq ; Clear the GHCB - - mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD - mov [rdx + 0x390], rax - mov rax, 114 ; Set SwExitCode valid bit - bts [rdx + 0x3f0], rax - inc rax ; Set SwExitInfo1 valid bit - bts [rdx + 0x3f0], rax - inc rax ; Set SwExitInfo2 valid bit - bts [rdx + 0x3f0], rax +; +----------------+ +; | Cr3 | rsp+40 +; +----------------+ +; | CountTofinish | r9 +; +----------------+ +; | TopOfApStack | r8 +; +----------------+ +; | ApTargetCState | rdx +; +----------------+ +; | MwaitSupport | rcx +; +----------------+ +; | the return | +; +----------------+ low address =20 - pop rdx - pop rcx - -NoSevEs: - cli ; Disable interrupt before switching to 3= 2-bit mode - mov rax, [rsp + 40] ; CountTofinish +AsmRelocateApLoopStart: + mov rax, r9 ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- =20 - mov r10, [rsp + 48] ; Pm16CodeSegment - mov rax, [rsp + 56] ; SevEsAPJumpTable - mov rbx, [rsp + 64] ; WakeupBuffer - mov rsp, r9 ; TopOfApStack - - push rax ; Save SevEsAPJumpTable - push rbx ; Save WakeupBuffer - push r10 ; Save Pm16CodeSegment - push rcx ; Save MwaitSupport - push rdx ; Save ApTargetCState - - lea rax, [PmEntry] ; rax <- The start address of transition = code - - push r8 - push rax - - ; - ; Clear R8 - R15, for reset, before going into 32-bit mode - ; - xor r8, r8 - xor r9, r9 - xor r10, r10 - xor r11, r11 - xor r12, r12 - xor r13, r13 - xor r14, r14 - xor r15, r15 - - ; - ; Far return into 32-bit mode - ; - retfq - -BITS 32 -PmEntry: - mov eax, cr0 - btr eax, 31 ; Clear CR0.PG - mov cr0, eax ; Disable paging and caches - - mov ecx, 0xc0000080 - rdmsr - and ah, ~ 1 ; Clear LME - wrmsr - mov eax, cr4 - and al, ~ (1 << 5) ; Clear PAE - mov cr4, eax - - pop edx - add esp, 4 - pop ecx, - add esp, 4 + mov rax, [rsp + 40] ; Cr3 + ; Do not push on old stack, since old stack is not mapped + ; in the page table pointed by cr3 + mov cr3, rax + mov rsp, r8 ; TopOfApStack =20 MwaitCheck: cmp cl, 1 ; Check mwait-monitor support jnz HltLoop - mov ebx, edx ; Save C-State to ebx + mov rbx, rdx ; Save C-State to ebx + MwaitLoop: cli - mov eax, esp ; Set Monitor Address + mov rax, rsp ; Set Monitor Address xor ecx, ecx ; ecx =3D 0 xor edx, edx ; edx =3D 0 monitor - mov eax, ebx ; Mwait Cx, Target C-State per eax[7:4] + mov rax, rbx ; Mwait Cx, Target C-State per eax[7:4] shl eax, 4 mwait jmp MwaitLoop =20 HltLoop: - pop edx ; PM16CodeSegment - add esp, 4 - pop ebx ; WakeupBuffer - add esp, 4 - pop eax ; SevEsAPJumpTable - add esp, 4 - cmp eax, 0 ; Check for SEV-ES - je DoHlt - - cli - ; - ; SEV-ES is enabled, use VMGEXIT (GHCB information already - ; set by caller) - ; -BITS 64 - rep vmmcall -BITS 32 - - ; - ; Back from VMGEXIT AP_HLT_LOOP - ; Push the FLAGS/CS/IP values to use - ; - push word 0x0002 ; EFLAGS - xor ecx, ecx - mov cx, [eax + 2] ; CS - push cx - mov cx, [eax] ; IP - push cx - push word 0x0000 ; For alignment, will be discarded - - push edx - push ebx - - mov edx, esi ; Restore RDX reset value - - retf - -DoHlt: cli hlt - jmp DoHlt + jmp HltLoop =20 -BITS 64 AsmRelocateApLoopEnd: =20 ;-------------------------------------------------------------------------= ------------ diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f9a46089d2..781acedfc5 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -94,6 +94,7 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegi= sterCpuFeaturesLib.inf CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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