From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98788+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98788+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1674035786; cv=none; d=zohomail.com; s=zohoarc; b=FATNTVU4Sw+x4+IGJC4q7rgfjIMA/kIE8odedUORkC6gR0K+qDfJE8m1Xy7hOX+oYTxQtsMkj0bJAc/QLtzErHGiwrHrGPV+TUxLxQpnNj4IdTJ0kGAtadfywnR6t1rqIIr4v78a2zVSB/DpMm9wzoh1w75/xp8kCOdQDuDmaQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674035786; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=tlfVKII39DhmrZSXpt9rLdWIB8v0h98fgHuZRVYxhFc=; b=IhFY+BRncH2QBxL8QyMclRJprnSXwox9z4gjSIACmBlYF+poMefIuRRsQtvGGEVlIOr1kBtV/Ke39OUL+bjpedRwlW9WUfCfLT3opp1RDtrg+JE1vm6t9VLPXxsWG+SYzgTdS1v7PJyJhJrcFJMiZyt6qtc7QHhk03ApVfuxcCI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98788+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674035786110694.47348302384; Wed, 18 Jan 2023 01:56:26 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9uP6YY1788612xeOjXEtWdnx; Wed, 18 Jan 2023 01:56:25 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.11831.1674035783379019296 for ; Wed, 18 Jan 2023 01:56:25 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="411184039" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="411184039" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2023 01:56:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="723026300" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="723026300" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by fmsmga008.fm.intel.com with ESMTP; 18 Jan 2023 01:56:23 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 1/5] UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB Data Date: Wed, 18 Jan 2023 17:56:16 +0800 Message-Id: <20230118095620.9860-2-jiaxin.wu@intel.com> In-Reply-To: <20230118095620.9860-1-jiaxin.wu@intel.com> References: <20230118095620.9860-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: k5QLRm0eI28hVVlt7F9h437Nx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674035785; bh=VLa/ToEpLdRAV6l5SZGRBkyoRGOPZ4Cnj/NYKZOWa8A=; h=Cc:Date:From:Reply-To:Subject:To; b=FCzEqBIOpn7xEu9uSF8rEKwyjAkeTQtQ7jkHMSWUuFHPVbmbsExR3ITnstoykJBoxMy qEKojHU4PpSDJgIcQt3sm7mOgCw5eH5aev8VhQg9i+ltQv3rwqli4d2mp/8v+KmECU6Hm 8afLuSVNUPoSwdXjW7OcmxZ+/FF7wS9ZLic= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674035787278100005 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The default SMBASE for the x86 processor is 0x30000. When SMI happens, CPU runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from CPU perspective is to relocate and program the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relocation happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program the new SMBASE itself. This patch adds the SMM Base HOB for any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for reach Processors. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 46 ++++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 2 files changed, 49 insertions(+) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid= /SmmBaseHob.h new file mode 100644 index 0000000000..488c0b76e9 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,46 @@ +/** @file + The Smm Base HOB is used to store the information of: + * The relocated SmBase address in array for each Processors. + + The default SMBASE for the x86 processor is 0x30000. When SMI happens, C= PU + runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is = within + SMBASE+0x10000. + + One of the SMM initialization from CPU perspective is to relocate and pr= ogram + the new SMBASE (in TSEG range) for each CPU thread. When the SMBASE relo= cation + happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB i= n HOB + database which tells the PiSmmCpuDxeSmm driver (which runs at a later ph= ase) + about the new SMBASE for each CPU thread. PiSmmCpuDxeSmm driver installs= the + SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for CPU thread Inde= x. + When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and pro= gram + the new SMBASE itself. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d,= 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// Describes the Number of all max supported processors. + /// + UINT64 NumberOfProcessors; + /// + /// Pointer to SmBase address for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..2afd08cdd2 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} =20 + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid =3D { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c= , 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94= , 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid =3D { 0xaa00d50b, 0x4911, 0x428f, { 0= xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98788): https://edk2.groups.io/g/devel/message/98788 Mute This Topic: https://groups.io/mt/96350760/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98789+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98789+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1674035788; cv=none; d=zohomail.com; s=zohoarc; b=RLU7eR5kPKPIhShuP+anBLFWUUwRS7iWUSj3ctYJtABSp2cpFTRL8Ltp/FA8iz2H2PRWm2fyN0NpYHRhGX1tK2tSWLc1fDT55seoHmlADrH8dNA5S8c9ylqKeE6NpT8EU4hravlvfOH/aCmiLVhfs62eAdP/15rTjBdQOIRxqxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674035788; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZVxeZTpdnBVt8a2P8OTaet6CilJdYbeZV5yCjZclaxA=; b=A5ITia0gkELvt0UhO5UGlDPvif5APyG3740YxNRHnMaGeDJ89HhztKAhENHlF/B5B9HjZpfXzlQzei8njy3zgrE8uaSIjBeabnNBAWanCwD9xDRWxNcBl6uMtiwv43cj5woE03tQZFhCiLjLKVyy9C+uAmSztQD62eQ4tndNNWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98789+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674035788532923.6793346601993; Wed, 18 Jan 2023 01:56:28 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZNK5YY1788612xqhnOBbHP2y; Wed, 18 Jan 2023 01:56:28 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.11831.1674035783379019296 for ; Wed, 18 Jan 2023 01:56:27 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="411184065" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="411184065" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2023 01:56:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="723026331" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="723026331" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by fmsmga008.fm.intel.com with ESMTP; 18 Jan 2023 01:56:25 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 2/5] UefiCpuPkg/PiSmmCpuDxeSmm: Fix invalid InitializeMpSyncData call Date: Wed, 18 Jan 2023 17:56:17 +0800 Message-Id: <20230118095620.9860-3-jiaxin.wu@intel.com> In-Reply-To: <20230118095620.9860-1-jiaxin.wu@intel.com> References: <20230118095620.9860-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: Jy0rEseuNfoF4MLjdP9AVouHx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674035788; bh=Gy20SNDEjGAt18CyysTMOHzX9nSEmDThYbIDzq446sY=; h=Cc:Date:From:Reply-To:Subject:To; b=jJQnfoQnjCm8HtWoZawazef4NiDJq3gz7CRHtl21iHwrm+MAtAnDKpr1/esd+bA2IFt TW3gnd9SQgagq3LJGvw+KlPx4ZBhG/XLpJwrgIo3hiT0z471ueIHLtDU9qNnj8T2izwU8 ptJUCI6AHJXrKGfQNbyPZgngxgs3Bi6y9X8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674035789278100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No need call InitializeMpSyncData during normal boot SMI init, because mSmmMpSyncData is NULL at that time. mSmmMpSyncData is allocated in InitializeMpServiceData, which is invoked after normal boot SMI init (SmmRelocateBases). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..f723b1d253 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -369,13 +369,11 @@ SmmInitHandler ( if (!mSmmS3Flag) { // // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); - } - - if (mIsBsp) { + } else if (mIsBsp) { // // BSP rebase is already done above. // Initialize private data during S3 resume // InitializeMpSyncData (); --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98789): https://edk2.groups.io/g/devel/message/98789 Mute This Topic: https://groups.io/mt/96350761/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98790+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98790+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1674035790; cv=none; d=zohomail.com; s=zohoarc; b=IGEdZnElhciOz1IMtTpjtRxp0YnpoaBrVTq52ItFHh8LPjIq7Xd4PkVlO/kzsr5TE3X5gBVfF1rbbosqeqebf5wM47Rcl+RWyF60WiYzYbkygve3hw4K4QnPNCxREszliqfC3vkI5mjVClW/6MyYB8IbE3F81oP0EatuKxPOF2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674035790; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=BAfyfhUoga/Tfsqeenllf7WNPnVkiU4PApNBXoNXdpU=; b=oF5qdCo66Uv2mtCWbtUuUr+um9j3fQrTBx7c8Rq34IDoEo7yib4jozyYDOlpbx0/kQp1i0uwuFhpbWkry1sJvaDOohMjiva05X2ce5fdfaGdylujm0w5C1ozg53kDLBNY+MlYju68Gf67PIa38V8rmg7Fur4UgGgHG8Kt2qBSkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98790+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674035790641336.554733804041; Wed, 18 Jan 2023 01:56:30 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id EOUbYY1788612xL4SIwux61k; Wed, 18 Jan 2023 01:56:30 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.11831.1674035783379019296 for ; Wed, 18 Jan 2023 01:56:29 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="411184089" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="411184089" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2023 01:56:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="723026366" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="723026366" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by fmsmga008.fm.intel.com with ESMTP; 18 Jan 2023 01:56:27 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 3/5] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info Date: Wed, 18 Jan 2023 17:56:18 +0800 Message-Id: <20230118095620.9860-4-jiaxin.wu@intel.com> In-Reply-To: <20230118095620.9860-1-jiaxin.wu@intel.com> References: <20230118095620.9860-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: cduT8CPm5uoRkrKpQCitbnPFx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674035790; bh=Sl/NZUEyfPPOM/n67d+eRBVjhN1KGVdoyTZI1XG9EhY=; h=Cc:Date:From:Reply-To:Subject:To; b=btzH40r2fxUiICOKTXQ6uKht7BMb2p1xA+UOghdZaU9FfTSflq5yn8enImKn8wTEtQi EJinD1pwIXKK9SRw2Srkg20hhyTd8waYaMciea+bfgawCwDlJ3Ujr2Eg9Zb4STvKJrJ0i Mmv/k090VInJto9AGlH4nnYpi7CqudzKPWI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674035791410100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PiSmmCpuDxeSmm shall retrieve the SMBASE addresses from SMM Base Hob and installs the SMI handler at [SMBASE+8000h] for each processor instead of relocating SMM Base addresses from SMRAM again if SMM Base Hob existed. With SMM Base Hob, PiSmmCpuDxeSmm does not need the RSM instruction to reload the SMBASE register with the new allocated SMBASE each time when it exits SMM. SMBASE Register for each processors have already been programmed and all SMBASE address have recorded in SMM Base Hob. So the same default SMBASE Address (0x30000) will not be used, thus the CPUs over-writing each other's SMM Save State Area will not happen in PiSmmCpuDxeSmm driver. This way makes the first SMI init can be executed in parallel and save boot time on multi-core system. Mainly changes as below: *Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. *Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for first SMI init before normal SMI sources happen. *Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 29 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 23 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 182 +++++++++++++++++++++--= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 24 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 5 files changed, 217 insertions(+), 42 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index fb4a44eab6..39c0b002f0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -822,13 +822,38 @@ SmmRestoreCpu ( // InitializeCpuBeforeRebase (); } =20 // - // Restore SMBASE for BSP and all APs + // Make sure the gSmmBaseHobGuid existence status is the same between no= rmal and S3 boot. // - SmmRelocateBases (); + ASSERT (mSmmRelocated =3D=3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid= ) !=3D NULL)); + if (mSmmRelocated !=3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) !=3D= NULL)) { + DEBUG (( + DEBUG_ERROR, + "gSmmBaseHobGuid %a produced in normal boot but %a in S3 boot!", + mSmmRelocated ? "is" : "is not", + mSmmRelocated ? "is not" : "is" + )); + CpuDeadLoop (); + } + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! + // + if (!mSmmRelocated) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execut= e first SMI init. + // + ExecuteFirstSmiInit (); + } =20 // // Skip initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index a0967eb69c..3744f35214 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1721,17 +1721,40 @@ SmiRendezvous ( UINTN Index; UINTN Cr2; =20 ASSERT (CpuIndex < mMaxNumberOfCpus); =20 + if (mSmmRelocated) { + ASSERT (mSmmInitialized !=3D NULL); + } + // // Save Cr2 because Page Fault exception in SMM may override its value, // when using on-demand paging for above 4G memory. // Cr2 =3D 0; SaveCr2 (&Cr2); =20 + if (mSmmRelocated && !mSmmInitialized[CpuIndex]) { + // + // Perform SmmInitHandler for CpuIndex + // + SmmInitHandler (); + + // + // Restore Cr2 + // + RestoreCr2 (Cr2); + + // + // Mark the first SMI init for CpuIndex has been done so as to avoid t= he reentry. + // + mSmmInitialized[CpuIndex] =3D TRUE; + + return; + } + // // Call the user register Startup function first. // if (mSmmMpSyncData->StartupProcedure !=3D NULL) { mSmmMpSyncData->StartupProcedure (mSmmMpSyncData->StartupProcArgs); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index f723b1d253..a39d8528db 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -57,11 +57,10 @@ SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate =3D &mSmmCpuPriva= teData; =20 // // SMM Relocation variables // volatile BOOLEAN *mRebased; -volatile BOOLEAN mIsBsp; =20 /// /// Handle for the SMM CPU Protocol /// EFI_HANDLE mSmmCpuHandle =3D NULL; @@ -83,10 +82,14 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribut= e =3D { EdkiiSmmClearMemoryAttributes }; =20 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; =20 +BOOLEAN mSmmRelocated =3D FALSE; +BOOLEAN *mSmmInitialized =3D NULL; +UINT32 mBspApicId =3D 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -341,58 +344,108 @@ VOID EFIAPI SmmInitHandler ( VOID ) { - UINT32 ApicId; - UINTN Index; + UINT32 ApicId; + UINTN Index; + BOOLEAN IsBsp; =20 // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId =3D GetApicId (); =20 + IsBsp =3D (BOOLEAN)(mBspApicId =3D=3D ApicId); + ASSERT (mNumberOfCpus <=3D mMaxNumberOfCpus); =20 for (Index =3D 0; Index < mNumberOfCpus; Index++) { if (ApicId =3D=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Process= orId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsBsp, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); =20 if (!mSmmS3Flag) { // // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); - } else if (mIsBsp) { + } else if (IsBsp) { // // BSP rebase is already done above. // Initialize private data during S3 resume // InitializeMpSyncData (); } =20 - // - // Hook return after RSM to set SMM re-based flag - // - SemaphoreHook (Index, &mRebased[Index]); + if (!mSmmRelocated) { + // + // Hook return after RSM to set SMM re-based flag + // + SemaphoreHook (Index, &mRebased[Index]); + } =20 return; } } =20 ASSERT (FALSE); } =20 +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute firs= t SMI init. + +**/ +VOID +ExecuteFirstSmiInit ( + VOID + ) +{ + UINTN Index; + + if (mSmmInitialized =3D=3D NULL) { + mSmmInitialized =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * mMaxNu= mberOfCpus); + } + + ASSERT (mSmmInitialized !=3D NULL); + if (mSmmInitialized =3D=3D NULL) { + return; + } + + // + // Reset the mSmmInitialized to false. + // + ZeroMem (mSmmInitialized, sizeof (BOOLEAN) * mMaxNumberOfCpus); + + // + // Get the BSP ApicId. + // + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] =3D=3D FALSE) { + } + } +} + /** Relocate SmmBases for each processor. =20 Execute on first boot and all S3 resumes =20 @@ -405,11 +458,10 @@ SmmRelocateBases ( { UINT8 BakBuf[BACK_BUF_SIZE]; SMRAM_SAVE_STATE_MAP BakBuf2; SMRAM_SAVE_STATE_MAP *CpuStatePtr; UINT8 *U8Ptr; - UINT32 ApicId; UINTN Index; UINTN BspIndex; =20 // // Make sure the reserved size is large enough for procedure SmmInitTemp= late. @@ -446,21 +498,20 @@ SmmRelocateBases ( CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize); =20 // // Retrieve the local APIC ID of current processor // - ApicId =3D GetApicId (); + mBspApicId =3D GetApicId (); =20 // // Relocate SM bases for all APs // This is APs' 1st SMI - rebase will be done here, and APs' default SMI= handler will be overridden by gcSmmInitTemplate // - mIsBsp =3D FALSE; BspIndex =3D (UINTN)-1; for (Index =3D 0; Index < mNumberOfCpus; Index++) { mRebased[Index] =3D FALSE; - if (ApicId !=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Processor= Id) { + if (mBspApicId !=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Proce= ssorId) { SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId= ); // // Wait for this AP to finish its 1st SMI // while (!mRebased[Index]) { @@ -475,12 +526,11 @@ SmmRelocateBases ( =20 // // Relocate BSP's SMM base // ASSERT (BspIndex !=3D (UINTN)-1); - mIsBsp =3D TRUE; - SendSmiIpi (ApicId); + SendSmiIpi (mBspApicId); // // Wait for the BSP to finish its 1st SMI // while (!mRebased[BspIndex]) { } @@ -559,10 +609,15 @@ PiCpuSmmEntry ( UINT32 RegEcx; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; UINT32 Cr3; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmBaseHobData; + + GuidHob =3D NULL; + SmmBaseHobData =3D NULL; =20 // // Initialize address fixup // PiSmmCpuSmmInitFixupAddress (); @@ -787,30 +842,55 @@ PiCpuSmmEntry ( // context must be reduced. // ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // - // Allocate buffer for all of the tiles. + // Check whether the Required TileSize is enough. // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.11 SMBASE Relocation - // For Pentium and Intel486 processors, the SMBASE values must be - // aligned on a 32-KByte boundary or the processor will enter shutdown - // state during the execution of a RSM instruction. + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Re= quired TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE_8= KB)); + CpuDeadLoop (); + return RETURN_BUFFER_TOO_SMALL; + } + // - // Intel486 processors: FamilyId is 4 - // Pentium processors : FamilyId is 5 + // Retrive the allocated SmmBase from gSmmBaseHobGuid. If found, + // means the SmBase relocation has been done. // - BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfC= pus - 1)); - if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + GuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); + if (GuidHob !=3D NULL) { + SmmBaseHobData =3D GET_GUID_HOB_DATA (GuidHob); + + ASSERT (SmmBaseHobData->NumberOfProcessors =3D=3D mMaxNumberOfCpus); + mSmmRelocated =3D TRUE; } else { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); - } + // + // When the HOB doesn't exist, allocate new SMBASE itself. + // + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + // + // Allocate buffer for all of the tiles. + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.11 SMBASE Relocation + // For Pentium and Intel486 processors, the SMBASE values must be + // aligned on a 32-KByte boundary or the processor will enter shutdo= wn + // state during the execution of a RSM instruction. + // + // Intel486 processors: FamilyId is 4 + // Pentium processors : FamilyId is 5 + // + BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberO= fCpus - 1)); + if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + } else { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); + } =20 - ASSERT (Buffer !=3D NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer,= EFI_PAGES_TO_SIZE (BufferPages))); + ASSERT (Buffer !=3D NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%= 08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } =20 // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // gSmmCpuPrivate->ProcessorInfo =3D (EFI_PROCESSOR_INFORMATION *)AllocateP= ool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); @@ -841,11 +921,12 @@ PiCpuSmmEntry ( // Retrieve APIC ID of each enabled processor from the MP Services proto= col. // Also compute the SMBASE address, CPU Save State address, and CPU Save= state // size for each CPU in the platform // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Ti= leSize - SMM_HANDLER_OFFSET; + mCpuHotPlugData.SmBase[Index] =3D mSmmRelocated ? (UINTN)SmmBaseHobDat= a->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof (SMRAM_SAVE_STATE_M= AP); gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { @@ -954,21 +1035,27 @@ PiCpuSmmEntry ( // Initialize IDT // InitializeSmmIdt (); =20 // - // Relocate SMM Base addresses to the ones allocated from SMRAM + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberO= fCpus); - ASSERT (mRebased !=3D NULL); - SmmRelocateBases (); + if (!mSmmRelocated) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumbe= rOfCpus); + ASSERT (mRebased !=3D NULL); + SmmRelocateBases (); =20 - // - // Call hook for BSP to perform extra actions in normal mode after all - // SMM base addresses have been relocated on all CPUs - // - SmmCpuFeaturesSmmRelocationComplete (); + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } =20 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); =20 // // SMM Time initialization @@ -995,10 +1082,25 @@ PiCpuSmmEntry ( ); } } } =20 + // + // For relocated SMBASE, some MSRs & CSRs are still required to be confi= gured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM I= PI) to execute first SMI init. + // + if (mSmmRelocated) { + ExecuteFirstSmiInit (); + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + // // Fill in SMM Reserved Regions // gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart =3D 0; gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize =3D 0; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 5f0a38e400..50c9695c4f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -23,10 +23,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =20 #include #include #include +#include =20 #include #include #include #include @@ -346,10 +347,29 @@ SmmWriteSaveState ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer ); =20 +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID + ); + +/** + Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute firs= t SMI init. + +**/ +VOID +ExecuteFirstSmiInit ( + VOID + ); + /** Read a CPU Save State register on the target processor. =20 This function abstracts the differences that whether the CPU Save State re= gister is in the IA32 CPU Save State Map or X64 CPU Save State Map. @@ -400,10 +420,14 @@ WriteSaveStateRegister ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ); =20 +extern BOOLEAN mSmmRelocated; +extern BOOLEAN *mSmmInitialized; +extern UINT32 mBspApicId; + extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; extern UINT32 mSmmCr0; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index b4b327f60c..6dbed17b96 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -112,10 +112,11 @@ =20 [Guids] gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # = it is used for S3 boot. gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONS= UMES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98790): https://edk2.groups.io/g/devel/message/98790 Mute This Topic: https://groups.io/mt/96350762/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98791+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98791+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1674035793; cv=none; d=zohomail.com; s=zohoarc; b=AaGt5PVU7fPyIzulilSffECrC9cnAmvmEsjIR0nBHRJUPXSQWT2zGsD9BMbh/mRMxswmrQiAJ9fsYJcKltUD+Om7uWmwj98a97WLlXphOM4sRf222jAlwQkEf9PH9HfRqaSZLTSxgWdMij+j8GtfN99DeScTczQvU1B/MNhoRhM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674035793; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=f+oHseXW263q8Yr4WYSSrKAbZw5ahr+mOFl3urAqKZQ=; b=BtNlR9EZVsA8CNVr558nFZfTM1+Ql5Pr0GKrTLIxrWd+a4lWOgMdHrXsbmj4KYMZCePdzBJWVjq1o+RTLiAkVQzW/1l6F4djMHsIRKCTs9f4LIv2Cta4+kQnQ3J9UrgR1MZ0cQ3MrLwuQUIUIe0jzNcFaQ8JFzU55OHiCv7b6WM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98791+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674035793226901.8928074705613; Wed, 18 Jan 2023 01:56:33 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2EnzYY1788612xydXROhXYPL; Wed, 18 Jan 2023 01:56:32 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.11831.1674035783379019296 for ; Wed, 18 Jan 2023 01:56:32 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="411184114" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="411184114" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2023 01:56:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="723026394" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="723026394" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by fmsmga008.fm.intel.com with ESMTP; 18 Jan 2023 01:56:29 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 4/5] UefiCpuPkg/SmmCpuFeaturesLib: Skip SMBASE configuration Date: Wed, 18 Jan 2023 17:56:19 +0800 Message-Id: <20230118095620.9860-5-jiaxin.wu@intel.com> In-Reply-To: <20230118095620.9860-1-jiaxin.wu@intel.com> References: <20230118095620.9860-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: iBPDXdyWJ8dYBKBoqt9DjnT1x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674035792; bh=XzlSq5ORZnfgxBKKXt8NPip4BiY3WiRzJkI8fGObpDY=; h=Cc:Date:From:Reply-To:Subject:To; b=d6az4PFjaxqhdiSDZhy/NeMElu2lN3kZEes1OyBDHDh/waNEE2S0wW+n1XTUfoMUlFV b+8hY1Uh1sUQt3qee9AxCza23PVBoR1RirLRORL2gC99XOomJ1BP6+ZSgxpnO+zUb23fm mOPkPIReslINjdjPBTfSp6Ya33O2yxT+Cps= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674035795339100004 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h | 2 ++ .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c | 23 ++++++++++++++++++= +--- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 ++++ .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 1 + UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1 - .../StandaloneMmCpuFeaturesLib.inf | 4 ++++ 6 files changed, 31 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h index fd3e902547..c2e4fbe96b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h @@ -7,15 +7,17 @@ **/ =20 #ifndef CPU_FEATURES_LIB_H_ #define CPU_FEATURES_LIB_H_ =20 +#include #include #include #include #include #include +#include =20 /** Performs library initialization. =20 This initialization function contains common functionality shared betwen= all diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index d5eaaa7a99..7c3836286b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -36,10 +36,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmmCpuFeaturesSmmRelocated; + // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs =3D TRUE; =20 @@ -142,10 +148,16 @@ CpuFeaturesLibInitialization ( // // Allocate array for state of SMRR enable on all CPUs // mSmrrEnabled =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLo= gicalProcessorNumber ()); ASSERT (mSmrrEnabled !=3D NULL); + + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + mSmmCpuFeaturesSmmRelocated =3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobG= uid) !=3D NULL); } =20 /** Called during the very first SMI into System Management Mode to initiali= ze CPU features, including SMBASE, for the currently executing CPU. Since = this @@ -185,14 +197,19 @@ SmmCpuFeaturesInitializeProcessor ( UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmCpuFeaturesSmmRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_S= MBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily // diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9ac7dde78f..280a4b8b39 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -31,10 +31,14 @@ [LibraryClasses] BaseLib PcdLib MemoryAllocationLib DebugLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 86d367e0a0..4bb045244b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -62,10 +62,11 @@ =20 [Guids] gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## System= Table gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## System= Table + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOME= TIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 3cf162ada0..455fe83991 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -6,11 +6,10 @@ =20 **/ =20 #include #include -#include #include #include #include #include #include diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLi= b.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index b1f60a5505..63259e44e7 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -32,10 +32,14 @@ [LibraryClasses] BaseLib DebugLib MemoryAllocationLib PcdLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98791): https://edk2.groups.io/g/devel/message/98791 Mute This Topic: https://groups.io/mt/96350763/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98792+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98792+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1674035794; cv=none; d=zohomail.com; s=zohoarc; b=Yqw59mp6dOriRKtBtBVB9nG73lkevN+OetbfLfSShINjBpXrW9Vc9xRItRxkgAKM0kTFQ3+OtxGa6m7pGYhO+Mtg5XKxtxJc5e4DrxJ4hdtpg4ss1kT9TXndX8pTWju56Etd04wtTdviUvmkkiQXxV76Gvis/FxIJ+xMnx8qgck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674035794; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=nyrxT3thvUAbZVwHvf+H3fsPciLG+HLtIUJgqAe1EKg=; b=aaj3IvtTT50E+Xje+dixbWhcdW4GSnG/kFtTzgXPztqrSw6a8FmsshCzMymPNa2q0f2pxTu1iFtBLRmFlD96mEwRMUigpp2ihuNgen257fuaQpD6I+ccrYx0Ma0eVZ/33ONCcwC18I/aHtHDuGg+O/tulkOO7M9anBOoJ4qk/G4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98792+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1674035794844587.9713911853688; Wed, 18 Jan 2023 01:56:34 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Qb5bYY1788612xXN4AsRKu3G; Wed, 18 Jan 2023 01:56:34 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.11831.1674035783379019296 for ; Wed, 18 Jan 2023 01:56:34 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="411184127" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="411184127" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2023 01:56:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10593"; a="723026401" X-IronPort-AV: E=Sophos;i="5.97,224,1669104000"; d="scan'208";a="723026401" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by fmsmga008.fm.intel.com with ESMTP; 18 Jan 2023 01:56:31 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Laszlo Ersek , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v3 5/5] OvmfPkg/SmmCpuFeaturesLib: Skip SMBASE configuration Date: Wed, 18 Jan 2023 17:56:20 +0800 Message-Id: <20230118095620.9860-6-jiaxin.wu@intel.com> In-Reply-To: <20230118095620.9860-1-jiaxin.wu@intel.com> References: <20230118095620.9860-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: TmFTWd09OXFEtEnl0O8RMq8Ux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1674035794; bh=7fOUiDHw0GRlU/q4z90AEtC5tEwjaor88BDdrENa4C8=; h=Cc:Date:From:Reply-To:Subject:To; b=TJw9KieSkEgp2M1Q6GuqGnunJ0OWP6JggIWjwemRSIDz8hxL/v9D+/CTZwyoNXSNdXJ 1SPZaapLXVHW+LbVrZ07C9DXF85noKumhQ9aQI2IqpHu9OYd4CS83sSgbWh6EAkOqyUOI uKyYCqyywZ2PiP/yCyiKhVpK/CQRWGcMxeI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1674035795325100002 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Laszlo Ersek Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 37 ++++++++++++++++--= ---- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 +++ 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 6693666d04..d2841af6a4 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -15,20 +15,28 @@ #include #include #include #include #include +#include #include #include #include #include +#include =20 // // EFER register LMA bit // #define LMA BIT10 =20 +// +// Indicate SmBase for each Processors has been relocated or not. If TRUE, +// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor= (). +// +BOOLEAN mSmmCpuFeaturesSmmRelocated; + /** The constructor function =20 @param[in] ImageHandle The firmware allocated handle for the EFI image. @param[in] SystemTable A pointer to the EFI System Table. @@ -41,10 +49,16 @@ EFIAPI SmmCpuFeaturesLibConstructor ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { + // + // If gSmmBaseHobGuid found, means SmBase info has been relocated and re= corded + // in the SmBase array. + // + mSmmCpuFeaturesSmmRelocated =3D (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobG= uid) !=3D NULL); + // // No need to program SMRRs on our virtual platform. // return EFI_SUCCESS; } @@ -83,20 +97,25 @@ SmmCpuFeaturesInitializeProcessor ( ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuState; =20 // - // Configure SMBASE. + // No need to configure SMBASE if SmBase relocation has been done. // - CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( - SMM_DEFAULT_SMBASE + - SMRAM_SAVE_STATE_MAP_OFF= SET - ); - if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; - } else { - CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmCpuFeaturesSmmRelocated) { + // + // Configure SMBASE. + // + CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( + SMM_DEFAULT_SMBASE + + SMRAM_SAVE_STATE_MAP_O= FFSET + ); + if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } else { + CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } } =20 // // No need to program SMRRs on our virtual platform. // diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 8a426a4c10..6a281518f5 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -33,10 +33,14 @@ MemoryAllocationLib PcdLib SafeIntLib SmmServicesTableLib UefiBootServicesTableLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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