From nobody Mon May 13 22:28:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98494+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98494+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673629364; cv=none; d=zohomail.com; s=zohoarc; b=kMJGq8T5RtYd5qKimBiKzYnRqvP75kGrQUsgNQzkpZoHr16pR6qcz7LTRx5YZlZMoApJx7radB5xJ/l/J/ky5afAMbkAEyXOioDjJIAEnhEuIVF0hBE3iMxiZLyXFacjG9yWuSjEMoD/vAaoNYtIt8i8s26cYSFnU8M13jB2tNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673629364; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=JA8Tam76Dv6ZHjyxPd12nN3qUSNsYTnWF/jhK/gOwko=; b=SPWf0RDrUtgaTSJsQK+AzxU7RTZ08BMaJdPmMALkMfn8rFPPW/qBwDt1/vDwR7U/XWXmyy814agRn/tI8diUaa/AFxsjzTpHHgoWb23yGJ5vbAOEXV/lL9VvO1n5X15A3hcvx8KIfrIJHrknXzYLooqM+m0TJS3pd9jyUQ/XZJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98494+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673629364585140.46400609108161; Fri, 13 Jan 2023 09:02:44 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id u0qwYY1788612xT3plFxCTux; Fri, 13 Jan 2023 09:02:44 -0800 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.80636.1673593525087688268 for ; Thu, 12 Jan 2023 23:05:25 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="323991897" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="323991897" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 23:05:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="608073483" X-IronPort-AV: E=Sophos;i="5.97,213,1669104000"; d="scan'208";a="608073483" X-Received: from william4-desk.gar.corp.intel.com ([10.5.215.176]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2023 23:05:21 -0800 From: william2.wang@intel.com To: devel@edk2.groups.io Cc: William2 Wang , Michael D Kinney , Liming Gao , Ray Ni , Donald Kuo , Chandana C Kumar Subject: [edk2-devel] [PATCH v1] Update Arch. MSR and CPUID to follow latest SDM. Date: Fri, 13 Jan 2023 15:03:05 +0800 Message-Id: <20230113070304.2047-1-william2.wang@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,william2.wang@intel.com X-Gm-Message-State: oSyU1y1TRpE41RAfwU6sSDUFx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673629364; bh=zYcg5H7v4PW2Na9wuuPTm7dJIzUtU/JfPrm/hnUg2KE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Ur8iuKctp/6BGol975rdxlCy/iJQ27o4aKHcq8aMRXMDYCkoGaYbFrFme/u553QKM0/ FinsID5PS6e73YJbruQ+jICZ8hH4zqB6N3ggcvbCrZQSTx5Vt3SLmlVn92xd8HFPoerPi HSrnZXtRmpd3VdM/85tF7+lEuIVRLrx7mLo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673629365722100002 From: William2 Wang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4262 https://bugzilla.tianocore.org/show_bug.cgi?id=3D4263 Update CPUID Leaf 06H to follow latest SDM. Update Architecture MSR contains the MSR10A.BIT23 and MSR195.BIT2-0 for overclocking undervolt protection. Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Donald Kuo Cc: Chandana C Kumar --- MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 198 ++++++++++++++++++++ MdePkg/Include/Register/Intel/Cpuid.h | 56 +++++- 2 files changed, 251 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Incl= ude/Register/Intel/ArchitecturalMsr.h index 071a8c689c..f548b56672 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -682,6 +682,149 @@ typedef union { UINT64 Uint64; } MSR_IA32_MTRRCAP_REGISTER; =20 +/** + Enumeration of Architectural Features (R/O). If CPUID.(EAX=3D07H, ECX=3D= 0):EDX[29]=3D1. + + @param ECX IA32_ARCH_CAPABILITIES (0x0000010A) + @param EAX Lower 32-bits of MSR value. + Described by the type IA32_ARCH_CAPABILITIES_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type IA32_ARCH_CAPABILITIES_REGISTER. + + Example usage + @code + IA32_ARCH_CAPABILITIES_REGISTER Msr; + + Msr.Uint64 =3D AsmReadMsr64 (IA32_ARCH_CAPABILITIES); + @endcode + @note IA32_ARCH_CAPABILITIES is defined as IA32_ARCH_CAPABILITIES in SDM. +**/ +#define IA32_ARCH_CAPABILITIES 0x0000010A + +/** + MSR information returned for MSR index #IA32_ARCH_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] RDCL_NO: The processor is not susceptible to Rogue Data = Cache Load (RDCL). + /// + UINT32 RDCL_NO : 1; + /// + /// [Bit 1] IBRS_ALL: The processor supports enhanced IBRS. + /// + UINT32 IBRS_ALL : 1; + /// + /// [Bit 2] RSBA: The processor supports RSB Alternate. Alternative br= anch predictors + /// may be used by RET instructions when the RSB is empty. SW using re= tpoline may be + /// affected by this behavior. + /// + UINT32 RSBA : 1; + /// + /// [Bit 3] SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor = need not flush the + /// L1D on VM entry. + /// + UINT32 SKIP_L1DFL_VMENTRY : 1; + /// + /// [Bit 4] SSB_NO: Processor is not susceptible to Speculative Store = Bypass. + /// + UINT32 SSB_NO : 1; + /// + /// [Bit 5] MDS_NO: Processor is not susceptible to Microarchitectural= Data Sampling (MDS). + /// + UINT32 MDS_NO : 1; + /// + /// [Bit 6] IF_PSCHANGE_MC_NO: The processor is not susceptible to a m= achine check error due to + /// modifying the size of a code page without TLB invalidation. + /// + UINT32 IF_PSCHANGE_MC_NO : 1; + /// + /// [Bit 7] TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR. + /// + UINT32 TSX_CTRL : 1; + /// + /// [Bit 8] TAA_NO: If 1, processor is not affected by TAA. + /// + UINT32 TAA_NO : 1; + UINT32 Reserved1 : 1; + /// + /// [Bit 10] MISC_PACKAGE_CTLS: The processor supports IA32_MISC_PACKA= GE_CTLS MSR. + /// + UINT32 MISC_PACKAGE_CTLS : 1; + /// + /// [Bit 11] ENERGY_FILTERING_CTL: The processor supports setting and = reading the + /// IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit. + /// + UINT32 ENERGY_FILTERING_CTL : 1; + /// + /// [Bit 12] DOITM: If 1, the processor supports Data Operand Independ= ent Timing Mode. + /// + UINT32 DOITM : 1; + /// + /// [Bit 13] SBDR_SSDP_NO: The processor is not affected by either the= Shared Buffers Data + /// Read (SBDR) vulnerability or the Sideband Stale Data Propagator (S= SDP). + /// + UINT32 SBDR_SSDP_NO : 1; + /// + /// [Bit 14] FBSDP_NO: The processor is not affected by the Fill Buffe= r Stale Data Propagator (FBSDP). + /// + UINT32 FBSDP_NO : 1; + /// + /// [Bit 15] PSDP_NO: The processor is not affected by vulnerabilities= involving the Primary Stale Data Propagator (PSDP). + /// + UINT32 PSDP_NO : 1; + UINT32 Reserved2 : 1; + /// + /// [Bit 17] FB_CLEAR: If 1, the processor supports overwrite of fill = buffer values as part of MD_CLEAR operations + /// with the VERW instruction. + /// + UINT32 FB_CLEAR : 1; + /// + /// [Bit 18] FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_= OPT_CTRL MSR + /// and allows software to set bit 3 of that MSR (FB_CLEAR_DIS). + /// + UINT32 FB_CLEAR_CTRL : 1; + /// + /// [Bit 19] RRSBA: A value of 1 indicates the processor may have the = RRSBA alternate prediction + /// behavior, if not disabled by RRSBA_DIS_U or RRSBA_DIS_S. + /// + UINT32 RRSBA : 1; + /// + /// [Bit 20] BHI_NO: A value of 1 indicates BHI_NO branch prediction b= ehavior, regardless of + /// the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit. + /// + UINT32 BHI_NO : 1; + // + /// [Bit 21] XAPIC_DISABLE_STATUS: Enumerates that the IA32_XAPIC_DISA= BLE_STATUS MSR exists, + /// and that bit 0 specifies whether the legacy xAPIC is disabled and = APIC state is locked to x2APIC. + /// + UINT32 XAPIC_DISABLE_STATUS : 1; + UINT32 Reserved3 : 1; + /// + /// [Bit 23] OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS= MSR exists. + /// + UINT32 OVERCLOCKING_STATUS : 1; + /// + /// [Bit 24] PBRSB_NO: If 1, the processor is not affected by issues r= elated to Post-Barrier + /// Return Stack Buffer Predictions. + /// + UINT32 PBRSB_NO : 1; + UINT32 Reserved4 : 7; + UINT32 Reserved5 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} IA32_ARCH_CAPABILITIES_REGISTER; + /** SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_0= 1H. =20 @@ -1035,6 +1178,61 @@ typedef union { UINT64 Uint64; } MSR_IA32_PERFEVTSEL_REGISTER; =20 +/** + Overclocking Status (R/O) IA32_ARCH_CAPABILITIES[bit 23] enumerates supp= ort for this MSR. + + @param ECX IA32_OVERCLOCKING_STATUS (0x00000195) + @param EAX Lower 32-bits of MSR value. + Described by the type IA32_OVERCLOCKING_STATUS_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type IA32_OVERCLOCKING_STATUS_REGISTER. + + Example usage + @code + IA32_OVERCLOCKING_STATUS_REGISTER Msr; + + Msr.Uint64 =3D AsmReadMsr64 (IA32_OVERCLOCKING_STATUS); + @endcode + @note IA32_OVERCLOCKING_STATUS is defined as IA32_OVERCLOCKING_STATUS in= SDM. +**/ +#define IA32_OVERCLOCKING_STATUS 0x00000195 + +/** + MSR information returned for MSR index #IA32_ARCH_CAPABILITIES +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] Indicates if specific forms of overclocking have been en= abled on this boot or reset + /// cycle: 0 indicates no, 1 indicates yes. + /// + UINT32 OverclockingUtilized : 1; + /// + /// [Bits 1] Indicates if the =E2=80=9CDynamic OC Undervolt Protectio= n=E2=80=9D security feature is active: + /// 0 indicates disabled, 1 indicates enabled. + /// + UINT32 UndervoltProtection : 1; + /// + /// [Bits 2] Indicates that overclocking capabilities have been unloc= ked by BIOS, + /// with or without overclocking: 0 indicates Not Secured, 1 indicates= Secure. + /// + UINT32 OverclockingSecureStatus : 1; + UINT32 Reserved1 : 29; + UINT32 Reserved2 : 32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} IA32_OVERCLOCKING_STATUS_REGISTER; + /** Current performance state(P-State) operating point (RO). Introduced at Display Family / Display Model 0F_03H. diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe= r/Intel/Cpuid.h index 350bf60252..46cdb827e2 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -1195,12 +1195,24 @@ typedef union { /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supporte= d if set. /// UINT32 FastAccessMode : 1; - UINT32 Reserved4 : 1; + /// + /// [Bit 19] IA32_HW_FEEDBACK_PTR MSR, IA32_HW_FEEDBACK_CONFIG MSR, + /// IA32_PACKAGE_THERM_STATUS MSR bit 26, and IA32_PACKAGE_THERM_INTER= RUPT MSR bit 25 are supported if set. + UINT32 HW_FEEDBACK : 1; /// /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported = if set. /// UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1; - UINT32 Reserved5 : 11; + UINT32 Reserved4 : 2; + /// + /// [Bit 23] Intel Thread Director supported if set. IA32_HW_FEEDBACK_= CHAR and + /// IA32_HW_FEEDBACK_THREAD_CONFIG MSRs are supported if set. + UINT32 ThreadDirector : 1; + /// + /// [Bit 24] IA32_THERM_INTERRUPT MSR bit 25 is supported if set. + /// + UINT32 IA32_THERM_INTERRUPT : 1; + UINT32 Reserved5 : 7; } Bits; /// /// All bit fields as a 32-bit value @@ -1252,7 +1264,13 @@ typedef union { /// (1B0H). /// UINT32 PerformanceEnergyBias : 1; - UINT32 Reserved2 : 28; + UINT32 Reserved2 : 4; + /// + /// {Bit 15:8] Number of Intel Thread Director classes supported by th= e processor. Information for that + /// many classes is written into the Intel Thread Director Table by th= e hardware. + /// + UINT32 ThreadDirectorClasses : 8; + UINT32 Reserved3 : 16; } Bits; /// /// All bit fields as a 32-bit value @@ -1260,6 +1278,38 @@ typedef union { UINT32 Uint32; } CPUID_THERMAL_POWER_MANAGEMENT_ECX; =20 +/** + CPUID Thermal and Power Management Information returned in EDX for CPUID= leaf + #CPUID_THERMAL_POWER_MANAGEMENT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// {Bits 7:0] Bitmap of supported hardware feedback interface capabil= ities. + /// + UINT32 InterfaceCapability : 8; + /// + /// {Bits 11:8] Enumerates the size of the hardware feedback interface= structure in number of 4 KB pages; + /// add one to the return value to get the result. + /// + UINT32 InterfaceStructureSize : 4; + UINT32 Reserved : 4; + /// + /// {Bits 31:16] : Index (starting at 0) of this logical processor's r= ow in the hardware feedback interface structure. + /// Note that on some parts the index may be same for multiple logical= processors. On some parts the + /// indices may not be contiguous, i.e., there may be unused rows in t= he hardware feedback interface structure. + /// + UINT32 LogicalProcessorRowIndex : 16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_THERMAL_POWER_MANAGEMENT_EDX; + /** CPUID Structured Extended Feature Flags Enumeration =20 --=20 2.34.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98494): https://edk2.groups.io/g/devel/message/98494 Mute This Topic: https://groups.io/mt/96241948/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-