From nobody Tue May 21 13:46:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98396+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98396+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1673565247; cv=none; d=zohomail.com; s=zohoarc; b=FigeG2grt3gIIYdSnrYowqenZG57HBvLFirmHHJqt6cC9oLNiCUitGoRDn23WOk8hCME/0FHzFabODHYQzVHVoiraCdRlB/uHZ87z7joBjSlsNU69t6CZFq0ri41sfBrbHRgtu3bSZC7rGBO77pmuII217rgIu7uf0apIf8QCeI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673565247; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=91nhW1LQGT9QAmRA9JEK0iAowKxGSJacU/WJilELLOA=; b=jmMTZuuRj+uSNii1AqM6Z7FsFC9z6X51wfpgqifcG8LwgHWXYXdHKDe7eUBesAgGQrbyWaNCeYWyv+7FKY8OjcM5UIyVsIh3IyJhQxEwGTwzLYrPe+hBcPYuqzOFWFb923SK3KqNDE8wnEw873nXblRPR9zsz2Z5jp7IYBjFGkg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98396+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673565247615152.19121390154805; Thu, 12 Jan 2023 15:14:07 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id IBroYY1788612xsYGosmLsTR; Thu, 12 Jan 2023 15:14:07 -0800 X-Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.groups.io with SMTP id smtpd.web10.72160.1673565246471614651 for ; Thu, 12 Jan 2023 15:14:06 -0800 X-Received: by mail-wr1-f47.google.com with SMTP id r2so19554798wrv.7 for ; Thu, 12 Jan 2023 15:14:06 -0800 (PST) X-Gm-Message-State: tSztSLi0scNpSL6NklHAYwFNx1787277AA= X-Google-Smtp-Source: AMrXdXvFB0lN0GxgwMzJGLT1aaJ89771pfjkO8nSW1XmQGYxJcDPXRUohKwJbl/eC3Lhz8CpcMYMIA== X-Received: by 2002:adf:e8c5:0:b0:2bd:d966:7fff with SMTP id k5-20020adfe8c5000000b002bdd9667fffmr2469061wrn.20.1673565244488; Thu, 12 Jan 2023 15:14:04 -0800 (PST) X-Received: from PC-PEDRO-ARCH.lan ([2001:8a0:7280:5801:9441:3dce:686c:bfc7]) by smtp.gmail.com with ESMTPSA id l7-20020a5d6747000000b002b57bae7174sm17472396wrw.5.2023.01.12.15.14.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 15:14:04 -0800 (PST) From: "Pedro Falcato" To: devel@edk2.groups.io Cc: Pedro Falcato , Isaac Oram , Theo Jehl , Gerd Hoffmann Subject: [edk2-devel] [PATCH edk2-platforms 1/2] QemuOpenBoardPkg: Redo PCI bus initialization Date: Thu, 12 Jan 2023 23:13:58 +0000 Message-Id: <20230112231359.452800-2-pedro.falcato@gmail.com> In-Reply-To: <20230112231359.452800-1-pedro.falcato@gmail.com> References: <20230112231359.452800-1-pedro.falcato@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pedro.falcato@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673565247; bh=4qXwdlrc2XrHszwfUD+RBCFAygtEW1dCH1uL4GyWfGI=; h=Cc:Date:From:Reply-To:Subject:To; b=j6P9/rlSH8zH/ru78OgDrOzI9hCdLA6eIp6OxB4EiChYQu3JmOck+g0W6+EVzrFStET vw/4JuvAuzDSXjWj+5QstJp2Ta+jAnR0Sgo8X9F+xP7m8XMLhKFY3JLt1OFOu/2pvcSCs 4qMVzAlOP0ns/kxOrLyeYVhhHC4YOyo+g5k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673565249291100007 Content-Type: text/plain; charset="utf-8" Rework PCI MMIO space into something more robust and compatible with various QEMU configurations. Also, set up 64-bit memory regions for 64-bit BARs and drop OvmfPkg's PciHostBridgeLib for MinPlatformPkg's PciHostBridgeLibSimple, which does the job just fine. (cc Gerd for possible comments given his experience with OVMF and qemu) Signed-off-by: Pedro Falcato Cc: Isaac Oram Cc: Theo Jehl Cc: Gerd Hoffmann Reviewed-by: Isaac Oram --- .../Include/Dsc/Stage2.dsc.inc | 4 +- .../QemuOpenBoardPkg/PlatformInitPei/Memory.c | 22 +- .../QemuOpenBoardPkg/PlatformInitPei/Pci.c | 227 +++++++++++++++--- .../QemuOpenBoardPkg/PlatformInitPei/Pcie.c | 106 -------- .../PlatformInitPei/PlatformInit.c | 17 +- .../PlatformInitPei/PlatformInit.h | 32 ++- .../PlatformInitPei/PlatformInitPei.inf | 18 +- .../QemuOpenBoardPkg/QemuOpenBoardPkg.dsc | 17 +- 8 files changed, 274 insertions(+), 169 deletions(-) delete mode 100644 Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc b/Pl= atform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc index d2e41ce79fda..c240c38cabef 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc @@ -3,14 +3,14 @@ # # @copyright # Copyright (C) 2022 Theo Jehl +# Copyright (c) 2023 Pedro Falcato All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent ## =20 [LibraryClasses.Common] ResetSystemLib | OvmfPkg/Library/ResetSystemLib/BaseResetSystem= Lib.inf - PciHostBridgeLib | OvmfPkg/Library/PciHostBridgeLib/PciHostBridge= Lib.inf - PciHostBridgeUtilityLib | OvmfPkg/Library/PciHostBridgeUtilityLib/PciHos= tBridgeUtilityLib.inf + PciHostBridgeLib | MinPlatformPkg/Pci/Library/PciHostBridgeLibSim= ple/PciHostBridgeLibSimple.inf DxeHardwareInfoLib | OvmfPkg/Library/HardwareInfoLib/DxeHardwareInf= oLib.inf =20 [LibraryClasses.Common.PEIM] diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c b/Plat= form/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c index 21705256191b..4f312c36016e 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c @@ -2,6 +2,7 @@ Memory probing and installation =20 Copyright (c) 2022 Theo Jehl All rights reserved. + Copyright (c) 2023 Pedro Falcato All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 @@ -53,12 +54,27 @@ GetMemoryBelow4Gb ( Size +=3D E820Entry.Length; } else { ASSERT (Size =3D=3D (UINT32)Size); - return (UINT32) Size; + return (UINT32)Size; } } =20 ASSERT (Size =3D=3D (UINT32)Size); - return (UINT32) Size; + return (UINT32)Size; +} + +STATIC UINT64 mTopNonHoleAddr; + +/** + Return the largest reserved/DRAM/etc address. + + @return Largest non-hole address. +**/ +UINT64 +GetTopNonHoleAddr ( + VOID + ) +{ + return mTopNonHoleAddr; } =20 /** @@ -222,6 +238,8 @@ InstallMemory ( E820Entry.BaseAddr + E820Entry.Length - 1, E820Entry.Type )); + + mTopNonHoleAddr =3D MAX (mTopNonHoleAddr, E820Entry.BaseAddr + E820Ent= ry.Length - 1); } =20 ASSERT (LargestE820Entry.Length !=3D 0); diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c b/Platfor= m/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c index 4e6b784d9890..d2724d205552 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c @@ -1,7 +1,8 @@ /** @file Pci.c - PCI Initialization for PIIX4 QEMU + PCI Initialization for QEMU platforms =20 Copyright (c) 2022 Theo Jehl All rights reserved. + Copyright (c) 2023 Pedro Falcato All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 @@ -9,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -16,55 +18,220 @@ #include #include =20 +typedef EFI_STATUS (*SETUP_PCI_CALLBACK)( + VOID + ); + +typedef struct PlatformInfo { + UINT16 PciIoBase; + UINT16 PciIoSize; + BOOLEAN HasPcie; + SETUP_PCI_CALLBACK SetupPci; +} QEMU_PLATFORM_INFO; + +/** + Set up PCI on the q35 platform. + + @retval EFI_SUCCESS Success. +**/ +STATIC +EFI_STATUS +PciSetupQ35 ( + VOID + ); + +STATIC +CONST +QEMU_PLATFORM_INFO PlatformData[] =3D +{ + { PIIX4_PCI_IO_BASE, PIIX4_PCI_IO_SIZE, FALSE, NULL }, + { Q35_PCI_IO_BASE, Q35_PCI_IO_SIZE, TRUE, PciSetupQ35 } +}; + +/** + Get platform info for the given platform. + range PCDs. Asserts on bad QEMU_PLATFORMs. + + @retval Pointer to the QEMU_PLATFORM_INFO. +**/ +STATIC +CONST +QEMU_PLATFORM_INFO * +GetPlatform ( + IN QEMU_PLATFORM Plat + ) +{ + ASSERT (Plat < QEMU_PLATFORM_MAX); + return &PlatformData[Plat]; +} + /** - Initialize PCI support for QEMU PIIX4 machine. + Initialise PCI QEMU platforms. =20 - It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridgeLib. + Updates PCI IO port and MMIO range PCDs. =20 @retval EFI_SUCCESS Initialization was a success. - @retval EFI_UNSUPPORTED Initialization failed (Memory below 4Gb probing= failed). **/ EFI_STATUS EFIAPI -InitializePciPIIX4 ( +InitializePci ( + IN QEMU_PLATFORM Platform + ) +{ + CONST QEMU_PLATFORM_INFO *PlatformData; + UINT32 Tolud; + UINT32 MemBase; + UINT32 MemSize; + UINT64 Mem64Base; + UINT64 Mem64Size; + UINT32 EcamBase; + + PlatformData =3D GetPlatform (Platform); + + ASSERT (PlatformData !=3D NULL); + + Tolud =3D GetMemoryBelow4Gb (); + + // + // Configure the IO port ranges PCDs based on the platform + // + PcdSet16S (PcdPciReservedIobase, PlatformData->PciIoBase); + PcdSet16S (PcdPciReservedIoLimit, PlatformData->PciIoBase + PlatformData= ->PciIoSize - 1); + + // + // Set up the PCI MMIO ranges + // Some context around this logic (after diving into QEMU source): + // Traditionally, QEMU seems to want to use a split at around + // 0xe0000000 (3.5GiB). After that things are reserved for PCI MMIO. + // However, PIIX4 grew a gigabyte_align option that can readjust this + // down to 0xc0000000 (3GiB). + // Q35 logic seems to dock lowmem at around 0x80000000 (2GiB) if it can't + // fit the whole lowmem under 4GB. If it can, it limits lowmem to 0xb000= 0000. + // + // It's worth noting that QEMU also grew an option to change lowmem base= d on the + // user's preferences. Because of all of this, it's near impossible to h= ardcode + // a range, so we grab TOLUD (not in a literal way, since QEMU does not = implement + // that register ;)) and calculate our PCI MMIO based on that. This also= makes it so + // the DSDT built by QEMU will have correct _CRS ranges. + // hw/pci-host/q35.c explicitly says our PCI hole ranges from [TOLUD, IO= APIC]. + // As far as I can tell, we seem to be allowed to add a 64-bit resource = range anywhere. + // + + MemBase =3D Tolud; + MemSize =3D PCI_MMIO_TOP_ADDRESS - MemBase; + + // + // Set things up in the following way: + // ---------------------------------- + // Mem32-decoding-region + // ---------------------------------- + // ECAM/MMCONFIG + // ---------------------------------- + // Misc top regions, 64-bit memory + // ---------------------------------- + // Mem64-decoding-region + // ---------------------------------- + // + + if (PlatformData->HasPcie) { + ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) < BASE_4GB); + EcamBase =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + EcamBase, + SIZE_256MB + ); + + BuildMemoryAllocationHob ( + EcamBase, + SIZE_256MB, + EfiMemoryMappedIO + ); + + // + // Adjust the PCI MEM window + // + MemSize =3D EcamBase - MemBase; + + DEBUG ((DEBUG_INFO, "PlatformInitPei: Using ECAM @ [%x, %x]\n", EcamBa= se, EcamBase + SIZE_256MB - 1)); + } + + PcdSetBoolS (PcdPciNoExtendedConfigSpace, !PlatformData->HasPcie); + + PcdSet32S (PcdPciReservedMemBase, MemBase); + PcdSet32S (PcdPciReservedMemLimit, MemBase + MemSize - 1); + + DEBUG ((DEBUG_INFO, "PlatformInitPei: PCI Mem window @ [%x, %x]\n", MemB= ase, MemBase + MemSize - 1)); + + // + // For simplicity, start the Mem64 region after every other + // valid non-hole memory region. + // Note: Unclear if this has any disadvantages. + // + Mem64Base =3D GetTopNonHoleAddr (); + + if (Mem64Base < BASE_4GB) { + Mem64Base =3D BASE_4GB; + } + + Mem64Size =3D SIZE_32GB; + + PcdSet64S (PcdPciReservedMemAbove4GBBase, Mem64Base); + PcdSet64S (PcdPciReservedMemAbove4GBLimit, Mem64Base + Mem64Size - 1); + + DEBUG ((DEBUG_INFO, "PlatformInitPei: PCI Mem64 window @ [%lx, %lx]\n", = Mem64Base, Mem64Base + Mem64Size - 1)); + + if (PlatformData->SetupPci) { + EFI_STATUS Status; + Status =3D PlatformData->SetupPci (); + + if (EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + Set up PCI on the q35 platform. + + @retval EFI_SUCCESS Success. +**/ +STATIC +EFI_STATUS +PciSetupQ35 ( VOID ) { - UINTN PciIoBase; - UINTN PciIoSize; - UINTN PciMmio32Base; - UINTN PciMmio32Size; + UINT64 PciExBarBase; + + PciExBarBase =3D PcdGet64 (PcdPciExpressBaseAddress); =20 // - // Setup PCI IO ranges for 440FX/PIIX4 platform + // Disable the ECAM before re-programming it. // - PciIoBase =3D PIIX4_PCI_IO_BASE; - PciIoSize =3D PIIX4_PCI_IO_SIZE; - - PcdSet64S (PcdPciIoBase, PciIoBase); - PcdSet64S (PcdPciIoSize, PciIoSize); + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); =20 // - // QEMU only allow a maximum of 2.8Gb of real memory below 4G - // PCI MMIO range below 4Gb starts at the end of real memory below 4G + // Now, program the PCIe ECAM into the MCH PCIEXBAR register. We do it i= n a high-low order + // as to avoid temporary misdecoding of addresses. // - PciMmio32Base =3D (UINTN)GetMemoryBelow4Gb (); =20 - if (PciMmio32Base =3D=3D 0) { - DEBUG ((DEBUG_ERROR, "Unable to detect memory below 4Gb\n")); - ASSERT (PciMmio32Base !=3D 0); - return EFI_UNSUPPORTED; - } - - DEBUG ((DEBUG_ERROR, "Memory below 4Gb: %x \n", PciMmio32Base)); + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), (UINT32)(RShiftU64 (= PciExBarBase, 32))); =20 // - // Maximum size being PCI_MMIO_TOP_ADDRESS - TopOfLowMem to avoid overla= pping with IO-APIC and other hardware mmio ranges + // Finally, program the low bits and simultaneously enable it. // - PciMmio32Size =3D PCI_MMIO_TOP_ADDRESS - PciMmio32Base; - - PcdSet64S (PcdPciMmio32Base, PciMmio32Base); - PcdSet64S (PcdPciMmio32Size, PciMmio32Size); + PciWrite32 ( + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), + (UINT32)PciExBarBase | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN + ); =20 return EFI_SUCCESS; } diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c b/Platfo= rm/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c deleted file mode 100644 index 0a5f0ff398de..000000000000 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c +++ /dev/null @@ -1,106 +0,0 @@ -/** @file Pcie.c - PCI Express initialization for QEMU Q35 - - Copyright (c) 2022 Theo Jehl All rights reserved. - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include "PlatformInit.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - Initialize PCI Express support for QEMU Q35 system. - It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridgeLib. - - @retval EFI_SUCCESS Initialization was successful -**/ -EFI_STATUS -EFIAPI -InitializePcie ( - VOID - ) -{ - UINTN PciBase; - UINTN PciSize; - UINTN PciIoBase; - UINTN PciIoSize; - - union { - UINT64 Uint64; - UINT32 Uint32[2]; - } PciExBarBase; - - PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - - // - // Build a reserved memory space for PCIE MMIO - // - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - PciExBarBase.Uint64, - SIZE_256MB - ); - - BuildMemoryAllocationHob ( - PciExBarBase.Uint64, - SIZE_256MB, - EfiReservedMemoryType - ); - - // - // Clear lower 32 bits of register - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); - - // - // Program PCIE MMIO Base address in MCH PCIEXBAR register - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); - - // - // Enable 256Mb MMIO space - // - PciWrite32 ( - DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), - PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN - ); - - // - // Disable PCI/PCIe MMIO above 4Gb - // - PcdSet64S (PcdPciMmio64Size, 0); - - // - // Set Pci MMIO space below 4GB - // - PciBase =3D (UINTN)(PcdGet64 (PcdPciExpressBaseAddress) + SIZE_256MB); - PciSize =3D PCI_MMIO_TOP_ADDRESS - PciBase; - - PcdSet64S (PcdPciMmio32Base, PciBase); - PcdSet64S (PcdPciMmio32Size, PciSize); - - // - // Set Pci IO port range - // - PciIoBase =3D Q35_PCI_IO_BASE; - PciIoSize =3D Q35_PCI_IO_SIZE; - - PcdSet64S (PcdPciIoBase, PciIoBase); - PcdSet64S (PcdPciIoSize, PciIoSize); - - return EFI_SUCCESS; -} diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c index 7849298b52d5..d23895afc967 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c @@ -2,6 +2,7 @@ Platform initialization PEIM for QEMU =20 Copyright (c) 2022 Theo Jehl All rights reserved. + Copyright (c) 2023 Pedro Falcato All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 @@ -36,8 +37,6 @@ PlatformInit ( if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "Memory installation failed\n")); return Status; - } else { - DEBUG ((DEBUG_INFO, "Memory installation success\n")); } =20 // @@ -48,7 +47,7 @@ PlatformInit ( EfiPlatformInfo =3D AllocateZeroPool (sizeof (EFI_HOB_PLATFORM_INFO)); if (EfiPlatformInfo =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "Failed to allocate pool for EFI_HOB_PLATFORM_INF= O\n")); - return EFI_UNSUPPORTED; + return EFI_OUT_OF_RESOURCES; } =20 // @@ -56,20 +55,14 @@ PlatformInit ( // DeviceId =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_O= FFSET)); DEBUG ((DEBUG_INFO, "Building gUefiOvmfPkgPlatformInfoGuid with Host bri= dge dev ID %x \n", DeviceId)); - (*EfiPlatformInfo).HostBridgeDevId =3D DeviceId; + EfiPlatformInfo->HostBridgeDevId =3D DeviceId; =20 BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, EfiPlatformInfo, sizeof= (EFI_HOB_PLATFORM_INFO)); =20 PcdSet16S (PcdOvmfHostBridgePciDevId, DeviceId); =20 // - // Initialize PCI or PCIe based on current emulated system + // Finally, initialize PCI MMIO ranges and possibly the MMCONFIG // - if (DeviceId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - DEBUG ((DEBUG_INFO, "Q35: Initialize PCIe\n")); - return InitializePcie (); - } else { - DEBUG ((DEBUG_INFO, "PIIX4: Initialize PCI\n")); - return InitializePciPIIX4 (); - } + return InitializePci (DeviceId =3D=3D INTEL_Q35_MCH_DEVICE_ID ? QEMU_PLA= TFORM_Q35 : QEMU_PLATFORM_PIIX4); } diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h index 771d2f958c40..f4044df3dbf5 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h @@ -2,6 +2,7 @@ Headers for PlatformInitPei PEIM =20 Copyright (c) 2022 Theo Jehl All rights reserved. + Copyright (c) 2023 Pedro Falcato All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 @@ -38,16 +39,23 @@ InstallMemory ( IN CONST EFI_PEI_SERVICES **PeiServices ); =20 -EFI_STATUS -EFIAPI -InitializePcie ( - VOID - ); +typedef enum Platforms { + QEMU_PLATFORM_PIIX4 =3D 0, + QEMU_PLATFORM_Q35, + QEMU_PLATFORM_MAX +} QEMU_PLATFORM; + +/** + Initialise PCI QEMU platforms. + + Updates PCI IO port and MMIO range PCDs. =20 + @retval EFI_SUCCESS Initialization was a success. +**/ EFI_STATUS EFIAPI -InitializePciPIIX4 ( - VOID +InitializePci ( + QEMU_PLATFORM Platform ); =20 EFI_STATUS @@ -56,4 +64,14 @@ MaxCpuInit ( VOID ); =20 +/** + Return the largest reserved/DRAM/etc address. + + @return Largest non-hole address. +**/ +UINT64 +GetTopNonHoleAddr ( + VOID + ); + #endif //QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_ diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei= .inf b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf index 43b1e13adfeb..5f42d46178f7 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf @@ -4,6 +4,7 @@ # Simple PEIM for QEMU PIIX4/Q35 Memory, SMP and PCI/PCI Express initiali= zation # # Copyright (c) 2022 Theo Jehl +# Copyright (c) 2023 Pedro Falcato All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent =20 [Defines] @@ -17,14 +18,15 @@ [Packages] OvmfPkg/OvmfPkg.dec MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec QemuOpenBoardPkg/QemuOpenBoardPkg.dec UefiCpuPkg/UefiCpuPkg.dec + MinPlatformPkg/MinPlatformPkg.dec =20 [Sources] PlatformInit.h PlatformInit.c Memory.c - Pcie.c Pci.c Cpu.c =20 @@ -43,13 +45,15 @@ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber - gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase - gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize - gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base - gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size - gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base - gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit + gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes =20 [FeaturePcd] diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc index f5c317c83e6a..b2b82b84be4c 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc @@ -4,6 +4,7 @@ # Description file for QemuOpenBoardPkg # # Copyright (c) 2022 Theo Jehl +# Copyright (c) 2023 Pedro Falcato All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent ## =20 @@ -78,9 +79,7 @@ gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort | = 0x402 gEfiMdePkgTokenSpaceGuid.PcdFSBClock | = 100000000 =20 - # PCIe base address for Q35 machines - # QEMU usable memory below 4G cannot exceed 2.8Gb - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress | = 0xB0000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = | 0xE0000000 =20 gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable | = TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange | = FALSE @@ -119,6 +118,18 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 0 gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber | 0 =20 + # All of these MinPlatform PCI PCDs are filled in PlatformInitPei + # They must be dynamic since we don't know what platform (ICH9 or PIIX4)= we're booting + # or how the memory map looks like. + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase = | 0xffffffffffffffff + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit = | 0 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase = | 0x90000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit = | 0 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase = | 0x2000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit = | 0xffff + + gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace = | TRUE + !if $(SMM_REQUIRED) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes | 8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase | = FALSE --=20 2.39.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Signed-off-by: Pedro Falcato Cc: Isaac Oram Cc: Theo Jehl Reviewed-by: Isaac Oram Reviewed-by: Theo Jehl --- .../QemuOpenBoardPkg/PlatformInitPei/Cpu.c | 2 +- .../QemuOpenBoardPkg/PlatformInitPei/Memory.c | 9 ++---- .../PlatformInitPei/PlatformInit.h | 28 ++++++++++++++----- 3 files changed, 25 insertions(+), 14 deletions(-) diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c b/Platfor= m/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c index e203b2654226..2fc62a0a3e77 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c @@ -20,7 +20,7 @@ /** Probe Qemu FW CFG device for current CPU count and report to MpInitLib. =20 - @return EFI_SUCCESS Detection was successful. + @retval EFI_SUCCESS Detection was successful. @retval EFI_UNSUPPORTED QEMU FW CFG device is not present. */ EFI_STATUS diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c b/Plat= form/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c index 4f312c36016e..223cace0ca98 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c @@ -86,8 +86,8 @@ GetTopNonHoleAddr ( STATIC VOID ReserveMmioRegion ( - EFI_PHYSICAL_ADDRESS Start, - UINT64 Length + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length ) { EFI_RESOURCE_TYPE ResourceType; @@ -121,7 +121,6 @@ InstallMemory ( ) { EFI_STATUS Status; - CONST EFI_PEI_SERVICES **PeiServicesTable; EFI_E820_ENTRY64 E820Entry; EFI_E820_ENTRY64 LargestE820Entry; QEMU_FW_CFG_FILE FwCfgFile; @@ -250,9 +249,7 @@ InstallMemory ( LargestE820Entry.BaseAddr + LargestE820Entry.Length - 1 )); =20 - PeiServicesTable =3D GetPeiServicesTablePointer (); - - Status =3D (*PeiServices)->InstallPeiMemory (PeiServicesTable, LargestE8= 20Entry.BaseAddr, LargestE820Entry.Length); + Status =3D (*PeiServices)->InstallPeiMemory (PeiServices, LargestE820Ent= ry.BaseAddr, LargestE820Entry.Length); =20 ASSERT_EFI_ERROR (Status); =20 diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h index f4044df3dbf5..f17df707188a 100644 --- a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h @@ -20,19 +20,27 @@ =20 #define PCI_MMIO_TOP_ADDRESS 0xFC000000 =20 -EFI_STATUS -EFIAPI -PlatformInit ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ); +/** + Return the memory size below 4GB. =20 + @return Size of memory below 4GB, in bytes. +**/ UINT32 EFIAPI GetMemoryBelow4Gb ( VOID ); =20 +/** + Install EFI memory by probing QEMU FW CFG devices for valid E820 entries. + It also reserves space for MMIO regions such as VGA, BIOS and APIC. + + @param[in] PeiServices PEI Services pointer. + + @retval EFI_SUCCESS Memory initialization succeded. + @retval EFI_UNSUPPORTED Installation failed (etc/e820 file was not found= ). + @retval EFI_NOT_FOUND QEMU FW CFG device is not present. +**/ EFI_STATUS EFIAPI InstallMemory ( @@ -58,6 +66,12 @@ InitializePci ( QEMU_PLATFORM Platform ); =20 +/** + Probe Qemu FW CFG device for current CPU count and report to MpInitLib. + + @retval EFI_SUCCESS Detection was successful. + @retval EFI_UNSUPPORTED QEMU FW CFG device is not present. + */ EFI_STATUS EFIAPI MaxCpuInit ( @@ -74,4 +88,4 @@ GetTopNonHoleAddr ( VOID ); =20 -#endif //QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_ +#endif // QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_ --=20 2.39.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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