From nobody Sun May 12 15:13:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98285+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98285+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673426113; cv=none; d=zohomail.com; s=zohoarc; b=CG8Fdk/6gJexPD2sVSVDdn/cDvcaxfnSpj+TrGFM3Eu9z+peNWMCbWjGoPMfqCHSgp4rqiEJ/FSMqXqW+wSzWAXyKJcpoYCcl7dd98u7Zfjr6mfV1VPWfoqQc6nAZomMrUZvG+bR5TO6BdMPA4UValuPL76TvcEMxZomotkOnN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673426113; h=Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=IJ1aHoI/UC37wTI67ur3WoBb5k6Yc5XIBSOs8/SUL8E=; b=CNmNZbg0lI+IijKUSk/ZYPA31/ehIdnzdcP0Xe9jCLfKbXt2ITTp+3KbSkQ2hRHOszD5Na5q7fYEcBa64m4LkCW0Hrmp4BQVLus0poPBJzVF4hqfO99eBvzx5qDKY/JRMi542pJ3qIP/CfF0FkPbMqX6fKvvNTMRhUhJ7CrbFns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98285+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673426113728349.0597543286184; Wed, 11 Jan 2023 00:35:13 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bkEZYY1788612xxNwH7Y8AQq; Wed, 11 Jan 2023 00:35:13 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.19050.1673426112445770912 for ; Wed, 11 Jan 2023 00:35:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="325368933" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="325368933" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 00:35:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="634885059" X-IronPort-AV: E=Sophos;i="5.96,315,1665471600"; d="scan'208";a="634885059" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga006.jf.intel.com with ESMTP; 11 Jan 2023 00:35:10 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v2] UefiCpuPkg: Support SMM Relocated SmBase handling Date: Wed, 11 Jan 2023 16:35:07 +0800 Message-Id: <20230111083507.8792-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: U6oBo0ugBm4uM69Vlk1rUbSix1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673426113; bh=GkaNfeHcPBXFT8vrnW/7HMkI7thPPVdff6r8MJvFTKQ=; h=Cc:Date:From:Reply-To:Subject:To; b=BiYmJeul2zjha+0/4QQkBNH2imx/FXfHIGt8EmsctQJEw0kDhBr3ZZAmR9WHffb33ns Dd2RuMX6KdpYUVLWWqlNqhFLxraXjYaaSemfV0qIHxabRqzaDMMu0l+XQynNTIiemem2e 2fXMqa+Ntb2y+axaRtHzdKPA9U4uwnOAQy4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673426114581100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Mainly changes as below: 1. Add Smm Base HOB, which is used to store the information of Smm Relocated SmBase array for each Processors; 2. Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. 3. Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init before normal SMI sources happen. 4. Call SmmCpuFeaturesInitializeProcessor() in parallel. v2: - Refine the coding style - Rename hob to gSmmBaseHobGuid - Update SmmInitHandler() to handle the SMM relocation - Correct the S3 for SMM relocation v1: - Thread: https://edk2.groups.io/g/devel/message/97748 Change-Id: Iec7bf25166bfeefb44a202285465a35b5debbce4 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Guid/SmmBaseHob.h | 36 +++++ .../Library/SmmCpuFeaturesLib/CpuFeaturesLib.h | 2 + .../SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c | 24 +++- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 + .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 1 + UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 1 - .../StandaloneMmCpuFeaturesLib.inf | 4 + UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 39 +++++- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 25 +++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 149 ++++++++++++++++-= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 21 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + UefiCpuPkg/UefiCpuPkg.dec | 3 + 13 files changed, 261 insertions(+), 49 deletions(-) create mode 100644 UefiCpuPkg/Include/Guid/SmmBaseHob.h diff --git a/UefiCpuPkg/Include/Guid/SmmBaseHob.h b/UefiCpuPkg/Include/Guid= /SmmBaseHob.h new file mode 100644 index 0000000000..4729bbb986 --- /dev/null +++ b/UefiCpuPkg/Include/Guid/SmmBaseHob.h @@ -0,0 +1,36 @@ +/** @file + The Smm Base HOB is used to store the information of: + * Smm Relocated SmBase array for each Processors + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_BASE_HOB_H_ +#define SMM_BASE_HOB_H_ + +#include +#include + +#define SMM_BASE_HOB_DATA_GUID \ + { \ + 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d,= 0x73} \ + } + +#pragma pack(1) +typedef struct { + /// + /// Describes the Number of all max supported processors. + /// + UINT64 NumberOfProcessors; + /// + /// Pointer to SmBase array for each Processors. + /// + UINT64 SmBase[]; +} SMM_BASE_HOB_DATA; +#pragma pack() + +extern EFI_GUID gSmmBaseHobGuid; + +#endif diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h b/UefiCp= uPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h index fd3e902547..c2e4fbe96b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/CpuFeaturesLib.h @@ -7,15 +7,17 @@ **/ =20 #ifndef CPU_FEATURES_LIB_H_ #define CPU_FEATURES_LIB_H_ =20 +#include #include #include #include #include #include +#include =20 /** Performs library initialization. =20 This initialization function contains common functionality shared betwen= all diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index d5eaaa7a99..9cedeee4bb 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -36,10 +36,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Set default value to assume IA-32 Architectural MSRs are used // UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; =20 +// +// Indicate Smm Relocation done or not +// +BOOLEAN mSmmRelocationDone; + // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs =3D TRUE; =20 @@ -142,10 +147,17 @@ CpuFeaturesLibInitialization ( // // Allocate array for state of SMRR enable on all CPUs // mSmrrEnabled =3D (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLo= gicalProcessorNumber ()); ASSERT (mSmrrEnabled !=3D NULL); + + // + // If gSmmBaseHobGuid found, means Smm Relocation has been done. + // + if (GetFirstGuidHob (&gSmmBaseHobGuid) !=3D NULL) { + mSmmRelocationDone =3D TRUE; + } } =20 /** Called during the very first SMI into System Management Mode to initiali= ze CPU features, including SMBASE, for the currently executing CPU. Since = this @@ -184,15 +196,17 @@ SmmCpuFeaturesInitializeProcessor ( UINT32 RegEax; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; =20 - // - // Configure SMBASE. - // - CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET); - CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + if (!mSmmRelocationDone) { + // + // Configure SMBASE. + // + CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_S= MBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily // diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9ac7dde78f..280a4b8b39 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -31,10 +31,14 @@ [LibraryClasses] BaseLib PcdLib MemoryAllocationLib DebugLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf index 86d367e0a0..4bb045244b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf @@ -62,10 +62,11 @@ =20 [Guids] gMsegSmramGuid ## SOMETIMES_CONSUMES ## HOB gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## System= Table gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## System= Table + gSmmBaseHobGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize ## SOME= TIMES_CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 3cf162ada0..455fe83991 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -6,11 +6,10 @@ =20 **/ =20 #include #include -#include #include #include #include #include #include diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLi= b.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf index b1f60a5505..63259e44e7 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf @@ -32,10 +32,14 @@ [LibraryClasses] BaseLib DebugLib MemoryAllocationLib PcdLib + HobLib + +[Guids] + gSmmBaseHobGuid ## CONSUMES =20 [FixedPcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOME= TIMES_CONSUMES =20 [FeaturePcd] diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index fb4a44eab6..0be869cc21 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -765,10 +765,11 @@ SmmRestoreCpu ( SMM_S3_RESUME_STATE *SmmS3ResumeState; IA32_DESCRIPTOR Ia32Idtr; IA32_DESCRIPTOR X64Idtr; IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER]; EFI_STATUS Status; + UINTN Index; =20 DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n")); =20 mSmmS3Flag =3D TRUE; =20 @@ -822,13 +823,47 @@ SmmRestoreCpu ( // InitializeCpuBeforeRebase (); } =20 // - // Restore SMBASE for BSP and all APs + // Retrive the allocated SmmBase from gSmmBaseHobGuid + // + if (GetFirstGuidHob (&gSmmBaseHobGuid) !=3D NULL) { + mSmmRelocated =3D TRUE; + } else { + mSmmRelocated =3D FALSE; + } + + // + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - SmmRelocateBases (); + if (!mSmmRelocated) { + // + // Restore SMBASE for BSP and all APs + // + SmmRelocateBases (); + } else { + mSmmInitialized =3D (BOOLEAN*)AllocateZeroPool (sizeof (BOOLEAN) * mMa= xNumberOfCpus); + ASSERT (mSmmInitialized !=3D NULL); + + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM in= it + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] =3D=3D FALSE) { + } + } + } =20 // // Skip initialization if mAcpiCpuData is not valid // if (mAcpiCpuData.NumberOfCpus > 0) { diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index a0967eb69c..09bf3dfe74 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1728,10 +1728,29 @@ SmiRendezvous ( // when using on-demand paging for above 4G memory. // Cr2 =3D 0; SaveCr2 (&Cr2); =20 + if (mSmmRelocated && !mSmmInitialized[CpuIndex]) { + // + // Perform SmmInitHandler for CpuIndex + // + SmmInitHandler (); + + // + // Restore Cr2 + // + RestoreCr2 (Cr2); + + // + // Mark the first SMI init for CpuIndex has been done so as to avoid t= he reentry. + // + mSmmInitialized[CpuIndex] =3D TRUE; + + return; + } + // // Call the user register Startup function first. // if (mSmmMpSyncData->StartupProcedure !=3D NULL) { mSmmMpSyncData->StartupProcedure (mSmmMpSyncData->StartupProcArgs); @@ -1882,13 +1901,13 @@ Exit: // RestoreCr2 (Cr2); } =20 /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIn= dex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackag= eFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which means not + specified yet. =20 **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..7c624decd5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -83,10 +83,14 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribut= e =3D { EdkiiSmmClearMemoryAttributes }; =20 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER]; =20 +BOOLEAN mSmmRelocated =3D FALSE; +BOOLEAN *mSmmInitialized =3D NULL; +UINT32 mBspApicId =3D 0; + // // SMM stack information // UINTN mSmmStackArrayBase; UINTN mSmmStackArrayEnd; @@ -343,27 +347,36 @@ SmmInitHandler ( VOID ) { UINT32 ApicId; UINTN Index; + BOOLEAN IsMonarch; + + IsMonarch =3D FALSE; =20 // // Update SMM IDT entries' code segment and load IDT // AsmWriteIdtr (&gcSmiIdtr); ApicId =3D GetApicId (); =20 ASSERT (mNumberOfCpus <=3D mMaxNumberOfCpus); =20 + if (!mSmmRelocated) { + IsMonarch =3D mIsBsp; + } else if (mBspApicId =3D=3D ApicId) { + IsMonarch =3D TRUE; + } + for (Index =3D 0; Index < mNumberOfCpus; Index++) { if (ApicId =3D=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Process= orId) { // // Initialize SMM specific features on the currently executing CPU // SmmCpuFeaturesInitializeProcessor ( Index, - mIsBsp, + IsMonarch, gSmmCpuPrivate->ProcessorInfo, &mCpuHotPlugData ); =20 if (!mSmmS3Flag) { @@ -371,23 +384,25 @@ SmmInitHandler ( // Check XD and BTS features on each processor on normal boot // CheckFeatureSupported (); } =20 - if (mIsBsp) { + if (!mSmmRelocated) { + if (mIsBsp) { + // + // BSP rebase is already done above. + // Initialize private data during S3 resume + // + InitializeMpSyncData (); + } + // - // BSP rebase is already done above. - // Initialize private data during S3 resume + // Hook return after RSM to set SMM re-based flag // - InitializeMpSyncData (); + SemaphoreHook (Index, &mRebased[Index]); } =20 - // - // Hook return after RSM to set SMM re-based flag - // - SemaphoreHook (Index, &mRebased[Index]); - return; } } =20 ASSERT (FALSE); @@ -561,11 +576,15 @@ PiCpuSmmEntry ( UINT32 RegEcx; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; UINT32 Cr3; + EFI_HOB_GUID_TYPE *GuidHob; + SMM_BASE_HOB_DATA *SmmRelocationInfoHobData; =20 + GuidHob =3D NULL; + SmmRelocationInfoHobData =3D NULL; // // Initialize address fixup // PiSmmCpuSmmInitFixupAddress (); PiSmmCpuSmiEntryFixupAddress (); @@ -789,30 +808,51 @@ PiCpuSmmEntry ( // context must be reduced. // ASSERT (TileSize <=3D (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_= STATE_MAP) - SMM_HANDLER_OFFSET)); =20 // - // Allocate buffer for all of the tiles. + // Check whether the Required TileSize is enough. // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.11 SMBASE Relocation - // For Pentium and Intel486 processors, the SMBASE values must be - // aligned on a 32-KByte boundary or the processor will enter shutdown - // state during the execution of a RSM instruction. + if (TileSize > SIZE_8KB) { + DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Re= quired TileSize =3D 0x%08x, Actual TileSize =3D 0x%08x\n", TileSize, SIZE_8= KB)); + ASSERT (TileSize <=3D SIZE_8KB); + return RETURN_BUFFER_TOO_SMALL; + } + // - // Intel486 processors: FamilyId is 4 - // Pentium processors : FamilyId is 5 + // Retrive the allocated SmmBase from gSmmBaseHobGuid // - BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfC= pus - 1)); - if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + GuidHob =3D GetFirstGuidHob (&gSmmBaseHobGuid); + if (GuidHob !=3D NULL) { + SmmRelocationInfoHobData =3D GET_GUID_HOB_DATA (GuidHob); + + ASSERT (SmmRelocationInfoHobData->NumberOfProcessors =3D=3D mMaxNumber= OfCpus); + mSmmRelocated =3D TRUE; } else { - Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); - } + DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n")); + // + // Allocate buffer for all of the tiles. + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.11 SMBASE Relocation + // For Pentium and Intel486 processors, the SMBASE values must be + // aligned on a 32-KByte boundary or the processor will enter shutdo= wn + // state during the execution of a RSM instruction. + // + // Intel486 processors: FamilyId is 4 + // Pentium processors : FamilyId is 5 + // + BufferPages =3D EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberO= fCpus - 1)); + if ((FamilyId =3D=3D 4) || (FamilyId =3D=3D 5)) { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_32KB); + } else { + Buffer =3D AllocateAlignedCodePages (BufferPages, SIZE_4KB); + } =20 - ASSERT (Buffer !=3D NULL); - DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer,= EFI_PAGES_TO_SIZE (BufferPages))); + ASSERT (Buffer !=3D NULL); + DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%= 08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages))); + } =20 // // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // gSmmCpuPrivate->ProcessorInfo =3D (EFI_PROCESSOR_INFORMATION *)AllocateP= ool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus); @@ -843,11 +883,12 @@ PiCpuSmmEntry ( // Retrieve APIC ID of each enabled processor from the MP Services proto= col. // Also compute the SMBASE address, CPU Save State address, and CPU Save= state // size for each CPU in the platform // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { - mCpuHotPlugData.SmBase[Index] =3D (UINTN)Buffer + Index * Ti= leSize - SMM_HANDLER_OFFSET; + mCpuHotPlugData.SmBase[Index] =3D mSmmRelocated ? (UINTN)SmmRelocation= InfoHobData->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER= _OFFSET; + gSmmCpuPrivate->CpuSaveStateSize[Index] =3D sizeof (SMRAM_SAVE_STATE_M= AP); gSmmCpuPrivate->CpuSaveState[Index] =3D (VOID *)(mCpuHotPlugData.S= mBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->Operation[Index] =3D SmmCpuNone; =20 if (Index < mNumberOfCpus) { @@ -956,21 +997,27 @@ PiCpuSmmEntry ( // Initialize IDT // InitializeSmmIdt (); =20 // - // Relocate SMM Base addresses to the ones allocated from SMRAM + // Check whether Smm Relocation is done or not. + // If not, will do the SmmBases Relocation here!!! // - mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberO= fCpus); - ASSERT (mRebased !=3D NULL); - SmmRelocateBases (); + if (!mSmmRelocated) { + // + // Relocate SMM Base addresses to the ones allocated from SMRAM + // + mRebased =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumbe= rOfCpus); + ASSERT (mRebased !=3D NULL); + SmmRelocateBases (); =20 - // - // Call hook for BSP to perform extra actions in normal mode after all - // SMM base addresses have been relocated on all CPUs - // - SmmCpuFeaturesSmmRelocationComplete (); + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } =20 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported)); =20 // // SMM Time initialization @@ -997,10 +1044,42 @@ PiCpuSmmEntry ( ); } } } =20 + // + // For relocated SMBASE, some MSRs & CSRs are still required to be confi= gured in SMM Mode for SMM Initialization. + // Those MSRs & CSRs must be configured before normal SMI sources happen. + // So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM I= PI) for SMM init + // + if (mSmmRelocated) { + mSmmInitialized =3D (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mM= axNumberOfCpus); + ASSERT (mSmmInitialized !=3D NULL); + + mBspApicId =3D GetApicId (); + + // + // Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM in= it + // + SendSmiIpi (mBspApicId); + SendSmiIpiAllExcludingSelf (); + + // + // Wait for all processors to finish its 1st SMI + // + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + while (mSmmInitialized[Index] =3D=3D FALSE) { + } + } + + // + // Call hook for BSP to perform extra actions in normal mode after all + // SMM base addresses have been relocated on all CPUs + // + SmmCpuFeaturesSmmRelocationComplete (); + } + // // Fill in SMM Reserved Regions // gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart =3D 0; gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize =3D 0; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 5f0a38e400..78a88e6f3c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -23,10 +23,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =20 #include #include #include +#include =20 #include #include #include #include @@ -346,10 +347,20 @@ SmmWriteSaveState ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer ); =20 +/** + C function for SMI handler. To change all processor's SMMBase Register. + +**/ +VOID +EFIAPI +SmmInitHandler ( + VOID +); + /** Read a CPU Save State register on the target processor. =20 This function abstracts the differences that whether the CPU Save State re= gister is in the IA32 CPU Save State Map or X64 CPU Save State Map. @@ -400,10 +411,14 @@ WriteSaveStateRegister ( IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ); =20 +extern BOOLEAN mSmmRelocated; +extern BOOLEAN *mSmmInitialized; +extern UINT32 mBspApicId; + extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; extern UINT32 mSmmCr0; X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; @@ -1486,13 +1501,13 @@ RegisterStartupProcedure ( IN EFI_AP_PROCEDURE Procedure, IN OUT VOID *ProcedureArguments OPTIONAL ); =20 /** - Initialize PackageBsp Info. Processor specified by mPackageFirstThreadIn= dex[PackageIndex] - will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which - means not specified yet. + Initialize mPackageFirstThreadIndex Info. Processor specified by mPackag= eFirstThreadIndex[PackageIndex] + will do the package-scope register programming. Set default CpuIndex to = (UINT32)-1, which means not + specified yet. =20 **/ VOID InitPackageFirstThreadIndexInfo ( VOID diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index b4b327f60c..6dbed17b96 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -112,10 +112,11 @@ =20 [Guids] gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # = it is used for S3 boot. gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable + gSmmBaseHobGuid ## CONSUMES =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONS= UMES diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cff239d528..2afd08cdd2 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -76,10 +76,13 @@ gEdkiiCpuFeaturesInitDoneGuid =3D { 0xc77c3a41, 0x61ab, 0x4143, { 0x98,= 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }} =20 ## Include/Guid/MicrocodePatchHob.h gEdkiiMicrocodePatchHobGuid =3D { 0xd178f11d, 0x8716, 0x418e, { 0xa1,= 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }} =20 + ## Include/Guid/SmmBaseHob.h + gSmmBaseHobGuid =3D { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c= , 0x25, 0xc5, 0xfc, 0x9d, 0x73 }} + [Protocols] ## Include/Protocol/SmmCpuService.h gEfiSmmCpuServiceProtocolGuid =3D { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94= , 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} gEdkiiSmmCpuRendezvousProtocolGuid =3D { 0xaa00d50b, 0x4911, 0x428f, { 0= xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }} =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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