From nobody Sat May 18 19:48:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+95358+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+95358+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1666150800; cv=none; d=zohomail.com; s=zohoarc; b=ecvpJ6zpqTu70w7fuReoWqJuvYUQ9igCdCwBNGdfFE3lkeI2OSvYA846eJn2n2lIQglW1ZNhRvMy29pU5GjtaNCXKzWux4/T9Jhiz+rl9xTO26zOiOIp/oQuFw2fq2lBR+604UpiukJWPuDGBMDqkioRzApsi1MpG9nOlvwhAGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1666150800; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; 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d="scan'208";a="286688426" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 20:39:59 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="958119565" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="958119565" X-Received: from lins2x-desk1.gar.corp.intel.com ([10.225.33.149]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 20:39:57 -0700 From: "JackX Lin" To: devel@edk2.groups.io Cc: JackX Lin , Ray Ni , Donald Kuo , Jiewen Yao , Rangasai V Chaganty , Chandana C Kumar , JackX Lin Subject: [edk2-devel] [edk2-platforms: PATCH] BIOS needs to present cores in order of relative performance in MADT Date: Wed, 19 Oct 2022 11:39:35 +0800 Message-Id: <20221019033935.626-1-jackx.lin@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,JackX.Lin@intel.com X-Gm-Message-State: fVHf3q5Giew89Gev5UUMrOPlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1666150800; bh=7kg8QiJscQ4H73c0/NRKfTrO1eTdfGmu4tUNxEKjFDw=; h=Cc:Date:From:Reply-To:Subject:To; b=RJS4Mtc8Kx1DqnJW+C1lR+F/ECiWRNHoy6R47kXYt7Y8sARhHR04VwldpdipsiC0lhA S2tdkFHNd9AqNtR9S0/9Elq4QUp6hJK8SxyWvzzELLHSsD9EVBY8y0PCScto5QzDhfvEU /pcQgnvSpXeDgCD8J5zPw8QF3HmV0B15hQU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1666150802780100001 Content-Type: text/plain; charset="utf-8" BIOS should keep MADT ordering by big core first then small core Cc: Ray Ni Cc: Donald Kuo Cc: Jiewen Yao Cc: Rangasai V Chaganty Cc: Chandana C Kumar Cc: JackX Lin --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 149 +++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 142 insertions(+), 7 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b= /Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index 6e57b638e0..02c1dd3a91 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -18,6 +18,7 @@ typedef struct { UINT32 Flags; UINT32 SocketNum; UINT32 Thread; + BOOLEAN IsBigCore; } EFI_CPU_ID_ORDER_MAP; =20 // @@ -131,6 +132,104 @@ AppendCpuMapTableEntry ( =20 } =20 +/** + Detect if Hetero Core is supported. + + @retval TRUE - Processor support HeteroCore + @retval FALSE - Processor doesnt support HeteroCore +**/ +BOOLEAN +EFIAPI +IsHeteroCoreSupported ( + VOID + ) +{ + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx; + + /// + /// Check Hetero feature is supported + /// with CPUID.(EAX=3D7,ECX=3D0):EDX[15]=3D1 + /// + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, NULL= , &Edx.Uint32); + if (Edx.Bits.Hybrid =3D=3D 1) { + return TRUE; + } + return FALSE; +} + +/** + Detect the type of core, whether it is Big/Small Core. + + @param[out] CoreType Output pointer that get CPUID_NATIVE_MODEL_= ID_INFO data + 10h - Quark + 20h - Atom + 30H - Knights + 40H - Core +**/ +VOID +EFIAPI +GetCoreType ( + OUT UINT8 *CoreType + ) +{ + UINT32 Eax; + + if (IsHeteroCoreSupported ()) { + // + // Check which is the running core by reading CPUID.(EAX=3D1AH, ECX=3D= 00H):EAX + // + AsmCpuid (CPUID_HYBRID_INFORMATION, &Eax, NULL, NULL, NULL); + *CoreType =3D (UINT8)((Eax & 0xFF000000) >> 24); + } else { + *CoreType =3D CPUID_CORE_TYPE_INTEL_CORE; + } +} + +/** + Function will go through all processors to identify Core or Atom + by checking Core Type and update in IsBigCore. + + @param[in] CpuApicIdOrderTable Point to a buffer which will be f= illed in Core type information. +**/ +VOID +STATIC +EFIAPI +CollectCpuCoreType ( + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable + ) +{ + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx; + UINT32 Eax; + UINTN ApNumber; + EFI_STATUS Status; + UINT8 CoreType; + + Status =3D mMpService->WhoAmI ( + mMpService, + &ApNumber + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Check Hetero feature is supported + /// with CPUID.(EAX=3D7,ECX=3D0):EDX[15]=3D1 + /// + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, NULL= , &Edx.Uint32); + if (Edx.Bits.Hybrid =3D=3D 1) { + // + // Check which is the running core by reading CPUID.(EAX=3D1AH, ECX=3D= 00H):EAX + // + AsmCpuid (CPUID_HYBRID_INFORMATION, &Eax, NULL, NULL, NULL); + CoreType =3D (UINT8) ((Eax & 0xFF000000) >> 24); + } else { + CoreType =3D CPUID_CORE_TYPE_INTEL_CORE; + } + + if (CoreType =3D=3D CPUID_CORE_TYPE_INTEL_CORE) { + CpuApicIdOrderTable[ApNumber].IsBigCore =3D TRUE; + } +} + /** Collect all processors information and create a Cpu Apic Id table. =20 @@ -138,7 +237,7 @@ AppendCpuMapTableEntry ( **/ EFI_STATUS CreateCpuLocalApicInTable ( - IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable ) { EFI_STATUS Status; @@ -146,9 +245,24 @@ CreateCpuLocalApicInTable ( UINT32 Index; UINT32 CurrProcessor; EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr; + EFI_CPU_ID_ORDER_MAP *TempCpuApicIdOrderTable; UINT32 Socket; =20 - Status =3D EFI_SUCCESS; + TempCpuApicIdOrderTable =3D AllocateZeroPool (mNumberOfCpus * sizeof (EF= I_CPU_ID_ORDER_MAP)); + if (TempCpuApicIdOrderTable =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + CollectCpuCoreType (TempCpuApicIdOrderTable); + mMpService->StartupAllAPs ( + mMpService, // This + (EFI_AP_PROCEDURE) CollectCpuCoreType, // Procedure + TRUE, // SingleThread + NULL, // WaitEvent + 0, // TimeoutInMicr= osecsond + TempCpuApicIdOrderTable, // ProcedureArgu= ment + NULL // FailedCpuList + ); =20 for (CurrProcessor =3D 0, Index =3D 0; CurrProcessor < mNumberOfCpus; Cu= rrProcessor++, Index++) { Status =3D mMpService->GetProcessorInfo ( @@ -157,9 +271,9 @@ CreateCpuLocalApicInTable ( &ProcessorInfoBuffer ); =20 - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *) &CpuApicIdOrderTable[Index]; + CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[Inde= x]; if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) !=3D 0) { - CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId; + CpuIdMapPtr->ApicId =3D (UINT32) ProcessorInfoBuffer.ProcessorId; CpuIdMapPtr->Thread =3D ProcessorInfoBuffer.Location.Thread; CpuIdMapPtr->Flags =3D ((ProcessorInfoBuffer.StatusFlag & PROCESSO= R_ENABLED_BIT) !=3D 0); CpuIdMapPtr->SocketNum =3D ProcessorInfoBuffer.Location.Package; @@ -184,22 +298,43 @@ CreateCpuLocalApicInTable ( // DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", GetApicId ())); =20 - // // Fill in AcpiProcessorUid. // for (Socket =3D 0; Socket < FixedPcdGet32 (PcdMaxCpuSocketCount); Socket= ++) { for (CurrProcessor =3D 0, Index =3D 0; CurrProcessor < mNumberOfCpus; = CurrProcessor++) { - if (CpuApicIdOrderTable[CurrProcessor].Flags && (CpuApicIdOrderTable= [CurrProcessor].SocketNum =3D=3D Socket)) { - CpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =3D (CpuApicId= OrderTable[CurrProcessor].SocketNum << mNumOfBitShift) + Index; + if (TempCpuApicIdOrderTable[CurrProcessor].Flags && (TempCpuApicIdOr= derTable[CurrProcessor].SocketNum =3D=3D Socket)) { + TempCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =3D (TempC= puApicIdOrderTable[CurrProcessor].SocketNum << mNumOfBitShift) + Index; Index++; } } } =20 + // + // Re-ordering Cpu cores information to CpuApicIdOrderTable + // by big core first, then small core. + // + for (Index =3D 0, CurrProcessor =3D 0; Index < mNumberOfCpus; Index++) { + if (TempCpuApicIdOrderTable[Index].IsBigCore) { + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTab= le[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } + + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + if (!(TempCpuApicIdOrderTable[Index].IsBigCore)) { + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTab= le[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } + DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. mNumOfBitShif= t =3D %x\n", mNumOfBitShift)); DebugDisplayReOrderTable (CpuApicIdOrderTable); =20 + if (TempCpuApicIdOrderTable !=3D NULL) { + FreePool (TempCpuApicIdOrderTable); + } + return Status; } =20 --=20 2.32.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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