From nobody Wed May 8 20:27:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93658+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93658+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1663002825; cv=none; d=zohomail.com; s=zohoarc; b=mdKBTdCwNBcmIEcp2TU0eIUkv9cxWRHWR/HSQuAwgKm7xADQcDQ3sMfdY/9qZZMabwAO9W88PL6E+e5Hd0ct6RAAdZOVP9KlMLirs0bVl4F1nMdEEME+bPEvWe2sdzXXSTf13a6ZANdvC9fmwoVr+t+3SAh4Slh2ShYM87KkUEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663002825; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=MbzvBDOipJONb8JVILMjFAueiDzx93lUR5H0sSeJjrE=; b=ddPmyEA1+ZPLeY/KfOxQ7xfJsOrUUifxAGPtye2czLXqWe9kwZkNIRP4116cmqGoks2wibngeZd3DwaORY0oKYfe6EIhmlhMZZo2BWcXFhUI80t/602L1h+d4DmdOSpBIz8tu/No/HdoOQX8lq7kp8sMKLmqyo+mj3KaSz/0bfQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93658+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1663002825862855.1689518503432; Mon, 12 Sep 2022 10:13:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id hNIoYY1788612x6DSK19iWQf; Mon, 12 Sep 2022 10:13:45 -0700 X-Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) by mx.groups.io with SMTP id smtpd.web12.1248.1663002824935050029 for ; Mon, 12 Sep 2022 10:13:45 -0700 X-Received: by mail-qt1-f169.google.com with SMTP id f26so4205885qto.11 for ; Mon, 12 Sep 2022 10:13:44 -0700 (PDT) X-Gm-Message-State: cd9kCm6DakASsBU0O9UH2Gdnx1787277AA= X-Google-Smtp-Source: AA6agR78u+Xw9SgZmmiXbn4yc4tRR55i7BYZVXjSFI5Vjabf7xK+eqNlYIncyBkS7/V/sf6+oiIqAw== X-Received: by 2002:a05:622a:c:b0:344:5f6d:4d9d with SMTP id x12-20020a05622a000c00b003445f6d4d9dmr23635733qtw.366.1663002823764; Mon, 12 Sep 2022 10:13:43 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:579e:d875:fc8f:d092]) by smtp.gmail.com with ESMTPSA id s5-20020ac87585000000b00346414a0ca1sm6863540qtq.1.2022.09.12.10.13.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 10:13:43 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Sai Chaganty , Isaac Oram , Nate DeSimone , Ankit Sinha , Chasel Chiu , Liming Gao , Eric Dong Subject: [edk2-devel] [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build Date: Mon, 12 Sep 2022 13:12:47 -0400 Message-Id: <20220912171250.1515536-2-benjamin.doron00@gmail.com> In-Reply-To: <20220912171250.1515536-1-benjamin.doron00@gmail.com> References: <20220912171250.1515536-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1663002825; bh=osZ8NENvabRdqUR0aB0CKT1/q54lf1hHKQF+YFZvm2Y=; h=Cc:Date:From:Reply-To:Subject:To; b=PagEBGX0PiPFOL9IS25zWTCJk1QDG0LZAulwk75hSO/KrEaZ0EBAL0o8+OFmxgwzq/K pfyDS12JKpVxBXbFcMHxHQg8R6+kJbvmpHf+OuRVB1FZxIyUSTyjDkoloTEESAZksWjJ+ 8AF1pu2iJ1MTTZ7zuJqFwtVFvbqPrJVNc3Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1663002827157100007 Content-Type: text/plain; charset="utf-8" The LockBox is used for S3 resume in the follow-up patches, but might be used to support other features too. So, the module is added to a MinPlatform FV here. Cc: Sai Chaganty Cc: Isaac Oram Cc: Nate DeSimone Cc: Ankit Sinha Cc: Chasel Chiu Cc: Liming Gao Cc: Eric Dong Signed-off-by: Benjamin Doron Reviewed-by: Isaac Oram --- Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc | 1 + Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf | 1 + 2 files changed, 2 insertions(+) diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc b= /Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc index edee4b5e9dfd..f7f14501fd7d 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc @@ -145,6 +145,7 @@ =20 UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferD= xe.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf =20 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerf= ormanceDxe.inf diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fd= f b/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf index 1983c94d6e37..90b7681915c3 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf @@ -21,6 +21,7 @@ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusC= odeHandlerSmm.inf #INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBuff= erDxe.inf +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf !endif =20 !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93658): https://edk2.groups.io/g/devel/message/93658 Mute This Topic: https://groups.io/mt/93637579/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 8 20:27:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93659+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93659+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1663002827; cv=none; d=zohomail.com; s=zohoarc; b=WaOXYSYkTCvksKU9GpuYgh3NkpZpTXUCIJJcmrfw9BbO5tp+fYQ68AR/GHBmyzPF96MgmruElCnLZHgQAxAbavMswQZHya220qXzo5HeUxmWeRiCDmcS7AkGHG2vKHsoybJHfKneeynnD5KaqX5UzvmaVswEFDhtzE2i4cROwHQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663002827; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wBKwVbgVOmpPQqrfIxKdXOEBP/w6gSrVhZIMFQ44l0g=; b=iMTkpSdjQvCKuQA09mJ70dAuUT8LxaEZpq+/HTtQtM85riX/7suNb7mOfOKQLeQwgFEgZ80kmTsUxkPOK0jh73A9BUt3AmXyYbm4RhzqKDJVnXHOqj0BQqibKCBAdPWHPLFp+aa/4sVGagu+bheK5mrgxqip9F5920StJkiXskU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93659+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1663002827405703.4336644587452; Mon, 12 Sep 2022 10:13:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id UQU6YY1788612xNwCPDzJWOK; Mon, 12 Sep 2022 10:13:47 -0700 X-Received: from mail-qt1-f176.google.com (mail-qt1-f176.google.com [209.85.160.176]) by mx.groups.io with SMTP id smtpd.web09.1286.1663002826321025760 for ; Mon, 12 Sep 2022 10:13:46 -0700 X-Received: by mail-qt1-f176.google.com with SMTP id b23so1797993qtr.13 for ; Mon, 12 Sep 2022 10:13:46 -0700 (PDT) X-Gm-Message-State: 1tDl7OhiROoDpvnOGSN582CNx1787277AA= X-Google-Smtp-Source: AA6agR69UDszk4DX/oTdoxI09BwGQeqHVr6jSy/JNaONgIr2wLrrwIQ5xIKjNPqVUzlj6dFXf+dDNw== X-Received: by 2002:ac8:5d8d:0:b0:344:a747:ac00 with SMTP id d13-20020ac85d8d000000b00344a747ac00mr24086483qtx.205.1663002825112; Mon, 12 Sep 2022 10:13:45 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:579e:d875:fc8f:d092]) by smtp.gmail.com with ESMTPSA id s5-20020ac87585000000b00346414a0ca1sm6863540qtq.1.2022.09.12.10.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 10:13:44 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Sai Chaganty , Isaac Oram , Liming Gao Subject: [edk2-devel] [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume Date: Mon, 12 Sep 2022 13:12:48 -0400 Message-Id: <20220912171250.1515536-3-benjamin.doron00@gmail.com> In-Reply-To: <20220912171250.1515536-1-benjamin.doron00@gmail.com> References: <20220912171250.1515536-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1663002827; bh=xV3EGxuNkI8HOVT1/CviLzUGbyayqWAukKgWz2LT8cQ=; h=Cc:Date:From:Reply-To:Subject:To; b=WFM1TNGwd+Fgv42cbPwp6f5R6keLBCcUonDYqt26l4TpbpvWBwxjk4F+QZ8cisrmGwU nZIP2utxTlUL1SWcL7fe6kEiICXMs9YYvtrHGZAdRkj/8/nf9xyrfAfOeFyhWaE+vs89H iSxHozwxgZhWclyWhAGPdNXR7CqdNV4YQtI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1663002829216100012 Content-Type: text/plain; charset="utf-8" Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries (policy overrides) required for successful S3 resume. Factored allocation logic into new module to avoid MinPlatform dependency on S3Feature package. TODO: Can optimise required size. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Signed-off-by: Benjamin Doron Reviewed-by: Isaac Oram --- .../S3FeaturePkg/Include/PostMemory.fdf | 12 ++ .../S3FeaturePkg/Include/PreMemory.fdf | 8 +- .../S3FeaturePkg/Include/S3Feature.dsc | 36 +++- .../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++ .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++ .../S3FeaturePkg/S3FeaturePkg.dsc | 3 + .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++- .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- .../Include/AcpiS3MemoryNvData.h | 22 +++ 9 files changed, 365 insertions(+), 11 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .c create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .inf create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvDat= a.h diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory= .fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf index 9e17f853c630..4e87b3e68d1a 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf @@ -2,7 +2,19 @@ # FDF file for post-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +## Dependencies + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + +## Save-state module stack + INF S3FeaturePkg/S3Dxe/S3Dxe.inf + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + +## Restore-state module stack + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor= Dxe.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.= fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index fdd16a4e0356..e130fa5f098d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -2,9 +2,15 @@ # FDF file for pre-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 -INF S3FeaturePkg/S3Pei/S3Pei.inf +## Dependencies + INF S3FeaturePkg/S3Pei/S3Pei.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + +## Restore-state module stack + INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.= dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index cc34e785076a..29e8f9e8530d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -7,6 +7,7 @@ # for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,6 +26,10 @@ !error "DXE_ARCH must be specified to build this feature!" !endif =20 +[PcdsFixedAtBuild] + # Attempts to improve performance at the cost of more DRAM usage + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE + ##########################################################################= ###### # # Library Class section - list of all Library Classes needed by this featu= re. @@ -32,7 +37,13 @@ ##########################################################################= ###### =20 [LibraryClasses.common.PEIM] - SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf + SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLi= b/PeiSmmControlLib.inf + +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf =20 ##########################################################################= ###### # @@ -60,8 +71,25 @@ # S3 Feature Package ##################################### =20 - # Add library instances here that are not included in package components= and should be tested - # in the package build. - # Add components here that should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf + +# +# Feature DXE Components +# + +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308 +# is completed. +[Components.X64] + ##################################### + # S3 Feature Package + ##################################### + + # Add components here that should be included in the package build. + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + S3FeaturePkg/S3Dxe/S3Dxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c new file mode 100644 index 000000000000..1a7ccb8eedab --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c @@ -0,0 +1,155 @@ +/** @file + Source code file for S3 DXE module + +Copyright (c) 2022, Baruch Binyamin Doron.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE) + +/** + Get the mem size in memory type information table. + + @return the mem size in memory type information table. +**/ +UINT64 +EFIAPI +GetMemorySizeInMemoryTypeInformation ( + VOID + ) +{ + EFI_STATUS Status; + EFI_MEMORY_TYPE_INFORMATION *MemoryData; + UINT8 Index; + UINTN TempPageNum; + + Status =3D EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGui= d, (VOID **) &MemoryData); + + if (EFI_ERROR (Status) || MemoryData =3D=3D NULL) { + return 0; + } + + TempPageNum =3D 0; + for (Index =3D 0; MemoryData[Index].Type !=3D EfiMaxMemoryType; Index++)= { + // + // Accumulate default memory size requirements + // + TempPageNum +=3D MemoryData[Index].NumberOfPages; + } + + return TempPageNum * EFI_PAGE_SIZE; +} + +/** + Get the mem size need to be consumed and reserved for PEI phase resume. + + @return the mem size to be reserved for PEI phase resume. +**/ +UINT64 +EFIAPI +GetPeiMemSize ( + VOID + ) +{ + UINT64 Size; + + Size =3D GetMemorySizeInMemoryTypeInformation (); + + return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +/** + Allocate EfiACPIMemoryNVS below 4G memory address. + + This function allocates EfiACPIMemoryNVS below 4G memory address. + + @param Size Size of memory to allocate. + + @return Allocated address for output. + +**/ +VOID * +EFIAPI +AllocateAcpiNvsMemoryBelow4G ( + IN UINTN Size + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + VOID *Buffer; + + Pages =3D EFI_SIZE_TO_PAGES (Size); + Address =3D 0xffffffff; + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + ASSERT_EFI_ERROR (Status); + + Buffer =3D (VOID *)(UINTN)Address; + ZeroMem (Buffer, Size); + + return Buffer; +} + +/** + Allocates memory to use on S3 resume. + + @param[in] ImageHandle Not used. + @param[in] SystemTable General purpose services available to e= very DXE driver. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +S3DxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT64 S3PeiMemSize; + UINT64 S3PeiMemBase; + ACPI_S3_MEMORY S3MemoryInfo; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__)); + + S3PeiMemSize =3D GetPeiMemSize (); + S3PeiMemBase =3D (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize); + ASSERT (S3PeiMemBase !=3D 0); + + S3MemoryInfo.S3PeiMemBase =3D S3PeiMemBase; + S3MemoryInfo.S3PeiMemSize =3D S3PeiMemSize; + + DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase)); + DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize)); + + Status =3D gRT->SetVariable ( + ACPI_S3_MEMORY_NV_NAME, + &gEfiAcpiVariableGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACC= ESS, + sizeof (S3MemoryInfo), + &S3MemoryInfo + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__)); + return EFI_SUCCESS; +} diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf new file mode 100644 index 000000000000..28589c2c869b --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf @@ -0,0 +1,49 @@ +### @file +# Component information file for the S3 DXE module. +# +# Copyright (c) 2022, Baruch Binyamin Doron.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D S3Dxe + FILE_GUID =3D 30926F92-CC83-4381-9F70-AC96EDB5BEE0 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + ENTRY_POINT =3D S3DxeEntryPoint + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + DebugLib + PcdLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + S3FeaturePkg/S3FeaturePkg.dec + +[Sources] + S3Dxe.c + +[Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize + +[FeaturePcd] + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable + +[Guids] + gEfiMemoryTypeInformationGuid ## CONSUMES + gEfiAcpiVariableGuid ## CONSUMES + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc b= /Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc index 2d1d197b2a95..cd4b1c4f198f 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc @@ -41,6 +41,9 @@ !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc =20 +[LibraryClasses.common.PEIM] + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf + # # This package always builds the feature. # diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c index b0aaa04962c8..6acb894b6fc9 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c @@ -2,12 +2,87 @@ Source code file for S3 PEI module =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Baruch Binyamin Doron.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 +#include +#include +#include #include #include +#include + +// TODO: Finalise implementation factoring +#define R_SA_PAM0 (0x80) +#define R_SA_PAM5 (0x85) +#define R_SA_PAM6 (0x86) + +/** + This function is called after FspSiliconInitDone installed PPI. + For FSP API mode, this is when FSP-M HOBs are installed into EDK2. + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Always return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +FspSiliconInitDoneNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT64 MchBaseAddress; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // Enable PAM regions for AP wakeup vector (resume) + // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here? + // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (te= st resume). Should we? + // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defin= ed for KabylakeSiliconPkg. + // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - th= is does not mean + // that the memory is unusable, perhaps this is precisely because it w= ill contain + // the AP wakeup vector. + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + MchBaseAddress =3D PCI_LIB_ADDRESS (0, 0, 0, 0); + PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33); + PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33); + PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33); + } + + // + // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case + // + Status =3D PeiInstallSmmAccessPpi (); + ASSERT_EFI_ERROR (Status); + + // + // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case + // + Status =3D PeiInstallSmmControlPpi (); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gFspSiliconInitDonePpiGuid, + FspSiliconInitDoneNotify +}; =20 /** S3 PEI module entry point @@ -25,12 +100,10 @@ S3PeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; + EFI_STATUS Status; =20 - // - // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case - // - Status =3D PeiInstallSmmAccessPpi (); + Status =3D PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc); + ASSERT_EFI_ERROR (Status); =20 return Status; } diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf index e485eac9521f..173919bb881e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -18,10 +18,13 @@ [LibraryClasses] PeimEntryPoint PeiServicesLib + DebugLib SmmAccessLib + SmmControlLib =20 [Packages] MdePkg/MdePkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/S3FeaturePkg.dec =20 @@ -31,5 +34,8 @@ [FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =20 +[Ppis] + gFspSiliconInitDonePpiGuid + [Depex] - gEfiPeiMemoryDiscoveredPpiGuid + TRUE diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/P= latform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h new file mode 100644 index 000000000000..0d75af8e9a03 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h @@ -0,0 +1,22 @@ +/** @file + Header file for NV data structure definition. + +Copyright (c) 2021, Baruch Binyamin Doron +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ACPI_S3_MEMORY_NV_DATA_H__ +#define __ACPI_S3_MEMORY_NV_DATA_H__ + +// +// NV data structure +// +typedef struct { + UINT64 S3PeiMemBase; + UINT64 S3PeiMemSize; +} ACPI_S3_MEMORY; + +#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo" + +#endif --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93659): https://edk2.groups.io/g/devel/message/93659 Mute This Topic: https://groups.io/mt/93637580/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 8 20:27:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93660+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93660+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1663002828; cv=none; d=zohomail.com; s=zohoarc; b=VPZe5l7VaH/ZFNJ4b81rLYAhh6EBmjCKkpBcdCErdLjwaGN7P+kgUXcdgwqScerIMFwEp3wyLNE7IDnRS3DZhyAL77dtOuVfJb90YNodkS9/YkVG7B1JAn7YN6DAmUXn107ZWy7fmY2Q48wlnYFSqx6+bZdGbtjRzH0+K9m+4/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663002828; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qDFHoL/ya0dGi16MJk1mhoS2pu6MZFNTlTXicHDNenY=; b=exzJrk639wV4B2X32ohHmbXM2aXZTLtON6QMZDAokWzh7KwBE3WLAoHYKbKlkVkfwAKM30odS5V7DLJLSieeJUwQCiXMKW8kYNrFvsNLLmhQceaQj01pXLyqpTULoKBtUj75PsL9GfWJzI7c8gGHKtnzvCAvSm/+ItvuJahEDRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93660+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1663002828877290.57432959149423; Mon, 12 Sep 2022 10:13:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 09iXYY1788612xbsP80QhnRx; Mon, 12 Sep 2022 10:13:48 -0700 X-Received: from mail-qk1-f173.google.com (mail-qk1-f173.google.com [209.85.222.173]) by mx.groups.io with SMTP id smtpd.web11.1284.1663002827717951297 for ; Mon, 12 Sep 2022 10:13:47 -0700 X-Received: by mail-qk1-f173.google.com with SMTP id d15so6510050qka.9 for ; Mon, 12 Sep 2022 10:13:47 -0700 (PDT) X-Gm-Message-State: wgcCfH2usNV1etdgRuEBO3bUx1787277AA= X-Google-Smtp-Source: AA6agR68lDeClu3mazkDyVRk6FWUl0QW559Xr6wvEap8G5YypeQcxnNVnIjQcOj45b2OGuCLQZ+RHA== X-Received: by 2002:a05:620a:15a1:b0:6cc:f925:7c89 with SMTP id f1-20020a05620a15a100b006ccf9257c89mr11487462qkk.319.1663002826619; Mon, 12 Sep 2022 10:13:46 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:579e:d875:fc8f:d092]) by smtp.gmail.com with ESMTPSA id s5-20020ac87585000000b00346414a0ca1sm6863540qtq.1.2022.09.12.10.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 10:13:46 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Ankit Sinha , Isaac Oram , Liming Gao , Eric Dong Subject: [edk2-devel] [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: Implement working S3 resume Date: Mon, 12 Sep 2022 13:12:49 -0400 Message-Id: <20220912171250.1515536-4-benjamin.doron00@gmail.com> In-Reply-To: <20220912171250.1515536-1-benjamin.doron00@gmail.com> References: <20220912171250.1515536-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1663002828; bh=npVT0HBLBUZT4IVvBzLZ0uLwMyf+J+horz7fmzIAG0A=; h=Cc:Date:From:Reply-To:Subject:To; b=QIcMYHtg4BO8A0SMsA/h+u8u13gaKXx4yLp6wjlyhtBGp+KDzdFIOB8UT3fwy74c2Oe tjnTZrN+ZqWGZLLbU961Jp+pZyjgi/xaXhZdPTfHgkE86YIXqvr2bI/jX5yHXRjQt/EeZ h/XJXWt4qp1v8ISXGntGa6oqOfj2lbVaLR4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1663002829177100011 Content-Type: text/plain; charset="utf-8" Consume S3 resume memory allocation on resume flow. Also, include complementary FirmwarePerformanceDataTablePei module in MinPlatform FV for S3 resume performance measurement. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Cc: Isaac Oram Cc: Liming Gao Cc: Eric Dong Signed-off-by: Benjamin Doron Reviewed-by: Isaac Oram --- .../FspWrapperHobProcessLib.c | 69 ++++++++++++++++++- .../PeiFspWrapperHobProcessLib.inf | 2 + .../Include/Dsc/CorePeiInclude.dsc | 2 + .../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++ 4 files changed, 76 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapper= HobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/Fsp= Wrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c index 7ee4d3a31c49..9bd6fe6290c5 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/FspWrapperHobProcessLib.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/FspWrapperHobProcessLib.c @@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include #include #include #include +#include =20 #include +#include =20 // // Additional pages are used by DXE memory manager. @@ -130,6 +133,55 @@ GetPeiMemSize ( return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE; } =20 +/** + Get S3 PEI memory information. + + @note At this point, memory is ready, and PeiServices are available to u= se. + Platform can get some data from SMRAM directly. + + @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase. + @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase. + + @return If S3 PEI memory information is got successfully. +**/ +EFI_STATUS +EFIAPI +GetS3MemoryInfo ( + OUT UINT64 *S3PeiMemSize, + OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; + UINTN DataSize; + ACPI_S3_MEMORY S3MemoryInfo; + + *S3PeiMemBase =3D 0; + *S3PeiMemSize =3D 0; + + Status =3D PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NU= LL, (VOID **) &VariablePpi); + ASSERT_EFI_ERROR (Status); + + DataSize =3D sizeof (S3MemoryInfo); + Status =3D VariablePpi->GetVariable ( + VariablePpi, + ACPI_S3_MEMORY_NV_NAME, + &gEfiAcpiVariableGuid, + NULL, + &DataSize, + &S3MemoryInfo + ); + ASSERT_EFI_ERROR (Status); + + if (EFI_ERROR (Status)) { + return Status; + } + + *S3PeiMemBase =3D S3MemoryInfo.S3PeiMemBase; + *S3PeiMemSize =3D S3MemoryInfo.S3PeiMemSize; + return EFI_SUCCESS; +} + /** Post FSP-M HOB process for Memory Resource Descriptor. =20 @@ -280,7 +332,7 @@ PostFspmHobProcess ( 0x1000 ); =20 - + if (BootMode !=3D BOOT_ON_S3_RESUME) { // // Capsule mode // @@ -337,7 +389,22 @@ PostFspmHobProcess ( if (Capsule !=3D NULL) { Status =3D Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, C= apsuleBuffer, CapsuleBufferLength); } + } else { + Status =3D GetS3MemoryInfo (&PeiMemSize, &PeiMemBase); + ASSERT_EFI_ERROR (Status); =20 + DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBa= se)); + DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSi= ze)); + + // + // Install efi memory + // + Status =3D PeiServicesInstallPeiMemory ( + PeiMemBase, + PeiMemSize + ); + ASSERT_EFI_ERROR (Status); + } =20 // // Create a memory allocation HOB at fixed location for MP Services PPI = AP wait loop. diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapper= HobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPk= g/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.= inf index b846e7af1d2d..e2aac36bf018 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf @@ -75,7 +75,9 @@ gZeroGuid gEfiGraphicsInfoHobGuid gEfiGraphicsDeviceInfoHobGuid + gEfiAcpiVariableGuid =20 [Ppis] gEfiPeiCapsulePpiGuid ## CONSUMES + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES gEdkiiSiliconInitializedPpiGuid ## PRODUCES diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b= /Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc index 08e50cac075f..f271fb26b189 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc @@ -41,3 +41,5 @@ NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf } !endif + + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerf= ormancePei.inf diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclud= e.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf index 3c2716d6728a..3edc239e5264 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf @@ -6,3 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwar= ePerformancePei.inf +!endif --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93660): https://edk2.groups.io/g/devel/message/93660 Mute This Topic: https://groups.io/mt/93637581/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 8 20:27:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93661+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93661+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1663002831; cv=none; d=zohomail.com; s=zohoarc; b=gzoGbr7F37UA/51J+6UWW/2vEw2Ezu3LnsmVV196cw8a7tDyvgf/tK4M5Gj43+lp8yXTGEpao+PvdE8ammryF9YD8dsnY6oq8FG1gYbW2ghkscu4+8dgCjEKKltwSK4ILxpH5DCEcUftG+4mRFevxx8jG3vHLmuGNxbq566yMfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663002831; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=G1WP61TXU3Vy94gmuUNWiUSlNqXgpOd5dJP10BZ3KZQ=; b=CFZ4KVpyUMBdm0Er1H3Y+NxAVFyCj9xUeN/zuUzAvugvdGUxBdXQ8q7sl/qLRYexUONsMDvCdG6OKwUj6ivq0cS8F9JXGFyCOZpTRXAywlgLTnrpogllSMBMPHQwqGc08ZdVj99juX+yAJvDUpw48vS29zqXZz3Us82HcCVsMkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93661+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1663002831560744.7170034045799; Mon, 12 Sep 2022 10:13:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RG1xYY1788612xom9Alcxg9v; Mon, 12 Sep 2022 10:13:50 -0700 X-Received: from mail-qk1-f169.google.com (mail-qk1-f169.google.com [209.85.222.169]) by mx.groups.io with SMTP id smtpd.web11.1285.1663002829346115139 for ; Mon, 12 Sep 2022 10:13:49 -0700 X-Received: by mail-qk1-f169.google.com with SMTP id 3so6120498qka.5 for ; Mon, 12 Sep 2022 10:13:49 -0700 (PDT) X-Gm-Message-State: s7mMvlpU6xgozoDaFIGHZnf7x1787277AA= X-Google-Smtp-Source: AA6agR4wf1wR4hqp5mAvSoOVD5jCci43gl4iyFr0VUkvzgtbDcvSUtpUopA8sU+qfszNemPDPapPBA== X-Received: by 2002:a05:620a:3192:b0:6cb:b2cd:f3a2 with SMTP id bi18-20020a05620a319200b006cbb2cdf3a2mr18603662qkb.2.1663002828039; Mon, 12 Sep 2022 10:13:48 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:579e:d875:fc8f:d092]) by smtp.gmail.com with ESMTPSA id s5-20020ac87585000000b00346414a0ca1sm6863540qtq.1.2022.09.12.10.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 10:13:47 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Chasel Chiu , Jeremy Soller , Sai Chaganty , Isaac Oram Subject: [edk2-devel] [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3 Date: Mon, 12 Sep 2022 13:12:50 -0400 Message-Id: <20220912171250.1515536-5-benjamin.doron00@gmail.com> In-Reply-To: <20220912171250.1515536-1-benjamin.doron00@gmail.com> References: <20220912171250.1515536-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1663002830; bh=DTjaMuJFk49Bx/m7iW2toZTe+lm+Ir2TKyM7XAm/NPE=; h=Cc:Date:From:Reply-To:Subject:To; b=Iw45nF40lkj/J4jPy73vv9nyOxhgFYb94cXEmqSDOB5T4pLNstHcAmiOCBCfD8EkZ6a mGcj5NlyUVEz4MrDREPpF01tQQrOU2tzldBAbLBYGHTXEVpLoY7NWs8qflQroLPRPF6BN 4pRUJ1oEKvf3+v3s3rQGYbyKnrb8Ih8JbLI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1663002833248100019 Content-Type: text/plain; charset="utf-8" Use silicon code to detect S3 resume state. Apply some relevant policy modifications. PcdPeiMemSize must be in common scope, for a DXE module to allocate required memory. Libraries that produce required PPIs are defined. BootScriptExecutorDxe should only be linked against a functionally compatible debug stack. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Chasel Chiu Cc: Jeremy Soller Cc: Sai Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron Reviewed-by: Isaac Oram --- .../PeiFspMiscUpdUpdateLib.c | 12 +++++- .../PeiSaPolicyUpdate.c | 12 +++++- .../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++++++++++-------- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 ++ .../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 ++++++++++ .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 ++------ .../PeiSiliconPolicyUpdateLib.c | 11 +++++- .../PeiSiliconPolicyUpdateLib.inf | 1 + .../PeiFspMiscUpdUpdateLib.c | 11 +++++- .../PeiSaPolicyUpdate.c | 12 +++++- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++++++++++++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../GalagoPro3/OpenBoardPkg.dsc | 15 ++++++++ .../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +- .../PeiFspMiscUpdUpdateLib.c | 12 +++++- .../PeiSaPolicyUpdate.c | 12 +++++- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../PeiKabylakeRvp3InitPreMemLib.c | 27 ++++++++++++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++++++ .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +- .../PeiSiliconPolicyUpdateLib.c | 11 +++++- .../PeiSiliconPolicyUpdateLib.inf | 1 + 24 files changed, 222 insertions(+), 40 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform= /Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index a9b7e446c8d6..7e4194bf4fe6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include + #include #include #include @@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c index 4621cbd3ca3a..98db86570368 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -40,7 +46,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialization is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeO= penBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInit= PreMemLib.c index 1c9a65399b54..3029354b96cd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c @@ -11,7 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include +#include #include #include #include @@ -267,25 +269,31 @@ AspireVn7Dash572GBoardBootModeDetect ( VOID ) { - UINT16 ABase; + EFI_BOOT_MODE BootMode; UINT32 SleepType; =20 DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); =20 - // TODO: Perform advanced detection (recovery/capsule) - // FIXME: This violates PI specification? But BOOT_WITH* would always ta= ke precedence - // over BOOT_ON_S{4,5}... - PchAcpiBaseGet (&ABase); - SleepType =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT= _SLP_TYP; + // Known sane defaults; TODO: Consider "default"? + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; =20 - switch (SleepType) { - case V_PCH_ACPI_PM1_CNT_S3: - return BOOT_ON_S3_RESUME; - case V_PCH_ACPI_PM1_CNT_S4: - return BOOT_ON_S4_RESUME; -// case V_PCH_ACPI_PM1_CNT_S5: -// return BOOT_ON_S5_RESUME; - default: - return BOOT_WITH_FULL_CONFIGURATION; + // TODO: Perform advanced detection (capsule/recovery) + // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assu= me" + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index cd9f979d313c..c53114e15450 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf @@ -25,11 +25,14 @@ TimerLib PchCycleDecodingLib PchResetLib + PciLib IoLib EcLib BoardEcLib GpioLib PeiLib + PeiServicesLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.dsc index efe29c617a02..20c42a7c1c20 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -249,6 +249,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -712,6 +713,26 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Library cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # Reverse-ranked priority list +# TODO: Requires testing +# - Strongly suspect DebugLibSerialPort constructor presents PeiDxeSerialP= ortLibMem dependency on services as a bug +!if FALSE # $(USE_MEMORY_LOGGING) =3D=3D TRUE + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialP= ortLibMem.inf +!endif + # Also, can debug CpuExceptionHandlerLib +!if $(USE_HDMI_DEBUG_PORT) =3D=3D TRUE + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPo= rtLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf +!endif + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoa= rdPkgPcd.dsc index 3ed7aa0a2b10..490c3ee6bf76 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc @@ -127,10 +127,7 @@ # PcdIpmiFeatureEnable will not be enabled (no BMC) # TODO: Can be build-time (user) choice gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable = |FALSE - # TODO: Continue developing support. Broken at present. - # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub - # - May require a PeiSmmControlLib to SMM communicate - gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |FALSE + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |TRUE # TODO: Definitions (now added SmbiosDxe) gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable = |TRUE # Requires actual hook-up @@ -335,6 +332,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -360,13 +358,8 @@ # 0x7F, 0xFF, 0x04, 0x00}
gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x02, 0x= 01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03,= 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0x04, 0x00} =20 -!if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x800 -!else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B #= TODO -!endif - # TODO: Consider using reserved space instead for debug log - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x200 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x4800 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100 !if $(TARGET) =3D=3D RELEASE gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 !else @@ -447,7 +440,6 @@ # Edk2 Configuration ###################################### gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp= dateLib/PeiSiliconPolicyUpdateLib.c index 3764f7c3ac09..04cd2e741489 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; @@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem ( =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + GtConfig =3D NULL; Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig); ASSERT_EFI_ERROR (Status); @@ -571,7 +576,11 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialization is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf index 1ce26fc3dcec..31a45292209d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib MemoryAllocationLib PeiLib + PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/= KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLi= bFsp/PeiFspMiscUpdUpdateLib.c index dbc84631acaa..ce309bd378d2 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include @@ -36,11 +37,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -75,7 +80,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/Kabyl= akeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/= PeiSaPolicyUpdate.c index 133b8c963f65..6fd45cc79f61 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialization is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Galag= oPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index d6c91cd2b94b..5b3a6921d0ee 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf @@ -23,6 +23,7 @@ PcdLib SiliconInitLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Ga= lagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c index 051dac0b204d..1cd2baf4a4dd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiGalagoPro3InitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiGalagoPro3InitPreMemLib.c @@ -14,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -236,5 +237,29 @@ GalagoPro3BoardBootModeDetect ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; + EFI_BOOT_MODE BootMode; + UINT32 SleepType; + + DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); + + // Known sane defaults + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } + } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/= GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index fe31f421356e..20ddac1d994d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf @@ -25,6 +25,7 @@ SiliconInitLib MultiBoardInitSupportLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index f0e9a21ccad9..219ef20e55f0 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -180,6 +180,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -494,6 +495,20 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Libraries cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # Reverse-ranked priority list +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdI2cHdmiDebugPortEnable =3D=3D T= RUE + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPo= rtLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf +!endif + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index 8180312f5ca5..7a73f5a831c6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -279,6 +279,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -380,7 +381,6 @@ ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Inte= l/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpda= teLibFsp/PeiFspMiscUpdUpdateLib.c index 699f4297fad6..71b03f2da464 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include #include - #include #include #include @@ -36,11 +36,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -73,7 +77,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/Kab= ylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLib= Fsp/PeiSaPolicyUpdate.c index d6ec3e38dd7e..e855207af0d1 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialization is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Kab= ylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 850fc514188b..e0022e8d6118 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf @@ -24,6 +24,7 @@ SiliconInitLib EcLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c index 87ae3b531ed6..02cd37227e50 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -330,5 +331,29 @@ KabylakeRvp3BoardBootModeDetect ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; + EFI_BOOT_MODE BootMode; + UINT32 SleepType; + + DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); + + // Known sane defaults + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } + } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index 23fe6b6f03c5..0112bf84a193 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf @@ -26,6 +26,7 @@ MultiBoardInitSupportLib EcLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 37837eeb04bf..1634d9b31f00 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -202,6 +202,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -506,6 +507,17 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Libraries cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # TODO: Insert a reverse-ranked priority list of compatible librarie= s here + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index cfd032814850..87510748783f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -279,6 +279,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -349,7 +350,6 @@ ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/Ka= bylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/Pe= iSiliconPolicyUpdateLib.c index 22aadc0221df..bd3da7f38416 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -513,6 +514,7 @@ SiliconPolicyUpdatePostMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; @@ -521,6 +523,9 @@ SiliconPolicyUpdatePostMem ( =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + GtConfig =3D NULL; Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig); ASSERT_EFI_ERROR (Status); @@ -535,7 +540,11 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialization is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/= PeiSiliconPolicyUpdateLib.inf index 25eae88f5989..e9a23593e133 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib MemoryAllocationLib PeiLib + PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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