From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93377+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93377+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549100; cv=none; d=zohomail.com; s=zohoarc; b=FAwuUUzTdxLt2HDPFJ8RcKlw9MldD8cueVvCYyJnSyHJii1I8/sxFaMBW/JD17w4tEIo8p+2BJY2iGOGcvEqLmYuKFDcqobyd/eil26nUPIuKg7Ucq7UP6kNwq0i8J4gutz3O2785YfeunSHF36qC8yfIolr6488Dq0ieXgfI0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549100; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=adAKceLTeYmy0Rg7Qv2Z1BR4M8kfHfr0jSAEuv7STPc=; b=gpdfDmr/ObG6d9aNLubK7V9T8znRaJqba9szb0Q9tI5OmkQIx1HzsCwGKdOGYJsjrDNDjF9LTDK7oQgv/etnvDR9B91zx58XZCnoZS5mqJvH15scXOHPiF49+/ElLQ5mka4boTA/UPqMK7Z3DTPjdhnWC0RGAKqqYjaUlnb297c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93377+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549100487165.33062605064686; Wed, 7 Sep 2022 04:11:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id E7MnYY1788612xNntoOg7cii; Wed, 07 Sep 2022 04:11:40 -0700 X-Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) by mx.groups.io with SMTP id smtpd.web10.6307.1662549099419980065 for ; Wed, 07 Sep 2022 04:11:39 -0700 X-Received: by mail-pf1-f177.google.com with SMTP id y127so14288070pfy.5 for ; Wed, 07 Sep 2022 04:11:39 -0700 (PDT) X-Gm-Message-State: AZ4b5H2ZyvmqxgQPs8390XoZx1787277AA= X-Google-Smtp-Source: AA6agR5vHBcP0UNqxsjNORCYbYXMB1CB+mUTpvUFvQfXKeH6OFc28gSqysQfR2Xc5cavwwYJL+eooQ== X-Received: by 2002:a63:455d:0:b0:434:d167:55cf with SMTP id u29-20020a63455d000000b00434d16755cfmr2870558pgk.28.1662549098692; Wed, 07 Sep 2022 04:11:38 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:11:38 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 01/19] MdePkg/Register: Add register definition header files for RISC-V Date: Wed, 7 Sep 2022 16:41:07 +0530 Message-Id: <20220907111125.539698-2-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549100; bh=GzwUftspzRl9d4lTPwEOzZoJDNjVEUvXYUeJ2Z9guRw=; h=Cc:Date:From:Reply-To:Subject:To; b=HQqigoIomL37nWTrkqnFLU9iCpNYRIbAvKX5UrhpiXICqt3/RCkn22MgX4k4IESH1hK 8tyWacRdqWAhEpINBO/iJlIzS2sdfNK0DfOdWeFBn5Fp7+xh2OAELkTGmuSCwWL9Pk0a0 rKYm04f1/9Wtw9SUMEcBhDApR3ipgbJ/ciI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549102188100003 Content-Type: text/plain; charset="utf-8" Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Signed-off-by: Sunil V L --- MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 ++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 +++++++ MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 129 ++++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 ++++ 4 files changed, 303 insertions(+) diff --git a/MdePkg/Include/Register/RiscV64/RiscVAsm.h b/MdePkg/Include/Re= gister/RiscV64/RiscVAsm.h new file mode 100644 index 000000000000..e566061b73e2 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVAsm.h @@ -0,0 +1,104 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_ASM_H__ +#define __RISCV_ASM_H__ + +#include + +#ifdef __ASSEMBLER__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#ifndef __ASSEMBLER__ + +#define csr_swap(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \ + : "=3Dr"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_read(csr) \ + ({ \ + register unsigned long __v; \ + __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \ + : "=3Dr"(__v) \ + : \ + : "memory"); \ + __v; \ + }) + +#define csr_write(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define csr_read_set(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \ + : "=3Dr"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_set(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define csr_read_clear(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \ + : "=3Dr"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_clear(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define wfi() \ + do { \ + __asm__ __volatile__("wfi" ::: "memory"); \ + } while (0) + +#define ebreak() \ + do { \ + __asm__ __volatile__("ebreak" ::: "memory"); \ + } while (0) + + +#endif /* !__ASSEMBLER__ */ + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVConst.h b/MdePkg/Include/= Register/RiscV64/RiscVConst.h new file mode 100644 index 000000000000..ea7e15119150 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVConst.h @@ -0,0 +1,46 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.
+ * + * Authors: + * Anup Patel + * This is leveraged from sbi_const.h in opensbi. + */ + +#ifndef __RISCV_CONST_H__ +#define __RISCV_CONST_H__ + +/* + * Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define __STR(s) #s +#define STRINGIFY(s) __STR(s) + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..5ad66ee7e7de --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,129 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_ENCODING_H__ +#define __RISCV_ENCODING_H__ + +#include + +/* clang-format off */ +#define MSTATUS_SIE _UL(0x00000002) +#define MSTATUS_MIE _UL(0x00000008) +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (_UL(1) << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE _UL(0x00000040) +#define MSTATUS_MPIE _UL(0x00000080) +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (_UL(1) << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (_UL(3) << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (_UL(1) << IRQ_S_SOFT) +#define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT) +#define MIP_MSIP (_UL(1) << IRQ_M_SOFT) +#define MIP_STIP (_UL(1) << IRQ_S_TIMER) +#define MIP_VSTIP (_UL(1) << IRQ_VS_TIMER) +#define MIP_MTIP (_UL(1) << IRQ_M_TIMER) +#define MIP_SEIP (_UL(1) << IRQ_S_EXT) +#define MIP_VSEIP (_UL(1) << IRQ_VS_EXT) +#define MIP_MEIP (_UL(1) << IRQ_M_EXT) +#define MIP_SGEIP (_UL(1) << IRQ_S_GEXT) +#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U _UL(0) +#define PRV_S _UL(1) +#define PRV_M _UL(3) + +#define SATP64_MODE _ULL(0xF000000000000000) +#define SATP64_ASID _ULL(0x0FFFF00000000000) +#define SATP64_PPN _ULL(0x00000FFFFFFFFFFF) + +#define SATP_MODE_OFF _UL(0) +#define SATP_MODE_SV32 _UL(1) +#define SATP_MODE_SV39 _UL(8) +#define SATP_MODE_SV48 _UL(9) +#define SATP_MODE_SV57 _UL(10) +#define SATP_MODE_SV64 _UL(11) + + +#define SATP_MODE SATP64_MODE + +/* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* =3D=3D=3D=3D=3D Supervisor-level CSRs =3D=3D=3D=3D=3D */ + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* =3D=3D=3D=3D=3D Trap/Exception Causes =3D=3D=3D=3D=3D */ + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..e9ccd34039ed --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,24 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __RISCV_IMPL_H_ +#define __RISCV_IMPL_H_ + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93377): https://edk2.groups.io/g/devel/message/93377 Mute This Topic: https://groups.io/mt/93522311/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93378+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93378+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549106; cv=none; d=zohomail.com; s=zohoarc; b=eJKcChKrhX2bBJdFa3Wa36sSdN4dJ2rdp0uE1bS4oRZ8LkGyB5CqT2AOL5nYsgvRxze5irDg/UJOqunLyXDrrsZ+CR9gi2t/NdPIJOrey8r9Ilux7uFypzKWo7fnuDm23J8TfVIV1V/wVtdsciEHP1hM8fsu5ZZu0hrwkfI3VGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549106; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=DFQD1I1RiDMcS6e86U+J0t6Al2mpSkbZGeXbxQNk1n0=; b=gkhmvNAgmbGY8smN6ZDLMV61qHOYfjxNU95GEcNClHLL0ORxTeffNumFdn+NsIgeEjfIdunMvm3nJaHFoF9/4gwb13d5Q6xif3axAZ39qBDGBJlEb8BZMzFSEQL+kLsXPIUcA4725mJWmLdRDfu8nAanxGP6pyxtGgfOHkBIPXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93378+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549106110172.619070529959; Wed, 7 Sep 2022 04:11:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tNoWYY1788612xMFsovlzKMQ; Wed, 07 Sep 2022 04:11:44 -0700 X-Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) by mx.groups.io with SMTP id smtpd.web10.6308.1662549104196316293 for ; Wed, 07 Sep 2022 04:11:44 -0700 X-Received: by mail-pg1-f178.google.com with SMTP id s206so13258699pgs.3 for ; Wed, 07 Sep 2022 04:11:44 -0700 (PDT) X-Gm-Message-State: H0ongZeQlLXWA6idiDCXLLWWx1787277AA= X-Google-Smtp-Source: AA6agR4CBDTnU7X+xCktdEWmAFhBHwBCsOVhiX7UBOiKurbFPCppvODkptmojXVS3JIkZf3xrJKRwg== X-Received: by 2002:a05:6a00:9a5:b0:536:29e:c91d with SMTP id u37-20020a056a0009a500b00536029ec91dmr3174290pfg.22.1662549103428; Wed, 07 Sep 2022 04:11:43 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:11:42 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 02/19] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Date: Wed, 7 Sep 2022 16:41:08 +0530 Message-Id: <20220907111125.539698-3-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549104; bh=hb4LO0uVbbaIDtuktHYwEo2fdy8tcWLBV2TyX8kgvXA=; h=Cc:Date:From:Reply-To:Subject:To; b=WorJqiNlN4cSLiR+AYM4yzJjTyg3Q4KMilEBKov2zfrMsYW7nAaTDQoHhOTrEk9+QAB 6PiwQDpOxVXotQ6kYX6fTn8y/lvRFFLkXPyYfaC5cJxFV5LpXPMU5ZOpyFKNIo3a1QVQG 1qS8ciNpcsl/DTavgwOFSYbuUTfQA8AkC5c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549108201100003 Content-Type: text/plain; charset="utf-8" RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition. Signed-off-by: Sunil V L --- MdePkg/MdePkg.dec | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index f1ebf9e251c1..8f1bcfdc3e97 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -1915,6 +1915,12 @@ [Protocols] ## Include/Protocol/ShellDynamicCommand.h gEfiShellDynamicCommandProtocolGuid =3D { 0x3c7200e9, 0x005f, 0x4ea4, {= 0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }} =20 + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid =3D { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x9= 5, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }} + # # [Error.gEfiMdePkgTokenSpaceGuid] # 0x80000001 | Invalid value provided. --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93378): https://edk2.groups.io/g/devel/message/93378 Mute This Topic: https://groups.io/mt/93522312/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93379+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93379+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549109; cv=none; d=zohomail.com; s=zohoarc; b=NX1GkMyd2pDA3zGPGtU3Y3Xx5NXLUGvlVIE1+mTRNaLwJJgV95lEChtK/ZCBqssJbDu6Y362x1iV0N31dD3yIMlXjtu6bP0piGukSevTtUmFiC8P6vMHflerxKXvxlV+ycQYDJnq5mSuJ9ZI6/hwJcJkdgmpk4yQ/hU8Q6CSz+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549109; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KRsLoxs9Oi3t4YyzXYBBaxl0yUdYNnhfYSFuJBkOM8c=; b=bY+zKBWpilAKpjTWNFWhxNH6DhSxLgh/gDKshg9CjpqtwjrUxgJup0H9zYuy0r8YD2C+wpESpQJYjLx1zaCc41vqsG+ZJ0Gy6vnwIGeEjijEGwJARhpFbS5oyuiJ5TQYkxNabvJSam3oTTAGf95u2UYDu/XZf7bBilfB5TCdFGk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93379+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166254910991367.78282783251223; Wed, 7 Sep 2022 04:11:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JbC6YY1788612xJYTfypJMSH; Wed, 07 Sep 2022 04:11:49 -0700 X-Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) by mx.groups.io with SMTP id smtpd.web10.6309.1662549108837533041 for ; Wed, 07 Sep 2022 04:11:48 -0700 X-Received: by mail-pf1-f170.google.com with SMTP id o126so5272238pfb.6 for ; Wed, 07 Sep 2022 04:11:48 -0700 (PDT) X-Gm-Message-State: nI3SALsgWdOh8Pd76w8odLVYx1787277AA= X-Google-Smtp-Source: AA6agR7mZtowmjroTOca5L3W1MAaf1h4lz9GhXwwnZN7Y22PHNjHIVtjBDhpwOUYA1rOq3aNSI2WnA== X-Received: by 2002:a63:8749:0:b0:430:83ed:ddfb with SMTP id i70-20020a638749000000b0043083edddfbmr2868085pge.346.1662549107975; Wed, 07 Sep 2022 04:11:47 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:11:47 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 03/19] MdePkg/Protocol: Add RiscVBootProtocol.h Date: Wed, 7 Sep 2022 16:41:09 +0530 Message-Id: <20220907111125.539698-4-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549109; bh=dD07NTDP5XA6ZPZqlxUuRE9Q+ZkkJ+FM8ofC6FA8e8E=; h=Cc:Date:From:Reply-To:Subject:To; b=Scv8SwBaOaSh3JR7eKMcyu+mWdUNipyAQCJr//JS49wSDCkq3JdTmqJJgRrsbn+fBOh +2sFaaMo/tXLzlgRcuodQK8lZ35uCWPF5Fh/VrYF+Jqy6tBCOmVT4JdoxZtnt3ISBWcPR 7EcL2pHH/Ua55tvctb+GubwY+KmdnDNbOtc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549110241100005 Content-Type: text/plain; charset="utf-8" RISC-V UEFI platforms need to implement RISCV_EFI_BOOT_PROTOCOL. Add header file with the definitions of this protocol. Signed-off-by: Sunil V L --- MdePkg/Include/Protocol/RiscVBootProtocol.h | 35 ++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h b/MdePkg/Include/P= rotocol/RiscVBootProtocol.h new file mode 100644 index 000000000000..7ceb7d830924 --- /dev/null +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,35 @@ + +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + Specification available at + https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RIS= CV_UEFI_PROTOCOL-spec.pdf + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _RISCV_BOOT_PROTOCOL_H_ +#define _RISCV_BOOT_PROTOCOL_H_ + +//extern EFI_GUID gRiscVEfiBootProtocolGuid; + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 +#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID) ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93379): https://edk2.groups.io/g/devel/message/93379 Mute This Topic: https://groups.io/mt/93522315/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93380+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93380+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549114; cv=none; d=zohomail.com; s=zohoarc; b=auVgsMZZHpbDHucKgaM4V5qvn60pO+jpwgHVptWBMvvOhFghyINzYH6gXDDe4MqBk9JhEPWmowqJ+RwTyjILhxncMMYw5/bVCUFXqD9lqLlEug7C0t7d5YG3sJPJQtmMo9l4dvp+y0he4qj3Gj780IfpvWg0ODIYhV1BRipcCy0= ARC-Message-Signature: i=1; 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Wed, 07 Sep 2022 04:11:53 -0700 X-Received: by mail-pj1-f50.google.com with SMTP id o4so14176064pjp.4 for ; Wed, 07 Sep 2022 04:11:53 -0700 (PDT) X-Gm-Message-State: jQfSIicx4aHMagWpL4LGthGVx1787277AA= X-Google-Smtp-Source: AA6agR6xsA8t0iV1bLbcxALyC+E1DmQ9vgphSUxkuj3O4RqdSaIXykjwiok17tb08iPcjlfE44KHYQ== X-Received: by 2002:a17:902:e8d8:b0:172:7e6b:c8ec with SMTP id v24-20020a170902e8d800b001727e6bc8ecmr3179230plg.171.1662549112628; Wed, 07 Sep 2022 04:11:52 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:11:52 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 04/19] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Date: Wed, 7 Sep 2022 16:41:10 +0530 Message-Id: <20220907111125.539698-5-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549113; bh=utY2HQeeZY+XHUgWthd7U2RseL7rH5cZuHjeXR0iv6E=; h=Cc:Date:From:Reply-To:Subject:To; b=lWtSW300auN04uu5pM66Q86sOgGLgLo/yhUC5eQoQzbaITyrZKrPwsx7axKijzlSbTk YlXViDB6fyGEImlWTaCcbsTglmx1MlVMBn6DUbEpsp5PmoE+rEQwoPWwWuT7A86zbeiNi yNJ3KP9qfR6bShg5Nvla0L0TQVc2ySq0Iyc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549116280100001 Content-Type: text/plain; charset="utf-8" Add few PCD variables for RISC-V platforms to indicate the memory locations of the firmware volumes, temporary RAM etc. Signed-off-by: Sunil V L --- MdeModulePkg/MdeModulePkg.dec | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 7d989108324a..557fc2f3d4a2 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2176,5 +2176,18 @@ [PcdsDynamicEx] # @Prompt 64bit VPD base address. gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64|0x0|UINT64|0x00030006 =20 +[PcdsFixedAtBuild.RISCV64] + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase|0|UINT32|0x50000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvSize|0|UINT32|0x50000001 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase|0|UINT32|0x50000003 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize|0|UINT32|0x50000004 + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase|0|UINT32|0x50000005 + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize|0|UINT32|0x50000006 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x50000= 007 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x50000008 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x50000009 + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT32|0x5000000a + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x5000000b + [UserExtensions.TianoCore."ExtraFiles"] MdeModulePkgExtra.uni --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 718323d9042c..5e94bde5fea9 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -350,6 +350,9 @@ [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsD= ynamic.X64, PcdsDynamicEx # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime = and ACPI NVS type after SmmReadyToLock. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0= x3213210F =20 +[PcdsFixedAtBuild.RISCV64] + gUefiCpuPkgTokenSpaceGuid.PcdRiscVTimerFrequencyInHz|0|UINT32|0x50000000 + [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DA= TA. # @Prompt The pointer to a CPU S3 data buffer. --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93381): https://edk2.groups.io/g/devel/message/93381 Mute This Topic: https://groups.io/mt/93522318/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93382+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93382+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549123; cv=none; d=zohomail.com; s=zohoarc; b=OG+P9NTP1shqVhhtrFqFoublcdCL/agFnBm5gnN58L47OnVU0aS2q3x8OPoFfhS+4H6bPwy0/WYt+7mVlOWajQk7m1v4Ngqmnk3QhNC7fokMoBVVGMKTCiMVWAguE4KxgrTapZoFtv8wscRxe1pJq8e7IogBqRuGA8k87AsyLFs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549123; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=81iUAKCPr/kJ5kBJUy0rzkvzzwnp6q3H+ZPy5UuP90k=; b=GFrmXn1XNZrZrzFTr+8mrHKwiiEW7K2QbiJ+bSP4hN5He8Kus8SQ8+SXNYoSNezyk71VnEbBkI0o4bnkiepzUPcktKsKFbOIKj+CmNEITttrbYyx7jp/yqpmJORReaniNobpNgK1bsxfklDAdxWgo4pIsE8eTMF7geSHbNvCsvE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93382+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549123962160.20957932624833; Wed, 7 Sep 2022 04:12:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id iXxIYY1788612xwOaYztthVk; Wed, 07 Sep 2022 04:12:03 -0700 X-Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web10.6313.1662549122987684154 for ; Wed, 07 Sep 2022 04:12:03 -0700 X-Received: by mail-pj1-f43.google.com with SMTP id p1-20020a17090a2d8100b0020040a3f75eso9476857pjd.4 for ; Wed, 07 Sep 2022 04:12:02 -0700 (PDT) X-Gm-Message-State: RNhalPBZ9MdxzFCfamqnotKDx1787277AA= X-Google-Smtp-Source: AA6agR486ubiFL95sOqEGL26Ah0vYsSiPObJhMY32zLZ0LJ3WVbejVMbkkfNFpWVvsm5Lo+PwDTmaw== X-Received: by 2002:a17:90b:2708:b0:200:22d2:6768 with SMTP id px8-20020a17090b270800b0020022d26768mr3460228pjb.73.1662549122289; Wed, 07 Sep 2022 04:12:02 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:01 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Date: Wed, 7 Sep 2022 16:41:12 +0530 Message-Id: <20220907111125.539698-7-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549123; bh=nDS4t5bYszze6tP99Ghma6cMzhA5FrSX2ncIuK4yk8M=; h=Cc:Date:From:Reply-To:Subject:To; b=MbEOctmNXLnmyPBYd13E1fV16ZSrBvrf11eYVptg1AxyQeq2+QJ8z7OOtyw1dM1eOKx Sd+wf40o0dtFsv4QX0TOMe/5va3OPAG6k4QfWcAAXFmwOzViocHU7/075iJ7zKEpFirpP PpOaMSR1GK7FJAcEFqJCLAEfwtHvwh/2DAw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549124374100001 Content-Type: text/plain; charset="utf-8" EDK2 in S-mode needs to use SSCRATCH register. Implement functions to set/get the SSCRATCH register. Signed-off-by: Sunil V L --- MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Include/Library/BaseLib.h | 10 ++++++ MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 ++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 6be5be9428f2..5429329e39b0 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuGen.S | GCC =20 [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index a6f9a194ef1c..a742de61a442 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -150,6 +150,16 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID +RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 // diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseL= ib/RiscV64/CpuGen.S new file mode 100644 index 000000000000..d11929cf3233 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------ +// +// Generic CPU related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93382): https://edk2.groups.io/g/devel/message/93382 Mute This Topic: https://groups.io/mt/93522320/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93383+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93383+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549130; cv=none; d=zohomail.com; s=zohoarc; b=HrBKpx8pBuuv3rRl55y4HN3LmVtGJU3phZOXxyHZB2/pNit2eyAJwYQI0G5Z7PbqL1f7gD+BjfoWePBnv3ehM9gXxLjwb3LP4CJz1kDZPPQ9gehnejtHxqSmct9i0LfNB4sgod+3qzVyIfCuxx9LDzwpCAnWdN0PGCG9DkF6YZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549130; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=73q7VjVnHFw6JVOCkEpdkreIrEbz53ea0tIlML7f6R0=; b=I+UoYc6QnKgNx2m85ZFdj1d2rLSnKUL31fy8iaRlOfxB12xmeX9vxBvH1YAmMfl5NK2rbR7qPYhUAf+CmD58HOMS8tEy4LK+8SSNhNvNc1NsCj5Ysi6Kjpd8PuXZjKihLHdbAgEpLTZhIyKnDWQkF+HsE8+5CDtwwzI3Fd4o1oQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93383+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549130253663.373659429872; Wed, 7 Sep 2022 04:12:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JUoEYY1788612xaUO6B0iYps; Wed, 07 Sep 2022 04:12:08 -0700 X-Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) by mx.groups.io with SMTP id smtpd.web11.6313.1662549128214841152 for ; Wed, 07 Sep 2022 04:12:08 -0700 X-Received: by mail-pl1-f177.google.com with SMTP id p18so14159130plr.8 for ; Wed, 07 Sep 2022 04:12:08 -0700 (PDT) X-Gm-Message-State: 2ESqoYjkP2ZFBBRQgNFXY42nx1787277AA= X-Google-Smtp-Source: AA6agR7CQsxLrjtrOIYuemYi2eY/akxs+R0mTTXbf4rpPhptuL1WWei1W02pygq37xUUW0x3TwuCew== X-Received: by 2002:a17:902:ef50:b0:171:516d:d2ce with SMTP id e16-20020a170902ef5000b00171516dd2cemr3267853plx.171.1662549127286; Wed, 07 Sep 2022 04:12:07 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:06 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 07/19] MdePkg: Add ArchTimerLib library Date: Wed, 7 Sep 2022 16:41:13 +0530 Message-Id: <20220907111125.539698-8-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549128; bh=idTK+wDwxi80hKLoHJb0X3RfIakAMTJGlPDkk8ZtkLc=; h=Cc:Date:From:Reply-To:Subject:To; b=mVSONqaieMB+X19PAysmALEhkJV8YX1RMCfeptAxy/GLEz/BimEcHLrWUifwbBAT5q9 1zfAjO5fVFdJHzbr4Owj1M7XbZnfJk2iv7s1fIbYUlwDnh2N928saIxHidglIFw1kKo+M CZmFBgfgwgMKLmL1OJKmtDIkLmPVRbRrLjo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549132386100003 Content-Type: text/plain; charset="utf-8" This library implements the TimerLib.h functionality. This library is similar to CpuTimerLib but needs the library constructor. Signed-off-by: Sunil V L --- MdePkg/Library/ArchTimerLib/ArchTimerLib.inf | 40 +++ MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c | 299 ++++++++++++++++++= ++ MdePkg/Library/ArchTimerLib/ArchTimerLib.uni | 14 + 3 files changed, 353 insertions(+) diff --git a/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf b/MdePkg/Library/= ArchTimerLib/ArchTimerLib.inf new file mode 100644 index 000000000000..b61ae58d0142 --- /dev/null +++ b/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf @@ -0,0 +1,40 @@ +## @file +# Timer Library Instance which needs a constructor for the architecture. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# Copyright (c) 2022, Ventana Micro System Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D ArchTimerLib + FILE_GUID =3D D3CF51A9-1CEA-4776-A8AB-CCFD14D7DAAF + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + MODULE_UNI_FILE =3D ArchTimerLib.uni + CONSTRUCTOR =3D ArchTimerLibConstructor + +[Sources.RISCV64] + RiscV64/CpuTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + FdtLib + HobLib + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdRiscVTimerFrequencyInHz ## CONSUMES + +[Guids] + gFdtHobGuid diff --git a/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c b/MdePkg/Lib= rary/ArchTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 000000000000..a81ac8c37cad --- /dev/null +++ b/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,299 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +STATIC UINT32 mTimeBaseFrequency; +STATIC BOOLEAN mTimeBaseFreqInitialized; + +UINT32 +InternalGetTimerFrequency( + VOID + ) +{ + return mTimeBaseFrequency; +} + + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D csr_read(CSR_TIME) + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - csr_read(CSR_TIME)) & (1 << (RISCV_TIMER_COMPARE_BITS= - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + InternalGetTimerFrequency() + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + InternalGetTimerFrequency() + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)csr_read (CSR_TIME); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return InternalGetTimerFrequency(); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, InternalGetTimerF= requency(), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= InternalGetTimerFrequency()); + + return NanoSeconds; +} + +STATIC +RETURN_STATUS +EFIAPI +FdtInitializeTimerFrequency ( + VOID + ) +{ + VOID *Hob; + VOID *Fdt; + INT32 CpusNode, Len; + const fdt32_t *Prop; + + Hob =3D GetFirstGuidHob (&gFdtHobGuid); + if ((Hob =3D=3D NULL) || (GET_GUID_HOB_DATA_SIZE (Hob) !=3D sizeof (UINT= 64))) { + DEBUG ((DEBUG_ERROR, "%a: No FDT Hob found\n", __FUNCTION__)); + return EFI_NOT_FOUND; + } + + Fdt =3D (VOID *)(UINTN)*(UINT64 *)GET_GUID_HOB_DATA (Hob); + + if (fdt_check_header (Fdt) !=3D 0) { + DEBUG (( + DEBUG_ERROR, + "%a: No DTB found @ 0x%p\n", + __FUNCTION__, + Fdt + )); + return EFI_NOT_FOUND; + } + + // The "cpus" node resides at the the root of the DT. Fetch it. + CpusNode =3D fdt_path_offset (Fdt, "/cpus"); + if (CpusNode < 0) { + DEBUG ((DEBUG_ERROR, "%a: Invalid /cpus node\n", __FUNCTION__)); + return EFI_NOT_FOUND; + } + + Prop =3D fdt_getprop((void *)Fdt, CpusNode, "timebase-frequency", &Len); + if (!Prop) { + DEBUG ((DEBUG_ERROR, "%a: timebase-frequency propertynot found\n", __F= UNCTION__)); + return EFI_NOT_FOUND; + } + + mTimeBaseFrequency =3D fdt32_to_cpu(*Prop); + DEBUG((DEBUG_INFO, "%a: Timer Frequency (DT) is set to 0x%x\n", __FUNCTI= ON__, mTimeBaseFrequency)); + + return EFI_SUCCESS; +} +/** + Initializes the Timer Frequency by reading it from the DTB + +**/ +RETURN_STATUS +EFIAPI +ArchTimerLibConstructor ( + VOID + ) +{ + EFI_STATUS Status; + + /* + * Initialize only once + */ + if (mTimeBaseFreqInitialized) { + return EFI_SUCCESS; + } + + mTimeBaseFreqInitialized =3D 1; + + Status =3D FdtInitializeTimerFrequency(); + + if (EFI_ERROR(Status)) { + mTimeBaseFrequency =3D PcdGet32 (PcdRiscVTimerFrequencyInHz); + DEBUG((DEBUG_INFO, "%a: Timer Frequency (PCD) is set to 0x%x\n", __FUN= CTION__, mTimeBaseFrequency)); + } + + return EFI_SUCCESS; +} diff --git a/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni b/MdePkg/Library/= ArchTimerLib/ArchTimerLib.uni new file mode 100644 index 000000000000..1c900bea42bf --- /dev/null +++ b/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni @@ -0,0 +1,14 @@ +// /** @file +// Base CPU Timer Library +// +// Provides basic timer support using architecture specific methods. +// +// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti= mer support using architecture specific methods" --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93383): https://edk2.groups.io/g/devel/message/93383 Mute This Topic: https://groups.io/mt/93522325/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93384+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93384+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549135; cv=none; d=zohomail.com; s=zohoarc; b=hGz6lQr32ZZLzzIdi4DLRv0lv/LRNShXXzVHU92wH3yU9h6F+IHde/0IkHF5i/+H3yv4XGF/PUoNZ2PV7qP/06Rb25E/BeYrBSTEFWAUTU8T1iDcjLtjVlYY+aupSGn/gEr4vgcYOcRoIyjQK6R+yO3Cg9ILQKZpdAI5LYFAf8k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549135; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7j2IP1xsMGMGh524tacaJr/gZGb/qWinDHiLEceURFU=; b=L3vjemYJDRELDcMIsvaXCrap/dfWZRjzDg/2Ge8JbRP5+m9kF2n56R5jitM6Y+il1kLDizBUHsRT10rMHPr5H57oE1GYewEUTjdAo1EalDr/CcX9nj+gs3HG05KvAxkH/E0iEZrTPl78O0RKiOkMCXC0dADGq+Ykea3qHMseDX0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93384+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549135168862.6326547436629; Wed, 7 Sep 2022 04:12:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id CnVtYY1788612xduR4z9tCO7; Wed, 07 Sep 2022 04:12:14 -0700 X-Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) by mx.groups.io with SMTP id smtpd.web11.6314.1662549134125279691 for ; Wed, 07 Sep 2022 04:12:14 -0700 X-Received: by mail-pj1-f54.google.com with SMTP id pj10so3755118pjb.2 for ; Wed, 07 Sep 2022 04:12:13 -0700 (PDT) X-Gm-Message-State: UweGiQHQa7iXoyBCoUIskYCrx1787277AA= X-Google-Smtp-Source: AA6agR79jA3hpGgL6q6u/flN8TSRVCHdeGme5p0BQgR35Mvamq8LpYziZKaUPeiZhP8Ue58eyBW2lw== X-Received: by 2002:a17:90b:35c5:b0:1fd:9087:6a70 with SMTP id nb5-20020a17090b35c500b001fd90876a70mr3506029pjb.158.1662549132691; Wed, 07 Sep 2022 04:12:12 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:11 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 08/19] MdePkg: Add RiscVSbiLib Library for RISC-V Date: Wed, 7 Sep 2022 16:41:14 +0530 Message-Id: <20220907111125.539698-9-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549134; bh=mJ2DK0UaEN0YLkwNYfdXKb84N4N/VVa6LSg5eYhtYQ8=; h=Cc:Date:From:Reply-To:Subject:To; b=D9XNro9QK7oKSnkeFlpGs8KpG27ySHAkEt/wWQ663J4pO30HVSPxIAaSj2yzUQ/isjL CLuvCiRQ+e7bwcnsM5rG3JU7NWr10VtU7Qw1oqFGkoyfEgzME000Ims3d/QFEI+JbwhAb sv2eyCxRWzZEqr0CYwAyhVgSAYYoiKvw9xU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549136407100001 Content-Type: text/plain; charset="utf-8" This library is required to make SBI ecalls from the S-mode EDK2. Signed-off-by: Sunil V L --- MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf | 27 +++ MdePkg/Include/Library/RiscVSbiLib.h | 129 +++++++++++ MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c | 228 ++++++++++++++++++++ 3 files changed, 384 insertions(+) diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf b/MdePkg/Library/Ri= scVSbiLib/RiscVSbiLib.inf new file mode 100644 index 000000000000..a621243a1a99 --- /dev/null +++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf @@ -0,0 +1,27 @@ +## @file +# RISC-V Library to call SBI ecalls +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVSbiLib + FILE_GUID =3D D742CF3D-E600-4009-8FB5-318073008508 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSbiLib + +[Sources] + RiscVSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib diff --git a/MdePkg/Include/Library/RiscVSbiLib.h b/MdePkg/Include/Library/= RiscVSbiLib.h new file mode 100644 index 000000000000..e94adb08fd40 --- /dev/null +++ b/MdePkg/Include/Library/RiscVSbiLib.h @@ -0,0 +1,129 @@ +/** @file + Library to call the RISC-V SBI ecalls + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Hart - Hardware Thread, similar to a CPU core + + Currently, EDK2 needs to call SBI only to set the time and to do system = reset. + +**/ + +#ifndef RISCV_SBI_LIB_H_ +#define RISCV_SBI_LIB_H_ + +#include + +/* SBI Extension IDs */ +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 + +/* SBI function IDs for TIME extension*/ +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for SRST extension */ +#define SBI_EXT_SRST_RESET 0x0 + +#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0 +#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1 +#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2 +#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT + +#define SBI_SRST_RESET_REASON_NONE 0x0 +#define SBI_SRST_RESET_REASON_SYSFAIL 0x1 + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree +} EFI_RISCV_FIRMWARE_CONTEXT; + + +// +// EDK2 OpenSBI firmware extension return status. +// +typedef struct { + UINTN Error; ///< SBI status code + UINTN Value; ///< Value returned +} SBI_RET; + +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ); + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ); + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ); + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ); + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ); + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ); + +#endif diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c b/MdePkg/Library/Risc= VSbiLib/RiscVSbiLib.c new file mode 100644 index 000000000000..39cc6628be6c --- /dev/null +++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c @@ -0,0 +1,228 @@ +/** @file + Instance of the SBI ecall library. + + It allows calling an SBI function via an ecall from S-Mode. + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +// +// Maximum arguments for SBI ecall +// It's possible to pass more but no SBI call uses more as of SBI 0.2. +// The additional arguments would have to be passed on the stack instead o= f as +// registers, like it's done now. +// +#define SBI_CALL_MAX_ARGS 6 + +/** + Call SBI call using ecall instruction. + + Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS. + + @param[in] ExtId SBI extension ID. + @param[in] FuncId SBI function ID. + @param[in] NumArgs Number of arguments to pass to the ecall. + @param[in] ... Argument list for the ecall. + + @retval Returns SBI_RET structure with value and error code. + +**/ +STATIC +SBI_RET +EFIAPI +SbiCall ( + IN UINTN ExtId, + IN UINTN FuncId, + IN UINTN NumArgs, + ... + ) +{ + UINTN I; + SBI_RET Ret; + UINTN Args[SBI_CALL_MAX_ARGS]; + VA_LIST ArgList; + + VA_START (ArgList, NumArgs); + + ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS); + + for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) { + if (I < NumArgs) { + Args[I] =3D VA_ARG (ArgList, UINTN); + } else { + // Default to 0 for all arguments that are not given + Args[I] =3D 0; + } + } + + VA_END (ArgList); + + register UINTN a0 asm ("a0") =3D Args[0]; + register UINTN a1 asm ("a1") =3D Args[1]; + register UINTN a2 asm ("a2") =3D Args[2]; + register UINTN a3 asm ("a3") =3D Args[3]; + register UINTN a4 asm ("a4") =3D Args[4]; + register UINTN a5 asm ("a5") =3D Args[5]; + register UINTN a6 asm ("a6") =3D (UINTN)(FuncId); + register UINTN a7 asm ("a7") =3D (UINTN)(ExtId); + + asm volatile ("ecall" \ + : "+r" (a0), "+r" (a1) \ + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \ + : "memory"); \ + Ret.Error =3D a0; + Ret.Value =3D a1; + return Ret; +} + +/** + Translate SBI error code to EFI status. + + @param[in] SbiError SBI error code + @retval EFI_STATUS +**/ +STATIC +EFI_STATUS +EFIAPI +TranslateError ( + IN UINTN SbiError + ) +{ + switch (SbiError) { + case SBI_SUCCESS: + return EFI_SUCCESS; + case SBI_ERR_FAILED: + return EFI_DEVICE_ERROR; + break; + case SBI_ERR_NOT_SUPPORTED: + return EFI_UNSUPPORTED; + break; + case SBI_ERR_INVALID_PARAM: + return EFI_INVALID_PARAMETER; + break; + case SBI_ERR_DENIED: + return EFI_ACCESS_DENIED; + break; + case SBI_ERR_INVALID_ADDRESS: + return EFI_LOAD_ERROR; + break; + case SBI_ERR_ALREADY_AVAILABLE: + return EFI_ALREADY_STARTED; + break; + default: + // + // Reaches here only if SBI has defined a new error type + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + break; + } +} + +/** + Clear pending timer interrupt bit and set timer for next event after Tim= e. + + To clear the timer without scheduling a timer event, set Time to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] Time The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ) +{ + SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time); +} + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ) +{ + SBI_RET Ret; + + Ret =3D SbiCall ( + SBI_EXT_SRST, + SBI_EXT_SRST_RESET, + 2, + ResetType, + ResetReason + ); + + return TranslateError (Ret.Error); +} + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ) +{ + *FirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT *)csr_read(CSR_SSCRATCH= ); +} + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + csr_write(CSR_SSCRATCH, FirmwareContext); +} + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + GetFirmwareContext (FirmwareContextPtr); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + SetFirmwareContext (FirmwareContextPtr); +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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To add support for other architectures like RISC-V, we need to build these files only for x86. Signed-off-by: Sunil V L --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf | = 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index e7a81bebdb13..bf33d54bae13 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -32,7 +32,7 @@ [Sources.X64] X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h =20 -[Sources.common] +[Sources.IA32, Sources.X64] CpuExceptionCommon.h CpuExceptionCommon.c PeiDxeSmmCpuException.c @@ -56,8 +56,10 @@ [LibraryClasses] SerialPortLib PrintLib SynchronizationLib - LocalApicLib PeCoffGetEntryPointLib MemoryAllocationLib DebugLib + +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib VmgExitLib --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93385): https://edk2.groups.io/g/devel/message/93385 Mute This Topic: https://groups.io/mt/93522337/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93386+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93386+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549161; cv=none; d=zohomail.com; s=zohoarc; b=BozAN324cmzFypR0BYHEkzenz7HFAEGTL6apw6MLlGbhnx3NWTMIei0FTmC6XwrAF+dKq9fdB7q1X8hE1NvL2bXG0PdeSn/9BHzgEcFPUOuM2vDTtm6dcnU32BOiyhhU9GnTOKlxzKo81y0BlOchC8C2fRQl775U9qgcrAdYTCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549161; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=X4o9TUB4o1G/geQeuAF2+8gr40jo7GKB+2SYl6aeIxw=; b=Wvq5XhFZ6hFCK22RirMfIRQW8qKZN/SC8xi+evoRP9VgvpoDwmkD75A3FQMAZ3jRtQQBAEYErGu812nOfjAg3QLmiYfYreorDFp/xWqIWOvFwGBFnosBCdpLc4OzfYLTmNPx6mO2djWtfF5IfTrAMlCKwnzeZnAuhF5BXYKUyEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93386+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16625491618231003.7213963265706; Wed, 7 Sep 2022 04:12:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id fLAtYY1788612xqcX5MydhEb; Wed, 07 Sep 2022 04:12:41 -0700 X-Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) by mx.groups.io with SMTP id smtpd.web11.6314.1662549134125279691 for ; Wed, 07 Sep 2022 04:12:40 -0700 X-Received: by mail-pj1-f54.google.com with SMTP id pj10so3756395pjb.2 for ; Wed, 07 Sep 2022 04:12:40 -0700 (PDT) X-Gm-Message-State: lzAjU8jU7MJvofQFAxFISfdQx1787277AA= X-Google-Smtp-Source: AA6agR6OlZnteW3qTedKaumc0sVxtgZ+MwD82RKFAHo/yZ6r0XC68dNDgdfbYIa+yiA2/UYCTzV4fQ== X-Received: by 2002:a17:902:ba8e:b0:172:ddb9:fe45 with SMTP id k14-20020a170902ba8e00b00172ddb9fe45mr3407462pls.86.1662549160014; Wed, 07 Sep 2022 04:12:40 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:39 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 10/19] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Date: Wed, 7 Sep 2022 16:41:16 +0530 Message-Id: <20220907111125.539698-11-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549161; bh=M+hevMdjO6u00e1VOVdZ3nS1DIvaOpfU6uks7/s9W1M=; h=Cc:Date:From:Reply-To:Subject:To; b=W+7ffhKyWL7P2mpmGLmWjLewrvLzfdmhN2OtrjhWA/bD6FM55TGDlc2VpwoeCO9fg2b XFX455D3PgFl67uUmZN3RRfm0Mcpj7KncwUHEQW/GsWekkVAUr9hsJd1n4bCblnuBGiEl Sh8/IvSSgtJQ/JTtDs8fn1n5Tvml9H9jxmM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549162593100001 Content-Type: text/plain; charset="utf-8" Add low level interfaces to register exception and interrupt handlers for RISC-V. Signed-off-by: Sunil V L --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 7 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h= | 112 ++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c= | 136 ++++++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S = | 105 +++++++++++++++ 4 files changed, 359 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index bf33d54bae13..8570b83e8afb 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -18,7 +18,7 @@ [Defines] # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.Ia32] @@ -38,6 +38,11 @@ [Sources.IA32, Sources.X64] PeiDxeSmmCpuException.c DxeException.c =20 +[Sources.RISCV64] + RiscV64/SupervisorTrapHandler.S + RiscV64/CpuExceptionHandlerLib.c + RiscV64/CpuExceptionHandlerLib.h + [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.h new file mode 100644 index 000000000000..1cc6dbe73420 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.h @@ -0,0 +1,112 @@ +/** @file + + RISC-V Exception Handler library definition file. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_ +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_ + +#include +#include +extern void +SupervisorModeTrap ( + void + ); + +// +// Index of SMode trap register +// +#define SMODE_TRAP_REGS_zero 0 +#define SMODE_TRAP_REGS_ra 1 +#define SMODE_TRAP_REGS_sp 2 +#define SMODE_TRAP_REGS_gp 3 +#define SMODE_TRAP_REGS_tp 4 +#define SMODE_TRAP_REGS_t0 5 +#define SMODE_TRAP_REGS_t1 6 +#define SMODE_TRAP_REGS_t2 7 +#define SMODE_TRAP_REGS_s0 8 +#define SMODE_TRAP_REGS_s1 9 +#define SMODE_TRAP_REGS_a0 10 +#define SMODE_TRAP_REGS_a1 11 +#define SMODE_TRAP_REGS_a2 12 +#define SMODE_TRAP_REGS_a3 13 +#define SMODE_TRAP_REGS_a4 14 +#define SMODE_TRAP_REGS_a5 15 +#define SMODE_TRAP_REGS_a6 16 +#define SMODE_TRAP_REGS_a7 17 +#define SMODE_TRAP_REGS_s2 18 +#define SMODE_TRAP_REGS_s3 19 +#define SMODE_TRAP_REGS_s4 20 +#define SMODE_TRAP_REGS_s5 21 +#define SMODE_TRAP_REGS_s6 22 +#define SMODE_TRAP_REGS_s7 23 +#define SMODE_TRAP_REGS_s8 24 +#define SMODE_TRAP_REGS_s9 25 +#define SMODE_TRAP_REGS_s10 26 +#define SMODE_TRAP_REGS_s11 27 +#define SMODE_TRAP_REGS_t3 28 +#define SMODE_TRAP_REGS_t4 29 +#define SMODE_TRAP_REGS_t5 30 +#define SMODE_TRAP_REGS_t6 31 +#define SMODE_TRAP_REGS_sepc 32 +#define SMODE_TRAP_REGS_sstatus 33 +#define SMODE_TRAP_REGS_sie 34 +#define SMODE_TRAP_REGS_last 35 + +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__) +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last) + +#pragma pack(1) +typedef struct { + // + // Below are follow the format of EFI_SYSTEM_CONTEXT + // + UINT64 zero; + UINT64 ra; + UINT64 sp; + UINT64 gp; + UINT64 tp; + UINT64 t0; + UINT64 t1; + UINT64 t2; + UINT64 s0; + UINT64 s1; + UINT64 a0; + UINT64 a1; + UINT64 a2; + UINT64 a3; + UINT64 a4; + UINT64 a5; + UINT64 a6; + UINT64 a7; + UINT64 s2; + UINT64 s3; + UINT64 s4; + UINT64 s5; + UINT64 s6; + UINT64 s7; + UINT64 s8; + UINT64 s9; + UINT64 s10; + UINT64 s11; + UINT64 t3; + UINT64 t4; + UINT64 t5; + UINT64 t6; + // + // Below are the additional information to + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap + // and not public to EFI environment. + // + UINT64 sepc; + UINT64 sstatus; + UINT64 sie; +} SMODE_TRAP_REGISTERS; +#pragma pack() + +#endif diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.c new file mode 100644 index 000000000000..f4427599a6b7 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.c @@ -0,0 +1,136 @@ +/** @file + RISC-V Exception Handler library implementation. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "CpuExceptionHandlerLib.h" + +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; + +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + csr_write (CSR_STVEC, SupervisorModeTrap); + return EFI_SUCCESS; +} + + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler)); + mInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} + + +/** + Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. + + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. + + @retval EFI_SUCCESS The stacks are assigned successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. +**/ +EFI_STATUS +EFIAPI +InitializeSeparateExceptionStacks ( + IN VOID *Buffer, + IN OUT UINTN *BufferSize + ) +{ + return EFI_SUCCESS; +} + +/** + Supervisor mode trap handler. + + @param[in] SmodeTrapReg Registers before trap occurred. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + SMODE_TRAP_REGISTERS *SmodeTrapReg + ) +{ + UINTN SCause; + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg; + // + // Check scasue register. + // + SCause =3D (UINTN)csr_read (CSR_SCAUSE); + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) { + // + // This is interrupt event. + // + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1)); + if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) { + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext); + } + } +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTr= apHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorT= rapHandler.S new file mode 100644 index 000000000000..649c4c5becf4 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandl= er.S @@ -0,0 +1,105 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuExceptionHandlerLib.h" + + .align 3 + .section .entry, "ax", %progbits + .globl SupervisorModeTrap +SupervisorModeTrap: + addi sp, sp, -SMODE_TRAP_REGS_SIZE + + /* Save all general regisers except SP */ + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + csrr t0, CSR_SSTATUS + and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE) + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + csrr t0, CSR_SEPC + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrr t0, CSR_SIE + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP */ + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrw CSR_SEPC, t0 + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + csrw CSR_SIE, t0 + csrr t0, CSR_SSTATUS + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + or t0, t0, t1 + csrw CSR_SSTATUS, t0 + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + addi sp, sp, SMODE_TRAP_REGS_SIZE + sret --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93386): https://edk2.groups.io/g/devel/message/93386 Mute This Topic: https://groups.io/mt/93522342/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93387+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93387+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549167; cv=none; d=zohomail.com; s=zohoarc; b=Pe3sCqAZtLxAWrAaayS/zd00Iay72i2CXpK6GoTsW+4L0Mm/QB2EL8DdvEoWBIzccLxjgvlhgfT2QdR1MU4Cfg4x0XI0zXoUyB9eraW1sfpvW7z2ER1YTYQekTkqDnyQs2nGWqqlpcJnKfX1qrJIh073NToAUMaCPdIxZm0w9d0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549167; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4WeC5fRGD9F3TVO5QGf1uu6BzSA9h24ZkBOQXVXtOpg=; b=T/+nqCrd+3vqJwc9UJ4A/WTlyNSqyYM2iufzoGlPGD0+O9MWq1mbL8KOqN8e39gAHHXGOqBSnPcGqFAoe3eccTZi/hY6N8W3azkWEshAcdimlzN2IPm47+AhReI9Ns7H5OTi8ym42J3V6MEquybH24QGrhQbfugu1VkNWcDF8zA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93387+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549167228262.603616315816; Wed, 7 Sep 2022 04:12:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id vz8bYY1788612xcQDdo3e1Qz; Wed, 07 Sep 2022 04:12:46 -0700 X-Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) by mx.groups.io with SMTP id smtpd.web09.6414.1662549166217641271 for ; Wed, 07 Sep 2022 04:12:46 -0700 X-Received: by mail-pf1-f170.google.com with SMTP id c198so4407337pfc.13 for ; Wed, 07 Sep 2022 04:12:46 -0700 (PDT) X-Gm-Message-State: bBTj62RD1MeG2bxRzKIKrOv8x1787277AA= X-Google-Smtp-Source: AA6agR66JhcUj7amgTN29d3QCzjnfy21WVA9IL55JGA9NlQ/XUTlDybjR9zz+77oOxW2SBkuE3VmbA== X-Received: by 2002:a65:6b95:0:b0:420:2cb1:68e5 with SMTP id d21-20020a656b95000000b004202cb168e5mr2889716pgw.220.1662549164878; Wed, 07 Sep 2022 04:12:44 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:44 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 11/19] MdePkg/Library: Add ResetSystemLib library Date: Wed, 7 Sep 2022 16:41:17 +0530 Message-Id: <20220907111125.539698-12-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549166; bh=2cpK5u4sukB3t0Wjy3M0xxhyRQdjZPO9s3ZJN+WLj1s=; h=Cc:Date:From:Reply-To:Subject:To; b=s0wdA3Qq7MgtcRM0339WyKRjY4AFZEIoOrZQPfcRgk6d04RWFiCLrIj416v/7TzFzH/ xhg71am0siiOHb+zNOsjza/jroA+7l0paamkpEu1GL/zTEEeT8L+SGZpaIj69KQ8nquMU oljMM/ZJ4/elw0Q/OGjniL2Q+eeA11/dMD8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549168580100001 Content-Type: text/plain; charset="utf-8" This library implements system reset interfaces like cold reboot, warm reboot etc. On RISC-V platforms, these are implemented using SBI calls. Signed-off-by: Sunil V L --- MdePkg/Library/ResetSystemLib/ResetSystemLib.inf | 35 ++++++ MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c | 128 +++++++++++++= +++++++ 2 files changed, 163 insertions(+) diff --git a/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf b/MdePkg/Libr= ary/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 000000000000..7c8a7d11423d --- /dev/null +++ b/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,35 @@ +## @file +# Library instance for ResetSystem library class +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ResetSystemLib + FILE_GUID =3D 425DC96A-BF26-4684-90F9-1B5FF43BE927 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ResetSystemLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources.RISCV64] + RiscV64/ResetSystemLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + DebugLib + +[LibraryClasses.RISCV64] + RiscVSbiLib diff --git a/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c b/MdePk= g/Library/ResetSystemLib/RiscV64/ResetSystemLib.c new file mode 100644 index 000000000000..c077ef6ac7f8 --- /dev/null +++ b/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c @@ -0,0 +1,128 @@ +/** @file + Reset System Library functions for RISC-V + + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + // Shut down via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE= ); +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform. The platform m= ay + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + // + // Can map to OpenSBI vendor or platform specific reset type. + // + return; +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,= or EfiResetShutdown + the data buffer starts with a Null-terminated = string, optionally + followed by additional binary data. The string= is a description + that the caller may use to further indicate th= e reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93387): https://edk2.groups.io/g/devel/message/93387 Mute This Topic: https://groups.io/mt/93522344/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93388+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93388+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549172; cv=none; d=zohomail.com; s=zohoarc; b=O3qoBZ5fLgG2YJ1mXCAy9KDd9zz7qPM1DeacDF3+csEqDSrAGmiEBmBqUX4+Dbars3wVYrhsYI3K9lKL9rgvUtVnOOFOG14bHyE0T9CBZjhR4qxgtg6ue727zNt+pVaTDpvPQ/Jhm1of7DWKXKah1uOBv0S8ovN41pRuR8hi6nw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549172; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=EkjezlWB7EJB0o62pipw2iciPeyejjBVbw+HhQG1wIw=; b=DSGueQWTlDnA1wd2qyvyIWiuZnih0ECWOYdNkXFjvUvQ7+BMsuVYw7thaaCMpMqSFm7/pMpNeGdkH8ySnJB2C8vDLujgWDVXViCOYul3oZS6cD3RkvP4suvTUTs1zPeWGwKks+3BmKwwywhEaju1Cf+0dIE4ncKT50m2+hE8BG8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93388+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549172317249.26317421422777; Wed, 7 Sep 2022 04:12:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BuhiYY1788612xa92De4hPno; Wed, 07 Sep 2022 04:12:51 -0700 X-Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) by mx.groups.io with SMTP id smtpd.web09.6415.1662549171240538325 for ; Wed, 07 Sep 2022 04:12:51 -0700 X-Received: by mail-pj1-f45.google.com with SMTP id t11-20020a17090a510b00b001fac77e9d1fso17903595pjh.5 for ; Wed, 07 Sep 2022 04:12:51 -0700 (PDT) X-Gm-Message-State: aItAXTPeSD0cXamQKZcynR1tx1787277AA= X-Google-Smtp-Source: AA6agR6kbrUs/FFicK7WeOt/GwCpmI56z4zdoCGUNgHjIiTHurdMMn+lrsDzlYus6iLMoMn8+BheyQ== X-Received: by 2002:a17:902:d48f:b0:16f:a73:bf04 with SMTP id c15-20020a170902d48f00b0016f0a73bf04mr3131719plg.43.1662549169706; Wed, 07 Sep 2022 04:12:49 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:49 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 12/19] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Date: Wed, 7 Sep 2022 16:41:18 +0530 Message-Id: <20220907111125.539698-13-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549171; bh=+5jvacRXkuqYB1bUXXSES/3KjLzZ/FDCxjQEiySwBNI=; h=Cc:Date:From:Reply-To:Subject:To; b=YOYpQM0AOMfyfnhCF8gKeImLezkI0s+WfvSzfVNjd3SI2YK3gR4xfnQmCBvX40MtPVH XMnLttnI8zpq36kOPApj/hatXxmOXgNpVS7cwWAb5TIB1e1HyPEewroGLldtsH/zmBeu5 7bv36vT9uQSXgViQaTkbWN9khwkk3loYvkg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549172643100001 Content-Type: text/plain; charset="utf-8" Generic RISC-V platforms will start in S-mode directly. Previous M-mode firmware like opensbi will branch to the entry point in this module. This module initializes the firmware context pointer and branches to the PEI phase. Signed-off-by: Sunil V L --- UefiCpuPkg/SecCore/SecCoreRiscV.inf | 59 ++ UefiCpuPkg/SecCore/RiscV64/SecMain.h | 63 ++ UefiCpuPkg/SecCore/RiscV64/SecMain.c | 796 ++++++++++++++++++++ UefiCpuPkg/SecCore/RiscV64/SecEntry.S | 23 + 4 files changed, 941 insertions(+) diff --git a/UefiCpuPkg/SecCore/SecCoreRiscV.inf b/UefiCpuPkg/SecCore/SecCo= reRiscV.inf new file mode 100644 index 000000000000..8ba6400f5319 --- /dev/null +++ b/UefiCpuPkg/SecCore/SecCoreRiscV.inf @@ -0,0 +1,59 @@ +## @file +# RISC-V SEC module which boots in S-mode. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SecMain + FILE_GUID =3D 42C30D8E-BFAD-4E77-9041-E7DAAE88DF7A + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/SecEntry.S + RiscV64/SecMain.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PlatformSecLib + PcdLib + CpuLib + PeCoffGetEntryPointLib + PeCoffExtraActionLib + RiscVSbiLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamSize + +[UserExtensions.TianoCore."ExtraFiles"] + SecCoreExtra.uni diff --git a/UefiCpuPkg/SecCore/RiscV64/SecMain.h b/UefiCpuPkg/SecCore/Risc= V64/SecMain.h new file mode 100644 index 000000000000..eeb368de02a2 --- /dev/null +++ b/UefiCpuPkg/SecCore/RiscV64/SecMain.h @@ -0,0 +1,63 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SEC_MAIN_H_ +#define _SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +#endif diff --git a/UefiCpuPkg/SecCore/RiscV64/SecMain.c b/UefiCpuPkg/SecCore/Risc= V64/SecMain.c new file mode 100644 index 000000000000..d9dacce319dc --- /dev/null +++ b/UefiCpuPkg/SecCore/RiscV64/SecMain.c @@ -0,0 +1,796 @@ +/** @file + RISC-V SEC phase module. + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +EFI_STATUS +EFIAPI +TemporaryRamDone ( + VOID + ); + +STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { + TemporaryRamMigration +}; + +STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { + TemporaryRamDone +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + &mTemporaryRamSupportPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiTemporaryRamDonePpiGuid, + &mTemporaryRamDonePpi + }, +}; + +/** Temporary RAM migration function. + + This function migrates the data from temporary RAM to permanent + memory. + + @param[in] PeiServices PEI service + @param[in] TemporaryMemoryBase Temporary memory base address + @param[in] PermanentMemoryBase Permanent memory base address + @param[in] CopySize Size to copy + +**/ +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + DEBUG ((DEBUG_INFO, + "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n", + __FUNCTION__, + TemporaryMemoryBase, + PermanentMemoryBase, + (UINT64)CopySize + )); + + OldHeap =3D (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap =3D (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1)); + + OldStack =3D (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); + NewStack =3D (VOID*)(UINTN)PermanentMemoryBase; + + CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap + CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack + + // + // Reset firmware context pointer + // + GetFirmwareContextPointer (&FirmwareContext); + FirmwareContext =3D (VOID *)FirmwareContext + (unsigned long)((UINTN)New= Stack - (UINTN)OldStack); + SetFirmwareContextPointer (FirmwareContext); + + DEBUG ((DEBUG_INFO, "%a: Firmware Context is relocated to 0x%x\n", __FUN= CTION__, FirmwareContext)); + + register UINTN a0 asm ("a0") =3D (UINTN)((UINTN)NewStack - (UINTN)OldSt= ack); + asm volatile ("add sp, sp, a0"::"r"(a0):); + return EFI_SUCCESS; +} + +/** Temprary RAM done function. + +**/ +EFI_STATUS EFIAPI TemporaryRamDone ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FU= NCTION__)); + return EFI_SUCCESS; +} +/** Return platform SEC PPI before PEI Core + + @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR. + +**/ +STATIC EFI_STATUS +GetPlatformPrePeiCorePpiDescriptor ( + IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList +) +{ + *ThisPpiList =3D mPrivateDispatchTable; + return EFI_SUCCESS; +} + +/** + Locates the main boot firmware volume. + + @param[in,out] BootFv On input, the base of the BootFv + On output, the decompressed main firmware volume + + @retval EFI_SUCCESS The main firmware volume was located and decompre= ssed + @retval EFI_NOT_FOUND The main firmware volume was not found + +**/ +EFI_STATUS +FindMainFv ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *Fv; + UINTN Distance; + + ASSERT (((UINTN)*BootFv & EFI_PAGE_MASK) =3D=3D 0); + + Fv =3D *BootFv; + Distance =3D (UINTN)(*BootFv)->FvLength; + do { + Fv =3D (EFI_FIRMWARE_VOLUME_HEADER *)((UINT8 *)Fv + EFI_PAGE_SI= ZE); + Distance +=3D EFI_PAGE_SIZE; + if (Distance > SIZE_32MB) { + return EFI_NOT_FOUND; + } + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + continue; + } + + if ((UINTN)Fv->FvLength < Distance) { + continue; + } + + *BootFv =3D Fv; + return EFI_SUCCESS; + } while (TRUE); +} + +/** + Locates a section within a series of sections + with the specified section type. + + The Instance parameter indicates which instance of the section + type to return. (0 is first instance, 1 is second...) + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[in] Instance The section instance number + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInstance ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + IN UINTN Instance, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfSections; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + // + // Loop through the FFS file sections within the PEI Core FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Sections; + EndOfSections =3D EndOfSection + SizeOfSections; + for ( ; ;) { + if (EndOfSection =3D=3D EndOfSections) { + break; + } + + CurrentAddress =3D (EndOfSection + 3) & ~(3ULL); + if (CurrentAddress >=3D EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the requested section type + // + if (Section->Type =3D=3D SectionType) { + if (Instance =3D=3D 0) { + *FoundSection =3D Section; + return EFI_SUCCESS; + } else { + Instance--; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Locates a section within a series of sections + with the specified section type. + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInSections ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + return FindFfsSectionInstance ( + Sections, + SizeOfSections, + SectionType, + 0, + FoundSection + ); +} + +/** + Locates a FFS file with the specified file type and a section + within that file with the specified section type. + + @param[in] Fv The firmware volume to search + @param[in] FileType The file type to locate + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsFileAndSection ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + IN EFI_FV_FILETYPE FileType, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "FV at %p does not have FV header signature\n", F= v)); + return EFI_VOLUME_CORRUPTED; + } + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Fv; + EndOfFirmwareVolume =3D CurrentAddress + Fv->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + Fv->HeaderLength; ; ) { + CurrentAddress =3D (EndOfFile + 7) & ~(7ULL); + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; + Size =3D FFS_FILE_SIZE (File); + if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the request file type + // + if (File->Type !=3D FileType) { + continue; + } + + Status =3D FindFfsSectionInSections ( + (VOID *)(File + 1), + (UINTN)EndOfFile - (UINTN)(File + 1), + SectionType, + FoundSection + ); + if (!EFI_ERROR (Status) || (Status =3D=3D EFI_VOLUME_CORRUPTED)) { + return Status; + } + } +} + +/** + Locates the compressed main firmware volume and decompresses it. + + @param[in,out] Fv On input, the firmware volume to search + On output, the decompressed BOOT/PEI FV + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +DecompressMemFvs ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **Fv + ) +{ + EFI_STATUS Status; + EFI_GUID_DEFINED_SECTION *Section; + UINT32 OutputBufferSize; + UINT32 ScratchBufferSize; + UINT16 SectionAttribute; + UINT32 AuthenticationStatus; + VOID *OutputBuffer; + VOID *ScratchBuffer; + EFI_COMMON_SECTION_HEADER *FvSection; + EFI_FIRMWARE_VOLUME_HEADER *PeiMemFv; + EFI_FIRMWARE_VOLUME_HEADER *DxeMemFv; + UINT32 FvHeaderSize; + UINT32 FvSectionSize; + + FvSection =3D (EFI_COMMON_SECTION_HEADER *)NULL; + + Status =3D FindFfsFileAndSection ( + *Fv, + EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, + EFI_SECTION_GUID_DEFINED, + (EFI_COMMON_SECTION_HEADER **)&Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find GUID defined section\n")); + return Status; + } + + Status =3D ExtractGuidedSectionGetInfo ( + Section, + &OutputBufferSize, + &ScratchBufferSize, + &SectionAttribute + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to GetInfo for GUIDed section\n")); + return Status; + } + + OutputBuffer =3D (VOID *)((UINT8 *)(UINTN)PcdGet32 (PcdDxeMemFvBase) + = SIZE_1MB); + ScratchBuffer =3D ALIGN_POINTER ((UINT8 *)OutputBuffer + OutputBufferSiz= e, SIZE_1MB); + + Status =3D ExtractGuidedSectionDecode ( + Section, + &OutputBuffer, + ScratchBuffer, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error during GUID section decode\n")); + return Status; + } + + Status =3D FindFfsSectionInstance ( + OutputBuffer, + OutputBufferSize, + EFI_SECTION_FIRMWARE_VOLUME_IMAGE, + 0, + &FvSection + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI FV section\n")); + return Status; + } + + ASSERT ( + SECTION_SIZE (FvSection) =3D=3D + (PcdGet32 (PcdPeiMemFvSize) + sizeof (*FvSection)) + ); + ASSERT (FvSection->Type =3D=3D EFI_SECTION_FIRMWARE_VOLUME_IMAGE); + + PeiMemFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdPeiMemFvB= ase); + CopyMem (PeiMemFv, (VOID *)(FvSection + 1), PcdGet32 (PcdPeiMemFvSize)); + + if (PeiMemFv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signa= ture\n", PeiMemFv)); + CpuDeadLoop (); + return EFI_VOLUME_CORRUPTED; + } + + Status =3D FindFfsSectionInstance ( + OutputBuffer, + OutputBufferSize, + EFI_SECTION_FIRMWARE_VOLUME_IMAGE, + 1, + &FvSection + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find DXE FV section\n")); + return Status; + } + + ASSERT (FvSection->Type =3D=3D EFI_SECTION_FIRMWARE_VOLUME_IMAGE); + + if (IS_SECTION2 (FvSection)) { + FvSectionSize =3D SECTION2_SIZE (FvSection); + FvHeaderSize =3D sizeof (EFI_COMMON_SECTION_HEADER2); + } else { + FvSectionSize =3D SECTION_SIZE (FvSection); + FvHeaderSize =3D sizeof (EFI_COMMON_SECTION_HEADER); + } + + ASSERT (FvSectionSize =3D=3D (PcdGet32 (PcdDxeMemFvSize) + FvHeaderSize)= ); + + DxeMemFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdDxeMemFvB= ase); + CopyMem (DxeMemFv, (VOID *)((UINTN)FvSection + FvHeaderSize), PcdGet32 (= PcdDxeMemFvSize)); + + if (DxeMemFv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signa= ture\n", DxeMemFv)); + CpuDeadLoop (); + return EFI_VOLUME_CORRUPTED; + } + *Fv =3D PeiMemFv; + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindPeiCoreImageBaseInFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + EFI_STATUS Status; + EFI_COMMON_SECTION_HEADER *Section; + + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_PE32, + &Section + ); + if (EFI_ERROR (Status)) { + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_TE, + &Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI Core image\n")); + return Status; + } + } + + *PeiCoreImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1); + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in,out] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +VOID +FindPeiCoreImageBase ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + + *PeiCoreImageBase =3D 0; + + FindMainFv (BootFv); + + DecompressMemFvs (BootFv); + + FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase); +} + +/** + Find core image base. + +**/ +EFI_STATUS +FindImageBase ( + IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr, + OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + *SecCoreImageBase =3D 0; + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)BootFirmwareVolumeP= tr; + EndOfFirmwareVolume =3D CurrentAddress + BootFirmwareVolumePtr->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + BootFirmwareVolumePtr->HeaderLength;= ; ) { + CurrentAddress =3D (EndOfFile + 7) & 0xfffffffffffffff8ULL; + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_NOT_FOUND; + } + + File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; + Size =3D FFS_FILE_SIZE (File); + if (Size < sizeof (*File)) { + return EFI_NOT_FOUND; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_NOT_FOUND; + } + + // + // Look for SEC Core + // + if (File->Type !=3D EFI_FV_FILETYPE_SECURITY_CORE) { + continue; + } + + // + // Loop through the FFS file sections within the FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(File + 1); + for ( ; ;) { + CurrentAddress =3D (EndOfSection + 3) & 0xfffffffffffffffcULL; + Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddres= s; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_NOT_FOUND; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfFile) { + return EFI_NOT_FOUND; + } + + // + // Look for executable sections + // + if ((Section->Type =3D=3D EFI_SECTION_PE32) || (Section->Type =3D=3D= EFI_SECTION_TE)) { + if (File->Type =3D=3D EFI_FV_FILETYPE_SECURITY_CORE) { + *SecCoreImageBase =3D (PHYSICAL_ADDRESS)(UINTN)(Section + 1); + } + + break; + } + } + + // + // SEC Core image found + // + if (*SecCoreImageBase !=3D 0) { + return EFI_SUCCESS; + } + } +} + +/* + Find and return Pei Core entry point. + + It also find SEC and PEI Core file debug information. It will report the= m if + remote debug is enabled. + +**/ +VOID +FindAndReportEntryPoints ( + IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS SecCoreImageBase; + EFI_PHYSICAL_ADDRESS PeiCoreImageBase; + PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; + + // + // Find SEC Core and PEI Core image base + // + Status =3D FindImageBase (*BootFirmwareVolumePtr, &SecCoreImageBase); + ASSERT_EFI_ERROR (Status); + + FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase); + + ZeroMem ((VOID *)&ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT)); + // + // Report SEC Core debug information when remote debug is enabled + // + ImageContext.ImageAddress =3D SecCoreImageBase; + ImageContext.PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)= ImageContext.ImageAddress); + PeCoffLoaderRelocateImageExtraAction (&ImageContext); + + // + // Report PEI Core debug information when remote debug is enabled + // + ImageContext.ImageAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)PeiCoreImageB= ase; + ImageContext.PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)= ImageContext.ImageAddress); + PeCoffLoaderRelocateImageExtraAction (&ImageContext); + + // + // Find PEI Core entry point + // + Status =3D PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (= VOID **)PeiCoreEntryPoint); + if (EFI_ERROR (Status)) { + *PeiCoreEntryPoint =3D 0; + } + + return; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_FIRMWARE_VOLUME_HEADER *BootFv; + EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_STATUS Status; + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __FUNCTION__, + BootHartId, + DeviceTreeAddress + )); + + // + // Process all libraries constructor function linked to SecCore. + // + ProcessLibraryConstructorList (); + + BootFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdSecMemFvBase); + + ASSERT(BootFv !=3D NULL); + SecCoreData.DataSize =3D (UINT16)sizeof (EFI_SEC_PEI_HAND_= OFF); + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN)FixedPcdGet32 (PcdSecMemFv= Size); + SecCoreData.TemporaryRamBase =3D (VOID *)(UINT64)FixedPcdGet32 (Pc= dSecPeiTempRamBase); + SecCoreData.TemporaryRamSize =3D (UINTN)FixedPcdGet32 (PcdSecPeiTe= mpRamSize); + SecCoreData.PeiTemporaryRamBase =3D SecCoreData.TemporaryRamBase; + SecCoreData.PeiTemporaryRamSize =3D SecCoreData.TemporaryRamSize >> 1; + SecCoreData.StackBase =3D (UINT8 *)SecCoreData.TemporaryRam= Base + (SecCoreData.TemporaryRamSize >> 1); + SecCoreData.StackSize =3D SecCoreData.TemporaryRamSize >> 1; + + DEBUG (( + DEBUG_INFO, + "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size= : 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackS= ize: 0x%x\n", + __FUNCTION__, + SecCoreData.BootFirmwareVolumeBase, + SecCoreData.BootFirmwareVolumeSize, + SecCoreData.TemporaryRamBase, + SecCoreData.TemporaryRamSize, + SecCoreData.PeiTemporaryRamBase, + SecCoreData.PeiTemporaryRamSize, + SecCoreData.StackBase, + SecCoreData.StackSize + )); + + FindAndReportEntryPoints ( + &BootFv, + &PeiCoreEntryPoint + ); + if (PeiCoreEntryPoint =3D=3D NULL) { + CpuDeadLoop (); + } + + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN) BootFv->FvLength; + + Status =3D GetPlatformPrePeiCorePpiDescriptor (&PpiList); + if (EFI_ERROR (Status)) { + PpiList =3D NULL; + } + + FirmwareContext.BootHartId =3D BootHartId; + FirmwareContext.FlattenedDeviceTree =3D (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + // + // Transfer the control to the PEI core + // + ASSERT (PeiCoreEntryPoint !=3D NULL); + (*PeiCoreEntryPoint)(&SecCoreData, PpiList); + + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/UefiCpuPkg/SecCore/RiscV64/SecEntry.S b/UefiCpuPkg/SecCore/Ris= cV64/SecEntry.S new file mode 100644 index 000000000000..1bd0174e278e --- /dev/null +++ b/UefiCpuPkg/SecCore/RiscV64/SecEntry.S @@ -0,0 +1,23 @@ +/* + Copyright (c) 2021-2022 , Hewlett Packard Enterprise Development LP. All= rights reserved. + Copyright (c) 2019 Western Digital Corporation or its affiliates. + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +.text +.align 3 + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdSecPeiTempRamBase) + li a5, FixedPcdGet32 (PcdSecPeiTempRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93388): https://edk2.groups.io/g/devel/message/93388 Mute This Topic: https://groups.io/mt/93522345/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93389+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93389+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549177; cv=none; d=zohomail.com; s=zohoarc; b=UpYjiiWSjuyGJdp7vj2m6KGbEuTrXqvUbQg24AAl7kzqYLpq+DVZzBHPxWZ9qZCt7s4RZALriPJR/0ku1jNddod1iyA7WxqPXqSpuft5k3xerjDCAwrA1lrLxqGy7QMDsj/OMzhQ8K2ac5uOnzE/5B9htjdE/83DpL1qlMKRTlw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549177; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=akOysab7DLQROnHDXh2pvQCQopyd3CFzCdGLhYHVGlY=; b=oFUQ8O7t911t5pZa7ATyRiWCxRSSvf6y0HxSqu9fsXBb+ToxCUrtBcWaABZmXY+jQYB/dpgn6tuGGueDe5zHWuK3hrJ8T/WbvIgJzv+ip6ZjLFDj8qe9YRMa+glHiCQHZvrd6d2UPyELx7ANOjG2Sr5vZd6wiC/5nRnNtTdXJOo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93389+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549177753875.5024295429408; Wed, 7 Sep 2022 04:12:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4c7nYY1788612xrQbmCD4SOo; Wed, 07 Sep 2022 04:12:56 -0700 X-Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mx.groups.io with SMTP id smtpd.web11.6322.1662549175801040599 for ; Wed, 07 Sep 2022 04:12:55 -0700 X-Received: by mail-pl1-f174.google.com with SMTP id c2so14176964plo.3 for ; Wed, 07 Sep 2022 04:12:55 -0700 (PDT) X-Gm-Message-State: zsc7zaPkUeNkijOEZ6XYmC4nx1787277AA= X-Google-Smtp-Source: AA6agR4tKHk2lYhA3bLRMwL2ZRKkVdJ3wMizh7LolmpNOEmaFG5Ela9i4bJzFcIAkh6exJxjcgs6xw== X-Received: by 2002:a17:902:ec83:b0:174:ce14:ee4 with SMTP id x3-20020a170902ec8300b00174ce140ee4mr3196342plg.17.1662549174775; Wed, 07 Sep 2022 04:12:54 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:54 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 13/19] MdePkg: Add PlatformPeiLib library Date: Wed, 7 Sep 2022 16:41:19 +0530 Message-Id: <20220907111125.539698-14-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549176; bh=4YTBcZqfJF9sRpMqvW0EfeRbqIq6uZQ2iqvNQr3OXPA=; h=Cc:Date:From:Reply-To:Subject:To; b=TlCgWE18fDMyV46tb9VlXMS+17pwG95/l/jURsedRZ4yFjTxH6g1bglWlZJp1B1R8BZ ilPDlvHJAGQ8l0w5bW5YOsxAGJyVjGQ0E2D4G0gHJRZy6AdBWPb3pWzJ9qSmSztJ5AOeU Bjw7nYp/aIN5NGdJKlNdPYte650pp8MzVTQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549178625100005 Content-Type: text/plain; charset="utf-8" This library is required in RISC-V to build the FDT Hob. The library can be leveraged by other architectures like ARM if required. Signed-off-by: Sunil V L --- MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf | 40 ++++++++++++ MdePkg/Include/Library/PlatformPeiLib.h | 15 +++++ MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c | 68 ++++++++++++++= ++++++ 3 files changed, 123 insertions(+) diff --git a/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf b/MdePkg/Libr= ary/PlatformPeiLib/PlatformPeiLib.inf new file mode 100644 index 000000000000..d682b3c0f908 --- /dev/null +++ b/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf @@ -0,0 +1,40 @@ +## @file +# Platform Initialization Pei Library +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformPeiLib + FILE_GUID =3D B35BD738-787B-47FB-8139-20193442CC49 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformPeiLib + +[Sources.RISCV64] + RiscV64/PlatformPeiLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DebugLib + HobLib + FdtLib + PcdLib + PeimEntryPoint + BaseLib + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Guids] + gFdtHobGuid ## PRODUCES diff --git a/MdePkg/Include/Library/PlatformPeiLib.h b/MdePkg/Include/Libra= ry/PlatformPeiLib.h new file mode 100644 index 000000000000..1e8c5f98cfe2 --- /dev/null +++ b/MdePkg/Include/Library/PlatformPeiLib.h @@ -0,0 +1,15 @@ +/** @file + Library to initialize platform data at PEI phase + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_PEI_LIB_H_ +#define _PLATFORM_PEI_LIB_H_ + +EFI_STATUS PlatformPeim(VOID); + +#endif diff --git a/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c b/MdePk= g/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c new file mode 100644 index 000000000000..e62aa26df9e5 --- /dev/null +++ b/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c @@ -0,0 +1,68 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#include + +#include + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUN= CTION__, FdtPointer)); + Base =3D FdtPointer; + ASSERT (Base !=3D NULL); + ASSERT (fdt_check_header (Base) =3D=3D 0); + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + ASSERT (NewBase !=3D NULL); + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + ASSERT (FdtHobData !=3D NULL); + *FdtHobData =3D (UINTN)NewBase; + + return EFI_SUCCESS; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549182; bh=9HDkQWeiKqxzlYXoOdceOvKysoHBv4/uNfhDPcVzWz8=; h=Cc:Date:From:Reply-To:Subject:To; b=p4BoCL3+ItioaXsyUwfvta7qnLijYH0kVMe+LbJfOnCubGaw8Q4ZwrSDn/q87LLtKWq Jnz3TdjzrwAEOdVWnnsmCxkfQ+Sc3qG2TFUHZ+x/GSZ2AFjaKmDMiC9OfyeoK5qKpcVbM dpsCSLF+zWuISuzVH87JKxp1y4UfTzafv5M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549184811100001 Content-Type: text/plain; charset="utf-8" Thie PEIM is required to do platform specific initialization like detecting the permanent memory and install memory HOB, install the FDT Hob etc. Signed-off-by: Sunil V L --- MdeModulePkg/Universal/PlatformPei/PlatformPei.inf | 65 ++++ MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h | 97 +++++ MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c | 83 +++++ MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c | 179 ++++++++++ MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c | 372 +++++++++++++= +++++++ 5 files changed, 796 insertions(+) diff --git a/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf b/MdeModule= Pkg/Universal/PlatformPei/PlatformPei.inf new file mode 100644 index 000000000000..220f4a7ee5f5 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf @@ -0,0 +1,65 @@ +## @file +# Platform PEI driver +# +# This module provides platform specific functions +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformPei + FILE_GUID =3D 0F26B9AF-3E38-46E8-9D35-0318E903E049 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePlatform + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/Fv.c + RiscV64/MemDetect.c + RiscV64/Platform.c + RiscV64/Platform.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Guids] + gEfiMemoryTypeInformationGuid + +[LibraryClasses] + DebugLib + HobLib + FdtLib + IoLib + PcdLib + PeimEntryPoint + PeiResourcePublicationLib + PlatformPeiLib + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Pcd.RISCV64] + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize + +[Ppis] + gEfiPeiMasterBootModePpiGuid + +[Depex] + TRUE diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h b/MdeMod= ulePkg/Universal/PlatformPei/RiscV64/Platform.h new file mode 100644 index 000000000000..6c23c722a360 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h @@ -0,0 +1,97 @@ +/** @file + Platform PEI module include file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_PEI_H_INCLUDED_ +#define PLATFORM_PEI_H_INCLUDED_ + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddressWidthInitialization ( + VOID + ); + +EFI_STATUS +PublishPeiMemory ( + VOID + ); + +UINT32 +GetSystemMemorySizeBelow4gb ( + VOID + ); + +VOID +InitializeRamRegions ( + VOID + ); + +EFI_STATUS +PeiFvInitialization ( + VOID + ); + +EFI_STATUS +InitializeXen ( + VOID + ); + +/** + Build processor and platform information for the U5 platform + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildRiscVSmbiosHobs ( + VOID + ); + +#endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c b/MdeModulePkg= /Universal/PlatformPei/RiscV64/Fv.c new file mode 100644 index 000000000000..15e77fcf7ec6 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c @@ -0,0 +1,83 @@ +/** @file + Build FV related hobs for platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PiPei.h" +#include "Platform.h" +#include +#include +#include +#include + +/** + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI + and DXE know about them. + + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully. + +**/ +EFI_STATUS +PeiFvInitialization ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n")); + + // Create a memory allocation HOB for the DXE FV. + // + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE + // firmware volumes at S3 resume too, hence we need to keep away the OS = from + // DXEFV as well. Otherwise we only need to keep away DXE itself from the + // DXEFV area. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdPeiMemFvBase), + PcdGet32 (PcdPeiMemFvSize), + EfiBootServicesData + ); + + + // + // Let DXE know about the DXE FV + // + BuildFvHob (PcdGet32 (PcdDxeMemFvBase), PcdGet32 (PcdDxeMemFvSize)); + DEBUG (( + DEBUG_INFO, + "Platform builds DXE FV at %x, size %x.\n", + PcdGet32 (PcdDxeMemFvBase), + PcdGet32 (PcdDxeMemFvSize) + )); + + // Create a memory allocation HOB for the DXE FV. + // + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE + // firmware volumes at S3 resume too, hence we need to keep away the OS = from + // DXEFV as well. Otherwise we only need to keep away DXE itself from the + // DXEFV area. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdDxeMemFvBase), + PcdGet32 (PcdDxeMemFvSize), + EfiBootServicesData + ); + + // + // Let PEI know about the DXE FV so it can find the DXE Core + // + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *)(UINTN)PcdGet32 (PcdDxeMemFvBase), + PcdGet32 (PcdDxeMemFvSize), + NULL, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c b/MdeMo= dulePkg/Universal/PlatformPei/RiscV64/MemDetect.c new file mode 100644 index 000000000000..3ebd29eba675 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c @@ -0,0 +1,179 @@ +/** @file + Memory Detection for Virtual Machines. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "Platform.h" + +STATIC EFI_PHYSICAL_ADDRESS SystemMemoryBase; +STATIC UINT64 SystemMemorySize; +STATIC EFI_PHYSICAL_ADDRESS MmodeResvBase; +STATIC UINT64 MmodeResvSize; + +/** + Publish PEI core memory. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +PublishPeiMemory ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + EFI_PHYSICAL_ADDRESS MemoryBase; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + EFI_STATUS Status; + UINT64 CurBase, CurSize; + UINT64 NewBase =3D 0, NewSize =3D 0; + UINT64 MemorySize; + INT32 Node, Prev; + INT32 Len; + VOID *FdtPointer; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + // Look for the lowest memory node + for (Prev =3D 0;; Prev =3D Node) { + Node =3D fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + // Check for memory node + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && AsciiStrnCmp (Type, "memory", Len) =3D=3D 0) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) { + + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", + __FUNCTION__, CurBase, CurBase + CurSize - 1)); + + if (NewBase > CurBase || NewBase =3D=3D 0) { + NewBase =3D CurBase; + NewSize =3D CurSize; + } + } else { + DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", + __FUNCTION__)); + } + } + } + + SystemMemoryBase =3D NewBase; + SystemMemorySize =3D NewSize; + + /* try to locate the reserved memory opensbi node */ + Node =3D fdt_path_offset(FdtPointer, "/reserved-memory/mmode_resv0"); + if (Node >=3D 0) { + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) { + NewBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + NewSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + DEBUG ((DEBUG_INFO, "%a: M-mode Base =3D 0x%lx, M-mode Size =3D 0x%l= x\n", + __FUNCTION__, NewBase, NewSize)); + MmodeResvBase =3D NewBase; + MmodeResvSize =3D NewSize; + } + } + + DEBUG ((DEBUG_INFO, "%a: SystemMemoryBase:0x%x SystemMemorySize:%x\n", + __FUNCTION__, SystemMemoryBase, SystemMemorySize)); + + // + // Initial 16MB needs to be reserved + // + MemoryBase =3D SystemMemoryBase + SIZE_16MB; + MemorySize =3D SystemMemorySize - SIZE_16MB; + + // + // Publish this memory to the PEI Core + // + Status =3D PublishSystemMemory (MemoryBase, MemorySize); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Publish system RAM and reserve memory regions. + +**/ +VOID +InitializeRamRegions ( + VOID + ) +{ + /* + * M-mode FW can be loaded anywhere in memory but should not overlap + * with the EDK2. This can happen if some other boot code loads the + * M-mode firmware. + * + * The M-mode firmware memory should be marked as reserved memory + * so that OS doesn't use it. + */ + DEBUG ((DEBUG_INFO, "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, MmodeResvBase, MmodeResvBase + MmodeResvSize)); + AddReservedMemoryBaseSizeHob(MmodeResvBase, MmodeResvSize); + + if (MmodeResvBase > SystemMemoryBase) { + DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, SystemMemoryBase, MmodeResvBase)); + AddMemoryRangeHob(SystemMemoryBase, MmodeResvBase); + } + + DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize)); + AddMemoryRangeHob(MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize); +} diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c b/MdeMod= ulePkg/Universal/PlatformPei/RiscV64/Platform.c new file mode 100644 index 000000000000..27d50a0e565e --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c @@ -0,0 +1,372 @@ +/** @file + Platform PEI driver + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Platform.h" + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D { + { EfiACPIMemoryNVS, 0x004 }, + { EfiACPIReclaimMemory, 0x008 }, + { EfiReservedMemoryType, 0x004 }, + { EfiRuntimeServicesData, 0x024 }, + { EfiRuntimeServicesCode, 0x030 }, + { EfiBootServicesCode, 0x180 }, + { EfiBootServicesData, 0xF00 }, + { EfiMaxMemoryType, 0x000 } +}; + +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiMasterBootModePpiGuid, + NULL + } +}; + +STATIC EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION; + +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Build reserved memory range resource HOB. + + @param MemoryBase Reserved memory range base address. + @param MemorySize Reserved memory range size. + +**/ +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Build memory map I/O resource using the base address + and the top address of memory range. + + @param MemoryBase Memory map I/O range base address. + @param MemoryLimit The top address of memory map I/O range + +**/ +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Create untested memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE, + MemoryBase, + MemorySize + ); +} + +/** + Create untested memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} + +/** + Add PCI resource. + +**/ +VOID +AddPciResource ( + VOID + ) +{ + // + // Platform-specific + // +} + +/** + Platform memory map initialization. + +**/ +VOID +MemMapInitialization ( + VOID + ) +{ + // + // Create Memory Type Information HOB + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof (mDefaultMemoryTypeInformation) + ); + + // + // Add PCI IO Port space available for PCI resource allocations. + // + AddPciResource (); +} + +/** + Platform misc initialization. + +**/ +VOID +MiscInitialization ( + VOID + ) +{ + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + // TODO: Determine this dynamically from the platform + // setting or the HART configuration. + // + BuildCpuHob (56, 32); +} + +/** + Check if system returns from S3. + + @return BOOLEAN TRUE, system returned from S3 + FALSE, system is not returned from S3 + +**/ +BOOLEAN +CheckResumeFromS3 ( + VOID + ) +{ + // + // Platform implementation-specific + // + return FALSE; +} + +/** + Platform boot mode initialization. + +**/ +VOID +BootModeInitialization ( + VOID + ) +{ + EFI_STATUS Status; + + if (CheckResumeFromS3()) { + DEBUG ((DEBUG_INFO, "This is wake from S3\n")); + } else { + DEBUG ((DEBUG_INFO, "This is normal boot\n")); + } + + Status =3D PeiServicesSetBootMode (mBootMode); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesInstallPpi (mPpiBootMode); + ASSERT_EFI_ERROR (Status); +} + +/** + Build processor information for U54 Coreplex processor. + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildCoreInformationHob ( + VOID + ) +{ +// return BuildRiscVSmbiosHobs (); + return EFI_SUCCESS; +} + +/** + Perform Platform PEI initialization. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +InitializePlatform ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); + Status =3D PlatformPeim(); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PlatformPeim failed\n")); + ASSERT (FALSE); + } + BootModeInitialization (); + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n")); + PublishPeiMemory (); + DEBUG ((DEBUG_INFO, "PEI memory published.\n")); + InitializeRamRegions (); + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n")); + + if (mBootMode !=3D BOOT_ON_S3_RESUME) { + PeiFvInitialization (); + MemMapInitialization (); + } + + MiscInitialization (); + Status =3D BuildCoreInformationHob (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n")); + ASSERT (FALSE); + } + + return EFI_SUCCESS; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93390): https://edk2.groups.io/g/devel/message/93390 Mute This Topic: https://groups.io/mt/93522349/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93391+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93391+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549187; cv=none; d=zohomail.com; s=zohoarc; b=WQ7TK/lSlyE1ZdxKwna7oeN5iQ+VhBmTOZqcFUwb5OeG1C4t7vVv4xUvrC+iPFGqp6rpZMWiN8Xf+et9RFFthhsZvYjmIt8XNF5dYIMi+gkrt4/lppbjMhjHAXGNL7hA5M0bw8S98+9dwAeK7+P9Eec1q40GOOEQWEzCD5PSYS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549187; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=piEGyGDYtIOrUohLHd28q5QmEwU/e7/SI/zizSOe3RY=; b=DOALysFh+yeDYy+Z47p2nSjPKLU8iKSa5MPx8jQ83QTQSKZvRZkKQUYDGnWaQuIlR/pTDUcyvZ78hldmIocnPBE/iUuLqAmMSGw168K1M3xoDrKV5ReEF9a2QYQEy6Wff1gIPewFzfnxNP+5Ragj0tJlnxnFvckeTwuaqvQIsIg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93391+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16625491874021017.2040116377689; Wed, 7 Sep 2022 04:13:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id TSq6YY1788612xnFinG42gTY; Wed, 07 Sep 2022 04:13:07 -0700 X-Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mx.groups.io with SMTP id smtpd.web08.6412.1662549186431576822 for ; Wed, 07 Sep 2022 04:13:06 -0700 X-Received: by mail-pj1-f41.google.com with SMTP id p1-20020a17090a2d8100b0020040a3f75eso9479220pjd.4 for ; Wed, 07 Sep 2022 04:13:06 -0700 (PDT) X-Gm-Message-State: pCMfaBjO3nk1wPQBEsLgwRyJx1787277AA= X-Google-Smtp-Source: AA6agR5IOdWHUJR0n1/3JdknVcAtvnEDIwltAgfrtz50Q2q7LRF/GFhDugsA/4R8BjJSZs+c5Nc07A== X-Received: by 2002:a17:902:ecc6:b0:174:90c5:613b with SMTP id a6-20020a170902ecc600b0017490c5613bmr3274794plh.28.1662549185661; Wed, 07 Sep 2022 04:13:05 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:13:05 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 15/19] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Date: Wed, 7 Sep 2022 16:41:21 +0530 Message-Id: <20220907111125.539698-16-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549187; bh=PGACwNsM3fbr/VjGFeEFnmbzGeeDO5IrMKTOJAzI2dk=; h=Cc:Date:From:Reply-To:Subject:To; b=uAne/jBWl78hGepL79+r2QWNABOzS9P6fa5sr8yHobMtLqgwJ2riedv8+803uyCGjCf cacb/sKwjnzEPFhpooMkusr3lf9jMpE3a5Q+TWjScTPcpu+DnqADT71uWo+pD1m5PPV8J 6zXTsuCSGp33cAzKt4VybP6jKNxZkVJKRp0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549188754100007 Content-Type: text/plain; charset="utf-8" Currently, CpuDxe driver is mostly x86 specific. Refactor the INF to allow other architectures like RISC-V. Signed-off-by: Sunil V L --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 235241899222..4f2ea42f1612 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -29,20 +29,22 @@ [LibraryClasses] DebugLib DxeServicesTableLib MemoryAllocationLib - MtrrLib UefiBootServicesTableLib UefiDriverEntryPoint - LocalApicLib - UefiCpuLib UefiLib CpuExceptionHandlerLib HobLib ReportStatusCodeLib - MpInitLib TimerLib PeCoffGetEntryPointLib =20 -[Sources] +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib + MpInitLib + MtrrLib + UefiCpuLib + +[Sources.IA32, Sources.X64] CpuDxe.c CpuDxe.h CpuGdt.c --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93391): https://edk2.groups.io/g/devel/message/93391 Mute This Topic: https://groups.io/mt/93522350/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93392+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93392+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549193; cv=none; d=zohomail.com; s=zohoarc; b=Sc96bt+JzSv50kyzEQbuRZcJG+06Yf/iqtG5ekfGfEhaX8oH7q9b31COPbaccwZGhx/wkKnsGSYulRHvDX03A3tjfcDaaVwwcs1lB133+v7wKbNCxUAms+t0qU1u87RMZk/wzVckeTqqrxD+02Ok0X3tc1tKgdLQUT4grLSa9M4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549193; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Cb+LKAfOMa6UGwE+BuQO9Egoso7xY61EbyRHhGVgkME=; b=EsaEVGBJ1pqGEa9h8o+XSJAe6barLg73trtO16S/3jYo2Mu7kPyo+OYhcJ+LS/mQ/+59pi/kIJfSTmcJNgqgRl6VF/oOBdghKgCwnbTYFGdeBF6bugZYGLoxKm3eVgxGPBChzDiUzjJKM/jJUlLjbZjAzg41YdF+/8gQHDafJWs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93392+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549193522181.30356921687394; Wed, 7 Sep 2022 04:13:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RokaYY1788612xjASZD1Oaus; Wed, 07 Sep 2022 04:13:13 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web12.6404.1662549191926144153 for ; Wed, 07 Sep 2022 04:13:12 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id d12so14167929plr.6 for ; Wed, 07 Sep 2022 04:13:11 -0700 (PDT) X-Gm-Message-State: 6zpSBrwndyWVXqAuRjrA61q6x1787277AA= X-Google-Smtp-Source: AA6agR61k0pSlr6fU5u1nFo74WQete8kzbeoDlDs4Eux0kGA8o6EozRKxTCziIELrbmU86AhwXURFA== X-Received: by 2002:a17:90b:1bc7:b0:200:7f05:3c2 with SMTP id oa7-20020a17090b1bc700b002007f0503c2mr13143423pjb.95.1662549190699; Wed, 07 Sep 2022 04:13:10 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:13:09 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 16/19] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Date: Wed, 7 Sep 2022 16:41:22 +0530 Message-Id: <20220907111125.539698-17-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549193; bh=HTr46StGKuWp+ipaiOddhucL0+F94gSIHcSdDlyqNH8=; h=Cc:Date:From:Reply-To:Subject:To; b=IVtD/EGTIDGC9nueAicfAq48R0e9Xq8aBiEh6vAUAI33rznqF+wWF3Kyrb7e5xESRoV tHpQKd6+FNqNZL8kIduh2wxOyG6iQXLwjMfIrmlpdjOPe8eMRHrLpIMAzZNjOOeEI8HUz i3zjqO9ICZGLa0N5zouyNSM77amuirB7E5Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549195113100001 Content-Type: text/plain; charset="utf-8" This DXE module initializes the RISC-V CPU by installing the CPU specific ARCH protocol handlers. This also initializes the RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms. Signed-off-by: Sunil V L --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 ++++++++++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 ++++++++++++++++++++ 3 files changed, 552 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f1612..17cf2b1ecd30 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -1,8 +1,12 @@ ## @file -# CPU driver installs CPU Architecture Protocol and CPU MP protocol. +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP protoc= ol. +# +# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V boot +# protocol # # Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,6 +48,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] MtrrLib UefiCpuLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + [Sources.IA32, Sources.X64] CpuDxe.c CpuDxe.h @@ -62,11 +69,18 @@ [Sources.X64] X64/CpuAsm.nasm X64/PagingAttribute.c =20 +[Sources.RISCV64] + RiscV64/CpuDxe.c + RiscV64/CpuDxe.h + [Protocols] gEfiCpuArchProtocolGuid ## PRODUCES gEfiMpServiceProtocolGuid ## PRODUCES gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES =20 +[Protocols.RISCV64] + gRiscVEfiBootProtocolGuid ## PRODUCES + [Guids] gIdleLoopEventGuid ## CONSUMES ## E= vent gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## S= ystemTable diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.h new file mode 100644 index 000000000000..f039759dbdaa --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h @@ -0,0 +1,200 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef CPU_DXE_H_ +#define CPU_DXE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c new file mode 100644 index 000000000000..4112b6b8c6b9 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -0,0 +1,337 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "CpuDxe.h" + +// +// Global Variables +// +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + mInterruptState =3D TRUE; + return EFI_SUCCESS; +} + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + mInterruptState =3D FALSE; + return EFI_SUCCESS; +} + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D mInterruptState; + return EFI_SUCCESS; +} + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__)); + return EFI_SUCCESS; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + + InitializeCpuExceptionHandlers(NULL); + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + Status =3D gBS->InstallProtocolInterface (&ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + + ASSERT_EFI_ERROR (Status); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, + &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93392): https://edk2.groups.io/g/devel/message/93392 Mute This Topic: https://groups.io/mt/93522351/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93393+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93393+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549197; cv=none; d=zohomail.com; s=zohoarc; b=YXYsZWn0xvD3qb/Ekrds128BL+NNo2XpnLILDE/54NenlGbNQGXe1MshvkWlgrVha5JVCFHvaQuM9BIA0hQxrKM0iuYMKovaHmoUX7bYYSRTdS/u2PvFlXPNfmRw45HbXF1vV6Dfp335r7cPaqCt4ArLu1NZwxW3va8i8tJfddc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549197; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QsdcBEj2ivnmkCR7T0e2xS6bOhenZ9+eZF1TKPj4gto=; b=ZQLkvCRUTdQcUtKvTUMFm/IuDmzVW1Eqj/077FV+2zhj24tHahgR2m62jQerBmih/FkRIh+AawWVL1YIoYj5VoRmK0nCTx3Ox8H9Vc8MgYUkM7HVpoXzraWDyjiq3Jr49beuTrLUxG8zxnwobeKvodNBLyWbH6gikM8Soa+0gtU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93393+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549197508425.731592752256; Wed, 7 Sep 2022 04:13:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id bBy8YY1788612xm8SVJS1H6g; Wed, 07 Sep 2022 04:13:17 -0700 X-Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) by mx.groups.io with SMTP id smtpd.web11.6328.1662549196457548227 for ; Wed, 07 Sep 2022 04:13:16 -0700 X-Received: by mail-pj1-f50.google.com with SMTP id x1-20020a17090ab00100b001fda21bbc90so17922239pjq.3 for ; Wed, 07 Sep 2022 04:13:16 -0700 (PDT) X-Gm-Message-State: FOWVg130F76pHzLccYXo9jBUx1787277AA= X-Google-Smtp-Source: AA6agR4taTfvPQtx44JHrP4w/6K8fkkRIf/RJe3dthFunjbIglVWk+1qtAWuQ/Ht3vAxL8m6/8WL1A== X-Received: by 2002:a17:902:db11:b0:175:4cdc:f32 with SMTP id m17-20020a170902db1100b001754cdc0f32mr3062118plx.58.1662549195416; Wed, 07 Sep 2022 04:13:15 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:13:15 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 17/19] MdeModulePkg/Universal: Add TimerDxe module Date: Wed, 7 Sep 2022 16:41:23 +0530 Message-Id: <20220907111125.539698-18-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549197; bh=6dzeWe2KEZDRHvvYTv33ERn8Hp27hpAeTPa6/paSmpE=; h=Cc:Date:From:Reply-To:Subject:To; b=dmsZsNYzb4EaVvndZLDEBf1fAeqhZC8n88t6NxX/IqiDNPSAMvXMXXvknyuStfRbbNH Dm5Espm7Yw6ze8M7W1xR62Yw7tMPQT3ZbZasY99S4WiKC8srgvXzgmklrF0uf2oZumBmF C5l5YMPBrobYqBzR4roU0ok+PYKB1i1WqYE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549199043100001 Content-Type: text/plain; charset="utf-8" This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Signed-off-by: Sunil V L --- MdeModulePkg/Universal/TimerDxe/TimerDxe.inf | 52 ++++ MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h | 174 ++++++++++++ MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c | 293 ++++++++++++++++++++ MdeModulePkg/Universal/TimerDxe/Timer.uni | 15 + MdeModulePkg/Universal/TimerDxe/TimerExtra.uni | 13 + 5 files changed, 547 insertions(+) diff --git a/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf b/MdeModulePkg/Un= iversal/TimerDxe/TimerDxe.inf new file mode 100644 index 000000000000..b291a1fcecb2 --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf @@ -0,0 +1,52 @@ +## @file +# Timer Arch protocol module +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D Timer + MODULE_UNI_FILE =3D Timer.uni + FILE_GUID =3D 055DDAC6-9142-4013-BF20-FC2E5BC325C9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D TimerDriverInitialize +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + CpuLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Sources.RISCV64] + RiscV64/Timer.h + RiscV64/Timer.c + +[Protocols] + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiTimerArchProtocolGuid ## PRODUCES + +[Depex] + gEfiCpuArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + TimerExtra.uni diff --git a/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h b/MdeModulePkg= /Universal/TimerDxe/RiscV64/Timer.h new file mode 100644 index 000000000000..32f56f8fe1ca --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h @@ -0,0 +1,174 @@ +/** @file + RISC-V Timer Architectural Protocol definitions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include + +#include +#include + +#include +#include +#include +#include + +// +// RISC-V use 100us timer. +// The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units +// +#define DEFAULT_TIMER_TICK_DURATION 100000 + +extern VOID RiscvSetTimerPeriod (UINT32 TimerPeriod); + +// +// Function Prototypes +// +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +; + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +; + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +; + +#endif diff --git a/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c b/MdeModulePkg= /Universal/TimerDxe/RiscV64/Timer.c new file mode 100644 index 000000000000..4deb91766d17 --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c @@ -0,0 +1,293 @@ +/** @file + RISC-V Timer Architectural Protocol + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Timer.h" +#include +#include + +// +// The handle onto which the Timer Architectural Protocol will be installed +// +STATIC EFI_HANDLE mTimerHandle =3D NULL; + +// +// The Timer Architectural Protocol that this driver produces +// +EFI_TIMER_ARCH_PROTOCOL mTimer =3D { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +// +// Pointer to the CPU Architectural Protocol instance +// +EFI_CPU_ARCH_PROTOCOL *mCpu; + +// +// The notification function to call on every timer interrupt. +// A bug in the compiler prevents us from initializing this here. +// +STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; + +// +// The current period of the timer interrupt +// +STATIC UINT64 mTimerPeriod =3D 0; + +/** + Timer Interrupt Handler. + + @param InterruptType The type of interrupt that occured + @param SystemContext A pointer to the system context when the interru= pt occured +**/ + +VOID +EFIAPI +TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 RiscvTimer; + + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + if (mTimerNotifyFunction !=3D NULL) { + mTimerNotifyFunction (mTimerPeriod); + } + csr_clear(CSR_SIE, SIP_STIP); // Disable SMode timer int + csr_clear(CSR_SIP, SIP_STIP); + if (mTimerPeriod =3D=3D 0) { + gBS->RestoreTPL (OriginalTPL); + csr_clear(CSR_SIE, SIP_STIP); // Disable SMode timer int + return; + } + RiscvTimer =3D csr_read(CSR_TIME); + SbiSetTimer (RiscvTimer +=3D mTimerPeriod); + gBS->RestoreTPL (OriginalTPL); + csr_set(CSR_SIE, SIP_STIP); // enable SMode timer int +} + +/** + + This function registers the handler NotifyFunction so it is called every= time + the timer interrupt fires. It also passes the amount of time since the = last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS= is + returned. If the CPU does not support registering a timer interrupt han= dler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a h= andler + when a handler is already registered, then EFI_ALREADY_STARTED is return= ed. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ER= ROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fire= s. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so i= t can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support time= r interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a = handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a hand= ler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be reg= istered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", Notify= Function)); + mTimerNotifyFunction =3D NotifyFunction; + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 RiscvTimer; + + DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod)); + + if (TimerPeriod =3D=3D 0) { + mTimerPeriod =3D 0; + csr_clear(CSR_SIE, SIP_STIP); // disable timer int + return EFI_SUCCESS; + } + + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us + RiscvTimer =3D csr_read(CSR_TIME); + SbiSetTimer(RiscvTimer + mTimerPeriod); + + mCpu->EnableInterrupt(mCpu); + csr_set(CSR_SIE, SIP_STIP); // enable timer int + return EFI_SUCCESS; +} + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + *TimerPeriod =3D mTimerPeriod; + return EFI_SUCCESS; +} + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize the pointer to our notify function. + // + mTimerNotifyFunction =3D NULL; + + // + // Make sure the Timer Architectural Protocol is not already installed i= n the system + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid); + + // + // Find the CPU architectural protocol. + // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= ) &mCpu); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be disabled + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, 0); + ASSERT_EFI_ERROR (Status); + + // + // Install interrupt handler for RISC-V Timer. + // + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be enabled at its default period + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATI= ON); + ASSERT_EFI_ERROR (Status); + + // + // Install the Timer Architectural Protocol onto a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mTimerHandle, + &gEfiTimerArchProtocolGuid, &mTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/MdeModulePkg/Universal/TimerDxe/Timer.uni b/MdeModulePkg/Unive= rsal/TimerDxe/Timer.uni new file mode 100644 index 000000000000..07272a8a787b --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/Timer.uni @@ -0,0 +1,15 @@ +// /** @file +// +// Timer Arch protocol strings. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Timer driver that= provides Timer Arch protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "Timer driver that= provides Timer Arch protocol." diff --git a/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni b/MdeModulePkg/= Universal/TimerDxe/TimerExtra.uni new file mode 100644 index 000000000000..ad80afe2674c --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni @@ -0,0 +1,13 @@ +// /** @file +// Timer Localized Strings and Content +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Timer DXE Driver" --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93393): https://edk2.groups.io/g/devel/message/93393 Mute This Topic: https://groups.io/mt/93522352/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93394+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93394+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549202; cv=none; d=zohomail.com; s=zohoarc; b=hB9wsLjC43l9ZTDhHmLfygYlBacs12x3fJahVN8mw2HPUErA7TvgqkJSO1Z6JUtflZSryTvm7acui0HLQlZmLg2EGYhusNYM5cMUIIukoddpIbcglZMaZOhXLaUq/+znnCqqROId2V64x9C4BTLoHXnPEPa+q5pmh5wGUeRhu7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549202; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tZ718Bh/h8q4ZS2UZLxA5ucewbhmhtoat2ACLfy5/NY=; b=fJCo6boh96w1zTDfdweYjkGjPEe0g3ul56tbldJI4qiomQue3nVfZQStK7VP47c59vq/jVR9bQE1Or+fl5Kx1of3yEKQM2z7w4mXZxhZJE3dXQmYTzLutVGvEWa5uwLVEHzeWOtqo07uv6300KbLWVyFBxWF67K1AywFKbTpmRs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93394+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549202317375.26924219365003; Wed, 7 Sep 2022 04:13:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5KhfYY1788612xBwOXBLJG1J; Wed, 07 Sep 2022 04:13:21 -0700 X-Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mx.groups.io with SMTP id smtpd.web08.6412.1662549186431576822 for ; Wed, 07 Sep 2022 04:13:21 -0700 X-Received: by mail-pj1-f41.google.com with SMTP id p1-20020a17090a2d8100b0020040a3f75eso9479851pjd.4 for ; Wed, 07 Sep 2022 04:13:21 -0700 (PDT) X-Gm-Message-State: HIPZhW8Il8SJ1tMwmPc18E9vx1787277AA= X-Google-Smtp-Source: AA6agR7XO1ny1BM0GQjCwNzEXw8Num35l2y2KQsnWKzSs0RxFpSvH/oMeeue596UmcueQ2Wg2gwIqQ== X-Received: by 2002:a17:903:284:b0:176:9bbd:3792 with SMTP id j4-20020a170903028400b001769bbd3792mr3267639plr.63.1662549200201; Wed, 07 Sep 2022 04:13:20 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.13.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:13:19 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 18/19] RISC-V: Add Qemu Virt platform support Date: Wed, 7 Sep 2022 16:41:24 +0530 Message-Id: <20220907111125.539698-19-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549201; bh=Ova7CFeUd7BFoR2hccwDmoKS6V9algCobbRa+ltVHbw=; h=Cc:Date:From:Reply-To:Subject:To; b=N4LCKCtHxmoQJl/W5QCgv4nAaKjq/SZYchucFUy2XMY9wyCwTIwxcWx7tQ2X3qjEFAi b7jbM5GaFpEfCuaZGBiRU5/lWDop0Q+Id+0uhwxYsFAZO4bNnENMz+IFJya0qpzL49py5 c3xX8qUKwjt+X2fPo7CryLMxVdSvRJbAETs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549203221100001 Content-Type: text/plain; charset="utf-8" Add build infrastructure files to boot qemu virt machine. EDK2 will boot as S-mode payload of opensbi. There is no integrated opensbi (M-mode firmware) within EDK2 for virt machine. It relies on the RISC-V calling convention that M-mode firmware like opensbi will pass the BootHartId and the DTB to EDK2. This helps to simplify the platform specific PCD variables required. It can parse the DTB to know all the details. Even for future ACPI support, EDK2 can parse the DTB to create static tables. Signed-off-by: Sunil V L --- OvmfPkg/RiscVVirt/RiscVVirt.dsc | 713 ++++++++++++++++++++ OvmfPkg/RiscVVirt/RiscVVirt.fdf | 379 +++++++++++ OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 49 ++ OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 +++ 4 files changed, 1220 insertions(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc b/OvmfPkg/RiscVVirt/RiscVVirt.= dsc new file mode 100644 index 000000000000..d189c047e817 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc @@ -0,0 +1,713 @@ +## @file +# RISC-V EFI on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D RiscVVirt + PLATFORM_GUID =3D 39DADB39-1B21-4867-838E-830B6149B9E0 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x0001001c + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D OvmfPkg/RiscVVirt/RiscVVirt.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D TRUE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D TRUE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC: *_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + TimerLib|MdePkg/Library/ArchTimerLib/ArchTimerLib.inf + TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf + RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRea= lTimeClockLib.inf + NorFlashPlatformLib|ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.i= nf + +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf +!endif + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +# ACPI not supported yet. + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common] +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + + RiscVSbiLib|MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + + # PCI Libraries + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf + DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + + # Virtio Support + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf + VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf + QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf + QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFw= CfgSimpleParserLib.inf + QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf + + # PCI support + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridge= LibNull.inf + + # Boot Manager +!if $(TPM2_ENABLE) =3D=3D TRUE + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT= cg2PhysicalPresenceLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= b/PeiDxeTpmPlatformHierarchyLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf +!endif + + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf + + # TODO: This would need to be made common for RISC-V and ARM or need to = copied + PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/Platfor= mBootManagerLib.inf + + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + +[LibraryClasses.common.SEC] +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + +[LibraryClasses.common.DXE_CORE] + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf + ResetSystemLib|MdePkg/Library/ResetSystemLib/ResetSystemLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ib.inf + PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf + PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf + PciHostBridgeLib|OvmfPkg/Fdt/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf + PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostB= ridgeUtilityLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + PlatformUpdateProgressLib|MdeModulePkg/Library/PlatformBootManagerLibNul= l/PlatformBootManagerLibNull.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000 + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x02 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + # + # F2 for UI APP + # + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"2.7" + + # Serial Port + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|9600 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1 + +##########################################################################= ###### +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform +# +##########################################################################= ###### + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 + + # Set video resolution for text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + UefiCpuPkg/SecCore/SecCoreRiscV.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + + # + # PEI Phase modules + # + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompress= Lib.inf + } + + MdeModulePkg/Universal/PlatformPei/PlatformPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + PlatformPeiLib|MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf + } + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompr= essLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + + MdeModulePkg/Universal/Metronome/Metronome.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # RISC-V Platform module + # + MdeModulePkg/Universal/TimerDxe/TimerDxe.inf + + # + # TODO: Move this to OvmfPkg? + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + + # + # RISC-V Core module + # + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + +# Graphic console + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Network Support + # + !include NetworkPkg/Network.dsc.inc + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # PCI support + # + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + NULL|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf + } + OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf + OvmfPkg/Virtio10Dxe/Virtio10.inf + + # + # Video support + # + OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf + OvmfPkg/VirtioGpuDxe/VirtioGpu.inf + OvmfPkg/PlatformDxe/Platform.inf + + # + # Platform Driver + # + OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf + EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf + OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf + OvmfPkg/VirtioScsiDxe/VirtioScsi.inf + OvmfPkg/VirtioNetDxe/VirtioNet.inf + OvmfPkg/VirtioRngDxe/VirtioRng.inf + + # + # TODO: Move this to OVMF/Generic + # + ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + # + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.in= f { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC= ommandLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Logo/LogoDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf { + + NULL|OvmfPkg/Library/BlobVerifierLibNull/BlobVerifierLibNull.inf + } + +# HTTPS(secure) support in GUI for updating ssl keys for PXE boot + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib= .inf + } + +# TFTP support for PXE boot + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpApp.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + + # HTTP support for PXE boot + ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf + } + ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf + } + +# HTTPS (secure) support for PXE boot + NetworkPkg/TlsDxe/TlsDxe.inf { + + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + RngLib|MdePkg/Library/DxeRngLib/DxeRngLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib= .inf + } + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf { + + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib= .inf + NULL|OvmfPkg/Library/TlsAuthConfigLib/TlsAuthConfigLib.inf + } + +[PcdsDynamicDefault.common] + # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this + # PCD and PcdPciDisableBusEnumeration above have not been assigned yet + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF + + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 + +[PcdsFeatureFlag.common] + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle= created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf b/OvmfPkg/RiscVVirt/RiscVVirt.= fdf new file mode 100644 index 000000000000..9996d8a299f8 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf @@ -0,0 +1,379 @@ +# @file +# Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Platform definitions +# + +!include RiscVVirt.fdf.inc + +##########################################################################= ###### + +[FD.RISCV_VIRT] +BaseAddress =3D $(FW_BASE_ADDRESS) +Size =3D $(FW_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +$(SECFV_OFFSET)|$(SECFV_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase|gEfiMdeModulePkgTokenSpaceG= uid.PcdSecMemFvSize +FV =3D SECFV + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc +##########################################################################= ###### + +[FD.RISCV_MEMFD] +BaseAddress =3D $(MEMFD_BASE_ADDRESS) +Size =3D 0x00a00000 +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D 0xa00 + +0x00000000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase|gEfiMdeModulePkgTokenS= paceGuid.PcdSecPeiTempRamSize + +0x00010000|0x001000 +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize + +0x00040000|0x00080000 +gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase|gEfiMdeModulePkgTokenSpaceG= uid.PcdPeiMemFvSize +FV =3D PEIFV + +0x00100000|0x00900000 +gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase|gEfiMdeModulePkgTokenSpaceG= uid.PcdDxeMemFvSize +FV =3D DXEFV + +##########################################################################= ################ + +[FV.SECFV] +BlockSize =3D 0x1000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# SEC Phase modules +# +# The code in this FV handles the initial firmware startup, and +# decompresses the PEI and DXE FVs which handles the rest of the boot sequ= ence. +# +INF UefiCpuPkg/SecCore/SecCoreRiscV.inf + +##########################################################################= ###### +[FV.PEIFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI PEI { + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeR= outerPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.i= nf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +} + +# +# PEI Phase modules +# +INF MdeModulePkg/Core/Pei/PeiMain.inf +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRou= terPei.inf +INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +# RISC-V Platform PEI Driver +INF MdeModulePkg/Universal/PlatformPei/PlatformPei.inf + +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +} + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf + +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +# +# PCI support +# +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf +INF OvmfPkg/Virtio10Dxe/Virtio10.inf + +# +# Video support +# +INF OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf +INF OvmfPkg/VirtioGpuDxe/VirtioGpu.inf +INF OvmfPkg/PlatformDxe/Platform.inf + +# +# Platform Driver +# +INF OvmfPkg/Fdt/VirtioFdtDxe/VirtioFdtDxe.inf +INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf +INF OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf +INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf +INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf +INF OvmfPkg/VirtioNetDxe/VirtioNet.inf +INF OvmfPkg/VirtioRngDxe/VirtioRng.inf +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + +INF MdeModulePkg/Universal/Metronome/Metronome.inf +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + +# TODO: Move this to OVMF? +INF ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf + +# RISC-V Platform Drivers +INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + +# RISC-V Core Drivers +INF MdeModulePkg/Universal/TimerDxe/TimerDxe.inf +INF UefiCpuPkg/CpuDxe/CpuDxe.inf + +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif + +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + +!ifndef $(SOURCE_DEBUG_ENABLE) +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +!endif + +INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand= .inf +INF ShellPkg/Application/Shell/Shell.inf + +# TFTP support for PXE boot +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpApp.inf + +# HTTP support for PXE boot +INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf +INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.inf + +# +# Network modules +# +!if $(E1000_ENABLE) + FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { + SECTION PE32 =3D Intel3.5/EFIX64/E3507X2.EFI + } +!endif + +!include NetworkPkg/Network.fdf.inc + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +INF MdeModulePkg/Application/UiApp/UiApp.inf +INF OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compressio= n. + # + SECTION FV_IMAGE =3D PEIFV + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.fdf.inc new file mode 100644 index 000000000000..6e08e8e9ba71 --- /dev/null +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -0,0 +1,49 @@ +## @file +# Definitions of Flash definition file on RiscVVirt RISC-V platform +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE FW_BASE_ADDRESS =3D 0x22000000 +DEFINE FW_SIZE =3D 0x00300000 +DEFINE FW_BLOCKS =3D 0x300 + +DEFINE CODE_BASE_ADDRESS =3D $(FW_BASE_ADDRESS) +DEFINE CODE_SIZE =3D 0x00240000 +DEFINE CODE_BLOCKS =3D 0x240 + + +# +# The size of memory region must be power of 2. +# The base address must be aligned with the size. +# +# FW memory region +# +DEFINE SECFV_OFFSET =3D 0x00000000 +DEFINE SECFV_SIZE =3D 0x00040000 +DEFINE FVMAIN_OFFSET =3D 0x00040000 +DEFINE FVMAIN_SIZE =3D 0x00200000 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET =3D 0x00240000 +DEFINE VARS_SIZE =3D 0x00040000 +DEFINE VARS_FTW_WORKING_OFFSET =3D 0x00280000 +DEFINE VARS_FTW_WORKING_SIZE =3D 0x00040000 +DEFINE VARS_FTW_SPARE_OFFSET =3D 0x002c0000 +DEFINE VARS_FTW_SPARE_SIZE =3D 0x00040000 + +# +# Base Address where SEC phase will decompress and load +# the PEI and DXE FVs +# +DEFINE MEMFD_BASE_ADDRESS =3D 0x80200000 diff --git a/OvmfPkg/RiscVVirt/VarStore.fdf.inc b/OvmfPkg/RiscVVirt/VarStor= e.fdf.inc new file mode 100644 index 000000000000..fd97db71d29d --- /dev/null +++ b/OvmfPkg/RiscVVirt/VarStore.fdf.inc @@ -0,0 +1,79 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3FFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93394): https://edk2.groups.io/g/devel/message/93394 Mute This Topic: https://groups.io/mt/93522353/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 14:50:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93395+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93395+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662549206; cv=none; d=zohomail.com; s=zohoarc; b=XoJ6PX2NIrhO5VFC6UxcCqeDC02QNOUtgP4lPjO9nXEAVHW77PX3Fs8fhPI9uIupzwRElIUCNCMbfhuSUVjLsKI1s8BRGmCIHwj8T9uuPfjw2F1fwN1Ivz4k0TqBozedR0RJTe37u+r+YM/PW2m2gh6Blj9Gbb9ETMj/89tWw1k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662549206; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=jCmm9EZIO5e29yc8QcesYVPi7onzJ2m3v0bExQYV1UA=; b=JVkasAVJSQgWpkOM9ES2ZCaDTf8l1jn2twGLvyrYvkS22GP7FdTi9FF2r5ExYNblNvgNzB8gSeL+QWo380rBBmIjIHxXBZmB2n6Vr94QlTPBKL7asAv7sOpR+jmOJy+SuUidD8W2piBB+58Mw+4bx0gsceUsGABS+xC9Kr4XUDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93395+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662549206370342.12558793725316; Wed, 7 Sep 2022 04:13:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id zFArYY1788612xspToDYP8Ma; Wed, 07 Sep 2022 04:13:26 -0700 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web12.6407.1662549205463076776 for ; Wed, 07 Sep 2022 04:13:25 -0700 X-Received: by mail-pf1-f176.google.com with SMTP id 123so4876087pfy.2 for ; Wed, 07 Sep 2022 04:13:25 -0700 (PDT) X-Gm-Message-State: j4PSktxuyyLSZjnZ0fHHOBKEx1787277AA= X-Google-Smtp-Source: AA6agR4UMlHWnzlykmaYp4gb42mvMH9VwXRUPkKP5I+xpqSMHYHOsU8wVxt3ah5CrlUd/wsUI1BIVQ== X-Received: by 2002:a63:4907:0:b0:434:731f:c0ae with SMTP id w7-20020a634907000000b00434731fc0aemr2929756pga.405.1662549204877; Wed, 07 Sep 2022 04:13:24 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.13.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:13:24 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH V2 19/19] Maintainers.txt: Add entry for new OvmfPkg/RiscVVirt Date: Wed, 7 Sep 2022 16:41:25 +0530 Message-Id: <20220907111125.539698-20-sunilvl@ventanamicro.com> In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662549206; bh=jCmm9EZIO5e29yc8QcesYVPi7onzJ2m3v0bExQYV1UA=; h=Cc:Date:From:Reply-To:Subject:To; b=a0QTOwyXConVr1Y8Yr3gGRzVMCG5iATcVrtP1YOlG63sJBwCIMngmTv2t6xoQtXVnUj nMcLeBHGoYlRQshtQhbt+de2AzDcC445q1GqtxGcxZm+Z1AtXzrkpznkDwGYIWqfQ+eu2 JBEtIaw7ifvu0DRaYcozy2CZSUbrHNoovnM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662549207137100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Sunil V L --- Maintainers.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 73ce13126b37..60610e83bbf1 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -528,6 +528,10 @@ F: OvmfPkg/XenResetVector/ R: Anthony Perard [sheep] R: Julien Grall [jgrall] =20 +OvmfPkg: RISC-V related modules +F: OvmfPkg/RiscVVirt +R: Sunil V L [vlsunil] + PcAtChipsetPkg F: PcAtChipsetPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93395): https://edk2.groups.io/g/devel/message/93395 Mute This Topic: https://groups.io/mt/93522366/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-