From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93262+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93262+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484133; cv=none; d=zohomail.com; s=zohoarc; b=GDr3tC+92TAJin7N6ftm+hogYrP57dijpY3EAUfTClCoTkoPgqwhUkG9SR8QAASbn8dqHp//Ttrjwjn1TBlWDNjFjOxJLQToqaXjNmrz0e5PBqSqKG8GWoo4QXnE4pmQSma8ewqEKZBwMtHD49SsG4h3dWuzuyI7Abtvr5Uw8hs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484133; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rOUBXRQVPS22y5FQLmloeL/4f1PTICMks40rd14Nk6M=; b=foHd0jyegTXGb1VuZf943pX04g0GrhD5lRoN7yLZbocwVeaTSihDNEOwTd9XfKXq4QDvqZOl/1lHS1LyP3dkX3ZVPGEnRHV1zsUe1tQ2iFR0lG8okD/rW9yaYXN7k5H5JX/d3DaxwrfqWu34ysR8TV9cXBr1XMeiQfHLTZsc9mQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93262+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484133279912.410312052506; Tue, 6 Sep 2022 10:08:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gijQYY1788612x4GKpbR2jQB; Tue, 06 Sep 2022 10:08:52 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web12.1904.1662484132293121015 for ; Tue, 06 Sep 2022 10:08:52 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id s14so2336652plr.4 for ; Tue, 06 Sep 2022 10:08:52 -0700 (PDT) X-Gm-Message-State: fc7LI4JQv99EOjW7ABiPbrhvx1787277AA= X-Google-Smtp-Source: AA6agR7kEgMUO0poX7VlHtd6Z+POjuv7513qw+gylEotQFeVbvtGIFp3NsnKjz9R3y0kAYkZ7upvpA== X-Received: by 2002:a17:902:d505:b0:175:5313:2a3f with SMTP id b5-20020a170902d50500b0017553132a3fmr29246142plg.70.1662484130848; Tue, 06 Sep 2022 10:08:50 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:08:50 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Date: Tue, 6 Sep 2022 22:38:21 +0530 Message-Id: <20220906170837.491525-2-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484132; bh=DgK8h++tNkX7NrmGn04O61WZTsjwr1Cg1Zx1+CbpjQg=; h=Cc:Date:From:Reply-To:Subject:To; b=YKGqe+4WXND7xAQj53f4xlK1vfUVMP/ZAVgglQ6ZMHreGxnvd3IVjggwUh65rNpNqa8 Ac9VjptKRTNSXRD/3U6XhhXMyasyGMim5C3RbztUpQ5T5xXrvlx+BR8DIOSd0p3ubFo+2 Ofw/uQ4u6yh2bRX28cCRCQA9YDA5sBi6kyg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484134830100007 Content-Type: text/plain; charset="utf-8" Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Signed-off-by: Sunil V L --- MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 ++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 +++++++ .../Include/Register/RiscV64/RiscVEncoding.h | 129 ++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 ++++ 4 files changed, 303 insertions(+) create mode 100644 MdePkg/Include/Register/RiscV64/RiscVAsm.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVConst.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h diff --git a/MdePkg/Include/Register/RiscV64/RiscVAsm.h b/MdePkg/Include/Re= gister/RiscV64/RiscVAsm.h new file mode 100644 index 0000000000..e566061b73 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVAsm.h @@ -0,0 +1,104 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_ASM_H__ +#define __RISCV_ASM_H__ + +#include + +#ifdef __ASSEMBLER__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#ifndef __ASSEMBLER__ + +#define csr_swap(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \ + : "=3Dr"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_read(csr) \ + ({ \ + register unsigned long __v; \ + __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \ + : "=3Dr"(__v) \ + : \ + : "memory"); \ + __v; \ + }) + +#define csr_write(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define csr_read_set(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \ + : "=3Dr"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_set(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define csr_read_clear(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \ + : "=3Dr"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_clear(csr, val) \ + ({ \ + unsigned long __v =3D (unsigned long)(val); \ + __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define wfi() \ + do { \ + __asm__ __volatile__("wfi" ::: "memory"); \ + } while (0) + +#define ebreak() \ + do { \ + __asm__ __volatile__("ebreak" ::: "memory"); \ + } while (0) + + +#endif /* !__ASSEMBLER__ */ + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVConst.h b/MdePkg/Include/= Register/RiscV64/RiscVConst.h new file mode 100644 index 0000000000..ea7e151191 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVConst.h @@ -0,0 +1,46 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.
+ * + * Authors: + * Anup Patel + * This is leveraged from sbi_const.h in opensbi. + */ + +#ifndef __RISCV_CONST_H__ +#define __RISCV_CONST_H__ + +/* + * Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define __STR(s) #s +#define STRINGIFY(s) __STR(s) + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 0000000000..5ad66ee7e7 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,129 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_ENCODING_H__ +#define __RISCV_ENCODING_H__ + +#include + +/* clang-format off */ +#define MSTATUS_SIE _UL(0x00000002) +#define MSTATUS_MIE _UL(0x00000008) +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (_UL(1) << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE _UL(0x00000040) +#define MSTATUS_MPIE _UL(0x00000080) +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (_UL(1) << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (_UL(3) << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (_UL(1) << IRQ_S_SOFT) +#define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT) +#define MIP_MSIP (_UL(1) << IRQ_M_SOFT) +#define MIP_STIP (_UL(1) << IRQ_S_TIMER) +#define MIP_VSTIP (_UL(1) << IRQ_VS_TIMER) +#define MIP_MTIP (_UL(1) << IRQ_M_TIMER) +#define MIP_SEIP (_UL(1) << IRQ_S_EXT) +#define MIP_VSEIP (_UL(1) << IRQ_VS_EXT) +#define MIP_MEIP (_UL(1) << IRQ_M_EXT) +#define MIP_SGEIP (_UL(1) << IRQ_S_GEXT) +#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U _UL(0) +#define PRV_S _UL(1) +#define PRV_M _UL(3) + +#define SATP64_MODE _ULL(0xF000000000000000) +#define SATP64_ASID _ULL(0x0FFFF00000000000) +#define SATP64_PPN _ULL(0x00000FFFFFFFFFFF) + +#define SATP_MODE_OFF _UL(0) +#define SATP_MODE_SV32 _UL(1) +#define SATP_MODE_SV39 _UL(8) +#define SATP_MODE_SV48 _UL(9) +#define SATP_MODE_SV57 _UL(10) +#define SATP_MODE_SV64 _UL(11) + + +#define SATP_MODE SATP64_MODE + +/* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* =3D=3D=3D=3D=3D Supervisor-level CSRs =3D=3D=3D=3D=3D */ + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* =3D=3D=3D=3D=3D Trap/Exception Causes =3D=3D=3D=3D=3D */ + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h new file mode 100644 index 0000000000..e9ccd34039 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,24 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __RISCV_IMPL_H_ +#define __RISCV_IMPL_H_ + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93262): https://edk2.groups.io/g/devel/message/93262 Mute This Topic: https://groups.io/mt/93506270/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93263+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93263+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484138; cv=none; d=zohomail.com; s=zohoarc; b=DLD5DdHLY2KEO7+C2Q8d0q9CoQO7sivvAV71y9l/i38dz6yUQR84Hvlu7WHPe7II7XSS3hlv1AkTbrLVAXkCi+UAkpXTiBwhilmt2szA0zPB7FECrxynM825re9RfyxZL3D5vhNrOE97ywKPYe/lvqgC1pUOicx5OhZDa3oaUeo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484138; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=T7TZxYoDvUaR4oteTPvBwPEIYN45QUW4zYu1FyxQltM=; b=YOEoGB3N63LotSU3TA54Zhow/YMC/8vK5a2ua3aTuGmXDxA40BiLWc4N0svvxac5vEDLN53/ZlGXyJYhs8tlEMrubzhQ8ha6gnZwCcG/Bi7jiDgzww/Qwwbe+WkWKlEvT+P7W4cjyIsUdOlLDZzv5CUJ6ihhUcAC1yk+81wy+Pk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93263+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484138739508.93406134501765; Tue, 6 Sep 2022 10:08:58 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id wY8UYY1788612xSbB8VXIcRL; Tue, 06 Sep 2022 10:08:58 -0700 X-Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) by mx.groups.io with SMTP id smtpd.web10.1919.1662484137696793086 for ; Tue, 06 Sep 2022 10:08:57 -0700 X-Received: by mail-pf1-f174.google.com with SMTP id 145so12025042pfw.4 for ; Tue, 06 Sep 2022 10:08:57 -0700 (PDT) X-Gm-Message-State: 5qBSFGsxhaTfH8vnjoWNb5PNx1787277AA= X-Google-Smtp-Source: AA6agR7Ic6hT4NedKHMjsJnVgk/sQZnIeEKHj8FE0XAgnn+8cofTvlQzk7S4fj+k9DLtgISTKhb+FA== X-Received: by 2002:a63:f007:0:b0:434:d865:8e5f with SMTP id k7-20020a63f007000000b00434d8658e5fmr774993pgh.314.1662484135526; Tue, 06 Sep 2022 10:08:55 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:08:55 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Date: Tue, 6 Sep 2022 22:38:22 +0530 Message-Id: <20220906170837.491525-3-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484138; bh=r6u+B99mL2HLfYOfg86ulJJS6vRmhKabhsPaTCoVclY=; h=Cc:Date:From:Reply-To:Subject:To; b=WBc1/PZ4y63pH2MLHdZ0RnY4vzt7Lur8oG90EAR1fRrdikrOnc4RUT0BevKlJn055Fs UxK4abJMIxsCwHLHyW0Js/xJEk6rz3J/8UoQEOaGVeBhDz2ACB58fZhnYFNmOs7fIucCJ TeYGJa/f0hTP3oDPMKjMBLnMUsyiI/vZ1Es= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484140964100003 Content-Type: text/plain; charset="utf-8" RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition. Signed-off-by: Sunil V L --- MdePkg/MdePkg.dec | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index f1ebf9e251..3010557bd8 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -1915,6 +1915,12 @@ ## Include/Protocol/ShellDynamicCommand.h gEfiShellDynamicCommandProtocolGuid =3D { 0x3c7200e9, 0x005f, 0x4ea4, {= 0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }} =20 + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid =3D { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x9= 5, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf}} + # # [Error.gEfiMdePkgTokenSpaceGuid] # 0x80000001 | Invalid value provided. --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93263): https://edk2.groups.io/g/devel/message/93263 Mute This Topic: https://groups.io/mt/93506274/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93264+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93264+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484143; cv=none; d=zohomail.com; s=zohoarc; b=a6jtluVWhbWCLP9YswSaon9SJAGieQJTY7lxMe14V41OLLu9q+MWFHqQbqv9OWhF2mw8fp01Ue0ThbZ2HCyMZ+o3lvvpEXRNfdhuJQUYhGkExZyz6mhA0q1+zxdpeBD5RwFcB0A+K0L/wSnfZaqRQjw2ZQC0f8TrjVeD5VN9+JQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484143; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=XFSp90FEdRiJQR4srJ4bEgN210qrDZeNoQmcf/nytjo=; b=i7LU5sqJlxQpWLTXoweJMuuXpMfa72Eu4HINDHWk/hGby6c4e4uqnh3AWzNfGDF0dCtTLk0GAD8sIXEU1NEikOb8UB0cwiReuGJm81iDvoDPmR3TM6Bj97q3ZVfl30enpV3eedhgjpKq3GMmCU/X6BoLczaViQsVMB8tau2LtTc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93264+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484143021506.6035991522367; Tue, 6 Sep 2022 10:09:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PifpYY1788612xOsOtgMfWq7; Tue, 06 Sep 2022 10:09:01 -0700 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web11.1850.1662484140909794611 for ; Tue, 06 Sep 2022 10:09:01 -0700 X-Received: by mail-pf1-f176.google.com with SMTP id q15so11993835pfn.11 for ; Tue, 06 Sep 2022 10:09:00 -0700 (PDT) X-Gm-Message-State: 5pWasYOEPsVLvlIECdcPgyymx1787277AA= X-Google-Smtp-Source: AA6agR5vOAaIj1M1TL8LdrqIkDwIBCbbnyCoO1omMKhMAJFu/qysNUcbW9qyuw31b1BdNRX008zfAA== X-Received: by 2002:a65:67d6:0:b0:430:5c6d:c089 with SMTP id b22-20020a6567d6000000b004305c6dc089mr24796835pgs.245.1662484140141; Tue, 06 Sep 2022 10:09:00 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.08.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:08:59 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h Date: Tue, 6 Sep 2022 22:38:23 +0530 Message-Id: <20220906170837.491525-4-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484141; bh=jv0g6FaNnZ/1skmISPfA81sRyS32RtS4iwW8Il+UL+E=; h=Cc:Date:From:Reply-To:Subject:To; b=ZU9vUTTKQnRQjgoLApCjpSoqUbkssErfTifXOY9mLj7t2ku9vvmP8ihLvKd/27DjxUb s17bidp/pVh5o9st1OnZD3YBHdAsyErq8PqHNXCC1I1od4Xe/ZejPVf7PYAIr8VPhcPOS T8FX9QUyszlDLNAdeq+AxSvZtcJXhNMA5Dw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484144764100003 Content-Type: text/plain; charset="utf-8" RISC-V UEFI platforms need to implement RISCV_EFI_BOOT_PROTOCOL. Add header file with the definitions of this protocol. Signed-off-by: Sunil V L --- MdePkg/Include/Protocol/RiscVBootProtocol.h | 35 +++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h b/MdePkg/Include/P= rotocol/RiscVBootProtocol.h new file mode 100644 index 0000000000..7ceb7d8309 --- /dev/null +++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,35 @@ + +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + Specification available at + https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RIS= CV_UEFI_PROTOCOL-spec.pdf + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _RISCV_BOOT_PROTOCOL_H_ +#define _RISCV_BOOT_PROTOCOL_H_ + +//extern EFI_GUID gRiscVEfiBootProtocolGuid; + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 +#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID) ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93264): https://edk2.groups.io/g/devel/message/93264 Mute This Topic: https://groups.io/mt/93506275/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93265+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93265+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484146; cv=none; d=zohomail.com; s=zohoarc; b=WgeeA0z0vqu4siyfsF7yglq+94+lBU/Na2HIMvn+YI3WHxy9pcionUzbymG8twQhBFHWOgKBE3fjB7tgx0YAdAzgdWTlojc+jc8GBqX4FHchIQKm9dxwjIgMF8Fm291NoZVMj/2hK9CkCHcZhtqQrsa7fInXBZAeb5I5dg+N4nA= ARC-Message-Signature: i=1; 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Tue, 06 Sep 2022 10:09:05 -0700 X-Received: by mail-pf1-f170.google.com with SMTP id x19so12036922pfr.1 for ; Tue, 06 Sep 2022 10:09:05 -0700 (PDT) X-Gm-Message-State: 0bYNziN6aq94ihULv2PqVOOax1787277AA= X-Google-Smtp-Source: AA6agR5sLNIBGVZWIU+Vb3IXA9u01vLLw+n9G50mu7BHGGA6VVZdbPqAjfhK9TVIzvVqukMn+kePgA== X-Received: by 2002:a63:2a49:0:b0:41d:95d8:3d3d with SMTP id q70-20020a632a49000000b0041d95d83d3dmr46669654pgq.43.1662484144594; Tue, 06 Sep 2022 10:09:04 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:04 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Date: Tue, 6 Sep 2022 22:38:24 +0530 Message-Id: <20220906170837.491525-5-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484146; bh=mkOZHgARoXOjQPN1gkB/Xe0OszCRUWI15zkX4SbMSpo=; h=Cc:Date:From:Reply-To:Subject:To; b=BBpxHwK0EyUjTcKjgIArwTeDW9ew1MWhkq/TdIcfz36NZFE9Ez3/N0vvWoJbVFOp8Jo irwLZ3S3JLioB+fNVctzI82OtfLMJHJwZW0v1oey8u6KzLrkKEgmjv4k14iRUzXMkSHp1 pcK7QK8sXQyXWvS9qcwVU2bGCSJcXR1bJLA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484146795100005 Content-Type: text/plain; charset="utf-8" Add few PCD variables for RISC-V platforms to indicate the memory locations of the firmware volumes, temporary RAM etc. Signed-off-by: Sunil V L --- MdeModulePkg/MdeModulePkg.dec | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 7d98910832..557fc2f3d4 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2176,5 +2176,18 @@ # @Prompt 64bit VPD base address. gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64|0x0|UINT64|0x00030006 =20 +[PcdsFixedAtBuild.RISCV64] + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase|0|UINT32|0x50000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvSize|0|UINT32|0x50000001 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase|0|UINT32|0x50000003 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize|0|UINT32|0x50000004 + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase|0|UINT32|0x50000005 + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize|0|UINT32|0x50000006 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x50000= 007 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x50000008 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x50000009 + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT32|0x5000000a + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x5000000b + [UserExtensions.TianoCore."ExtraFiles"] MdeModulePkgExtra.uni --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 718323d904..5e94bde5fe 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -350,6 +350,9 @@ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime = and ACPI NVS type after SmmReadyToLock. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0= x3213210F =20 +[PcdsFixedAtBuild.RISCV64] + gUefiCpuPkgTokenSpaceGuid.PcdRiscVTimerFrequencyInHz|0|UINT32|0x50000000 + [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DA= TA. # @Prompt The pointer to a CPU S3 data buffer. --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93266): https://edk2.groups.io/g/devel/message/93266 Mute This Topic: https://groups.io/mt/93506281/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93267+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93267+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484157; cv=none; d=zohomail.com; s=zohoarc; b=AljRggzy7O8WpkuNW1Ku63DFHdo7JI0sjfPHJPKmqoNcQ2vpB0zCfhgLFphOb+VuyAVGqxTqL1a/wY9LeEuwOCEA/pDdaz21LAnS9WBOVdkhkbc7XVd+dEdCON05RPGGKbDXKSsXt+4Kw6RgQXSqRUeXtvVbCjDLTaxPMZUSQbE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484157; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=EPTAsO9S+lDeHRnfofzwo+Ef9LLR5MpvJlC/6Mj2PRk=; b=gIZf2I1WigMwqAHKYFsg5Wmq7QX+UngAgK2FOkP9LSt6I/jrrC/aCvfCah5nYVH85CGyMTcrbHL2S6W4+sdn0HL3172x4kHyVRPCmjFFB5leb2uBY6/p82Sd+BIJTmbr3jQvToCYYWefettTevhOSwvPKly8UgGpTh/JRcnzOsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93267+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484157774267.8666488322467; Tue, 6 Sep 2022 10:09:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pXoDYY1788612xb4MX4Mi3fI; Tue, 06 Sep 2022 10:09:16 -0700 X-Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) by mx.groups.io with SMTP id smtpd.web08.1929.1662484155893154707 for ; Tue, 06 Sep 2022 10:09:15 -0700 X-Received: by mail-pj1-f47.google.com with SMTP id o2-20020a17090a9f8200b0020025a22208so8416907pjp.2 for ; Tue, 06 Sep 2022 10:09:15 -0700 (PDT) X-Gm-Message-State: vy2ozeJh7NQBUHO7VqoQs4Hpx1787277AA= X-Google-Smtp-Source: AA6agR7pTHoWuXPL8wO0PDBjfMDf4MDU4OV5Nr9/DagduSsoMGhLQ2Y4Mk/xhKPAxe6OyEVMfTB9xQ== X-Received: by 2002:a17:903:245:b0:172:bf22:fc5 with SMTP id j5-20020a170903024500b00172bf220fc5mr55371089plh.101.1662484155138; Tue, 06 Sep 2022 10:09:15 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:13 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Date: Tue, 6 Sep 2022 22:38:26 +0530 Message-Id: <20220906170837.491525-7-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484156; bh=0hfH1U+L7CDDRQNge5b+sMdk6qmTuRQcC5CrmQfbWvE=; h=Cc:Date:From:Reply-To:Subject:To; b=UbJ8TjlahM8U0lhdEU6UV+CwsEkIuA1djs/4nS1SPd9BwGwl/KiFwEevdE7k0R82Pk9 x9huBocEjCvdtUdUDKnmbTsHCrrZ/ryp79atXWHjS06MWZHyzqnFMsN12Bq2HKpvd5cVR dHyo22UoZSqb+QaTgGW1ITyR6YESpEsWaNY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484158873100003 Content-Type: text/plain; charset="utf-8" EDK2 in S-mode needs to use SSCRATCH register. Implement functions to set/get the SSCRATCH register. Signed-off-by: Sunil V L --- MdePkg/Include/Library/BaseLib.h | 10 ++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuGen.S diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index a6f9a194ef..a742de61a4 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -150,6 +150,16 @@ typedef struct { =20 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 =20 +VOID +RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) =20 // diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 6be5be9428..5429329e39 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,7 @@ RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuGen.S | GCC =20 [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseL= ib/RiscV64/CpuGen.S new file mode 100644 index 0000000000..d11929cf32 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------ +// +// Generic CPU related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ + +#include +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93267): https://edk2.groups.io/g/devel/message/93267 Mute This Topic: https://groups.io/mt/93506283/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93268+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93268+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484162; cv=none; d=zohomail.com; s=zohoarc; b=NncWy1nNgaFcHiUBdUdSqT7FjzvRFv11YI1iC3b3SzUNq2T+BNmmvj7TARLrEmz060zfzmHP1NU7+KCl2YOu34VrrzIDYwrsJike/GICh6MuUYVDIt4EiEWoZ1z4TusyaCVOlNTXLIVBNRKX3b9L+v3QTJIqh8DeEha3p2p7hMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484162; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xINEfUU9lNBYB5fco4Dq0/Ud8p0+KB/MogEjMERLMbc=; b=MQN19WuRlr1BlPsVUKMOs3bR8PIO7IHPFCnQj5YFHd6kwSwHOQV0kFw1HMGNiU70Ebt8mBo6pfafC+s7vQeg5hmZ1JDrZxSrwj8m7tEkB2lGFULoYloGD/hlpW+rE8ktvDptbU2RvIgrtS3poGfkH9Kzva5FJIK9/MvTK0k0+uQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93268+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484162949712.6309050129479; Tue, 6 Sep 2022 10:09:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gtq3YY1788612xyeKmAozQey; Tue, 06 Sep 2022 10:09:21 -0700 X-Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) by mx.groups.io with SMTP id smtpd.web11.1854.1662484160753503252 for ; Tue, 06 Sep 2022 10:09:20 -0700 X-Received: by mail-pj1-f54.google.com with SMTP id x1-20020a17090ab00100b001fda21bbc90so15634556pjq.3 for ; Tue, 06 Sep 2022 10:09:20 -0700 (PDT) X-Gm-Message-State: 58YtFwnDsbAVBLVk4EI0SRorx1787277AA= X-Google-Smtp-Source: AA6agR76yMvpmkFs8pEblp04akOeqepxl54Zj0OKzFsQSaPfgdwnns7uWDK1mAN9l2m+tO7ouOGnQg== X-Received: by 2002:a17:90a:8911:b0:1fa:c8f7:1450 with SMTP id u17-20020a17090a891100b001fac8f71450mr25059932pjn.123.1662484159931; Tue, 06 Sep 2022 10:09:19 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:19 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library Date: Tue, 6 Sep 2022 22:38:27 +0530 Message-Id: <20220906170837.491525-8-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484161; bh=v4ATtwQe/NAPm030QgEbVVLHgq8qJmCKh1tmpphB5Xs=; h=Cc:Date:From:Reply-To:Subject:To; b=wmPhRsKhyR+coMEWgUCM+zxuD2gKGYtqnZ5PcHJ/DRbmqq35YNgGELMHdG0W7E38NCO 2c1PvWz/mE2790OpXuLvKr4SmF/RBK9PxMg1gYSt8cve/0yy61XadekisZk7mdxwMrhbs X8sDimFTNxkf9mM09+OULIm+1iYdaI+bK2A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484164996100003 Content-Type: text/plain; charset="utf-8" This library implements the TimerLib.h functionality. This library is similar to CpuTimerLib but needs the library constructor. Signed-off-by: Sunil V L --- MdePkg/Library/ArchTimerLib/ArchTimerLib.inf | 40 +++ MdePkg/Library/ArchTimerLib/ArchTimerLib.uni | 14 + .../ArchTimerLib/RiscV64/CpuTimerLib.c | 299 ++++++++++++++++++ 3 files changed, 353 insertions(+) create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.inf create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.uni create mode 100644 MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c diff --git a/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf b/MdePkg/Library/= ArchTimerLib/ArchTimerLib.inf new file mode 100644 index 0000000000..b61ae58d01 --- /dev/null +++ b/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf @@ -0,0 +1,40 @@ +## @file +# Timer Library Instance which needs a constructor for the architecture. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
+# Copyright (c) 2022, Ventana Micro System Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D ArchTimerLib + FILE_GUID =3D D3CF51A9-1CEA-4776-A8AB-CCFD14D7DAAF + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + MODULE_UNI_FILE =3D ArchTimerLib.uni + CONSTRUCTOR =3D ArchTimerLibConstructor + +[Sources.RISCV64] + RiscV64/CpuTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + FdtLib + HobLib + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdRiscVTimerFrequencyInHz ## CONSUMES + +[Guids] + gFdtHobGuid diff --git a/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni b/MdePkg/Library/= ArchTimerLib/ArchTimerLib.uni new file mode 100644 index 0000000000..1c900bea42 --- /dev/null +++ b/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni @@ -0,0 +1,14 @@ +// /** @file +// Base CPU Timer Library +// +// Provides basic timer support using architecture specific methods. +// +// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library" + +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti= mer support using architecture specific methods" diff --git a/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c b/MdePkg/Lib= rary/ArchTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 0000000000..a81ac8c37c --- /dev/null +++ b/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,299 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +STATIC UINT32 mTimeBaseFrequency; +STATIC BOOLEAN mTimeBaseFreqInitialized; + +UINT32 +InternalGetTimerFrequency( + VOID + ) +{ + return mTimeBaseFrequency; +} + + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks =3D csr_read(CSR_TIME) + Delay; + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - csr_read(CSR_TIME)) & (1 << (RISCV_TIMER_COMPARE_BITS= - 1))) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + InternalGetTimerFrequency() + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + InternalGetTimerFrequency() + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)csr_read (CSR_TIME); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 32 - 1; + } + + return InternalGetTimerFrequency(); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, InternalGetTimerF= requency(), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder = * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u),= InternalGetTimerFrequency()); + + return NanoSeconds; +} + +STATIC +RETURN_STATUS +EFIAPI +FdtInitializeTimerFrequency ( + VOID + ) +{ + VOID *Hob; + VOID *Fdt; + INT32 CpusNode, Len; + const fdt32_t *Prop; + + Hob =3D GetFirstGuidHob (&gFdtHobGuid); + if ((Hob =3D=3D NULL) || (GET_GUID_HOB_DATA_SIZE (Hob) !=3D sizeof (UINT= 64))) { + DEBUG ((DEBUG_ERROR, "%a: No FDT Hob found\n", __FUNCTION__)); + return EFI_NOT_FOUND; + } + + Fdt =3D (VOID *)(UINTN)*(UINT64 *)GET_GUID_HOB_DATA (Hob); + + if (fdt_check_header (Fdt) !=3D 0) { + DEBUG (( + DEBUG_ERROR, + "%a: No DTB found @ 0x%p\n", + __FUNCTION__, + Fdt + )); + return EFI_NOT_FOUND; + } + + // The "cpus" node resides at the the root of the DT. Fetch it. + CpusNode =3D fdt_path_offset (Fdt, "/cpus"); + if (CpusNode < 0) { + DEBUG ((DEBUG_ERROR, "%a: Invalid /cpus node\n", __FUNCTION__)); + return EFI_NOT_FOUND; + } + + Prop =3D fdt_getprop((void *)Fdt, CpusNode, "timebase-frequency", &Len); + if (!Prop) { + DEBUG ((DEBUG_ERROR, "%a: timebase-frequency propertynot found\n", __F= UNCTION__)); + return EFI_NOT_FOUND; + } + + mTimeBaseFrequency =3D fdt32_to_cpu(*Prop); + DEBUG((DEBUG_INFO, "%a: Timer Frequency (DT) is set to 0x%x\n", __FUNCTI= ON__, mTimeBaseFrequency)); + + return EFI_SUCCESS; +} +/** + Initializes the Timer Frequency by reading it from the DTB + +**/ +RETURN_STATUS +EFIAPI +ArchTimerLibConstructor ( + VOID + ) +{ + EFI_STATUS Status; + + /* + * Initialize only once + */ + if (mTimeBaseFreqInitialized) { + return EFI_SUCCESS; + } + + mTimeBaseFreqInitialized =3D 1; + + Status =3D FdtInitializeTimerFrequency(); + + if (EFI_ERROR(Status)) { + mTimeBaseFrequency =3D PcdGet32 (PcdRiscVTimerFrequencyInHz); + DEBUG((DEBUG_INFO, "%a: Timer Frequency (PCD) is set to 0x%x\n", __FUN= CTION__, mTimeBaseFrequency)); + } + + return EFI_SUCCESS; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93268): https://edk2.groups.io/g/devel/message/93268 Mute This Topic: https://groups.io/mt/93506285/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93269+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93269+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484168; cv=none; d=zohomail.com; s=zohoarc; b=jgjLUVUUskxfqgBYA1eHo1VHVwrd6poKucZQs6vWWaBvt293u0+AO4sj/4OLfSC6EYXQa0orStz5bxPlvR5+tfFt6ZZjQTKK3RpIpHuUCowjcMyBa3y4U4ab3Q/e4/kcE1+szSwsOrH8PQRnUzeAK8BPtNQUpos6uMpA2f/XUPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484168; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KQ0y+QvcuXKKwlJv5ovEEjR5M4jgyHE+qs1dEL2f8b8=; b=k2UMWBPjBajzy1mfDpGU0h+VTknpo2f0qCOsVxVsnnq08SR2gAob1/zZ8ZRKRvqmLHia/iIqXITi8KE6Sc9T7jaQarKjykCtEbHIL0SEYEjZolz4jKi7tBh2Dof4c4yePQ+fWLgT3jH7VVHjmlxk1adu3pqrUExac48sUbWV8Ok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93269+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166248416817243.0098733129588; Tue, 6 Sep 2022 10:09:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gL2oYY1788612xEXgvZ5cAaU; Tue, 06 Sep 2022 10:09:26 -0700 X-Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) by mx.groups.io with SMTP id smtpd.web08.1930.1662484166158039579 for ; Tue, 06 Sep 2022 10:09:26 -0700 X-Received: by mail-pg1-f181.google.com with SMTP id w63so2730790pgb.7 for ; Tue, 06 Sep 2022 10:09:26 -0700 (PDT) X-Gm-Message-State: sWTNLC1hDwLH3Idj57X779F0x1787277AA= X-Google-Smtp-Source: AA6agR4pDnfTIq7U93wkd6bqItjZMyC35/CPf2FVAclBpTJhBpHe7w5pVAjRJrvzTKNssWE2HCCu0w== X-Received: by 2002:a63:1a16:0:b0:430:581d:827f with SMTP id a22-20020a631a16000000b00430581d827fmr25920018pga.276.1662484165157; Tue, 06 Sep 2022 10:09:25 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:24 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V Date: Tue, 6 Sep 2022 22:38:28 +0530 Message-Id: <20220906170837.491525-9-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484166; bh=jpHxhP8BYJEyOGSEMURmK8kCqkddE6gLv3mwsFFD9A4=; h=Cc:Date:From:Reply-To:Subject:To; b=NQdjBf96j6GAmyCMZfVcvh8V99LTxFl31LEuhqW3/eSngbqD7NreLrdvmmyd36ZM+BF yhH1Qy9f1coMC52FBGXB2pKsYnxvfXnb4PLIY5Xz2fNYGzSSzsIPDKTs4+4qCcRNBYHp9 HKgIzZFXcktMiL9wkR8T9RpTbF4o8V2jSz0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484168955100003 Content-Type: text/plain; charset="utf-8" This library is required to make SBI ecalls from the S-mode EDK2. Signed-off-by: Sunil V L --- MdePkg/Include/Library/RiscVSbiLib.h | 129 ++++++++++++ MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c | 228 +++++++++++++++++++++ MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf | 28 +++ 3 files changed, 385 insertions(+) create mode 100644 MdePkg/Include/Library/RiscVSbiLib.h create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf diff --git a/MdePkg/Include/Library/RiscVSbiLib.h b/MdePkg/Include/Library/= RiscVSbiLib.h new file mode 100644 index 0000000000..e94adb08fd --- /dev/null +++ b/MdePkg/Include/Library/RiscVSbiLib.h @@ -0,0 +1,129 @@ +/** @file + Library to call the RISC-V SBI ecalls + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Glossary: + - Hart - Hardware Thread, similar to a CPU core + + Currently, EDK2 needs to call SBI only to set the time and to do system = reset. + +**/ + +#ifndef RISCV_SBI_LIB_H_ +#define RISCV_SBI_LIB_H_ + +#include + +/* SBI Extension IDs */ +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 + +/* SBI function IDs for TIME extension*/ +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for SRST extension */ +#define SBI_EXT_SRST_RESET 0x0 + +#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0 +#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1 +#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2 +#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT + +#define SBI_SRST_RESET_REASON_NONE 0x0 +#define SBI_SRST_RESET_REASON_SYSFAIL 0x1 + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI Service table + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree +} EFI_RISCV_FIRMWARE_CONTEXT; + + +// +// EDK2 OpenSBI firmware extension return status. +// +typedef struct { + UINTN Error; ///< SBI status code + UINTN Value; ///< Value returned +} SBI_RET; + +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ); + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ); + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ); + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ); + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ); + +/** + Set pointer to OpenSBI Firmware Context + + Set the pointer of firmware context. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ); + +#endif diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c b/MdePkg/Library/Risc= VSbiLib/RiscVSbiLib.c new file mode 100644 index 0000000000..39cc6628be --- /dev/null +++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c @@ -0,0 +1,228 @@ +/** @file + Instance of the SBI ecall library. + + It allows calling an SBI function via an ecall from S-Mode. + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +// +// Maximum arguments for SBI ecall +// It's possible to pass more but no SBI call uses more as of SBI 0.2. +// The additional arguments would have to be passed on the stack instead o= f as +// registers, like it's done now. +// +#define SBI_CALL_MAX_ARGS 6 + +/** + Call SBI call using ecall instruction. + + Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS. + + @param[in] ExtId SBI extension ID. + @param[in] FuncId SBI function ID. + @param[in] NumArgs Number of arguments to pass to the ecall. + @param[in] ... Argument list for the ecall. + + @retval Returns SBI_RET structure with value and error code. + +**/ +STATIC +SBI_RET +EFIAPI +SbiCall ( + IN UINTN ExtId, + IN UINTN FuncId, + IN UINTN NumArgs, + ... + ) +{ + UINTN I; + SBI_RET Ret; + UINTN Args[SBI_CALL_MAX_ARGS]; + VA_LIST ArgList; + + VA_START (ArgList, NumArgs); + + ASSERT (NumArgs <=3D SBI_CALL_MAX_ARGS); + + for (I =3D 0; I < SBI_CALL_MAX_ARGS; I++) { + if (I < NumArgs) { + Args[I] =3D VA_ARG (ArgList, UINTN); + } else { + // Default to 0 for all arguments that are not given + Args[I] =3D 0; + } + } + + VA_END (ArgList); + + register UINTN a0 asm ("a0") =3D Args[0]; + register UINTN a1 asm ("a1") =3D Args[1]; + register UINTN a2 asm ("a2") =3D Args[2]; + register UINTN a3 asm ("a3") =3D Args[3]; + register UINTN a4 asm ("a4") =3D Args[4]; + register UINTN a5 asm ("a5") =3D Args[5]; + register UINTN a6 asm ("a6") =3D (UINTN)(FuncId); + register UINTN a7 asm ("a7") =3D (UINTN)(ExtId); + + asm volatile ("ecall" \ + : "+r" (a0), "+r" (a1) \ + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \ + : "memory"); \ + Ret.Error =3D a0; + Ret.Value =3D a1; + return Ret; +} + +/** + Translate SBI error code to EFI status. + + @param[in] SbiError SBI error code + @retval EFI_STATUS +**/ +STATIC +EFI_STATUS +EFIAPI +TranslateError ( + IN UINTN SbiError + ) +{ + switch (SbiError) { + case SBI_SUCCESS: + return EFI_SUCCESS; + case SBI_ERR_FAILED: + return EFI_DEVICE_ERROR; + break; + case SBI_ERR_NOT_SUPPORTED: + return EFI_UNSUPPORTED; + break; + case SBI_ERR_INVALID_PARAM: + return EFI_INVALID_PARAMETER; + break; + case SBI_ERR_DENIED: + return EFI_ACCESS_DENIED; + break; + case SBI_ERR_INVALID_ADDRESS: + return EFI_LOAD_ERROR; + break; + case SBI_ERR_ALREADY_AVAILABLE: + return EFI_ALREADY_STARTED; + break; + default: + // + // Reaches here only if SBI has defined a new error type + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + break; + } +} + +/** + Clear pending timer interrupt bit and set timer for next event after Tim= e. + + To clear the timer without scheduling a timer event, set Time to a + practically infinite value or mask the timer interrupt by clearing sie.S= TIE. + + @param[in] Time The time offset to the next scheduled t= imer interrupt. +**/ +VOID +EFIAPI +SbiSetTimer ( + IN UINT64 Time + ) +{ + SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time); +} + +EFI_STATUS +EFIAPI +SbiSystemReset ( + IN UINTN ResetType, + IN UINTN ResetReason + ) +{ + SBI_RET Ret; + + Ret =3D SbiCall ( + SBI_EXT_SRST, + SBI_EXT_SRST_RESET, + 2, + ResetType, + ResetReason + ); + + return TranslateError (Ret.Error); +} + +/** + Get firmware context of the calling hart. + + @param[out] FirmwareContext The firmware context pointer. + @retval EFI_SUCCESS The operation succeeds. +**/ +VOID +EFIAPI +GetFirmwareContext ( + OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext + ) +{ + *FirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT *)csr_read(CSR_SSCRATCH= ); +} + +/** + Set firmware context of the calling hart. + + @param[in] FirmwareContext The firmware context pointer. +**/ +VOID +EFIAPI +SetFirmwareContext ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + csr_write(CSR_SSCRATCH, FirmwareContext); +} + +/** + Get pointer to OpenSBI Firmware Context + + Get the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to retrieve pointer to the + Firmware Context. +**/ +VOID +EFIAPI +GetFirmwareContextPointer ( + IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr + ) +{ + GetFirmwareContext (FirmwareContextPtr); +} + +/** + Set the pointer to OpenSBI Firmware Context + + Set the pointer of firmware context through OpenSBI FW Extension SBI. + + @param FirmwareContextPtr Pointer to Firmware Context. +**/ +VOID +EFIAPI +SetFirmwareContextPointer ( + IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr + ) +{ + SetFirmwareContext (FirmwareContextPtr); +} diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf b/MdePkg/Library/Ri= scVSbiLib/RiscVSbiLib.inf new file mode 100644 index 0000000000..b01f909300 --- /dev/null +++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf @@ -0,0 +1,28 @@ +## @file +# RISC-V Library to call SBI ecalls +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVSbiLib + FILE_GUID =3D D742CF3D-E600-4009-8FB5-318073008508 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVSbiLib + +[Sources] + RiscVSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93269): https://edk2.groups.io/g/devel/message/93269 Mute This Topic: https://groups.io/mt/93506288/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93270+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93270+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484171; cv=none; d=zohomail.com; s=zohoarc; b=dB+sO0zCC4K9gOZCtS8awjEZ9I2TBeKsSkelzJge1ZD6CerCrIbrIRLMF9Z1mIcu5V7OwFTX5NoVsyIptB5b7J36PQ99orb0AcntYeYVjdBt9D2PTGgCrroDb9pNJeQVn4Uf/lwaFGX/An2g7jFh2UcTvF8uQGj/ZXUAjIq8WB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484171; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tK59MgXw1eu4byaXbAdJO5zGhuSQKfjAx/Zy1LmXS9k=; b=KWhvJYuz4NlhhiMsDSVdQg/24FBK8bjwCMlxSPvPzuAvEJyua6ejlf+e9ouBVyhvzqNVzDqdnHY3rLompXYZOZ2YKgEGDXEnJx++k6Nliwgwv39gtAUnZY7AoZRIFX6QaG/q76qwu9LNc31/KkQOwlNM2hZZSYWTRk/qc+z0wsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93270+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484171677698.7453249989303; Tue, 6 Sep 2022 10:09:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1nuYYY1788612xptuV7c3EEN; Tue, 06 Sep 2022 10:09:31 -0700 X-Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) by mx.groups.io with SMTP id smtpd.web09.1945.1662484170667681449 for ; Tue, 06 Sep 2022 10:09:30 -0700 X-Received: by mail-pl1-f181.google.com with SMTP id 9so8704568plj.11 for ; Tue, 06 Sep 2022 10:09:30 -0700 (PDT) X-Gm-Message-State: 9NPi6gnhCwBba4ujVcvDrRsIx1787277AA= X-Google-Smtp-Source: AA6agR5SxhNO0EqxNQlj2EHx4rKzQcd5Qvsez3qevlTwJFYvVz1BByVaI4jxVrv5gHcQqKBNZb0M1g== X-Received: by 2002:a17:90b:4f91:b0:1cd:3a73:3a5d with SMTP id qe17-20020a17090b4f9100b001cd3a733a5dmr19643697pjb.98.1662484170049; Tue, 06 Sep 2022 10:09:30 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:29 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures Date: Tue, 6 Sep 2022 22:38:29 +0530 Message-Id: <20220906170837.491525-10-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484171; bh=31snF4Pr9YVm4zGQjvn7GljYYslIjYnOGRfZ/+MOjeE=; h=Cc:Date:From:Reply-To:Subject:To; b=W+a40JvTUUsnFzEj1TbIp+sJgwa51F7uaYdNrvo8MPQE6ZkmH+nhGAd4nywKbZS6BWC qHmoSvT/kp6KzpqjoojLpUE0NUZTRGDOgfI9dmtpPx04iGFk+PnMsaRAF96ZY+T0OgpBb BRy4TkWIyNQVaSCWGGFnR2Nw5KhOn4Ruu98= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484173081100003 Content-Type: text/plain; charset="utf-8" Currently the common sources mean x86 only in this library. To add support for other architectures like RISC-V, we need to build these files only for x86. Signed-off-by: Sunil V L --- .../CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index e7a81bebdb..bf33d54bae 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -32,7 +32,7 @@ X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h =20 -[Sources.common] +[Sources.IA32, Sources.X64] CpuExceptionCommon.h CpuExceptionCommon.c PeiDxeSmmCpuException.c @@ -56,8 +56,10 @@ SerialPortLib PrintLib SynchronizationLib - LocalApicLib PeCoffGetEntryPointLib MemoryAllocationLib DebugLib + +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib VmgExitLib --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93270): https://edk2.groups.io/g/devel/message/93270 Mute This Topic: https://groups.io/mt/93506290/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93271+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93271+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484177; cv=none; d=zohomail.com; s=zohoarc; b=fJ9kf9zM3UpK6g2HIa4GP0XyLl69mBJRqOmjMpzsonh2df51XQF52L/qkmWJF4iSl/TZO7mtFDtAS7QntUotCdTGnFHTX55M7hUqq81n5C1bPs3JE8NdoeKMtuexvcavX9f42Y7JDhD/8VtJSHcXW6u9n8wPDPHGGya/dauTNos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484177; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1a4VZpLn44epm5iy/sE7fn8Hnen5zx+l2E2ifiSxiIo=; b=PQ6BVBWjtBK/j/IsPTRsAwh018GXf07k1lqGens9oHqPw7jhgm7agUW8OEW6DbGWxJQfX0F3Y0OKNKZJxdRy9Tr86JUmq7VezCOph4WxsqYm0zw9AQVeMKSSoDzm6oX6lmdHhcCvTHnwgyupA0E0H7aWe6ziIOvftvZLPcE+wNQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93271+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166248417769940.987696589583834; Tue, 6 Sep 2022 10:09:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eudWYY1788612xng4r07XmF1; Tue, 06 Sep 2022 10:09:36 -0700 X-Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) by mx.groups.io with SMTP id smtpd.web09.1945.1662484170667681449 for ; Tue, 06 Sep 2022 10:09:35 -0700 X-Received: by mail-pl1-f181.google.com with SMTP id 9so8704788plj.11 for ; Tue, 06 Sep 2022 10:09:35 -0700 (PDT) X-Gm-Message-State: ndwujpUMKKZHkDU0l597R13Qx1787277AA= X-Google-Smtp-Source: AA6agR4etZes6zRJHzfhUQEgYBTyKF0EaNPMmEMvzkrIyrpqxIZO8uXBbDAvjwaNpX7+Qa5v6SHVsA== X-Received: by 2002:a17:902:e5c3:b0:176:d1b9:ee33 with SMTP id u3-20020a170902e5c300b00176d1b9ee33mr3947025plf.122.1662484174870; Tue, 06 Sep 2022 10:09:34 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:34 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Date: Tue, 6 Sep 2022 22:38:30 +0530 Message-Id: <20220906170837.491525-11-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484176; bh=VmxBlw2ede3Mm+VmiQl/lCby80iFZQjPCDgOfrLlMQk=; h=Cc:Date:From:Reply-To:Subject:To; b=j/jTV+z1C3sYJXpbjFk+IwzPNv5X8krWUvVQozoJABsBrNtQpqU+CGO6l6Z4taVrHL3 yxNYLUIWAjII5TRd2zHr8EWwGMdmydcZfv2V69KNu4oE4qLCTYoR6VlrAjXXlBhST01/a 8r869pZdfMNGLFIyCA7m1C/JATRfWqKo6sw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484179249100003 Content-Type: text/plain; charset="utf-8" Add low level interfaces to register exception and interrupt handlers for RISC-V. Signed-off-by: Sunil V L --- .../DxeCpuExceptionHandlerLib.inf | 7 +- .../RiscV64/CpuExceptionHandlerLib.c | 136 ++++++++++++++++++ .../RiscV64/CpuExceptionHandlerLib.h | 112 +++++++++++++++ .../RiscV64/SupervisorTrapHandler.S | 105 ++++++++++++++ 4 files changed, 359 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuEx= ceptionHandlerLib.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuEx= ceptionHandlerLib.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/Super= visorTrapHandler.S diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index bf33d54bae..8570b83e8a 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -18,7 +18,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.Ia32] @@ -38,6 +38,11 @@ PeiDxeSmmCpuException.c DxeException.c =20 +[Sources.RISCV64] + RiscV64/SupervisorTrapHandler.S + RiscV64/CpuExceptionHandlerLib.c + RiscV64/CpuExceptionHandlerLib.h + [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.c new file mode 100644 index 0000000000..f4427599a6 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.c @@ -0,0 +1,136 @@ +/** @file + RISC-V Exception Handler library implementation. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "CpuExceptionHandlerLib.h" + +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; + +/** + Initializes all CPU exceptions entries and provides the default exceptio= n handlers. + + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + csr_write (CSR_STVEC, SupervisorModeTrap); + return EFI_SUCCESS; +} + + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHa= ndler for a processor + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled. + The installed handler is called once for each processor interrupt or exc= eption. + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned. + + @param[in] InterruptType Defines which interrupt or exception to ho= ok. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called + when a processor interrupt occurs. If this= parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler)); + mInterruptHandlers[InterruptType] =3D InterruptHandler; + return EFI_SUCCESS; +} + + +/** + Setup separate stacks for certain exception handlers. + If the input Buffer and BufferSize are both NULL, use global variable if= possible. + + @param[in] Buffer Point to buffer used to separate exceptio= n stack. + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer. + If the size is not enough, the return sta= tus will + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize + will be the size it needs. + + @retval EFI_SUCCESS The stacks are assigned successfully. + @retval EFI_UNSUPPORTED This function is not supported. + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small. +**/ +EFI_STATUS +EFIAPI +InitializeSeparateExceptionStacks ( + IN VOID *Buffer, + IN OUT UINTN *BufferSize + ) +{ + return EFI_SUCCESS; +} + +/** + Supervisor mode trap handler. + + @param[in] SmodeTrapReg Registers before trap occurred. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + SMODE_TRAP_REGISTERS *SmodeTrapReg + ) +{ + UINTN SCause; + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg; + // + // Check scasue register. + // + SCause =3D (UINTN)csr_read (CSR_SCAUSE); + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) { + // + // This is interrupt event. + // + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1)); + if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) { + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext); + } + } +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.h new file mode 100644 index 0000000000..1cc6dbe734 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.h @@ -0,0 +1,112 @@ +/** @file + + RISC-V Exception Handler library definition file. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_ +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_ + +#include +#include +extern void +SupervisorModeTrap ( + void + ); + +// +// Index of SMode trap register +// +#define SMODE_TRAP_REGS_zero 0 +#define SMODE_TRAP_REGS_ra 1 +#define SMODE_TRAP_REGS_sp 2 +#define SMODE_TRAP_REGS_gp 3 +#define SMODE_TRAP_REGS_tp 4 +#define SMODE_TRAP_REGS_t0 5 +#define SMODE_TRAP_REGS_t1 6 +#define SMODE_TRAP_REGS_t2 7 +#define SMODE_TRAP_REGS_s0 8 +#define SMODE_TRAP_REGS_s1 9 +#define SMODE_TRAP_REGS_a0 10 +#define SMODE_TRAP_REGS_a1 11 +#define SMODE_TRAP_REGS_a2 12 +#define SMODE_TRAP_REGS_a3 13 +#define SMODE_TRAP_REGS_a4 14 +#define SMODE_TRAP_REGS_a5 15 +#define SMODE_TRAP_REGS_a6 16 +#define SMODE_TRAP_REGS_a7 17 +#define SMODE_TRAP_REGS_s2 18 +#define SMODE_TRAP_REGS_s3 19 +#define SMODE_TRAP_REGS_s4 20 +#define SMODE_TRAP_REGS_s5 21 +#define SMODE_TRAP_REGS_s6 22 +#define SMODE_TRAP_REGS_s7 23 +#define SMODE_TRAP_REGS_s8 24 +#define SMODE_TRAP_REGS_s9 25 +#define SMODE_TRAP_REGS_s10 26 +#define SMODE_TRAP_REGS_s11 27 +#define SMODE_TRAP_REGS_t3 28 +#define SMODE_TRAP_REGS_t4 29 +#define SMODE_TRAP_REGS_t5 30 +#define SMODE_TRAP_REGS_t6 31 +#define SMODE_TRAP_REGS_sepc 32 +#define SMODE_TRAP_REGS_sstatus 33 +#define SMODE_TRAP_REGS_sie 34 +#define SMODE_TRAP_REGS_last 35 + +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__) +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last) + +#pragma pack(1) +typedef struct { + // + // Below are follow the format of EFI_SYSTEM_CONTEXT + // + UINT64 zero; + UINT64 ra; + UINT64 sp; + UINT64 gp; + UINT64 tp; + UINT64 t0; + UINT64 t1; + UINT64 t2; + UINT64 s0; + UINT64 s1; + UINT64 a0; + UINT64 a1; + UINT64 a2; + UINT64 a3; + UINT64 a4; + UINT64 a5; + UINT64 a6; + UINT64 a7; + UINT64 s2; + UINT64 s3; + UINT64 s4; + UINT64 s5; + UINT64 s6; + UINT64 s7; + UINT64 s8; + UINT64 s9; + UINT64 s10; + UINT64 s11; + UINT64 t3; + UINT64 t4; + UINT64 t5; + UINT64 t6; + // + // Below are the additional information to + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap + // and not public to EFI environment. + // + UINT64 sepc; + UINT64 sstatus; + UINT64 sie; +} SMODE_TRAP_REGISTERS; +#pragma pack() + +#endif diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTr= apHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorT= rapHandler.S new file mode 100644 index 0000000000..649c4c5bec --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandl= er.S @@ -0,0 +1,105 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "CpuExceptionHandlerLib.h" + + .align 3 + .section .entry, "ax", %progbits + .globl SupervisorModeTrap +SupervisorModeTrap: + addi sp, sp, -SMODE_TRAP_REGS_SIZE + + /* Save all general regisers except SP */ + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + csrr t0, CSR_SSTATUS + and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE) + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + csrr t0, CSR_SEPC + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrr t0, CSR_SIE + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP */ + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp) + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp) + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp) + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp) + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp) + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp) + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp) + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp) + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp) + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp) + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp) + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp) + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp) + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp) + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp) + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp) + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp) + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp) + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp) + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp) + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp) + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp) + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp) + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp) + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp) + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp) + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp) + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp) + + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp) + csrw CSR_SEPC, t0 + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp) + csrw CSR_SIE, t0 + csrr t0, CSR_SSTATUS + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp) + or t0, t0, t1 + csrw CSR_SSTATUS, t0 + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp) + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp) + addi sp, sp, SMODE_TRAP_REGS_SIZE + sret --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93271): https://edk2.groups.io/g/devel/message/93271 Mute This Topic: https://groups.io/mt/93506294/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93272+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93272+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484182; cv=none; d=zohomail.com; s=zohoarc; b=fI0Bh718WceaVcyxFJ2Zj39uPdrZdVev5sSLySxX2hTN/W2Qs9PslcIlQBvYXKjBxL2nNlMFcoEfhxwYxN2Ss21AYbQp8gcpQ05knew/RmU86BRzZhpE5+wV3zEXaxaf3H8vTyQf3FF6dfBXlecH0U0wKyf2er0umkW0z4I6CXk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484182; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=l8aHJsBDsNoqwRf39TFUz0uDRQpP6Fnf/NuxjALIjcE=; b=XEdkFRSX7erpKpukW1kHDCE5eviVvLtxC4EvQURu18p64mHxgAGdm8GC3vtlptgJMhFDbt6ZdGLo/GXsxyG7NMm0DPHr9LzjO/Wy/PepojQy1eLy2fnhfNvIINASwArY6A+xToR/1YtoPho7kDS7jOsTBEVrNuTRZjn18uCZ/08= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93272+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484182613185.3224747549151; Tue, 6 Sep 2022 10:09:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5PajYY1788612xrqna4pOdg5; Tue, 06 Sep 2022 10:09:42 -0700 X-Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mx.groups.io with SMTP id smtpd.web08.1934.1662484181498725806 for ; Tue, 06 Sep 2022 10:09:41 -0700 X-Received: by mail-pg1-f169.google.com with SMTP id v4so11174212pgi.10 for ; Tue, 06 Sep 2022 10:09:41 -0700 (PDT) X-Gm-Message-State: WC9YrgpeuNe6WIT81hBYt953x1787277AA= X-Google-Smtp-Source: AA6agR6EpoKH6fWSwgTkmdNm54uANp8zUImysl+pT7862rWnreqEL/rzekl9q1bZUenObvXY8f8oBA== X-Received: by 2002:a05:6a00:1586:b0:537:f5f:11d0 with SMTP id u6-20020a056a00158600b005370f5f11d0mr57049325pfk.64.1662484180378; Tue, 06 Sep 2022 10:09:40 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:39 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library Date: Tue, 6 Sep 2022 22:38:31 +0530 Message-Id: <20220906170837.491525-12-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484182; bh=vY25gXJpTJ6TeJTb4TWJtLY41iUTffJ0dux0D674iC0=; h=Cc:Date:From:Reply-To:Subject:To; b=WtVdB3Nfc6ikhA2v/ccLY8/ZR8dVwqY9FsQKV++vGrbLWZCTn0wPGvSKNWUxfP90Lx2 +o4dK5CCp4rTM8MHorWEwanqVLwhkTTAtZLCmWOroK/MiZNhuUGWaHg5oa6IPyLh+guDs Nd+/hTKTPYZQtVVfDiuYDB9BPlmibC/CzzI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484183143100001 Content-Type: text/plain; charset="utf-8" This library implements system reset interfaces like cold reboot, warm reboot etc. On RISC-V platforms, these are implemented using SBI calls. Signed-off-by: Sunil V L --- .../Library/ResetSystemLib/ResetSystemLib.inf | 35 +++++ .../ResetSystemLib/RiscV64/ResetSystemLib.c | 128 ++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 MdePkg/Library/ResetSystemLib/ResetSystemLib.inf create mode 100644 MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c diff --git a/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf b/MdePkg/Libr= ary/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 0000000000..7c8a7d1142 --- /dev/null +++ b/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,35 @@ +## @file +# Library instance for ResetSystem library class +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ResetSystemLib + FILE_GUID =3D 425DC96A-BF26-4684-90F9-1B5FF43BE927 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ResetSystemLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources.RISCV64] + RiscV64/ResetSystemLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + DebugLib + +[LibraryClasses.RISCV64] + RiscVSbiLib diff --git a/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c b/MdePk= g/Library/ResetSystemLib/RiscV64/ResetSystemLib.c new file mode 100644 index 0000000000..c077ef6ac7 --- /dev/null +++ b/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c @@ -0,0 +1,128 @@ +/** @file + Reset System Library functions for RISC-V + + Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // Warm Reset via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_N= ONE); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + // Shut down via SBI ecall + SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE= ); +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform. The platform m= ay + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + // + // Can map to OpenSBI vendor or platform specific reset type. + // + return; +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm,= or EfiResetShutdown + the data buffer starts with a Null-terminated = string, optionally + followed by additional binary data. The string= is a description + that the caller may use to further indicate th= e reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93272): https://edk2.groups.io/g/devel/message/93272 Mute This Topic: https://groups.io/mt/93506296/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93273+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93273+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484187; cv=none; d=zohomail.com; s=zohoarc; b=cuWajqio/A8JB0ZybKRbkuFmmOVS2IkggEeLxggpkSJnv2TXM1R1au/znp6jlJDAdURT/X59T8JzIh2t+trZCR6rtKWVeCxvZSgHFeMYNSGOYCijHZF8KEG7+V9pjQiXVyqbCmmOxcNMjaB46gImEF/UFf6Zhty5Oau0mkQLKoc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484187; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8qMDP6GNCJUJXkAvY/Nxuhasm/1AU83T+uYzgE0L9dE=; b=AesXF7Scn45FNPyNuZyEcrEGB7swkYDgLukOF0JHZQ/ucrQctnJzfX7BDAZgLcxD/HthZDWUkL7ZBNaets0SRsouEz/XxMZQyiQTrCb9CT9wwqegsM4OztYBlGt9iPaHBnK7SM6e4cQNmk8zpFqtc2jS1Mc/LlHfTenVIFA+/X8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93273+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166248418783179.99139425989006; Tue, 6 Sep 2022 10:09:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1m7vYY1788612xevPoGKLENT; Tue, 06 Sep 2022 10:09:47 -0700 X-Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by mx.groups.io with SMTP id smtpd.web08.1938.1662484186426365861 for ; Tue, 06 Sep 2022 10:09:46 -0700 X-Received: by mail-pl1-f172.google.com with SMTP id x23so11927842pll.7 for ; Tue, 06 Sep 2022 10:09:46 -0700 (PDT) X-Gm-Message-State: o2nevh4VmH702bKW8W10FrqCx1787277AA= X-Google-Smtp-Source: AA6agR5yEEn27ztlEJXtC1TCgZcIKUmBWre7z+EjDpJFkeOgSxBUw3VhsQvp+G5/jVd8mxxIKe9k7A== X-Received: by 2002:a17:902:e549:b0:174:d234:6116 with SMTP id n9-20020a170902e54900b00174d2346116mr42489790plf.131.1662484185222; Tue, 06 Sep 2022 10:09:45 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:44 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Date: Tue, 6 Sep 2022 22:38:32 +0530 Message-Id: <20220906170837.491525-13-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484187; bh=ID98dA3G4ZNAXgWbNxQ/oZ8eP1rSrQdcHgtiaByZurE=; h=Cc:Date:From:Reply-To:Subject:To; b=uW6nB0Sf6FDd0FmdI+7rDKtVKkHcKtbqa/ja9aXeF1zQIT3GG+hmJbAMiNnyUZZq139 1+kj5jaU3I4d9YEAuuopMLyFbc4RuRHQtNek23CYYibhdD/N9IxWBW84AHKyDXYdkuu3M HhBZmIVZZXPHsJ1nxHuf/S6RJECqNhomNYg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484189381100003 Content-Type: text/plain; charset="utf-8" Generic RISC-V platforms will start in S-mode directly. Previous M-mode firmware like opensbi will branch to the entry point in this module. This module initializes the firmware context pointer and branches to the PEI phase. Signed-off-by: Sunil V L --- UefiCpuPkg/SecCore/RiscV64/SecEntry.S | 23 + UefiCpuPkg/SecCore/RiscV64/SecMain.c | 796 ++++++++++++++++++++++++++ UefiCpuPkg/SecCore/RiscV64/SecMain.h | 63 ++ UefiCpuPkg/SecCore/SecCoreRiscV.inf | 59 ++ 4 files changed, 941 insertions(+) create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecEntry.S create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.c create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.h create mode 100644 UefiCpuPkg/SecCore/SecCoreRiscV.inf diff --git a/UefiCpuPkg/SecCore/RiscV64/SecEntry.S b/UefiCpuPkg/SecCore/Ris= cV64/SecEntry.S new file mode 100644 index 0000000000..1bd0174e27 --- /dev/null +++ b/UefiCpuPkg/SecCore/RiscV64/SecEntry.S @@ -0,0 +1,23 @@ +/* + Copyright (c) 2021-2022 , Hewlett Packard Enterprise Development LP. All= rights reserved. + Copyright (c) 2019 Western Digital Corporation or its affiliates. + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +.text +.align 3 + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdSecPeiTempRamBase) + li a5, FixedPcdGet32 (PcdSecPeiTempRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup diff --git a/UefiCpuPkg/SecCore/RiscV64/SecMain.c b/UefiCpuPkg/SecCore/Risc= V64/SecMain.c new file mode 100644 index 0000000000..d9dacce319 --- /dev/null +++ b/UefiCpuPkg/SecCore/RiscV64/SecMain.c @@ -0,0 +1,796 @@ +/** @file + RISC-V SEC phase module. + + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +EFI_STATUS +EFIAPI +TemporaryRamDone ( + VOID + ); + +STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { + TemporaryRamMigration +}; + +STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { + TemporaryRamDone +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + &mTemporaryRamSupportPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiTemporaryRamDonePpiGuid, + &mTemporaryRamDonePpi + }, +}; + +/** Temporary RAM migration function. + + This function migrates the data from temporary RAM to permanent + memory. + + @param[in] PeiServices PEI service + @param[in] TemporaryMemoryBase Temporary memory base address + @param[in] PermanentMemoryBase Permanent memory base address + @param[in] CopySize Size to copy + +**/ +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + DEBUG ((DEBUG_INFO, + "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n", + __FUNCTION__, + TemporaryMemoryBase, + PermanentMemoryBase, + (UINT64)CopySize + )); + + OldHeap =3D (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap =3D (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1)); + + OldStack =3D (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); + NewStack =3D (VOID*)(UINTN)PermanentMemoryBase; + + CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap + CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack + + // + // Reset firmware context pointer + // + GetFirmwareContextPointer (&FirmwareContext); + FirmwareContext =3D (VOID *)FirmwareContext + (unsigned long)((UINTN)New= Stack - (UINTN)OldStack); + SetFirmwareContextPointer (FirmwareContext); + + DEBUG ((DEBUG_INFO, "%a: Firmware Context is relocated to 0x%x\n", __FUN= CTION__, FirmwareContext)); + + register UINTN a0 asm ("a0") =3D (UINTN)((UINTN)NewStack - (UINTN)OldSt= ack); + asm volatile ("add sp, sp, a0"::"r"(a0):); + return EFI_SUCCESS; +} + +/** Temprary RAM done function. + +**/ +EFI_STATUS EFIAPI TemporaryRamDone ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FU= NCTION__)); + return EFI_SUCCESS; +} +/** Return platform SEC PPI before PEI Core + + @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR. + +**/ +STATIC EFI_STATUS +GetPlatformPrePeiCorePpiDescriptor ( + IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList +) +{ + *ThisPpiList =3D mPrivateDispatchTable; + return EFI_SUCCESS; +} + +/** + Locates the main boot firmware volume. + + @param[in,out] BootFv On input, the base of the BootFv + On output, the decompressed main firmware volume + + @retval EFI_SUCCESS The main firmware volume was located and decompre= ssed + @retval EFI_NOT_FOUND The main firmware volume was not found + +**/ +EFI_STATUS +FindMainFv ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *Fv; + UINTN Distance; + + ASSERT (((UINTN)*BootFv & EFI_PAGE_MASK) =3D=3D 0); + + Fv =3D *BootFv; + Distance =3D (UINTN)(*BootFv)->FvLength; + do { + Fv =3D (EFI_FIRMWARE_VOLUME_HEADER *)((UINT8 *)Fv + EFI_PAGE_SI= ZE); + Distance +=3D EFI_PAGE_SIZE; + if (Distance > SIZE_32MB) { + return EFI_NOT_FOUND; + } + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + continue; + } + + if ((UINTN)Fv->FvLength < Distance) { + continue; + } + + *BootFv =3D Fv; + return EFI_SUCCESS; + } while (TRUE); +} + +/** + Locates a section within a series of sections + with the specified section type. + + The Instance parameter indicates which instance of the section + type to return. (0 is first instance, 1 is second...) + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[in] Instance The section instance number + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInstance ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + IN UINTN Instance, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfSections; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + // + // Loop through the FFS file sections within the PEI Core FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Sections; + EndOfSections =3D EndOfSection + SizeOfSections; + for ( ; ;) { + if (EndOfSection =3D=3D EndOfSections) { + break; + } + + CurrentAddress =3D (EndOfSection + 3) & ~(3ULL); + if (CurrentAddress >=3D EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the requested section type + // + if (Section->Type =3D=3D SectionType) { + if (Instance =3D=3D 0) { + *FoundSection =3D Section; + return EFI_SUCCESS; + } else { + Instance--; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Locates a section within a series of sections + with the specified section type. + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInSections ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + return FindFfsSectionInstance ( + Sections, + SizeOfSections, + SectionType, + 0, + FoundSection + ); +} + +/** + Locates a FFS file with the specified file type and a section + within that file with the specified section type. + + @param[in] Fv The firmware volume to search + @param[in] FileType The file type to locate + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsFileAndSection ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + IN EFI_FV_FILETYPE FileType, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "FV at %p does not have FV header signature\n", F= v)); + return EFI_VOLUME_CORRUPTED; + } + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Fv; + EndOfFirmwareVolume =3D CurrentAddress + Fv->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + Fv->HeaderLength; ; ) { + CurrentAddress =3D (EndOfFile + 7) & ~(7ULL); + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; + Size =3D FFS_FILE_SIZE (File); + if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the request file type + // + if (File->Type !=3D FileType) { + continue; + } + + Status =3D FindFfsSectionInSections ( + (VOID *)(File + 1), + (UINTN)EndOfFile - (UINTN)(File + 1), + SectionType, + FoundSection + ); + if (!EFI_ERROR (Status) || (Status =3D=3D EFI_VOLUME_CORRUPTED)) { + return Status; + } + } +} + +/** + Locates the compressed main firmware volume and decompresses it. + + @param[in,out] Fv On input, the firmware volume to search + On output, the decompressed BOOT/PEI FV + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +DecompressMemFvs ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **Fv + ) +{ + EFI_STATUS Status; + EFI_GUID_DEFINED_SECTION *Section; + UINT32 OutputBufferSize; + UINT32 ScratchBufferSize; + UINT16 SectionAttribute; + UINT32 AuthenticationStatus; + VOID *OutputBuffer; + VOID *ScratchBuffer; + EFI_COMMON_SECTION_HEADER *FvSection; + EFI_FIRMWARE_VOLUME_HEADER *PeiMemFv; + EFI_FIRMWARE_VOLUME_HEADER *DxeMemFv; + UINT32 FvHeaderSize; + UINT32 FvSectionSize; + + FvSection =3D (EFI_COMMON_SECTION_HEADER *)NULL; + + Status =3D FindFfsFileAndSection ( + *Fv, + EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, + EFI_SECTION_GUID_DEFINED, + (EFI_COMMON_SECTION_HEADER **)&Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find GUID defined section\n")); + return Status; + } + + Status =3D ExtractGuidedSectionGetInfo ( + Section, + &OutputBufferSize, + &ScratchBufferSize, + &SectionAttribute + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to GetInfo for GUIDed section\n")); + return Status; + } + + OutputBuffer =3D (VOID *)((UINT8 *)(UINTN)PcdGet32 (PcdDxeMemFvBase) + = SIZE_1MB); + ScratchBuffer =3D ALIGN_POINTER ((UINT8 *)OutputBuffer + OutputBufferSiz= e, SIZE_1MB); + + Status =3D ExtractGuidedSectionDecode ( + Section, + &OutputBuffer, + ScratchBuffer, + &AuthenticationStatus + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error during GUID section decode\n")); + return Status; + } + + Status =3D FindFfsSectionInstance ( + OutputBuffer, + OutputBufferSize, + EFI_SECTION_FIRMWARE_VOLUME_IMAGE, + 0, + &FvSection + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI FV section\n")); + return Status; + } + + ASSERT ( + SECTION_SIZE (FvSection) =3D=3D + (PcdGet32 (PcdPeiMemFvSize) + sizeof (*FvSection)) + ); + ASSERT (FvSection->Type =3D=3D EFI_SECTION_FIRMWARE_VOLUME_IMAGE); + + PeiMemFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdPeiMemFvB= ase); + CopyMem (PeiMemFv, (VOID *)(FvSection + 1), PcdGet32 (PcdPeiMemFvSize)); + + if (PeiMemFv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signa= ture\n", PeiMemFv)); + CpuDeadLoop (); + return EFI_VOLUME_CORRUPTED; + } + + Status =3D FindFfsSectionInstance ( + OutputBuffer, + OutputBufferSize, + EFI_SECTION_FIRMWARE_VOLUME_IMAGE, + 1, + &FvSection + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find DXE FV section\n")); + return Status; + } + + ASSERT (FvSection->Type =3D=3D EFI_SECTION_FIRMWARE_VOLUME_IMAGE); + + if (IS_SECTION2 (FvSection)) { + FvSectionSize =3D SECTION2_SIZE (FvSection); + FvHeaderSize =3D sizeof (EFI_COMMON_SECTION_HEADER2); + } else { + FvSectionSize =3D SECTION_SIZE (FvSection); + FvHeaderSize =3D sizeof (EFI_COMMON_SECTION_HEADER); + } + + ASSERT (FvSectionSize =3D=3D (PcdGet32 (PcdDxeMemFvSize) + FvHeaderSize)= ); + + DxeMemFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdDxeMemFvB= ase); + CopyMem (DxeMemFv, (VOID *)((UINTN)FvSection + FvHeaderSize), PcdGet32 (= PcdDxeMemFvSize)); + + if (DxeMemFv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signa= ture\n", DxeMemFv)); + CpuDeadLoop (); + return EFI_VOLUME_CORRUPTED; + } + *Fv =3D PeiMemFv; + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindPeiCoreImageBaseInFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + EFI_STATUS Status; + EFI_COMMON_SECTION_HEADER *Section; + + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_PE32, + &Section + ); + if (EFI_ERROR (Status)) { + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_TE, + &Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI Core image\n")); + return Status; + } + } + + *PeiCoreImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1); + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in,out] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +VOID +FindPeiCoreImageBase ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + + *PeiCoreImageBase =3D 0; + + FindMainFv (BootFv); + + DecompressMemFvs (BootFv); + + FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase); +} + +/** + Find core image base. + +**/ +EFI_STATUS +FindImageBase ( + IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr, + OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + *SecCoreImageBase =3D 0; + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)BootFirmwareVolumeP= tr; + EndOfFirmwareVolume =3D CurrentAddress + BootFirmwareVolumePtr->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + BootFirmwareVolumePtr->HeaderLength;= ; ) { + CurrentAddress =3D (EndOfFile + 7) & 0xfffffffffffffff8ULL; + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_NOT_FOUND; + } + + File =3D (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress; + Size =3D FFS_FILE_SIZE (File); + if (Size < sizeof (*File)) { + return EFI_NOT_FOUND; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_NOT_FOUND; + } + + // + // Look for SEC Core + // + if (File->Type !=3D EFI_FV_FILETYPE_SECURITY_CORE) { + continue; + } + + // + // Loop through the FFS file sections within the FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(File + 1); + for ( ; ;) { + CurrentAddress =3D (EndOfSection + 3) & 0xfffffffffffffffcULL; + Section =3D (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddres= s; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_NOT_FOUND; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfFile) { + return EFI_NOT_FOUND; + } + + // + // Look for executable sections + // + if ((Section->Type =3D=3D EFI_SECTION_PE32) || (Section->Type =3D=3D= EFI_SECTION_TE)) { + if (File->Type =3D=3D EFI_FV_FILETYPE_SECURITY_CORE) { + *SecCoreImageBase =3D (PHYSICAL_ADDRESS)(UINTN)(Section + 1); + } + + break; + } + } + + // + // SEC Core image found + // + if (*SecCoreImageBase !=3D 0) { + return EFI_SUCCESS; + } + } +} + +/* + Find and return Pei Core entry point. + + It also find SEC and PEI Core file debug information. It will report the= m if + remote debug is enabled. + +**/ +VOID +FindAndReportEntryPoints ( + IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS SecCoreImageBase; + EFI_PHYSICAL_ADDRESS PeiCoreImageBase; + PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; + + // + // Find SEC Core and PEI Core image base + // + Status =3D FindImageBase (*BootFirmwareVolumePtr, &SecCoreImageBase); + ASSERT_EFI_ERROR (Status); + + FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase); + + ZeroMem ((VOID *)&ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT)); + // + // Report SEC Core debug information when remote debug is enabled + // + ImageContext.ImageAddress =3D SecCoreImageBase; + ImageContext.PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)= ImageContext.ImageAddress); + PeCoffLoaderRelocateImageExtraAction (&ImageContext); + + // + // Report PEI Core debug information when remote debug is enabled + // + ImageContext.ImageAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)PeiCoreImageB= ase; + ImageContext.PdbPointer =3D PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)= ImageContext.ImageAddress); + PeCoffLoaderRelocateImageExtraAction (&ImageContext); + + // + // Find PEI Core entry point + // + Status =3D PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (= VOID **)PeiCoreEntryPoint); + if (EFI_ERROR (Status)) { + *PeiCoreEntryPoint =3D 0; + } + + return; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_FIRMWARE_VOLUME_HEADER *BootFv; + EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_STATUS Status; + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __FUNCTION__, + BootHartId, + DeviceTreeAddress + )); + + // + // Process all libraries constructor function linked to SecCore. + // + ProcessLibraryConstructorList (); + + BootFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdSecMemFvBase); + + ASSERT(BootFv !=3D NULL); + SecCoreData.DataSize =3D (UINT16)sizeof (EFI_SEC_PEI_HAND_= OFF); + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN)FixedPcdGet32 (PcdSecMemFv= Size); + SecCoreData.TemporaryRamBase =3D (VOID *)(UINT64)FixedPcdGet32 (Pc= dSecPeiTempRamBase); + SecCoreData.TemporaryRamSize =3D (UINTN)FixedPcdGet32 (PcdSecPeiTe= mpRamSize); + SecCoreData.PeiTemporaryRamBase =3D SecCoreData.TemporaryRamBase; + SecCoreData.PeiTemporaryRamSize =3D SecCoreData.TemporaryRamSize >> 1; + SecCoreData.StackBase =3D (UINT8 *)SecCoreData.TemporaryRam= Base + (SecCoreData.TemporaryRamSize >> 1); + SecCoreData.StackSize =3D SecCoreData.TemporaryRamSize >> 1; + + DEBUG (( + DEBUG_INFO, + "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size= : 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackS= ize: 0x%x\n", + __FUNCTION__, + SecCoreData.BootFirmwareVolumeBase, + SecCoreData.BootFirmwareVolumeSize, + SecCoreData.TemporaryRamBase, + SecCoreData.TemporaryRamSize, + SecCoreData.PeiTemporaryRamBase, + SecCoreData.PeiTemporaryRamSize, + SecCoreData.StackBase, + SecCoreData.StackSize + )); + + FindAndReportEntryPoints ( + &BootFv, + &PeiCoreEntryPoint + ); + if (PeiCoreEntryPoint =3D=3D NULL) { + CpuDeadLoop (); + } + + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN) BootFv->FvLength; + + Status =3D GetPlatformPrePeiCorePpiDescriptor (&PpiList); + if (EFI_ERROR (Status)) { + PpiList =3D NULL; + } + + FirmwareContext.BootHartId =3D BootHartId; + FirmwareContext.FlattenedDeviceTree =3D (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + // + // Transfer the control to the PEI core + // + ASSERT (PeiCoreEntryPoint !=3D NULL); + (*PeiCoreEntryPoint)(&SecCoreData, PpiList); + + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/UefiCpuPkg/SecCore/RiscV64/SecMain.h b/UefiCpuPkg/SecCore/Risc= V64/SecMain.h new file mode 100644 index 0000000000..eeb368de02 --- /dev/null +++ b/UefiCpuPkg/SecCore/RiscV64/SecMain.h @@ -0,0 +1,63 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SEC_MAIN_H_ +#define _SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +#endif diff --git a/UefiCpuPkg/SecCore/SecCoreRiscV.inf b/UefiCpuPkg/SecCore/SecCo= reRiscV.inf new file mode 100644 index 0000000000..8ba6400f53 --- /dev/null +++ b/UefiCpuPkg/SecCore/SecCoreRiscV.inf @@ -0,0 +1,59 @@ +## @file +# RISC-V SEC module which boots in S-mode. +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D SecMain + FILE_GUID =3D 42C30D8E-BFAD-4E77-9041-E7DAAE88DF7A + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/SecEntry.S + RiscV64/SecMain.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PlatformSecLib + PcdLib + CpuLib + PeCoffGetEntryPointLib + PeCoffExtraActionLib + RiscVSbiLib + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamSize + +[UserExtensions.TianoCore."ExtraFiles"] + SecCoreExtra.uni --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93273): https://edk2.groups.io/g/devel/message/93273 Mute This Topic: https://groups.io/mt/93506298/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93274+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93274+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484191; cv=none; d=zohomail.com; s=zohoarc; b=eQpz/kITmlmF4yrODBqatA5xyEf5OmXE2t5XBlnf3y0VeZ4Rg2KYI9Cisd8zWJIDxHeOwlib3TSigWCLlR9nii8GgS16jM2UdKBV5zK0XnwMO/O30fqJ2dmBgRj8ww/5q0uZcINK8IpgVFTnrEk5ALZWnSy8IfoLmSRjn40kEyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484191; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ssTGOLgd+AibzXs51rI7trVXZX9xHxEjY6V2EkCiRLA=; b=b12PrjBeuT+K3kdmIr9K5lo1e5shTGnHxHS9yTmIFPFER8qZX/BqXMA+sqTNfzqUBI6FHFjbK3VNOMzHhu0nlfGQvTIE4nr5/DBFtrmZ6+TuRNt2p+TZW/4ziLiL2f5sjjaGyYRfYrHgTM2xT/90fIBvqpTzWn5yciBRotYszZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93274+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484191951910.4504915501464; Tue, 6 Sep 2022 10:09:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PinpYY1788612xvImxAmBQqc; Tue, 06 Sep 2022 10:09:51 -0700 X-Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) by mx.groups.io with SMTP id smtpd.web12.1919.1662484190796837187 for ; Tue, 06 Sep 2022 10:09:50 -0700 X-Received: by mail-pf1-f178.google.com with SMTP id 145so12027504pfw.4 for ; Tue, 06 Sep 2022 10:09:50 -0700 (PDT) X-Gm-Message-State: pCuTb7dL3ln2l6ALaj7k0HAnx1787277AA= X-Google-Smtp-Source: AA6agR74h5hoHNvicMvCVPdYJFePH87zef5STx6boBThom4VJdbVtaWf6dE24uQWqDFxHb94FDSi5A== X-Received: by 2002:a05:6a00:1388:b0:53e:6456:99a2 with SMTP id t8-20020a056a00138800b0053e645699a2mr12770pfg.43.1662484190045; Tue, 06 Sep 2022 10:09:50 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:49 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library Date: Tue, 6 Sep 2022 22:38:33 +0530 Message-Id: <20220906170837.491525-14-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484191; bh=CQqUWiOnRD69JCgIR9wRjj4j9TAny0Z0qUO6j4xXBKo=; h=Cc:Date:From:Reply-To:Subject:To; b=VNBECdsNXmO0lbonQ8mJBBR35cA41UE1JqDz0G8B8gtGe7wTGHlZ1HC45XMY13d7wlp pQL1EzbMwv2coQ5hY1G3vYepqqJyntvRJMhLGJ4gePRpalwa4tYitXW0Sk6jiSDA4Cc/D 4/f70Jy/YQyN3GFeHod/J1v827pkAowVoqY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484193241100001 Content-Type: text/plain; charset="utf-8" This library is required in RISC-V to build the FDT Hob. The library can be leveraged by other architectures like ARM if required. Signed-off-by: Sunil V L --- MdePkg/Include/Library/PlatformPeiLib.h | 15 ++++ .../Library/PlatformPeiLib/PlatformPeiLib.inf | 40 +++++++++++ .../PlatformPeiLib/RiscV64/PlatformPeiLib.c | 68 +++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 MdePkg/Include/Library/PlatformPeiLib.h create mode 100644 MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf create mode 100644 MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c diff --git a/MdePkg/Include/Library/PlatformPeiLib.h b/MdePkg/Include/Libra= ry/PlatformPeiLib.h new file mode 100644 index 0000000000..1e8c5f98cf --- /dev/null +++ b/MdePkg/Include/Library/PlatformPeiLib.h @@ -0,0 +1,15 @@ +/** @file + Library to initialize platform data at PEI phase + + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese= rved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_PEI_LIB_H_ +#define _PLATFORM_PEI_LIB_H_ + +EFI_STATUS PlatformPeim(VOID); + +#endif diff --git a/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf b/MdePkg/Libr= ary/PlatformPeiLib/PlatformPeiLib.inf new file mode 100644 index 0000000000..d682b3c0f9 --- /dev/null +++ b/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf @@ -0,0 +1,40 @@ +## @file +# Platform Initialization Pei Library +# +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformPeiLib + FILE_GUID =3D B35BD738-787B-47FB-8139-20193442CC49 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformPeiLib + +[Sources.RISCV64] + RiscV64/PlatformPeiLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DebugLib + HobLib + FdtLib + PcdLib + PeimEntryPoint + BaseLib + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Guids] + gFdtHobGuid ## PRODUCES diff --git a/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c b/MdePk= g/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c new file mode 100644 index 0000000000..e62aa26df9 --- /dev/null +++ b/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c @@ -0,0 +1,68 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#include + +#include + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUN= CTION__, FdtPointer)); + Base =3D FdtPointer; + ASSERT (Base !=3D NULL); + ASSERT (fdt_check_header (Base) =3D=3D 0); + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + ASSERT (NewBase !=3D NULL); + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + ASSERT (FdtHobData !=3D NULL); + *FdtHobData =3D (UINTN)NewBase; + + return EFI_SUCCESS; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Tue, 06 Sep 2022 10:09:56 -0700 X-Received: by mail-pj1-f52.google.com with SMTP id q3so11978493pjg.3 for ; Tue, 06 Sep 2022 10:09:56 -0700 (PDT) X-Gm-Message-State: wUTOyUM69EUMxDkqf0yQcTUYx1787277AA= X-Google-Smtp-Source: AA6agR6s2S72ZcileFGaOS2ZCO4IvFpqR0NwkKDrUJjNP1HxZ6xhDHqfzqTL35VUg4YYbeeDHrcAXQ== X-Received: by 2002:a17:90b:33c9:b0:200:9ec2:f2eb with SMTP id lk9-20020a17090b33c900b002009ec2f2ebmr4377226pjb.29.1662484194992; Tue, 06 Sep 2022 10:09:54 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:54 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Date: Tue, 6 Sep 2022 22:38:34 +0530 Message-Id: <20220906170837.491525-15-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484197; bh=bwqUqSy5NQxlvxMaOrIsQbvHa4c7CI2BNReIxsCJnY8=; h=Cc:Date:From:Reply-To:Subject:To; b=XggwXhK5LiFTkv+L2AVZbg7Bux62u7s/z3rxlHAHMwdGs97+NQiLT4rXePPrJHZD7+1 4ON+KNvlY4SCN+F36GRbjAfJjulDAUtoAGPwgWBCWw03hHkWtmrdUHNBKIVivz/EDoWrU j2mzugAwyNJcEi+nXbcGro7cPP6SOUZs8WI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484199235100001 Content-Type: text/plain; charset="utf-8" Thie PEIM is required to do platform specific initialization like detecting the permanent memory and install memory HOB, install the FDT Hob etc. Signed-off-by: Sunil V L --- .../Universal/PlatformPei/PlatformPei.inf | 65 +++ .../Universal/PlatformPei/RiscV64/Fv.c | 83 ++++ .../Universal/PlatformPei/RiscV64/MemDetect.c | 179 +++++++++ .../Universal/PlatformPei/RiscV64/Platform.c | 372 ++++++++++++++++++ .../Universal/PlatformPei/RiscV64/Platform.h | 97 +++++ 5 files changed, 796 insertions(+) create mode 100644 MdeModulePkg/Universal/PlatformPei/PlatformPei.inf create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h diff --git a/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf b/MdeModule= Pkg/Universal/PlatformPei/PlatformPei.inf new file mode 100644 index 0000000000..220f4a7ee5 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf @@ -0,0 +1,65 @@ +## @file +# Platform PEI driver +# +# This module provides platform specific functions +# +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D PlatformPei + FILE_GUID =3D 0F26B9AF-3E38-46E8-9D35-0318E903E049 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePlatform + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + RiscV64/Fv.c + RiscV64/MemDetect.c + RiscV64/Platform.c + RiscV64/Platform.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Guids] + gEfiMemoryTypeInformationGuid + +[LibraryClasses] + DebugLib + HobLib + FdtLib + IoLib + PcdLib + PeimEntryPoint + PeiResourcePublicationLib + PlatformPeiLib + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Pcd.RISCV64] + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize + +[Ppis] + gEfiPeiMasterBootModePpiGuid + +[Depex] + TRUE diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c b/MdeModulePkg= /Universal/PlatformPei/RiscV64/Fv.c new file mode 100644 index 0000000000..15e77fcf7e --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c @@ -0,0 +1,83 @@ +/** @file + Build FV related hobs for platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PiPei.h" +#include "Platform.h" +#include +#include +#include +#include + +/** + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI + and DXE know about them. + + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully. + +**/ +EFI_STATUS +PeiFvInitialization ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n")); + + // Create a memory allocation HOB for the DXE FV. + // + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE + // firmware volumes at S3 resume too, hence we need to keep away the OS = from + // DXEFV as well. Otherwise we only need to keep away DXE itself from the + // DXEFV area. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdPeiMemFvBase), + PcdGet32 (PcdPeiMemFvSize), + EfiBootServicesData + ); + + + // + // Let DXE know about the DXE FV + // + BuildFvHob (PcdGet32 (PcdDxeMemFvBase), PcdGet32 (PcdDxeMemFvSize)); + DEBUG (( + DEBUG_INFO, + "Platform builds DXE FV at %x, size %x.\n", + PcdGet32 (PcdDxeMemFvBase), + PcdGet32 (PcdDxeMemFvSize) + )); + + // Create a memory allocation HOB for the DXE FV. + // + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE + // firmware volumes at S3 resume too, hence we need to keep away the OS = from + // DXEFV as well. Otherwise we only need to keep away DXE itself from the + // DXEFV area. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdDxeMemFvBase), + PcdGet32 (PcdDxeMemFvSize), + EfiBootServicesData + ); + + // + // Let PEI know about the DXE FV so it can find the DXE Core + // + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *)(UINTN)PcdGet32 (PcdDxeMemFvBase), + PcdGet32 (PcdDxeMemFvSize), + NULL, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c b/MdeMo= dulePkg/Universal/PlatformPei/RiscV64/MemDetect.c new file mode 100644 index 0000000000..3ebd29eba6 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c @@ -0,0 +1,179 @@ +/** @file + Memory Detection for Virtual Machines. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "Platform.h" + +STATIC EFI_PHYSICAL_ADDRESS SystemMemoryBase; +STATIC UINT64 SystemMemorySize; +STATIC EFI_PHYSICAL_ADDRESS MmodeResvBase; +STATIC UINT64 MmodeResvSize; + +/** + Publish PEI core memory. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +PublishPeiMemory ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + EFI_PHYSICAL_ADDRESS MemoryBase; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + EFI_STATUS Status; + UINT64 CurBase, CurSize; + UINT64 NewBase =3D 0, NewSize =3D 0; + UINT64 MemorySize; + INT32 Node, Prev; + INT32 Len; + VOID *FdtPointer; + + FirmwareContext =3D NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + // Look for the lowest memory node + for (Prev =3D 0;; Prev =3D Node) { + Node =3D fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + // Check for memory node + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && AsciiStrnCmp (Type, "memory", Len) =3D=3D 0) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) { + + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", + __FUNCTION__, CurBase, CurBase + CurSize - 1)); + + if (NewBase > CurBase || NewBase =3D=3D 0) { + NewBase =3D CurBase; + NewSize =3D CurSize; + } + } else { + DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", + __FUNCTION__)); + } + } + } + + SystemMemoryBase =3D NewBase; + SystemMemorySize =3D NewSize; + + /* try to locate the reserved memory opensbi node */ + Node =3D fdt_path_offset(FdtPointer, "/reserved-memory/mmode_resv0"); + if (Node >=3D 0) { + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len); + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) { + NewBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + NewSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + DEBUG ((DEBUG_INFO, "%a: M-mode Base =3D 0x%lx, M-mode Size =3D 0x%l= x\n", + __FUNCTION__, NewBase, NewSize)); + MmodeResvBase =3D NewBase; + MmodeResvSize =3D NewSize; + } + } + + DEBUG ((DEBUG_INFO, "%a: SystemMemoryBase:0x%x SystemMemorySize:%x\n", + __FUNCTION__, SystemMemoryBase, SystemMemorySize)); + + // + // Initial 16MB needs to be reserved + // + MemoryBase =3D SystemMemoryBase + SIZE_16MB; + MemorySize =3D SystemMemorySize - SIZE_16MB; + + // + // Publish this memory to the PEI Core + // + Status =3D PublishSystemMemory (MemoryBase, MemorySize); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Publish system RAM and reserve memory regions. + +**/ +VOID +InitializeRamRegions ( + VOID + ) +{ + /* + * M-mode FW can be loaded anywhere in memory but should not overlap + * with the EDK2. This can happen if some other boot code loads the + * M-mode firmware. + * + * The M-mode firmware memory should be marked as reserved memory + * so that OS doesn't use it. + */ + DEBUG ((DEBUG_INFO, "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, MmodeResvBase, MmodeResvBase + MmodeResvSize)); + AddReservedMemoryBaseSizeHob(MmodeResvBase, MmodeResvSize); + + if (MmodeResvBase > SystemMemoryBase) { + DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, SystemMemoryBase, MmodeResvBase)); + AddMemoryRangeHob(SystemMemoryBase, MmodeResvBase); + } + + DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n", + __FUNCTION__, MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize)); + AddMemoryRangeHob(MmodeResvBase + MmodeResvSize, + SystemMemoryBase + SystemMemorySize); +} diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c b/MdeMod= ulePkg/Universal/PlatformPei/RiscV64/Platform.c new file mode 100644 index 0000000000..27d50a0e56 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c @@ -0,0 +1,372 @@ +/** @file + Platform PEI driver + + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Platform.h" + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D { + { EfiACPIMemoryNVS, 0x004 }, + { EfiACPIReclaimMemory, 0x008 }, + { EfiReservedMemoryType, 0x004 }, + { EfiRuntimeServicesData, 0x024 }, + { EfiRuntimeServicesCode, 0x030 }, + { EfiBootServicesCode, 0x180 }, + { EfiBootServicesData, 0xF00 }, + { EfiMaxMemoryType, 0x000 } +}; + +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiMasterBootModePpiGuid, + NULL + } +}; + +STATIC EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION; + +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Build reserved memory range resource HOB. + + @param MemoryBase Reserved memory range base address. + @param MemorySize Reserved memory range size. + +**/ +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Build memory map I/O resource using the base address + and the top address of memory range. + + @param MemoryBase Memory map I/O range base address. + @param MemoryLimit The top address of memory map I/O range + +**/ +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Create untested memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE, + MemoryBase, + MemorySize + ); +} + +/** + Create untested memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} + +/** + Add PCI resource. + +**/ +VOID +AddPciResource ( + VOID + ) +{ + // + // Platform-specific + // +} + +/** + Platform memory map initialization. + +**/ +VOID +MemMapInitialization ( + VOID + ) +{ + // + // Create Memory Type Information HOB + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof (mDefaultMemoryTypeInformation) + ); + + // + // Add PCI IO Port space available for PCI resource allocations. + // + AddPciResource (); +} + +/** + Platform misc initialization. + +**/ +VOID +MiscInitialization ( + VOID + ) +{ + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + // TODO: Determine this dynamically from the platform + // setting or the HART configuration. + // + BuildCpuHob (56, 32); +} + +/** + Check if system returns from S3. + + @return BOOLEAN TRUE, system returned from S3 + FALSE, system is not returned from S3 + +**/ +BOOLEAN +CheckResumeFromS3 ( + VOID + ) +{ + // + // Platform implementation-specific + // + return FALSE; +} + +/** + Platform boot mode initialization. + +**/ +VOID +BootModeInitialization ( + VOID + ) +{ + EFI_STATUS Status; + + if (CheckResumeFromS3()) { + DEBUG ((DEBUG_INFO, "This is wake from S3\n")); + } else { + DEBUG ((DEBUG_INFO, "This is normal boot\n")); + } + + Status =3D PeiServicesSetBootMode (mBootMode); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesInstallPpi (mPpiBootMode); + ASSERT_EFI_ERROR (Status); +} + +/** + Build processor information for U54 Coreplex processor. + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildCoreInformationHob ( + VOID + ) +{ +// return BuildRiscVSmbiosHobs (); + return EFI_SUCCESS; +} + +/** + Perform Platform PEI initialization. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +InitializePlatform ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); + Status =3D PlatformPeim(); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PlatformPeim failed\n")); + ASSERT (FALSE); + } + BootModeInitialization (); + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n")); + PublishPeiMemory (); + DEBUG ((DEBUG_INFO, "PEI memory published.\n")); + InitializeRamRegions (); + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n")); + + if (mBootMode !=3D BOOT_ON_S3_RESUME) { + PeiFvInitialization (); + MemMapInitialization (); + } + + MiscInitialization (); + Status =3D BuildCoreInformationHob (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n")); + ASSERT (FALSE); + } + + return EFI_SUCCESS; +} diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h b/MdeMod= ulePkg/Universal/PlatformPei/RiscV64/Platform.h new file mode 100644 index 0000000000..6c23c722a3 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h @@ -0,0 +1,97 @@ +/** @file + Platform PEI module include file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_PEI_H_INCLUDED_ +#define PLATFORM_PEI_H_INCLUDED_ + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddressWidthInitialization ( + VOID + ); + +EFI_STATUS +PublishPeiMemory ( + VOID + ); + +UINT32 +GetSystemMemorySizeBelow4gb ( + VOID + ); + +VOID +InitializeRamRegions ( + VOID + ); + +EFI_STATUS +PeiFvInitialization ( + VOID + ); + +EFI_STATUS +InitializeXen ( + VOID + ); + +/** + Build processor and platform information for the U5 platform + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildRiscVSmbiosHobs ( + VOID + ); + +#endif // _PLATFORM_PEI_H_INCLUDED_ --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93275): https://edk2.groups.io/g/devel/message/93275 Mute This Topic: https://groups.io/mt/93506301/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93276+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93276+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484201; cv=none; d=zohomail.com; s=zohoarc; b=BQd4J1tBlPU2WPZjElHGXIdATtpkkLnr7bp/0sN59i9eNZSLo15ww3HXzlmzbXNjhatbjH8GwflfpWRSjCHMHDLZnVbshmwcIf7jB1EUpoPbyB9P7o9e1Hi1maPAsMtroKAs8s7bClDEl9HNOY4H3M7CLnJCOEtrY89FUeRwr5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484201; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Eb+HJSmMySLcvBsnVsP37j8aBZEuxalJUFdKys1GV5U=; b=T44sLuYl56V11lgLrb8QEY5f5zxNvGfYoztixy9FUwhZIV7RCg2fMShUBV/5OOIV9wdrtjbf0rdTFHs/77Q4/r64chvM1JvzJZDqoh3+EzkVmN2oiU/9SLW5+dNb4Sg5J1oZH7CHDSBeniDpLFBgM88jV8gUzxphsjqIbMzNb+E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93276+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484201696581.6788488728423; Tue, 6 Sep 2022 10:10:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4BMiYY1788612xM2IbtUiRoy; Tue, 06 Sep 2022 10:10:01 -0700 X-Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mx.groups.io with SMTP id smtpd.web12.1922.1662484200710974135 for ; Tue, 06 Sep 2022 10:10:00 -0700 X-Received: by mail-pj1-f46.google.com with SMTP id n65-20020a17090a5ac700b001fbb4fad865so12056501pji.1 for ; Tue, 06 Sep 2022 10:10:00 -0700 (PDT) X-Gm-Message-State: l2o2F2EzlNAnS5ypQPtGucfPx1787277AA= X-Google-Smtp-Source: AA6agR5Wn1puNIBoq9Uhup4Sp2NgKjd2ioF0iS3NLpyYjsgIwDQ1XcHcHTcLvLQIF2Sv6RUhYg6nVA== X-Received: by 2002:a17:902:8ec7:b0:172:ac9c:4757 with SMTP id x7-20020a1709028ec700b00172ac9c4757mr54541299plo.163.1662484199827; Tue, 06 Sep 2022 10:09:59 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:59 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Date: Tue, 6 Sep 2022 22:38:35 +0530 Message-Id: <20220906170837.491525-16-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484201; bh=c7/IE19B2Uq+nl3Tulb4boAcmHwzoVICTwv8iU76aIw=; h=Cc:Date:From:Reply-To:Subject:To; b=sXFp05Q3XRbgyyrtf284Z/4lQhd6NMY0Yc7cOEOSTI4k+Avw//SiLeKi1kBdoLGQnsf jnYNNJ90k+Mmmxv0SyaVSZvx11KveO5dtlTD+HM1yTgV6Bagw2JzTGooBHP7LOP/2y4OK U1qKp0ddud2GIFWVH3kW7oqwYynVitKnM48= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484203217100007 Content-Type: text/plain; charset="utf-8" Currently, CpuDxe driver is mostly x86 specific. Refactor the INF to allow other architectures like RISC-V. Signed-off-by: Sunil V L --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 2352418992..4f2ea42f16 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -29,20 +29,22 @@ DebugLib DxeServicesTableLib MemoryAllocationLib - MtrrLib UefiBootServicesTableLib UefiDriverEntryPoint - LocalApicLib - UefiCpuLib UefiLib CpuExceptionHandlerLib HobLib ReportStatusCodeLib - MpInitLib TimerLib PeCoffGetEntryPointLib =20 -[Sources] +[LibraryClasses.IA32, LibraryClasses.X64] + LocalApicLib + MpInitLib + MtrrLib + UefiCpuLib + +[Sources.IA32, Sources.X64] CpuDxe.c CpuDxe.h CpuGdt.c --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93276): https://edk2.groups.io/g/devel/message/93276 Mute This Topic: https://groups.io/mt/93506302/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93277+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93277+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484208; cv=none; d=zohomail.com; s=zohoarc; b=LTsqg/PPhEYQ1EQzqxxJQPCz+AHA54tqPrYbLKiFobWODzu+1ibZTomSPaUXa6nplkykJ11wWYY7j/7PVsEEn8xmss5wamvFExNRVE4UfX+McqD1CSljLG4qKgdoH6kJXY0BuwLvvdzzXL2BdKZEzgW2DSFx5XyKf918ucuFsCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484208; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=05NV6PfEaH4ZR/qoyUvOXksHBPkkqifVZIHgmKtllDQ=; b=N+SMbKSEfI/TIKkHb5/YZbZQAKdzkG3W85dCXUm5u0lXmJvvfZij/Pyc/KKWQ9dYc4heSHMSDejRH9emrsTnQLuQsaC/3XZPLXt7wfMjjjE+RnIorZclXukh3yFLMKpXf/chZAGMvP/MqRhfDCkUhYq8ae9/96gjZI/E/YaQc00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93277+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484208112489.50728812188936; Tue, 6 Sep 2022 10:10:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SyRbYY1788612xmjjhVPzIZP; Tue, 06 Sep 2022 10:10:06 -0700 X-Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) by mx.groups.io with SMTP id smtpd.web12.1928.1662484206141079667 for ; Tue, 06 Sep 2022 10:10:06 -0700 X-Received: by mail-pj1-f52.google.com with SMTP id z9-20020a17090a468900b001ffff693b27so10651906pjf.2 for ; Tue, 06 Sep 2022 10:10:06 -0700 (PDT) X-Gm-Message-State: vpu9DtPQOoqocSEvtg0tWgAPx1787277AA= X-Google-Smtp-Source: AA6agR7irAA5piJJIF+NiBRlna5BZQrrhV4/5EMrd+RmKBcdnfGF1sLm5HjGlJiuTeYVZkRr0xKogw== X-Received: by 2002:a17:90b:3b92:b0:200:ad6a:d762 with SMTP id pc18-20020a17090b3b9200b00200ad6ad762mr1799928pjb.227.1662484205073; Tue, 06 Sep 2022 10:10:05 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.10.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:10:04 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Date: Tue, 6 Sep 2022 22:38:36 +0530 Message-Id: <20220906170837.491525-17-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484206; bh=F0sNsmE1Iw9c5Xo4hD1DxuCCQKQwct0HcIm5NJk1IqQ=; h=Cc:Date:From:Reply-To:Subject:To; b=qIKNcIXoDl08H5rhY2hpfK/odcer9v4KVUoFk3iU6nl4XLlDHUgxu8ufeFGWO7ukCoC ePWY7RQGonD6wNKwX8VudoNRRA1lrsNy9ply8CVfa9sBpEYkRYhgytw79LElXQmUtsqw9 /5/17D8xyW0Nj5AntcXEmS/ih636++ia1+k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484209285100003 Content-Type: text/plain; charset="utf-8" This DXE module initializes the RISC-V CPU by installing the CPU specific ARCH protocol handlers. This also initializes the RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms. Signed-off-by: Sunil V L --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 +++++++++++++++++++++++++++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++ 3 files changed, 552 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -1,8 +1,12 @@ ## @file -# CPU driver installs CPU Architecture Protocol and CPU MP protocol. +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP protoc= ol. +# +# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V boot +# protocol # # Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,6 +48,9 @@ MtrrLib UefiCpuLib =20 +[LibraryClasses.RISCV64] + RiscVSbiLib + [Sources.IA32, Sources.X64] CpuDxe.c CpuDxe.h @@ -62,11 +69,18 @@ X64/CpuAsm.nasm X64/PagingAttribute.c =20 +[Sources.RISCV64] + RiscV64/CpuDxe.c + RiscV64/CpuDxe.h + [Protocols] gEfiCpuArchProtocolGuid ## PRODUCES gEfiMpServiceProtocolGuid ## PRODUCES gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES =20 +[Protocols.RISCV64] + gRiscVEfiBootProtocolGuid ## PRODUCES + [Guids] gIdleLoopEventGuid ## CONSUMES ## E= vent gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## S= ystemTable diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c new file mode 100644 index 0000000000..4112b6b8c6 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -0,0 +1,337 @@ +/** @file + RISC-V CPU DXE driver. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "CpuDxe.h" + +// +// Global Variables +// +STATIC BOOLEAN mInterruptState =3D FALSE; +STATIC EFI_HANDLE mCpuHandle =3D NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId =3D mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; + +EFI_CPU_ARCH_PROTOCOL gCpu =3D { + CpuFlushCpuDataCache, + CpuEnableInterrupt, + CpuDisableInterrupt, + CpuGetInterruptState, + CpuInit, + CpuRegisterInterruptHandler, + CpuGetTimerValue, + CpuSetMemoryAttributes, + 1, // NumberOfTimers + 4 // DmaBufferAlignment +}; + +// +// CPU Arch Protocol Functions +// + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ) +{ + return EFI_SUCCESS; +} + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + EnableInterrupts (); + mInterruptState =3D TRUE; + return EFI_SUCCESS; +} + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ) +{ + DisableInterrupts (); + mInterruptState =3D FALSE; + return EFI_SUCCESS; +} + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ) +{ + if (State =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *State =3D mInterruptState; + return EFI_SUCCESS; +} + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); +} + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol. + + This function modifies the attributes for the memory region specified by= BaseAddress and + Length from their current attributes to the attributes specified by Attr= ibutes. + + @param This The EFI_CPU_ARCH_PROTOCOL instance. + @param BaseAddress The physical address that is the start address = of a memory region. + @param Length The size in bytes of the memory region. + @param Attributes The bit mask of attributes to set for the memor= y region. + + @retval EFI_SUCCESS The attributes were set for the memory reg= ion. + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by + BaseAddress and Length cannot be modified. + @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combinatio= n of attributes that + cannot be set together. + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of + the memory resource range. + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory + resource range specified by BaseAddress an= d Length. + The bit mask of attributes is not support = for the memory resource + range specified by BaseAddress and Length. + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ) +{ + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__)); + return EFI_SUCCESS; +} + +/** + Initialize the state information for the CPU Architectural Protocol. + + @param ImageHandle Image handle this driver. + @param SystemTable Pointer to the System Table. + + @retval EFI_SUCCESS Thread can be successfully created + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Cannot create the thread + +**/ +EFI_STATUS +EFIAPI +InitializeCpu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext !=3D NULL); + if (FirmwareContext =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n")); + return EFI_NOT_FOUND; + } + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext)); + + mBootHartId =3D FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId)); + + + InitializeCpuExceptionHandlers(NULL); + + // + // Make sure interrupts are disabled + // + DisableInterrupts (); + + Status =3D gBS->InstallProtocolInterface (&ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + + ASSERT_EFI_ERROR (Status); + + // + // Install CPU Architectural Protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mCpuHandle, + &gEfiCpuArchProtocolGuid, + &gCpu, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.h new file mode 100644 index 0000000000..f039759dbd --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h @@ -0,0 +1,200 @@ +/** @file + RISC-V CPU DXE module header file. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef CPU_DXE_H_ +#define CPU_DXE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Flush CPU data cache. If the instruction cache is fully coherent + with all DMA operations then function can just return EFI_SUCCESS. + + @param This Protocol instance structure + @param Start Physical address to start flushing from. + @param Length Number of bytes to flush. Round up to chipset + granularity. + @param FlushType Specifies the type of flush operation to perfo= rm. + + @retval EFI_SUCCESS If cache was flushed + @retval EFI_UNSUPPORTED If flush type is not supported. + @retval EFI_DEVICE_ERROR If requested range could not be flushed. + +**/ +EFI_STATUS +EFIAPI +CpuFlushCpuDataCache ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS Start, + IN UINT64 Length, + IN EFI_CPU_FLUSH_TYPE FlushType + ); + +/** + Enables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were enabled in the CPU + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuEnableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Disables CPU interrupts. + + @param This Protocol instance structure + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU. + +**/ +EFI_STATUS +EFIAPI +CpuDisableInterrupt ( + IN EFI_CPU_ARCH_PROTOCOL *This + ); + +/** + Return the state of interrupts. + + @param This Protocol instance structure + @param State Pointer to the CPU's current interrupt st= ate + + @retval EFI_SUCCESS If interrupts were disabled in the CPU. + @retval EFI_INVALID_PARAMETER State is NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetInterruptState ( + IN EFI_CPU_ARCH_PROTOCOL *This, + OUT BOOLEAN *State + ); + +/** + Generates an INIT to the CPU. + + @param This Protocol instance structure + @param InitType Type of CPU INIT to perform + + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be + seen. + @retval EFI_DEVICE_ERROR If CPU INIT failed. + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. + +**/ +EFI_STATUS +EFIAPI +CpuInit ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_CPU_INIT_TYPE InitType + ); + +/** + Registers a function to be called from the CPU interrupt handler. + + @param This Protocol instance structure + @param InterruptType Defines which interrupt to hook. IA-32 + valid range is 0x00 through 0xFF + @param InterruptHandler A pointer to a function of type + EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. A null + pointer is an error condition. + + @retval EFI_SUCCESS If handler installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er + for InterruptType was previously installe= d. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or + InterruptType was not previously installe= d. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType + is not supported. + +**/ +EFI_STATUS +EFIAPI +CpuRegisterInterruptHandler ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ); + +/** + Returns a timer value from one of the CPU's internal timers. There is no + inherent time interval between ticks but is a function of the CPU freque= ncy. + + @param This - Protocol instance structure. + @param TimerIndex - Specifies which CPU timer is requested. + @param TimerValue - Pointer to the returned timer value. + @param TimerPeriod - A pointer to the amount of time that passes + in femtoseconds (10-15) for each increment + of TimerValue. If TimerValue does not + increment at a predictable rate, then 0 is + returned. The amount of time that has + passed between two calls to GetTimerValue() + can be calculated with the formula + (TimerValue2 - TimerValue1) * TimerPeriod. + This parameter is optional and may be NULL. + + @retval EFI_SUCCESS - If the CPU timer count was returned. + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers. + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer. + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL. + +**/ +EFI_STATUS +EFIAPI +CpuGetTimerValue ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN UINT32 TimerIndex, + OUT UINT64 *TimerValue, + OUT UINT64 *TimerPeriod OPTIONAL + ); + +/** + Set memory cacheability attributes for given range of memeory. + + @param This Protocol instance structure + @param BaseAddress Specifies the start address of the + memory range + @param Length Specifies the length of the memory range + @param Attributes The memory cacheability for the memory ra= nge + + @retval EFI_SUCCESS If the cacheability of that memory range = is + set successfully + @retval EFI_UNSUPPORTED If the desired operation cannot be done + @retval EFI_INVALID_PARAMETER The input parameter is not correct, + such as Length =3D 0 + +**/ +EFI_STATUS +EFIAPI +CpuSetMemoryAttributes ( + IN EFI_CPU_ARCH_PROTOCOL *This, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +#endif --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93277): https://edk2.groups.io/g/devel/message/93277 Mute This Topic: https://groups.io/mt/93506303/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 10 02:49:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93278+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93278+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1662484213; cv=none; d=zohomail.com; s=zohoarc; b=Y+F4/scsOoUex8Rbf4PoreW6fhmnvg9FG/6A+3Wnu2oU3CcvEfEV3za5c7YpBGAm1q1Ph3PeEV3lXSJnBntzF5LPKSLnAmHzQt0djDO9MvRCxB+tyjoL1xFxNITKR0S4UPgEpIENqLYu45TzIMKB9bNQMlIdJkpE3cbc0yj5d+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662484213; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=FZsR/tgAJfnnN2UzqWb5z++tb6PxKUgAkXAxJgtvz+c=; b=YYmkGp7wGC+vOUSpifNXP58uaZPfuSUUfy+x5cL0zHQfy/ATF1SfYVn7hT1OuhiLrt0pl5+0OCDjrA/XtiS1adOHmjkgJibu2CeXQ22Fef/EA/Uzw+h/596Ep20n5IpkhtLxBMjhjswDNL8RT8eLkLu2mbQ0l55CRq+p9WpbKPg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93278+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662484213218879.2195355526559; Tue, 6 Sep 2022 10:10:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id VPgWYY1788612xdmwWeMeG3D; Tue, 06 Sep 2022 10:10:11 -0700 X-Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web10.1933.1662484211232953545 for ; Tue, 06 Sep 2022 10:10:11 -0700 X-Received: by mail-pl1-f173.google.com with SMTP id 9so8706415plj.11 for ; Tue, 06 Sep 2022 10:10:11 -0700 (PDT) X-Gm-Message-State: zOS5D2ILofdwngb7VkSvLf5Ox1787277AA= X-Google-Smtp-Source: AA6agR5UlwpZQKrwuIhmwN8cmoARu1DdJpRoYTznAyEVDFjuv7kw9OFXn4ijtjsdd1FJw4/0kOZuyQ== X-Received: by 2002:a17:90b:1d8b:b0:200:5367:5ecd with SMTP id pf11-20020a17090b1d8b00b0020053675ecdmr13433924pjb.165.1662484210018; Tue, 06 Sep 2022 10:10:10 -0700 (PDT) X-Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:10:09 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [edk2-devel] [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module Date: Tue, 6 Sep 2022 22:38:37 +0530 Message-Id: <20220906170837.491525-18-sunilvl@ventanamicro.com> In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662484211; bh=lemiYfcUk5BIjKt4l9mMVNIR1r1kkfra41tqL+bfVmY=; h=Cc:Date:From:Reply-To:Subject:To; b=AAVoz02MbavvChdRAapGYV0AXXZ9gVeslyI5Wa5S9uYRSaCiMG5xsVyc7l1gZiv//2R QdkxtgZpKCVXDUgGYS6gp49MF32xk+1mrn75IvnBP/JJDMx4CkzbLc5ZVmL5XOlhV8oaZ aQ8rlaVML1aptG+BGecApWmXBBfc+frWFbs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662484215283100001 Content-Type: text/plain; charset="utf-8" This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Signed-off-by: Sunil V L --- .../Universal/TimerDxe/RiscV64/Timer.c | 293 ++++++++++++++++++ .../Universal/TimerDxe/RiscV64/Timer.h | 174 +++++++++++ MdeModulePkg/Universal/TimerDxe/Timer.uni | 15 + MdeModulePkg/Universal/TimerDxe/TimerDxe.inf | 52 ++++ .../Universal/TimerDxe/TimerExtra.uni | 13 + 5 files changed, 547 insertions(+) create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h create mode 100644 MdeModulePkg/Universal/TimerDxe/Timer.uni create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerDxe.inf create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerExtra.uni diff --git a/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c b/MdeModulePkg= /Universal/TimerDxe/RiscV64/Timer.c new file mode 100644 index 0000000000..4deb91766d --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c @@ -0,0 +1,293 @@ +/** @file + RISC-V Timer Architectural Protocol + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Timer.h" +#include +#include + +// +// The handle onto which the Timer Architectural Protocol will be installed +// +STATIC EFI_HANDLE mTimerHandle =3D NULL; + +// +// The Timer Architectural Protocol that this driver produces +// +EFI_TIMER_ARCH_PROTOCOL mTimer =3D { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +// +// Pointer to the CPU Architectural Protocol instance +// +EFI_CPU_ARCH_PROTOCOL *mCpu; + +// +// The notification function to call on every timer interrupt. +// A bug in the compiler prevents us from initializing this here. +// +STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; + +// +// The current period of the timer interrupt +// +STATIC UINT64 mTimerPeriod =3D 0; + +/** + Timer Interrupt Handler. + + @param InterruptType The type of interrupt that occured + @param SystemContext A pointer to the system context when the interru= pt occured +**/ + +VOID +EFIAPI +TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 RiscvTimer; + + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + if (mTimerNotifyFunction !=3D NULL) { + mTimerNotifyFunction (mTimerPeriod); + } + csr_clear(CSR_SIE, SIP_STIP); // Disable SMode timer int + csr_clear(CSR_SIP, SIP_STIP); + if (mTimerPeriod =3D=3D 0) { + gBS->RestoreTPL (OriginalTPL); + csr_clear(CSR_SIE, SIP_STIP); // Disable SMode timer int + return; + } + RiscvTimer =3D csr_read(CSR_TIME); + SbiSetTimer (RiscvTimer +=3D mTimerPeriod); + gBS->RestoreTPL (OriginalTPL); + csr_set(CSR_SIE, SIP_STIP); // enable SMode timer int +} + +/** + + This function registers the handler NotifyFunction so it is called every= time + the timer interrupt fires. It also passes the amount of time since the = last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS= is + returned. If the CPU does not support registering a timer interrupt han= dler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a h= andler + when a handler is already registered, then EFI_ALREADY_STARTED is return= ed. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ER= ROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fire= s. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so i= t can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support time= r interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a = handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a hand= ler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be reg= istered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", Notify= Function)); + mTimerNotifyFunction =3D NotifyFunction; + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 RiscvTimer; + + DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod)); + + if (TimerPeriod =3D=3D 0) { + mTimerPeriod =3D 0; + csr_clear(CSR_SIE, SIP_STIP); // disable timer int + return EFI_SUCCESS; + } + + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us + RiscvTimer =3D csr_read(CSR_TIME); + SbiSetTimer(RiscvTimer + mTimerPeriod); + + mCpu->EnableInterrupt(mCpu); + csr_set(CSR_SIE, SIP_STIP); // enable timer int + return EFI_SUCCESS; +} + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + *TimerPeriod =3D mTimerPeriod; + return EFI_SUCCESS; +} + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize the pointer to our notify function. + // + mTimerNotifyFunction =3D NULL; + + // + // Make sure the Timer Architectural Protocol is not already installed i= n the system + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid); + + // + // Find the CPU architectural protocol. + // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= ) &mCpu); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be disabled + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, 0); + ASSERT_EFI_ERROR (Status); + + // + // Install interrupt handler for RISC-V Timer. + // + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be enabled at its default period + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATI= ON); + ASSERT_EFI_ERROR (Status); + + // + // Install the Timer Architectural Protocol onto a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mTimerHandle, + &gEfiTimerArchProtocolGuid, &mTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h b/MdeModulePkg= /Universal/TimerDxe/RiscV64/Timer.h new file mode 100644 index 0000000000..32f56f8fe1 --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h @@ -0,0 +1,174 @@ +/** @file + RISC-V Timer Architectural Protocol definitions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include + +#include +#include + +#include +#include +#include +#include + +// +// RISC-V use 100us timer. +// The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units +// +#define DEFAULT_TIMER_TICK_DURATION 100000 + +extern VOID RiscvSetTimerPeriod (UINT32 TimerPeriod); + +// +// Function Prototypes +// +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +; + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +; + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +; + +#endif diff --git a/MdeModulePkg/Universal/TimerDxe/Timer.uni b/MdeModulePkg/Unive= rsal/TimerDxe/Timer.uni new file mode 100644 index 0000000000..07272a8a78 --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/Timer.uni @@ -0,0 +1,15 @@ +// /** @file +// +// Timer Arch protocol strings. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Timer driver that= provides Timer Arch protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "Timer driver that= provides Timer Arch protocol." diff --git a/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf b/MdeModulePkg/Un= iversal/TimerDxe/TimerDxe.inf new file mode 100644 index 0000000000..b291a1fcec --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf @@ -0,0 +1,52 @@ +## @file +# Timer Arch protocol module +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D Timer + MODULE_UNI_FILE =3D Timer.uni + FILE_GUID =3D 055DDAC6-9142-4013-BF20-FC2E5BC325C9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D TimerDriverInitialize +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + CpuLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[LibraryClasses.RISCV64] + RiscVSbiLib + +[Sources.RISCV64] + RiscV64/Timer.h + RiscV64/Timer.c + +[Protocols] + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiTimerArchProtocolGuid ## PRODUCES + +[Depex] + gEfiCpuArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + TimerExtra.uni diff --git a/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni b/MdeModulePkg/= Universal/TimerDxe/TimerExtra.uni new file mode 100644 index 0000000000..ad80afe267 --- /dev/null +++ b/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni @@ -0,0 +1,13 @@ +// /** @file +// Timer Localized Strings and Content +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Timer DXE Driver" --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93278): https://edk2.groups.io/g/devel/message/93278 Mute This Topic: https://groups.io/mt/93506306/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-