From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93232+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93232+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476810; cv=none; d=zohomail.com; s=zohoarc; b=k+dIB1TeODfvq+a7ifFd5E/5Xr+YMzAKLbiGczdcWhxTaar/2PnmeXV+geJ2hW2F3SpSj07UTsqOVtqn8Tk4S81Y5cK57ta1UOpHuG7ED7/LGV/lybUErIeossjrCmG7bwzizRvSVFhMIxZmUqTmPV9Ckr5kPzWVLworaKvVC18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476810; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Oz88aZ4GMYUQMLTjKyaVPy35b8aCdEPgFnYABek1sOM=; b=OP+BvE/2OaJqWOn3AWy86PzFhXIQHPi8ywNeAPJmkvvvf9rXBp2Ie4qb3fTn3hoK4sIrZyOby0+vl6C8qXm+f+5v/kghz/Pt/kcp+NbYSQ2y3wmWs4M8sJRtlliHWcSamghz8RUD6uFEJ67V51wnaVNkFNfpReGJMyTlYjWWeeo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93232+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166247681052142.66250110623639; Tue, 6 Sep 2022 08:06:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cKHpYY1788612xcoRSSlQbRz; Tue, 06 Sep 2022 08:06:50 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.248.1662476809473562870 for ; Tue, 06 Sep 2022 08:06:49 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 00FF261561; Tue, 6 Sep 2022 15:06:49 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6AE80C433C1; Tue, 6 Sep 2022 15:06:47 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 1/7] ArmPkg/ArmMmuLib: don't replace table entries with block entries Date: Tue, 6 Sep 2022 17:06:33 +0200 Message-Id: <20220906150639.157227-2-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: DSWprLSHKE1f1rrs8L8vbuYFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476810; bh=0732GoGqyrabaHeVYeIE+o9A+6ruRfyL4GnU75rbENw=; h=Cc:Date:From:Reply-To:Subject:To; b=C44nllVTDcLOJmBjQ117YQd7tgzedtq7BYrWYtV6A2Iq8TKHGsFfXmCq6XT4Q8SDAng nlEiqFoyAPjueJBx7ZUqSWMGz17pTpwNbEfUBVYSdQghokeHkVNES5nx8EXSfCPndiW8A FHTwlNlPJ5Auy0DkM98cPbgVd7hpBeYLs6c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476812199100005 Content-Type: text/plain; charset="utf-8" Drop the optimization that replaces table entries with block entries and frees the page tables in the subhierarchy that is being replaced. This rarely occurs in practice anyway, and will require more elaborate TLB maintenance once we switch to a different approach when running at EL1, where we no longer disable the MMU and nuke the TLB entirely every time we update a descriptor in a way that requires break-before-make (BBM). Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index e5ecc7375153..34f1031c4de3 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -197,12 +197,9 @@ UpdateRegionMappingRecursive ( // than a block, and recurse to create the block or page entries at // the next level. No block mappings are allowed at all at level 0, // so in that case, we have to recurse unconditionally. - // If we are changing a table entry and the AttributeClearMask is non-= zero, - // we cannot replace it with a block entry without potentially losing - // attribute information, so keep the table entry in that case. // if ((Level =3D=3D 0) || (((RegionStart | BlockEnd) & BlockMask) !=3D 0= ) || - (IsTableEntry (*Entry, Level) && (AttributeClearMask !=3D 0))) + IsTableEntry (*Entry, Level)) { ASSERT (Level < 3); =20 @@ -294,20 +291,7 @@ UpdateRegionMappingRecursive ( EntryValue |=3D (Level =3D=3D 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3 : TT_TYPE_BLOCK_ENTRY; =20 - if (IsTableEntry (*Entry, Level)) { - // - // We are replacing a table entry with a block entry. This is only - // possible if we are keeping none of the original attributes. - // We can free the table entry's page table, and all the ones below - // it, since we are dropping the only possible reference to it. - // - ASSERT (AttributeClearMask =3D=3D 0); - TranslationTable =3D (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOC= K_ENTRY); - ReplaceTableEntry (Entry, EntryValue, RegionStart, TRUE); - FreePageTablesRecursive (TranslationTable, Level + 1); - } else { - ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE); - } + ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE); } } =20 --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93232): https://edk2.groups.io/g/devel/message/93232 Mute This Topic: https://groups.io/mt/93503038/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93235+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93235+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476815; cv=none; d=zohomail.com; s=zohoarc; b=lpUz6taDX1DGgB0v9019fk1xpKKt9xFiTSx6dKW6rZlzvNT9XGJKENKnCC1cwMGYwPc309X5bpTmBhLMKbFVcDgU1FvZVWYFyTwNyZUu0dYZbgL50V7+sa50LfDDhy/wK4bmqsVQK430tV869OgYQo3YIR7uBWY15QGc18Okbk8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476815; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZlZ9DT/5Ulmvs6gHZwHF74CErUemzSSu/vLn8WUjxx4=; b=RZdNzXlr3Y8oVSJcNdsHR5sU51T7MoTxVHbqQQw/KzIZjngcC5zdmUbwmXRIgoCPmkvy0WG/7u6yuuWfk1TQ4IXFSBnW0fE1QTEUwsIdcHTy4uTRJyShLkh+GbZxUHHr1ZZs3NUPN9cYfOvcrUVUUUe0QcVpDOuN6NGELPQOPR8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93235+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166247681583384.1717587853584; Tue, 6 Sep 2022 08:06:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id k3c9YY1788612xeEFh9klwZt; Tue, 06 Sep 2022 08:06:55 -0700 X-Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web10.240.1662476814137499351 for ; Tue, 06 Sep 2022 08:06:54 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1AAF9B81916; Tue, 6 Sep 2022 15:06:51 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id D47AEC433B5; Tue, 6 Sep 2022 15:06:48 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 2/7] ArmPkg/ArmMmuLib: use shadow page tables for break-before-make at EL1 Date: Tue, 6 Sep 2022 17:06:34 +0200 Message-Id: <20220906150639.157227-3-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: tTS4v4RdSXsXJvfTU7G0CeKdx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476815; bh=4ctyBQzOYTyu5HwY+orXfGChPYOYJoZAIBsZtObB+7w=; h=Cc:Date:From:Reply-To:Subject:To; b=DYRpqq2RiuohnPFEApA/azgg59FH7KcUflnUI0syJbFK5QSd+qaGX69OvYKAo6G+BYj BRy3fkKMvCqj+UsuatojV9qWAt1xLyWqRYLAMDX8r/3tFIka+6V0Jx73ST5nB/k+Pzk4K gubW+7Gb8ApSh9icaI9lGFHCOwhb2LpOX8Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476816291100014 Content-Type: text/plain; charset="utf-8" When executing at EL1, disabling and re-enabling the MMU every time we need to replace a live translation entry is slightly problematic, given that memory accesses performed with the MMU off have non-cacheable attributes and are therefore non-coherent. On bare metal, we can deal with this by adding some barriers and cache invalidation instructions, but when running under virtualization, elaborate trapping and cache maintenance logic is necessary on the part of the hypervisor, and this is better avoided. So let's switch to a different approach when running at EL1, and use two sets of page tables with different ASIDs, and non-global attributes for all mappings. This allows us to switch between those sets without having to care about break-before-make, which means we can manipulate the primary translation while running from the secondary. To avoid splitting block mappings unnecessarily in the shadow page tables, add a special case to the recursive mapping routines to retain a block mapping that already covers a region that we are trying to map, and has the right attributes. Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 4 + ArmPkg/Include/Chipset/AArch64Mmu.h | 1 + ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 154 +++++++++++= ++++----- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 15 +- 4 files changed, 138 insertions(+), 36 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AA= rch64/Mmu.c index 8bb33046e707..d15eb158ad60 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -313,6 +313,10 @@ EfiAttributeToArmAttribute ( ArmAttributes |=3D TT_PXN_MASK; } =20 + if (ArmReadCurrentEL () =3D=3D AARCH64_EL1) { + ArmAttributes |=3D TT_NG; + } + return ArmAttributes; } =20 diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/A= Arch64Mmu.h index 2ea2cc0a874d..763dc53908e2 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -67,6 +67,7 @@ =20 #define TT_NS BIT5 #define TT_AF BIT10 +#define TT_NG BIT11 =20 #define TT_SH_NON_SHAREABLE (0x0 << 8) #define TT_SH_OUTER_SHAREABLE (0x2 << 8) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 34f1031c4de3..747ebc533511 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -25,23 +25,31 @@ ArmMemoryAttributeToPageAttribute ( IN ARM_MEMORY_REGION_ATTRIBUTES Attributes ) { + UINT64 NonGlobal; + + if (ArmReadCurrentEL () =3D=3D AARCH64_EL1) { + NonGlobal =3D TT_NG; + } else { + NonGlobal =3D 0; + } + switch (Attributes) { case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE: - return TT_ATTR_INDX_MEMORY_WRITE_BACK; + return TT_ATTR_INDX_MEMORY_WRITE_BACK | NonGlobal; =20 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: - return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; + return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE | NonG= lobal; =20 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH: - return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; + return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE | N= onGlobal; =20 // Uncached and device mappings are treated as outer shareable by defa= ult, case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED: - return TT_ATTR_INDX_MEMORY_NON_CACHEABLE; + return TT_ATTR_INDX_MEMORY_NON_CACHEABLE | NonGlobal; =20 default: ASSERT (0); @@ -50,7 +58,7 @@ ArmMemoryAttributeToPageAttribute ( if (ArmReadCurrentEL () =3D=3D AARCH64_EL2) { return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; } else { - return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; + return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK | TT= _NG; } } } @@ -203,7 +211,14 @@ UpdateRegionMappingRecursive ( { ASSERT (Level < 3); =20 - if (!IsTableEntry (*Entry, Level)) { + if (IsBlockEntry (*Entry, Level) && (AttributeClearMask =3D=3D 0) && + ((*Entry & TT_ATTRIBUTES_MASK) =3D=3D AttributeSetMask)) + { + // The existing block entry already covers the region we are + // trying to map with the correct attributes so no need to do + // anything here + continue; + } else if (!IsTableEntry (*Entry, Level)) { // // No table entry exists yet, so we need to allocate a page table // for the next level. @@ -304,7 +319,8 @@ UpdateRegionMapping ( IN UINT64 RegionStart, IN UINT64 RegionLength, IN UINT64 AttributeSetMask, - IN UINT64 AttributeClearMask + IN UINT64 AttributeClearMask, + IN UINT64 *RootTable ) { UINTN T0SZ; @@ -320,7 +336,7 @@ UpdateRegionMapping ( RegionStart + RegionLength, AttributeSetMask, AttributeClearMask, - ArmGetTTBR0BaseAddress (), + RootTable, GetRootTableLevel (T0SZ) ); } @@ -329,14 +345,26 @@ STATIC EFI_STATUS FillTranslationTable ( IN UINT64 *RootTable, - IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion, + IN BOOLEAN IsSecondary ) { + // + // Omit non-memory mappings from the shadow page tables, which only need= to + // cover system RAM. + // + if (IsSecondary && + (MemoryRegion->Attributes !=3D ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BAC= K)) + { + return EFI_SUCCESS; + } + return UpdateRegionMapping ( MemoryRegion->VirtualBase, MemoryRegion->Length, ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | = TT_AF, - 0 + 0, + RootTable ); } =20 @@ -380,6 +408,10 @@ GcdAttributeToPageAttribute ( PageAttributes |=3D TT_AP_NO_RO; } =20 + if (ArmReadCurrentEL () =3D=3D AARCH64_EL1) { + PageAttributes |=3D TT_NG; + } + return PageAttributes | TT_AF; } =20 @@ -390,8 +422,9 @@ ArmSetMemoryAttributes ( IN UINT64 Attributes ) { - UINT64 PageAttributes; - UINT64 PageAttributeMask; + UINT64 PageAttributes; + UINT64 PageAttributeMask; + EFI_STATUS Status; =20 PageAttributes =3D GcdAttributeToPageAttribute (Attributes); PageAttributeMask =3D 0; @@ -404,13 +437,36 @@ ArmSetMemoryAttributes ( PageAttributes &=3D TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; PageAttributeMask =3D ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | TT_PXN_MASK | TT_XN_MASK); + } else if ((ArmReadCurrentEL () =3D=3D AARCH64_EL1) && + ((PageAttributes & TT_ATTR_INDX_MASK) =3D=3D TT_ATTR_INDX_MEM= ORY_WRITE_BACK)) + { + // + // Update the shadow page tables if we are running at EL1 and are mapp= ing + // memory. This is needed because we may be adding memory that may be = used + // later on for allocating page tables, and these need to be shadowed = as + // well so we can update them safely. Strip the attributes so we don't + // fragment the shadow page tables unnecessarily. (Note that adding d= evice + // memory here and stripping the XN attributes would be bad, as it cou= ld + // result in speculative instruction fetches from MMIO regions.) + // + Status =3D UpdateRegionMapping ( + BaseAddress, + Length, + (PageAttributes & ~(TT_AP_MASK | TT_PXN_MASK | TT_UXN_MASK)= ) | TT_AP_NO_RW, + 0, + ArmGetTTBR0BaseAddress () + EFI_PAGE_SIZE + ); + if (EFI_ERROR (Status)) { + return Status; + } } =20 return UpdateRegionMapping ( BaseAddress, Length, PageAttributes, - PageAttributeMask + PageAttributeMask, + ArmGetTTBR0BaseAddress () ); } =20 @@ -423,7 +479,13 @@ SetMemoryRegionAttribute ( IN UINT64 BlockEntryMask ) { - return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryM= ask); + return UpdateRegionMapping ( + BaseAddress, + Length, + Attributes, + BlockEntryMask, + ArmGetTTBR0BaseAddress () + ); } =20 EFI_STATUS @@ -503,13 +565,15 @@ ArmConfigureMmu ( OUT UINTN *TranslationTableSize OPTIONAL ) { - VOID *TranslationTable; - UINTN MaxAddressBits; - UINT64 MaxAddress; - UINTN T0SZ; - UINTN RootTableEntryCount; - UINT64 TCR; - EFI_STATUS Status; + UINT64 *TranslationTable; + UINTN MaxAddressBits; + UINT64 MaxAddress; + UINTN T0SZ; + UINTN RootTableEntryCount; + UINT64 TCR; + EFI_STATUS Status; + ARM_MEMORY_REGION_DESCRIPTOR *MemTab; + UINTN NumRootPages; =20 if (MemoryTable =3D=3D NULL) { ASSERT (MemoryTable !=3D NULL); @@ -538,6 +602,8 @@ ArmConfigureMmu ( // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2 TCR =3D T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB; =20 + NumRootPages =3D 1; + // Set the Physical Address Size using MaxAddress if (MaxAddress < SIZE_4GB) { TCR |=3D TCR_PS_4GB; @@ -564,6 +630,8 @@ ArmConfigureMmu ( // Due to Cortex-A57 erratum #822227 we must set TG1[1] =3D=3D 1, rega= rdless of EPD1. TCR =3D T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1; =20 + NumRootPages =3D 2; + // Set the Physical Address Size using MaxAddress if (MaxAddress < SIZE_4GB) { TCR |=3D TCR_IPS_4GB; @@ -608,19 +676,11 @@ ArmConfigureMmu ( ArmSetTCR (TCR); =20 // Allocate pages for translation table - TranslationTable =3D AllocatePages (1); + TranslationTable =3D AllocatePages (NumRootPages); if (TranslationTable =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } =20 - // - // We set TTBR0 just after allocating the table to retrieve its location= from - // the subsequent functions without needing to pass this value across the - // functions. The MMU is only enabled after the translation tables are - // populated. - // - ArmSetTTBR0 (TranslationTable); - if (TranslationTableBase !=3D NULL) { *TranslationTableBase =3D TranslationTable; } @@ -637,15 +697,14 @@ ArmConfigureMmu ( TranslationTable, RootTableEntryCount * sizeof (UINT64) ); + ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64)); =20 - while (MemoryTable->Length !=3D 0) { - Status =3D FillTranslationTable (TranslationTable, MemoryTable); + for (MemTab =3D MemoryTable; MemTab->Length !=3D 0; MemTab++) { + Status =3D FillTranslationTable (TranslationTable, MemTab, FALSE); if (EFI_ERROR (Status)) { goto FreeTranslationTable; } - - MemoryTable++; } =20 // @@ -661,16 +720,41 @@ ArmConfigureMmu ( MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRI= TE_BACK) ); =20 + ArmSetTTBR0 (TranslationTable); + ArmDisableAlignmentCheck (); ArmEnableStackAlignmentCheck (); ArmEnableInstructionCache (); ArmEnableDataCache (); =20 ArmEnableMmu (); + + if (NumRootPages > 1) { + // + // Clone all memory ranges into the shadow page tables that we will use + // to temporarily switch to when manipulating live entries + // + ZeroMem ( + TranslationTable + TT_ENTRY_COUNT, + RootTableEntryCount * sizeof (UINT64) + ); + + for (MemTab =3D MemoryTable; MemTab->Length !=3D 0; MemTab++) { + Status =3D FillTranslationTable ( + TranslationTable + TT_ENTRY_COUNT, + MemTab, + TRUE + ); + if (EFI_ERROR (Status)) { + goto FreeTranslationTable; + } + } + } + return EFI_SUCCESS; =20 FreeTranslationTable: - FreePages (TranslationTable, 1); + FreePages (TranslationTable, NumRootPages); return Status; } =20 diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/Arm= Pkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S index 66ebca571e63..6929e081ed8d 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S @@ -59,7 +59,20 @@ ASM_FUNC(ArmReplaceLiveTranslationEntry) dsb nsh =20 EL1_OR_EL2_OR_EL3(x3) -1:__replace_entry 1 +1:mrs x8, ttbr0_el1 + add x9, x8, #0x1000 // advance to shadow page table + orr x9, x9, #1 << 48 // use different ASID for shadow translatio= ns + msr ttbr0_el1, x9 + isb + str x1, [x0] // install the entry and make it observeable + dsb ishst // to the page table walker + isb + lsr x2, x2, #12 + tlbi vae1is, x2 // invalidate the updated entry + dsb ish + isb + msr ttbr0_el1, x8 // switch back to original translation + isb b 4f 2:__replace_entry 2 b 4f --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93235): https://edk2.groups.io/g/devel/message/93235 Mute This Topic: https://groups.io/mt/93503043/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93233+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93233+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476813; cv=none; d=zohomail.com; s=zohoarc; b=m+2qPF1pWUJ7gaM/8arBAXWq5fIm23H0yu+ViobFhITDCT2nx1TkofwCNzr5ICrvpgZNeVURErVJ0GX2lmXu1JBLFBhJ721an0xNpDgV01jSI7lpiwoT29jHPpi+HMDOC3PDDCagOFpL50yVAxDVcPcSi8yYvRdvc0vZWl2pcko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476813; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=E5kMzsQ4S0A9SKAAN9J1jRIFx7Tqla3NxV4Pi6hEO6w=; b=P+FmVOMfJGPJm4TwbeFzD8GlnvzLpaHf/8uONBR4aYtGTOPC1jNIgM9TJIvKX6xsbkmeFAS5flAgoBUc0zGUSs+4w2/W0btFOqtsNvnsoXG1ZrnAIHGVJCx4NBj8rEk7tfzAruueG7Bxd9xXGtYnkGPf1bnwx4wZCES5YPuAOKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93233+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662476813761522.727718160466; Tue, 6 Sep 2022 08:06:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 03GrYY1788612x1TzbmjgGh9; Tue, 06 Sep 2022 08:06:53 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web08.240.1662476812674215756 for ; Tue, 06 Sep 2022 08:06:52 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DFA2061561; Tue, 6 Sep 2022 15:06:51 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C492C433C1; Tue, 6 Sep 2022 15:06:50 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 3/7] ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled Date: Tue, 6 Sep 2022 17:06:35 +0200 Message-Id: <20220906150639.157227-4-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: YoLRta2bX1M5AAp5UQxxRQnvx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476813; bh=rWhcu5h2tvuH5fylkxSHmXwaxg71qlkr3HhGC2Ank/s=; h=Cc:Date:From:Reply-To:Subject:To; b=O5xOkTNjRf788RGVgC2yxs4qVkpPF4FLT2+kDyskeMhz18THH4ikIs0EJ7GvsvlNsaf Z48Nc9qFImqf3FTPM0xhN4lfZnCddMRiFk8zTolANCMgBU+/UtFRCpcF/ndrpweBascs5 kFku2hu9yYbCb6SgAK4XZwCaBC9lIgmT0uQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476814444100009 Content-Type: text/plain; charset="utf-8" Permit the use of this library with the MMU and caches already enabled. This removes the need for any cache maintenance for coherency, and is generally better for robustness and performance, especially when running under virtualization. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 30 +++++++++++--------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 747ebc533511..ebd39ab4a657 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -689,14 +689,16 @@ ArmConfigureMmu ( *TranslationTableSize =3D RootTableEntryCount * sizeof (UINT64); } =20 - // - // Make sure we are not inadvertently hitting in the caches - // when populating the page tables. - // - InvalidateDataCacheRange ( - TranslationTable, - RootTableEntryCount * sizeof (UINT64) - ); + if (!ArmMmuEnabled ()) { + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange ( + TranslationTable, + RootTableEntryCount * sizeof (UINT64) + ); + } =20 ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64)); =20 @@ -722,12 +724,14 @@ ArmConfigureMmu ( =20 ArmSetTTBR0 (TranslationTable); =20 - ArmDisableAlignmentCheck (); - ArmEnableStackAlignmentCheck (); - ArmEnableInstructionCache (); - ArmEnableDataCache (); + if (!ArmMmuEnabled ()) { + ArmDisableAlignmentCheck (); + ArmEnableStackAlignmentCheck (); + ArmEnableInstructionCache (); + ArmEnableDataCache (); =20 - ArmEnableMmu (); + ArmEnableMmu (); + } =20 if (NumRootPages > 1) { // --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93233): https://edk2.groups.io/g/devel/message/93233 Mute This Topic: https://groups.io/mt/93503039/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93234+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93234+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476815; cv=none; d=zohomail.com; s=zohoarc; b=YpUowBjFLFfe+hBvMLM6SIu3HFfBrSWXOZQpvRTmxc8HdlLA7b4fjiKS2rHMjM+TtD8QPlEpecgJ93xYTh+2z6NFW4bakfxD3TsCrXpMmTWhbsz0W2wq+Obj57E2Zcdf5dVATADGNtwj5i04c6QwOWe2ou8D7YNQ8nrn6kzNxjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476815; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=w8i6kDtxPoE62IJYzOW9OrjkSw1oDpqxdq+nQn4RlLg=; b=lGzLVsjLmTZwhkcZYLj9K9BC9i8Ux9g9Ap3JK1EyEbYuWZ1BS9hGVN+XTnBRpkShCcZ10RbeuES1iutIfH0K/IctCelb/1g9mmZSXGPd6osP/Q8wguzE1lq0uVRDmOss+7INBcTF6bZK1tB/buqXp7WCO0fQhC4+ReuaH/OeD4Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93234+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662476815438476.42511476425307; Tue, 6 Sep 2022 08:06:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id L9w3YY1788612xWAkbZ0P0sx; Tue, 06 Sep 2022 08:06:55 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.249.1662476813719122373 for ; Tue, 06 Sep 2022 08:06:53 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E440C61584; Tue, 6 Sep 2022 15:06:52 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id B53A0C433B5; Tue, 6 Sep 2022 15:06:51 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 4/7] ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled Date: Tue, 6 Sep 2022 17:06:36 +0200 Message-Id: <20220906150639.157227-5-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: KW2YrqInbwWprqCeGxHcAB73x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476815; bh=JynlRAIFK55/NUhBl8ikW7vnqdiqHLx5xyKxQXhIBDw=; h=Cc:Date:From:Reply-To:Subject:To; b=pDkMXeA+149E5cwryyIczG/gckyzjzPxsssNjXnCbKjM+8Vyz6MYAopWczBrLTNJRoX UVs/l1zDxGpfnuD9H/g56aFRqUhtYVzwK56u7XtgX92+0vnble2H6nYnssM8mlhgR5PcE t7qVnw+I9eoVCiAxbkw9+32cmos5//er4Gs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476816242100013 Content-Type: text/plain; charset="utf-8" Some platforms may set up a preliminary ID map in flash and enter EFI with the MMU and caches enabled, as this removes a lot of the complexity around cache coherency. Let's take this into account, and avoid touching the MMU controls or perform cache invalidation when the MMU is enabled at entry. Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 22 +++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePei= Core/PrePeiCore.c index 9c4b25df953d..8b86c6e69abd 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -58,17 +58,19 @@ CEntryPoint ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - // Data Cache enabled on Primary core when MMU is enabled. - ArmDisableDataCache (); - // Invalidate instruction cache - ArmInvalidateInstructionCache (); - // Enable Instruction Caches on all cores. - ArmEnableInstructionCache (); + if (!ArmMmuEnabled ()) { + // Data Cache enabled on Primary core when MMU is enabled. + ArmDisableDataCache (); + // Invalidate instruction cache + ArmInvalidateInstructionCache (); + // Enable Instruction Caches on all cores. + ArmEnableInstructionCache (); =20 - InvalidateDataCacheRange ( - (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), - PcdGet32 (PcdCPUCorePrimaryStackSize) - ); + InvalidateDataCacheRange ( + (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), + PcdGet32 (PcdCPUCorePrimaryStackSize) + ); + } =20 // // Note: Doesn't have to Enable CPU interface in non-secure world, --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93234): https://edk2.groups.io/g/devel/message/93234 Mute This Topic: https://groups.io/mt/93503042/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93236+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93236+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476817; cv=none; d=zohomail.com; s=zohoarc; b=Hw008kTBd15UMvWoxtEq/ppGpwkJELbN0T7TKYsY0cgFtQ73jUKgaMR9g4E1CbnThIqFmT2/hgCVNqzkUWI1/nqlo93Q7Xw2U+dTjdNz7OZ5TxyJz0uJCcJrfATkqfE+GBXx32kJXcWNBfrRRojKqLAfHq/57uYp7Dv1iD+OpiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476817; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=uoSOdKdqlUbsyacdbMFz6LHO5HglCCL/REN+XxK5120=; b=Bk92dxQPCSBzMGFGkiG0JwE3x2WUBOEYsmd2T1Loa6k4LECIdcONlnBbf9/CJNZVZlmFQ6b/radl32B9LtRbS31uCbyQI33smVsiEb3soH1nqBpcU8/6Zl/RlYEr6XVKEz4xBea2xvMSWpFCvizgDxtQXmb3JYAvC5qTz7lrPeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93236+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662476817585842.4187214168603; Tue, 6 Sep 2022 08:06:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HsReYY1788612xXaQSbw8S8y; Tue, 06 Sep 2022 08:06:56 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web09.250.1662476815343980903 for ; Tue, 06 Sep 2022 08:06:55 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B9D3F6156C; Tue, 6 Sep 2022 15:06:54 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2B293C433C1; Tue, 6 Sep 2022 15:06:53 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 5/7] ArmVirtPkg/ArmVirtQemu: implement ArmPlatformLib with static ID map Date: Tue, 6 Sep 2022 17:06:37 +0200 Message-Id: <20220906150639.157227-6-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: zAlzD248BOnLr70YAK5eV2Ywx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476816; bh=/FxRU8WTFlpa0C47l3wlos7YsmevHr5j05T0hmXrQvQ=; h=Cc:Date:From:Reply-To:Subject:To; b=pD9E13zansvhHwGjNdI5Ye2whtNd2m2J3nekN6Ap8EBcB2IFrkr4deG/ZrAbcC7J047 c81LgWuANp3C1ZnN6FLxNOYLgGcoQgjNyXKWrBvYc/Ygb7q2qHXbwY3rorZSWX87FxtoG rAUUbLzTmKbGLScS9dD+wywR0TIK1UiWI9k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476818313100024 Content-Type: text/plain; charset="utf-8" To substantially reduce the amount of processing that takes place with the MMU and caches off, implement a version of ArmPlatformLib specific for QEMU/mach-virt in AArch64 mode that carries a statically allocated and populated ID map that covers the NOR flash and device region, and 128 MiB of DRAM at the base of memory (0x4000_0000). Note that 128 MiB has always been the minimum amount of DRAM we support for this configuration, and the existing code already ASSERT()s in DEBUG mode when booting with less. Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S | 111 ++= ++++++++++++++++++ ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.c | 64 ++= +++++++++ ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf | 40 ++= +++++ ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S | 57 ++= ++++++++ 4 files changed, 272 insertions(+) diff --git a/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelpe= r.S b/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S new file mode 100644 index 000000000000..7b78e2928710 --- /dev/null +++ b/ArmVirtPkg/Library/ArmPlatformLibQemu/AArch64/ArmPlatformHelper.S @@ -0,0 +1,111 @@ +// +// Copyright (c) 2022, Google LLC. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// + +#include + + .macro mov_i, reg:req, imm:req + movz \reg, :abs_g3:\imm + movk \reg, :abs_g2_nc:\imm + movk \reg, :abs_g1_nc:\imm + movk \reg, :abs_g0_nc:\imm + .endm + + .set MAIR_DEV_nGnRnE, 0x00 + .set MAIR_MEM_NC, 0x44 + .set MAIR_MEM_WT, 0xbb + .set MAIR_MEM_WBWA, 0xff + .set mairval, MAIR_DEV_nGnRnE | (MAIR_MEM_NC << 8) | (MAIR_MEM_WT << 1= 6) | (MAIR_MEM_WBWA << 24) + + .set TCR_TG0_4KB, 0x0 << 14 + .set TCR_TG1_4KB, 0x2 << 30 + .set TCR_IPS_SHIFT, 32 + .set TCR_EPD1, 0x1 << 23 + .set TCR_SH_INNER, 0x3 << 12 + .set TCR_RGN_OWB, 0x1 << 10 + .set TCR_RGN_IWB, 0x1 << 8 + .set tcrval, TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1 | TCR_RGN_OWB + .set tcrval, tcrval | TCR_RGN_IWB | TCR_SH_INNER + + .set SCTLR_ELx_I, 0x1 << 12 + .set SCTLR_ELx_SA, 0x1 << 3 + .set SCTLR_ELx_C, 0x1 << 2 + .set SCTLR_ELx_M, 0x1 << 0 + .set SCTLR_EL1_SPAN, 0x1 << 23 + .set SCTLR_EL1_WXN, 0x1 << 19 + .set SCTLR_EL1_SED, 0x1 << 8 + .set SCTLR_EL1_ITD, 0x1 << 7 + .set SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0= x1 << 28) | (0x1 << 29) + .set sctlrval, SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_IT= D | SCTLR_EL1_SED + .set sctlrval, sctlrval | SCTLR_ELx_I | SCTLR_EL1_SPAN | SCTLR_EL1_RES1 + + +ASM_FUNC(ArmPlatformPeiBootAction) + mov_i x0, mairval + mov_i x1, tcrval + adrp x2, idmap + orr x2, x2, #0xff << 48 // set non-zero ASID + mov_i x3, sctlrval + + mrs x6, id_aa64mmfr0_el1 // get the supported PA range + and x6, x6, #0xf // isolate PArange bits + cmp x6, #6 // 0b0110 =3D=3D 52 bits + sub x6, x6, #1 // subtract 1 + cinc x6, x6, ne // add back 1 unless PArange =3D=3D 52 bi= ts + bfi x1, x6, #32, #3 // copy updated PArange into TCR_EL1.IPS + + cmp x6, #3 // 0b0011 =3D=3D 42 bits + sub x6, x6, #1 // subtract 1 + cinc x6, x6, lt // add back 1 unless VA range >=3D 42 + + mov x7, #32 + sub x6, x7, x6, lsl #2 // T0SZ for PArange !=3D 42 + mov x7, #64 - 42 // T0SZ for PArange =3D=3D 42 + csel x6, x6, x7, ne + orr x1, x1, x6 // set T0SZ field in TCR + + cmp x6, #64 - 40 // VA size < 40 bits? + add x4, x2, #0x1000 // advance to level 1 descriptor + csel x2, x4, x2, gt + + msr mair_el1, x0 // set up the 1:1 mapping + msr tcr_el1, x1 + msr ttbr0_el1, x2 + isb + + tlbi vmalle1 // invalidate any cached translations + ic iallu // invalidate the I-cache + dsb nsh + isb + + msr sctlr_el1, x3 // enable MMU and caches + isb + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + mov x0, xzr + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + mov x0, #1 + ret diff --git a/ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.c b/A= rmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.c new file mode 100644 index 000000000000..1de80422ee4c --- /dev/null +++ b/ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.c @@ -0,0 +1,64 @@ +/** @file + + Copyright (c) 2011-2012, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Return the current Boot Mode. + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world. + + This function is called by the ArmPlatformPkg/PrePi or + ArmPlatformPkg/PlatformPei in the PEI phase. + + @param[in] MpId ID of the calling CPU + + @return RETURN_SUCCESS unless the operation failed +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +/** + Return the Platform specific PPIs. + + This function exposes the Platform Specific PPIs. They can be used by any + PrePi modules or passed to the PeiCore by PrePeiCore. + + @param[out] PpiListSize Size in Bytes of the Platform PPI List + @param[out] PpiList Platform PPI List + +**/ +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D 0; + *PpiList =3D NULL; +} diff --git a/ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf b= /ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf new file mode 100644 index 000000000000..b2ecdfa061cb --- /dev/null +++ b/ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.inf @@ -0,0 +1,40 @@ +## @file +# ArmPlatformLib implementation for QEMU/mach-virt on AArch64 that contai= ns a +# statically allocated 1:1 mapping of the first 128 MiB of DRAM, as well = as +# the NOR flash and the device region +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2022, Google LLC. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D ArmPlatformLibQemu + FILE_GUID =3D 40af3a25-f02c-4aef-94ef-7ac0282d21d4 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + DebugLib + +[Sources.common] + ArmPlatformLibQemu.c + IdMap.S + +[Sources.AArch64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S b/ArmVirtPkg/Lib= rary/ArmPlatformLibQemu/IdMap.S new file mode 100644 index 000000000000..4a4b7b77ed83 --- /dev/null +++ b/ArmVirtPkg/Library/ArmPlatformLibQemu/IdMap.S @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-2-Clause-Patent +// Copyright 2022 Google LLC +// Author: Ard Biesheuvel + + .set TT_TYPE_BLOCK, 0x1 + .set TT_TYPE_PAGE, 0x3 + .set TT_TYPE_TABLE, 0x3 + + .set TT_AF, 0x1 << 10 + .set TT_NG, 0x1 << 11 + .set TT_RO, 0x2 << 6 + .set TT_XN, 0x3 << 53 + + .set TT_MT_DEV, 0x0 << 2 // MAIR #0 + .set TT_MT_MEM, (0x3 << 2) | (0x3 << 8) // MAIR #3 + + .set PAGE_XIP, TT_TYPE_PAGE | TT_MT_MEM | TT_AF | TT_RO | TT_NG + .set BLOCK_DEV, TT_TYPE_BLOCK | TT_MT_DEV | TT_AF | TT_XN | TT_NG + .set BLOCK_MEM, TT_TYPE_BLOCK | TT_MT_MEM | TT_AF | TT_XN | TT_NG + + .globl idmap + .section ".rodata.idmap", "a", %progbits + .align 12 + +idmap: /* level 0 */ + .quad 1f + TT_TYPE_TABLE + .fill 511, 8, 0x0 + +1: /* level 1 */ + .quad 20f + TT_TYPE_TABLE // 1 GB of flash and device mapp= ings + .quad 21f + TT_TYPE_TABLE // up to 1 GB of DRAM + .fill 510, 8, 0x0 // 510 GB of remaining VA space + +20: /* level 2 */ + .quad 3f + TT_TYPE_TABLE // up to 2 MB of flash + .fill 63, 8, 0x0 // 126 MB of unused flash + .set idx, 64 + .rept 448 + .quad BLOCK_DEV | (idx << 21) // 896 MB of RW- device mappings + .set idx, idx + 1 + .endr + +21: /* level 2 */ + .set idx, 0x40000000 >> 21 + .rept 64 + .quad BLOCK_MEM | (idx << 21) // 128 MB of RW- memory mappings + .set idx, idx + 1 + .endr + .fill 448, 8, 0x0 + +3: /* level 3 */ + .quad 0x0 // omit first 4k page + .set idx, 1 + .rept 511 + .quad PAGE_XIP | (idx << 12) // 2044 KiB of R-X flash mappings + .set idx, idx + 1 + .endr --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93236): https://edk2.groups.io/g/devel/message/93236 Mute This Topic: https://groups.io/mt/93503044/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93237+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93237+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476817; cv=none; d=zohomail.com; s=zohoarc; b=YiYikTJ4F4I5ew95T+2H4j1y4HbFY6gPM1N02TvMkB4i5Drzh2rx+S3lcfblU7I23aoM3lwiZOxLzhZhiSjYrI3VGSV9YYN7sp+Y1Gh8UNhScTCEilP2/J7qBTxU/VM3+kN05sX+GXVWJMOeTSTeWBI8ZvyIg+kSvrirzjQ1bL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476817; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3gCk4ekzU+hZMqSTtYLCxFGJuXEHMHCTK26O09DYMak=; b=HJDRH1GitNL60ym92hg/nl62LMiuF+GvjNixeeGenMHjPvBvC2olN9FFfWjRK2mCXpNesSy73Ih3NQoM7+Tcb2SkaETKEGMgUnyJl2dGzkSxWj8jG8yqb4UGV49viJG/fNyJjPUfx79MYJmzqHNmcwl9AJogQNPhg2eaTXioYIc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93237+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662476817845266.7858517860923; Tue, 6 Sep 2022 08:06:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SViyYY1788612xVeQgnqeJu0; Tue, 06 Sep 2022 08:06:57 -0700 X-Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web10.241.1662476816790671295 for ; Tue, 06 Sep 2022 08:06:56 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2C73D6154C; Tue, 6 Sep 2022 15:06:56 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9471FC433D6; Tue, 6 Sep 2022 15:06:54 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 6/7] ArmVirtPkg/ArmVirtQemu: use first 128 MiB as permanent PEI memory Date: Tue, 6 Sep 2022 17:06:38 +0200 Message-Id: <20220906150639.157227-7-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: khwRk7b7Iy2ViTfMjV1Qm2uSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476817; bh=xTrBL/BRVh+8EJ8UHV3dAAO5mm2UYKtQVgY4LMGgPk0=; h=Cc:Date:From:Reply-To:Subject:To; b=WM2HSrnlFrm7Wl0tQoP0sLlWx2nhqLD9cab3D5PpTwG0es9tayAfoDTvg8O8vikOlDy MezP79ow3pC2ooZWAQIsoT/K0a/6Abp0J/eMY6RGOqUrc9VIVkK3oFhPaA0iVKCDHGybX MJEvzMa1Gy0ZRGqvKd5awF1tmz29n2LzkYQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476818298100023 Content-Type: text/plain; charset="utf-8" In order to allow booting with the MMU and caches enabled really early, we need to ensure that the code that populates the page tables can access those page tables with the statically defined ID map active. So let's put the permanent PEI RAM in the first 128 MiB of memory, which we will cover with this initial ID map (as it is the minimum supported DRAM size for ArmVirtQemu). Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/MemoryInitPei/MemoryInitPeim.c | 105 ++++++++++++++++++++ ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf | 68 +++++++++++++ 2 files changed, 173 insertions(+) diff --git a/ArmVirtPkg/MemoryInitPei/MemoryInitPeim.c b/ArmVirtPkg/MemoryI= nitPei/MemoryInitPeim.c new file mode 100644 index 000000000000..d61fa55efaaa --- /dev/null +++ b/ArmVirtPkg/MemoryInitPei/MemoryInitPeim.c @@ -0,0 +1,105 @@ +/** @file + + Copyright (c) 2011, ARM Limited. All rights reserved. + Copyright (c) 2022, Google LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ); + +/** + Build the memory type information HOB that describes how many pages of e= ach + type to preallocate when initializing the GCD memory map. +**/ +VOID +EFIAPI +BuildMemoryTypeInformationHob ( + VOID + ) +{ + EFI_MEMORY_TYPE_INFORMATION Info[10]; + + Info[0].Type =3D EfiACPIReclaimMemory; + Info[0].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory); + Info[1].Type =3D EfiACPIMemoryNVS; + Info[1].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS); + Info[2].Type =3D EfiReservedMemoryType; + Info[2].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiReservedMemoryType); + Info[3].Type =3D EfiRuntimeServicesData; + Info[3].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiRuntimeServicesData); + Info[4].Type =3D EfiRuntimeServicesCode; + Info[4].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiRuntimeServicesCode); + Info[5].Type =3D EfiBootServicesCode; + Info[5].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiBootServicesCode); + Info[6].Type =3D EfiBootServicesData; + Info[6].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiBootServicesData); + Info[7].Type =3D EfiLoaderCode; + Info[7].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiLoaderCode); + Info[8].Type =3D EfiLoaderData; + Info[8].NumberOfPages =3D PcdGet32 (PcdMemoryTypeEfiLoaderData); + + // Terminator for the list + Info[9].Type =3D EfiMaxMemoryType; + Info[9].NumberOfPages =3D 0; + + BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, &Info, sizeof (Info)); +} + +/** + Module entry point. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS unless the operation failed. +**/ +EFI_STATUS +EFIAPI +InitializeMemory ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + UINTN UefiMemoryBase; + EFI_STATUS Status; + + ASSERT (PcdGet64 (PcdSystemMemorySize) >=3D SIZE_128MB); + ASSERT (PcdGet64 (PcdSystemMemoryBase) < (UINT64)MAX_ALLOC_ADDRESS); + + // + // Put the permanent PEI memory in the first 128 MiB of DRAM so that + // it is covered by the statically configured ID map. + // + UefiMemoryBase =3D (UINTN)PcdGet64 (PcdSystemMemoryBase) + SIZE_128MB + - FixedPcdGet32 (PcdSystemMemoryUefiRegionSize); + + Status =3D PeiServicesInstallPeiMemory ( + UefiMemoryBase, + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MemoryPeim ( + UefiMemoryBase, + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf b/ArmVirtPkg/Memor= yInitPei/MemoryInitPeim.inf new file mode 100644 index 000000000000..f4492719c350 --- /dev/null +++ b/ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf @@ -0,0 +1,68 @@ +## @file +# Implementation of MemoryInitPeim that uses the first 128 MiB at the bas= e of +# DRAM as permanent PEI memory +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2022, Google LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D MemoryInit + FILE_GUID =3D 0fbffd44-f98f-4e1c-9922-e9b21f13c3f8 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeMemory + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM +# + +[Sources] + MemoryInitPeim.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + PeimEntryPoint + DebugLib + HobLib + ArmLib + ArmPlatformLib + MemoryInitPeiLib + +[Guids] + gEfiMemoryTypeInformationGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93237): https://edk2.groups.io/g/devel/message/93237 Mute This Topic: https://groups.io/mt/93503046/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 12 07:39:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93238+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93238+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1662476821; cv=none; d=zohomail.com; s=zohoarc; b=JisggaaKxeH/zAuakRXtjH43tea1S9wjFbbTB9UcdgxQ4JithD57VBPxYTNGIat8/nsuk9ASSlTHx7AJcN8+7/ykETMN7XTTv0t4m7Kvvi2Ej4ezSZVml4KROpjdVeL7PSWVTO2nwU/nhJMzdqbEWPulBYy+v/livGf2cm66I3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662476821; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=fjUTePSaNDtrLR1kimeSRVE2vhJLAjh4DX8/WCTw4uE=; b=jYO6qZebPC5pHQMiIY41Ogi+p8wQp1FDqhwiG8XxOhYgjuu9SzgYUP5TKb8FqkzEol5Bnnlbm/9gREsArMrEwiIOGB7GRfnl60R/mKPIage7ZP5hPlbHUPKHj6NzzWwctUA+x4xeWKrvaSzNcw2dKfkhIkgmwLYu8RQfm1kUI+U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93238+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166247682158211.765154425753167; Tue, 6 Sep 2022 08:07:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OgvRYY1788612xaFoYYQcbCc; Tue, 06 Sep 2022 08:07:01 -0700 X-Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web11.251.1662476820207519776 for ; Tue, 06 Sep 2022 08:07:00 -0700 X-Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 45FC9B81908; Tue, 6 Sep 2022 15:06:58 +0000 (UTC) X-Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B7B8C43470; Tue, 6 Sep 2022 15:06:55 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 7/7] ArmVirtPkg/ArmVirtQemu: enable initial ID map at early boot Date: Tue, 6 Sep 2022 17:06:39 +0200 Message-Id: <20220906150639.157227-8-ardb@kernel.org> In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ardb@kernel.org X-Gm-Message-State: 9qFs6lYeBj9iSSd3YSaVzGzVx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662476821; bh=MzXBNTVaNbwDsjSHyUTKTHkUxtBYEhNkhOdnNdhw++0=; h=Cc:Date:From:Reply-To:Subject:To; b=RauMsQnUqtRft1aOGw3W4tv9+P5HZdgyqcBPYri3KrrfPRJofhF9SdymD3vy10bFC0l eHzmGYLxCLRKHOr7vbv1DW7I3whnJ+AXDyXwFu9EjwzDx7JjrvKTG/yJmDJJqj5FtgiWn aqAlmeUpzoUMxKqlIjQQ3zGX6jjMa6wkt74= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662476822311100001 Content-Type: text/plain; charset="utf-8" Now that we have all the pieces in place, switch the AArch64 version of ArmVirtQemu to a mode where the first thing it does out of reset is enable a preliminary ID map that covers the NOR flash and sufficient DRAM to create the UEFI page tables as usual. The advantage of this is that no manipulation of memory occurs any longer before the MMU is enabled, which removes the need for explicit coherency management, which is cumbersome and bad for performance. It also means we no longer need to build all components that may execute with the MMU off (including BASE libraries) with strict alignment. Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/ArmVirtQemu.dsc | 12 +++++++++--- ArmVirtPkg/ArmVirtQemu.fdf | 2 +- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc index 302c0d2a4e29..2bf360d1b87b 100644 --- a/ArmVirtPkg/ArmVirtQemu.dsc +++ b/ArmVirtPkg/ArmVirtQemu.dsc @@ -63,8 +63,6 @@ [LibraryClasses.common] QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFw= CfgSimpleParserLib.inf QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf =20 - ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibN= ull.inf - TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf NorFlashPlatformLib|ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.i= nf =20 @@ -92,6 +90,12 @@ [LibraryClasses.common] TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi= bNull/PeiDxeTpmPlatformHierarchyLib.inf !endif =20 +[LibraryClasses.AARCH64] + ArmPlatformLib|ArmVirtPkg/Library/ArmPlatformLibQemu/ArmPlatformLibQemu.= inf + +[LibraryClasses.ARM] + ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibN= ull.inf + [LibraryClasses.common.PEIM] ArmVirtMemInfoLib|ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoP= eiLib.inf =20 @@ -112,6 +116,8 @@ [LibraryClasses.common.UEFI_DRIVER] UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf =20 [BuildOptions] + GCC:*_*_AARCH64_CC_XIPFLAGS =3D -mno-strict-align + !include NetworkPkg/NetworkBuildOptions.dsc.inc =20 ##########################################################################= ###### @@ -310,7 +316,7 @@ [Components.common] PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf } ArmPlatformPkg/PlatformPei/PlatformPeim.inf - ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf ArmPkg/Drivers/CpuPei/CpuPei.inf =20 MdeModulePkg/Universal/Variable/Pei/VariablePei.inf diff --git a/ArmVirtPkg/ArmVirtQemu.fdf b/ArmVirtPkg/ArmVirtQemu.fdf index b5e2253295fe..7f17aeb3ad0d 100644 --- a/ArmVirtPkg/ArmVirtQemu.fdf +++ b/ArmVirtPkg/ArmVirtQemu.fdf @@ -107,7 +107,7 @@ [FV.FVMAIN_COMPACT] INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf INF MdeModulePkg/Core/Pei/PeiMain.inf INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf - INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmVirtPkg/MemoryInitPei/MemoryInitPeim.inf INF ArmPkg/Drivers/CpuPei/CpuPei.inf INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf --=20 2.35.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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