From nobody Sun May 12 05:13:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93138+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93138+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1662367786; cv=none; d=zohomail.com; s=zohoarc; b=VZGjExlOfQpcv4jH7zINNU4w0e89hSqoRXtfMNfaiuofCPoK6lnzVUTa0IXSWgLf6MO4m+kp+nT0Wp/nJodgZCfh/rilDMzJTy3ihaEuAoEoXcsc14qiK/ptt1/vxi5vVJCmlwG4L+A2vHc01DqgkSB+xHHUu+bR0a+216Bs+1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662367786; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=uBnh/G4Du7Bq4ssGxfiDCBePKLE6QoLGEaO7fpX7QYk=; b=cAMxWlU/fRk1SKXtjcDh0Q474XIJp4aRp+zhigsCTJ28/RQ8R4SlSJk9XCZcyhWvhxZxtldSgt1Bs86M6W3FGTU9JXKJmedJ20U9hNumvw275snukuxTukTby83xEMELo5cPwcahEI7ri3eXWyWeoYB432G5uGGvnwc4Q6fHXYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93138+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662367786370289.33541874137507; Mon, 5 Sep 2022 01:49:46 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id akmuYY1788612xEYmdRPJwF1; Mon, 05 Sep 2022 01:49:45 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.22740.1662367784835192573 for ; Mon, 05 Sep 2022 01:49:45 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10460"; a="296345763" X-IronPort-AV: E=Sophos;i="5.93,290,1654585200"; d="scan'208";a="296345763" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2022 01:49:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,290,1654585200"; d="scan'208";a="590839558" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by orsmga006.jf.intel.com with ESMTP; 05 Sep 2022 01:49:42 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Jenny Huang , Ray Ni , Rangasai V Chaganty , Robert Kowalewski Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when change TTM Date: Mon, 5 Sep 2022 16:49:28 +0800 Message-Id: <20220905084928.636-1-w.sheng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com X-Gm-Message-State: c9kQI7mrCt5t8WnqK5KUwxvpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662367785; bh=J7PPaqwFPZzQ/uW0xBG/TH/1VjW0F1RTl6VI0bDh0wA=; h=Cc:Date:From:Reply-To:Subject:To; b=OKi5R/oNuKYEXXBmdu60QA1WQXbpn6kkvKL0dIyQAKTPl/AgXpEDS+lzE14AEJyo1QG uh2g8fM/S+O2dY3uDL9NgLQRi7QyQe4xIO9GoTzfi9zGZ4yLgjLuxegQGp9sdcs1zo79F Nh96La2VMUdNxuE3csA82wJ9E9t5chfdZxY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662367787952100001 Content-Type: text/plain; charset="utf-8" In Abort DMA Mode(ADM), hardware will abort all DMA operations without the need to set up a roottable. Enable Abort DMA Mode, when change Translation Table Mode(TTM) Change-Id: I74207fe96ef7a57d89a355d40dfbdd36186f06c3 Signed-off-by: Sheng Wei Cc: Jenny Huang Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Robert Kowalewski --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 157 +++++++++++----- .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf | 1 + .../Feature/VTd/IntelVTdDxe/VtdReg.c | 169 +++++++++++++----- .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 12 +- 4 files changed, 245 insertions(+), 94 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index b5b78f779..24beccd26 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -361,6 +361,68 @@ InvalidateIOTLB ( return EFI_SUCCESS; } =20 +/** + Clear Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +ClearGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & (~BitMask)); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D BitMask); +} + +/** + Set Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +SetGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | BitMask); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become not zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D 0); +} + /** Enable DMAR translation in pre-mem phase. =20 @@ -383,13 +445,10 @@ EnableDmarPreMem ( DEBUG ((DEBUG_INFO, "RTADDR_REG : 0x%016lx \n", RtaddrRegValue)); MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, RtaddrRegValue); =20 - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP); - DEBUG ((DEBUG_INFO, "EnableDmarPreMem: waiting for RTPS bit to be set...= \n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); DEBUG ((DEBUG_INFO, "EnableDmarPreMem: R_GSTS_REG =3D 0x%x \n", Reg32)); =20 // @@ -405,12 +464,7 @@ EnableDmarPreMem ( // // Enable VTd // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE); - DEBUG ((DEBUG_INFO, "EnableDmarPreMem: Waiting B_GSTS_REG_TE ...\n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 DEBUG ((DEBUG_INFO, "VTD () enabled!<<<<<<\n")); =20 @@ -434,22 +488,43 @@ EnableDmar ( { UINT32 Reg32; UINTN VtdUnitBaseAddress; + BOOLEAN TEWasEnabled; =20 VtdUnitBaseAddress =3D VTdUnitInfo->VtdUnitBaseAddress; =20 DEBUG ((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%x] \n", VtdUnitBase= Address)); =20 - DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); - MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTable); + // + // Check TE was enabled or not. + // + TEWasEnabled =3D ((MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG) & B_GSTS= _REG_TE) =3D=3D B_GSTS_REG_TE); =20 - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP); + if (TEWasEnabled && (VTdUnitInfo->ECapReg.Bits.ADMS =3D=3D 1) && PcdGetB= ool (PcdVTdSupportAbortDmaMode)) { + // + // For implementations reporting Enhanced SRTP Support (ESRTPS) field = as + // Clear in the Capability register, software must not modify this fie= ld while + // DMA remapping is active (TES=3D1 in Global Status register). + // + if (VTdUnitInfo->CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); + } + + // + // Enable ADM + // + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) (RootEntryTab= le | V_RTADDR_REG_TTM_ADM)); + + DEBUG((DEBUG_INFO, "Enable Abort DMA Mode...\n")); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); + + } else { + DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTabl= e); + + } =20 DEBUG ((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); - DEBUG ((DEBUG_INFO, "EnableDmar: R_GSTS_REG =3D 0x%x \n", Reg32)); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); =20 // // Init DMAr Fault Event and Data registers @@ -471,15 +546,19 @@ EnableDmar ( // InvalidateIOTLB (VTdUnitInfo); =20 + if (TEWasEnabled && (VTdUnitInfo->ECapReg.Bits.ADMS =3D=3D 1) && PcdGetB= ool (PcdVTdSupportAbortDmaMode)) { + if (VTdUnitInfo->CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); + } + + DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTabl= e); + } + // // Enable VTd // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE); - DEBUG ((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 DEBUG ((DEBUG_INFO, "VTD () enabled!<<<<<<\n")); =20 @@ -500,8 +579,6 @@ DisableDmar ( ) { UINT32 Reg32; - UINT32 Status; - UINT32 Command; =20 DEBUG ((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBas= eAddress)); =20 @@ -516,28 +593,12 @@ DisableDmar ( // // Set TE (Translation Enable: BIT31) of Global command register to zero // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status & ~B_GMCD_REG_TE); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); - - // - // Poll on TE Status bit of Global status register to become zero - // - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 // // Set SRTP (Set Root Table Pointer: BIT30) of Global command register i= n order to update the root table pointerDisable VTd // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status | B_GMCD_REG_SRTP); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); =20 Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); @@ -568,12 +629,12 @@ EnableVTdTranslationProtectionBlockDma ( =20 DEBUG ((DEBUG_INFO, "EnableVTdTranslationProtectionBlockDma - 0x%08x\n",= VtdUnitBaseAddress)); =20 - DEBUG ((DEBUG_INFO, "PcdVTdSupportAbortDmaMode : %d\n", FixedPcdGetBool = (PcdVTdSupportAbortDmaMode))); + DEBUG ((DEBUG_INFO, "PcdVTdSupportAbortDmaMode : %d\n", PcdGetBool (PcdV= TdSupportAbortDmaMode))); =20 ECapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_ECAP_REG); DEBUG ((DEBUG_INFO, "ECapReg.ADMS : %d\n", ECapReg.Bits.ADMS)); =20 - if ((ECapReg.Bits.ADMS =3D=3D 1) && FixedPcdGetBool (PcdVTdSupportAbortD= maMode)) { + if ((ECapReg.Bits.ADMS =3D=3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMod= e)) { // // Use Abort DMA Mode // diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= Dxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe= .inf index 387f90e37..b152831c0 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf @@ -75,6 +75,7 @@ [Pcd] gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode ## CONSUMES =20 [Depex] gEfiPciRootBridgeIoProtocolGuid diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index c7a56cf57..396aa4a70 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -475,6 +475,92 @@ DisablePmr ( return ; } =20 +/** + Clear Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +ClearGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & (~BitMask)); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D BitMask); +} + +/** + Set Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +SetGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | BitMask); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become not zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D 0); +} + +/** + Update Root Table Address Register + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] EnableADM TRUE - Enable ADM in TTM bits +**/ +VOID +UpdateRootTableAddressRegister ( + IN UINTN VtdIndex, + IN BOOLEAN EnableADM + ) +{ + UINT64 Reg64; + + if (mVtdUnitInformation[VtdIndex].ExtRootEntryTable !=3D NULL) { + DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[Vt= dIndex].ExtRootEntryTable)); + Reg64 =3D (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTab= le | (EnableADM ? V_RTADDR_REG_TTM_ADM : BIT11); + } else { + DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[VtdIn= dex].RootEntryTable)); + Reg64 =3D (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable = | (EnableADM ? V_RTADDR_REG_TTM_ADM : 0); + } + MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_RTADDR= _REG, Reg64); +} + /** Enable DMAR translation. =20 @@ -488,25 +574,43 @@ EnableDmar ( { UINTN Index; UINT32 Reg32; + UINTN VtdUnitBaseAddress; + BOOLEAN TEWasEnabled; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { - DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index)); + VtdUnitBaseAddress =3D mVtdUnitInformation[Index].VtdUnitBaseAddress; + DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] BAR [0x%x]\n", = Index, VtdUnitBaseAddress)); + + // + // Check TE was enabled or not. + // + TEWasEnabled =3D ((MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG) & B_GS= TS_REG_TE) =3D=3D B_GSTS_REG_TE); + + if (TEWasEnabled && (mVtdUnitInformation[Index].ECapReg.Bits.ADMS =3D= =3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMode)) { + // + // For implementations reporting Enhanced SRTP Support (ESRTPS) fiel= d as + // Clear in the Capability register, software must not modify this f= ield while + // DMA remapping is active (TES=3D1 in Global Status register). + // + if (mVtdUnitInformation[Index].CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); + } + + // + // Enable ADM + // + UpdateRootTableAddressRegister (Index, TRUE); + + DEBUG((DEBUG_INFO, "Enable Abort DMA Mode...\n")); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 - if (mVtdUnitInformation[Index].ExtRootEntryTable !=3D NULL) { - DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[= Index].ExtRootEntryTable)); - MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11); } else { - DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Ind= ex].RootEntryTable)); - MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable); - } + UpdateRootTableAddressRegister (Index, FALSE); =20 - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Reg32 | B_GMCD_REG_SRTP); + } =20 DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n")= ); - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); =20 // // Init DMAr Fault Event and Data registers @@ -528,15 +632,19 @@ EnableDmar ( // InvalidateIOTLB (Index); =20 + if (TEWasEnabled && (mVtdUnitInformation[Index].ECapReg.Bits.ADMS =3D= =3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMode)) { + if (mVtdUnitInformation[Index].CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); + } + + UpdateRootTableAddressRegister (Index, FALSE); + } + // // Enable VTd // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Reg32 | B_GMCD_REG_TE); - DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + DEBUG ((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index)); } @@ -565,8 +673,6 @@ DisableDmar ( UINTN Index; UINTN SubIndex; UINT32 Reg32; - UINT32 Status; - UINT32 Command; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index)); @@ -582,32 +688,15 @@ DisableDmar ( // // Set TE (Translation Enable: BIT31) of Global command register to ze= ro // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status & ~B_GMCD_REG_TE); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); - - // - // Poll on TE Status bit of Global status register to become zero - // - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + ClearGlobalCommandRegisterBits (mVtdUnitInformation[Index].VtdUnitBase= Address, B_GMCD_REG_TE); =20 // // Set SRTP (Set Root Table Pointer: BIT30) of Global command register= in order to update the root table pointerDisable VTd // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status | B_GMCD_REG_SRTP); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); - - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (mVtdUnitInformation[Index].VtdUnitBaseAd= dress, B_GSTS_REG_RTPS); =20 Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); + DEBUG ((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); =20 DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index)); =20 diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index c36d130a0..9166e599a 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -135,12 +135,6 @@ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32= |0x0000000A gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT= 32|0x0000000B =20 - ## Indicates if VTd Abort DMA Mode is supported.

- # TRUE - Support VTd abort DMA mode. - # FALSE - Not support VTd abort DMA mode. - # @Prompt VTd abort DMA mode support. - gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode|FALSE|BOOLEAN|0= x0000000C - [PcdsFixedAtBuild, PcdsPatchableInModule] ## Error code for VTd error.

# EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
@@ -178,3 +172,9 @@ # @Prompt The VTd PEI DMA buffer size for S3. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT3= 2|0x00000004 =20 + ## Indicates if VTd Abort DMA Mode is supported.

+ # TRUE - Support VTd abort DMA mode. + # FALSE - Not support VTd abort DMA mode. + # @Prompt VTd abort DMA mode support. + gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode|FALSE|BOOLEAN|0= x0000000C + --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93138): https://edk2.groups.io/g/devel/message/93138 Mute This Topic: https://groups.io/mt/93474620/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-