From nobody Sat May 18 06:50:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91518+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91518+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658205744; cv=none; d=zohomail.com; s=zohoarc; b=NLU/D2tipXo1VeMX3OR+dwha+EC9g/7g2g/VWvBcENRn5Tv1dqYAn8biPJ56Ws3TvORbZKc5Gjjj9LFdAGxMfWdL9C4MyrPixerqDJpbz9+zE75mpuWLvPv9nZ4/nY6xv3HmFeMBLYo1rhUiOu3yXsNCcKmFjxKzK27r1zjDm1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658205744; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7Y94FyVLzLb7Rres4ds1JpPIIoG8DPP9xW+aVt+0nGM=; b=GMrP+8fZnbs0hal9HrI+3jf1Zs2EvhF8s3qYdlRC6piWShHUXO1Y+7I+FrIwbn9C2WlFKXZf3NIP3+rzhEYqp2t73wMA8DYgfejUt0MLg7A4BUI0S0Pcq8pA091PVrdT4jAtEDDqTNxTQRRp5JLKB2C+doGLCkX1+WfCaqCeTIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91518+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658205744982210.90187500296258; Mon, 18 Jul 2022 21:42:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2OJdYY1788612xqnEQPFy9K6; Mon, 18 Jul 2022 21:42:24 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web09.36915.1658205742703133618 for ; Mon, 18 Jul 2022 21:42:23 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10412"; a="286403625" X-IronPort-AV: E=Sophos;i="5.92,282,1650956400"; d="scan'208";a="286403625" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 21:42:22 -0700 X-IronPort-AV: E=Sophos;i="5.92,282,1650956400"; d="scan'208";a="572690843" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.209.104.23]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 21:42:22 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH 1/2] IntelFsp2Pkg: Support 64bit FspResetType for X64 build. Date: Mon, 18 Jul 2022 21:42:09 -0700 Message-Id: <20220719044210.2911-2-chasel.chiu@intel.com> In-Reply-To: <20220719044210.2911-1-chasel.chiu@intel.com> References: <20220719044210.2911-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: DQmiXWyUhgIU2sgKPNhddZeNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658205744; bh=+NyWZ2XH51dzjIatLcRH7n8d6mW2mh+r5y1JgTMrwXw=; h=Cc:Date:From:Reply-To:Subject:To; b=sk1X3vxBfcfUKtxpmo2QkGcUXhZw5P8NWePiwnK6Zrbhl1Z81N+wSa+kbBR5+VDDiIm t4vSqZAsxw1o3lEoeUi43LCrKMA3WQvfFi5uxkSmbwk0kf3YXtP0nuxvN6Q2LUgqelDMO Md46qxntFDa1f0/AS78Ayh87TuRayRujTx0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658205746800100006 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3999 FspResetType will be either 32bit or 64 bit basing on the build type. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c | 10 +++++----- IntelFsp2Pkg/Include/FspEas/FspApi.h | 61 ++++++++++++++++= +++++++++++++++++---------------------------- IntelFsp2Pkg/Include/Library/FspCommonLib.h | 2 +- IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h | 4 ++-- 4 files changed, 41 insertions(+), 36 deletions(-) diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c b/IntelFs= p2Pkg/Library/BaseFspCommonLib/FspCommonLib.c index 67e08a9e7e..a22b0e7825 100644 --- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c +++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c @@ -200,13 +200,13 @@ SetFspCoreStackPointer ( UINT32 StackContextLen; =20 FspData =3D GetFspGlobalDataPointer (); - StackContextLen =3D sizeof(CONTEXT_STACK) / sizeof(UINTN); + StackContextLen =3D sizeof (CONTEXT_STACK) / sizeof (UINTN); =20 // // Reserve space for the ContinuationFunc two parameters // - OldStack =3D (UINTN *)FspData->CoreStack; - NewStack =3D (UINTN *)NewStackTop - StackContextLen - 2; + OldStack =3D (UINTN *)FspData->CoreStack; + NewStack =3D (UINTN *)NewStackTop - StackContextLen - 2; FspData->CoreStack =3D (UINTN)NewStack; while (StackContextLen-- !=3D 0) { *NewStack++ =3D *OldStack++; @@ -533,7 +533,7 @@ SetPhaseStatusCode ( VOID EFIAPI FspApiReturnStatusReset ( - IN UINT32 FspResetType + IN EFI_STATUS FspResetType ) { volatile BOOLEAN LoopUntilReset; @@ -546,7 +546,7 @@ FspApiReturnStatusReset ( /// calls the FSP API without honoring the reset request by FSP /// do { - SetFspApiReturnStatus ((EFI_STATUS)FspResetType); + SetFspApiReturnStatus (FspResetType); Pei2LoaderSwitchStack (); DEBUG ((DEBUG_ERROR, "!!!ERROR: FSP has requested BootLoader for res= et. But BootLoader has not honored the reset\n")); DEBUG ((DEBUG_ERROR, "!!!ERROR: Please add support in BootLoader to = honor the reset request from FSP\n")); diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index b36bc2b9ae..5e47f475db 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -11,19 +11,24 @@ #define _FSP_API_H_ =20 #include +#include =20 /// /// FSP Reset Status code -/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code +/// These are defined in FSP EAS v2.4 section 13.2.2 - OEM Status Code /// @{ -#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001 -#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002 -#define FSP_STATUS_RESET_REQUIRED_3 0x40000003 -#define FSP_STATUS_RESET_REQUIRED_4 0x40000004 -#define FSP_STATUS_RESET_REQUIRED_5 0x40000005 -#define FSP_STATUS_RESET_REQUIRED_6 0x40000006 -#define FSP_STATUS_RESET_REQUIRED_7 0x40000007 -#define FSP_STATUS_RESET_REQUIRED_8 0x40000008 + +#define ENCODE_RESET_REQUEST(ResetType) \ + ((EFI_STATUS)((MAX_BIT >> 1) | (ResetType))) +#define FSP_STATUS_RESET_REQUIRED_COLD ENCODE_RESET_REQUEST(1) +#define FSP_STATUS_RESET_REQUIRED_WARM ENCODE_RESET_REQUEST(2) +#define FSP_STATUS_RESET_REQUIRED_3 ENCODE_RESET_REQUEST(3) +#define FSP_STATUS_RESET_REQUIRED_4 ENCODE_RESET_REQUEST(4) +#define FSP_STATUS_RESET_REQUIRED_5 ENCODE_RESET_REQUEST(5) +#define FSP_STATUS_RESET_REQUIRED_6 ENCODE_RESET_REQUEST(6) +#define FSP_STATUS_RESET_REQUIRED_7 ENCODE_RESET_REQUEST(7) +#define FSP_STATUS_RESET_REQUIRED_8 ENCODE_RESET_REQUEST(8) +#define FSP_STATUS_VARIABLE_REQUEST ENCODE_RESET_REQUEST(10) /// @} =20 /// @@ -135,18 +140,18 @@ typedef struct { /// /// Revision of the structure is 2 for this version of the specification. /// - UINT8 Revision; - UINT8 Reserved[3]; + UINT8 Revision; + UINT8 Reserved[3]; /// /// Length of the structure in bytes. The current value for this field i= s 32. /// - UINT32 Length; + UINT32 Length; /// /// FspDebugHandler Optional debug handler for the bootloader to receive= debug messages /// occurring during FSP execution. /// - EFI_PHYSICAL_ADDRESS FspDebugHandler; - UINT8 Reserved1[16]; + EFI_PHYSICAL_ADDRESS FspDebugHandler; + UINT8 Reserved1[16]; } FSPT_ARCH2_UPD; =20 /// @@ -197,37 +202,37 @@ typedef struct { /// /// Revision of the structure is 3 for this version of the specification. /// - UINT8 Revision; - UINT8 Reserved[3]; + UINT8 Revision; + UINT8 Reserved[3]; /// /// Length of the structure in bytes. The current value for this field i= s 64. /// - UINT32 Length; + UINT32 Length; /// /// Pointer to the temporary stack base address to be /// consumed inside FspMemoryInit() API. /// - EFI_PHYSICAL_ADDRESS StackBase; + EFI_PHYSICAL_ADDRESS StackBase; /// /// Temporary stack size to be consumed inside /// FspMemoryInit() API. /// - UINT64 StackSize; + UINT64 StackSize; /// /// Size of memory to be reserved by FSP below "top /// of low usable memory" for bootloader usage. /// - UINT32 BootLoaderTolumSize; + UINT32 BootLoaderTolumSize; /// /// Current boot mode. /// - UINT32 BootMode; + UINT32 BootMode; /// /// Optional event handler for the bootloader to be informed of events o= ccurring during FSP execution. /// This value is only valid if Revision is >=3D 2. /// - EFI_PHYSICAL_ADDRESS FspEventHandler; - UINT8 Reserved1[24]; + EFI_PHYSICAL_ADDRESS FspEventHandler; + UINT8 Reserved1[24]; } FSPM_ARCH2_UPD; =20 /// @@ -266,18 +271,18 @@ typedef struct { /// /// Revision of the structure is 2 for this version of the specification. /// - UINT8 Revision; - UINT8 Reserved[3]; + UINT8 Revision; + UINT8 Reserved[3]; /// /// Length of the structure in bytes. The current value for this field i= s 32. /// - UINT32 Length; + UINT32 Length; /// /// FspEventHandler Optional event handler for the bootloader to be info= rmed of events /// occurring during FSP execution. /// - EFI_PHYSICAL_ADDRESS FspEventHandler; - UINT8 Reserved1[16]; + EFI_PHYSICAL_ADDRESS FspEventHandler; + UINT8 Reserved1[16]; } FSPS_ARCH2_UPD; =20 /// diff --git a/IntelFsp2Pkg/Include/Library/FspCommonLib.h b/IntelFsp2Pkg/Inc= lude/Library/FspCommonLib.h index b5e38568e2..13b67f8822 100644 --- a/IntelFsp2Pkg/Include/Library/FspCommonLib.h +++ b/IntelFsp2Pkg/Include/Library/FspCommonLib.h @@ -302,7 +302,7 @@ SetPhaseStatusCode ( VOID EFIAPI FspApiReturnStatusReset ( - IN UINT32 FspResetType + IN EFI_STATUS FspResetType ); =20 #endif diff --git a/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h b/IntelFsp2Pk= g/Include/Library/FspSwitchStackLib.h index f049361d78..ff66e48ae2 100644 --- a/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h +++ b/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h @@ -30,7 +30,7 @@ =20 =20 **/ -UINT32 +EFI_STATUS EFIAPI Pei2LoaderSwitchStack ( VOID @@ -46,7 +46,7 @@ Pei2LoaderSwitchStack ( =20 =20 **/ -UINT32 +EFI_STATUS EFIAPI Loader2PeiSwitchStack ( VOID --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91518): https://edk2.groups.io/g/devel/message/91518 Mute This Topic: https://groups.io/mt/92476843/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 06:50:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91519+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91519+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658205744; cv=none; d=zohomail.com; s=zohoarc; b=AVGHs0GIQq9j1S/wLLkn6CuxftNWpIBp1hj8dfMN2Oa/h0GYjkkv2t5GAx+1O7YB7YUU662wfimkTfswPwKvUeOsQUmlWQEIndkE+fJfIHmcrgG7uB5XZArjePRZ5EZ5Yc70xZhir1QV4tq0kM/tqcwvdtFpRvJNjL67nT3qaTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658205744; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=WZ2ev8gNoH4A+dHpFE42QOuiIS7fObMmJQw+3fULcwA=; b=AHEnhXxQMhpiJZ4YQ6eOOGBKmlq3hpw8+a7G4VJOO7LYPtI6mRcylRXlKNws6Mn9VtwO5A75ZzcTDlLcQMm4NxrjkKaMei2dlw8GgkhKnR+h68h7BGqRFFpOntcEcYw0zQMNW9W6jyDcJ4P3mGwdLLUJQCRnwV/+CH67OLB+nns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91519+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658205744606835.6135387629247; Mon, 18 Jul 2022 21:42:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jKVXYY1788612xRSEfzpDcTq; Mon, 18 Jul 2022 21:42:24 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web09.36915.1658205742703133618 for ; Mon, 18 Jul 2022 21:42:23 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10412"; a="286403626" X-IronPort-AV: E=Sophos;i="5.92,282,1650956400"; d="scan'208";a="286403626" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 21:42:22 -0700 X-IronPort-AV: E=Sophos;i="5.92,282,1650956400"; d="scan'208";a="572690846" X-Received: from cchiu4-mobl.gar.corp.intel.com ([10.209.104.23]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 21:42:22 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [edk2-devel] [PATCH 2/2] IntelFsp2WrapperPkg: Support 64bit FspResetType for X64 build. Date: Mon, 18 Jul 2022 21:42:10 -0700 Message-Id: <20220719044210.2911-3-chasel.chiu@intel.com> In-Reply-To: <20220719044210.2911-1-chasel.chiu@intel.com> References: <20220719044210.2911-1-chasel.chiu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: YbXYhDiwKOzdVfaEtjuB1tLLx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658205744; bh=h33por6wa1B7HPnKT+2cd8BpSRLEj2wiVRvL9fMQXfg=; h=Cc:Date:From:Reply-To:Subject:To; b=E5RKBE03KEOdOBqAFYdaIOXKN4tA5Fl2L+88PuGTpzV6+X87BlbCaRPoIV5HTvQQ0r9 5w1gTlvcqv2jLdbVxHygy+iJzF4nOSN60TF5V9Q7p622ke78cp4ftBRwlDX6gcpW7WiYO NLfPin1zl8/JNhvCCZZcSCZ9xGKnfLwGDt0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658205746801100007 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3999 FspResetType will be either 32bit or 64 bit basing on the build type. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c = | 6 +++--- IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c = | 10 +++++----- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c = | 15 +++++++-------- IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c = | 5 ++++- IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrapperPlat= formLibSample.c | 2 +- IntelFsp2WrapperPkg/Include/Library/FspWrapperPlatformLib.h = | 2 +- 6 files changed, 21 insertions(+), 19 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c = b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c index 21385ac0b2..7aa2c93e99 100644 --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c @@ -97,7 +97,7 @@ OnPciEnumerationComplete ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration requested res= et 0x%x\n", Status)); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 if (Status !=3D EFI_SUCCESS) { @@ -140,7 +140,7 @@ OnReadyToBoot ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot requested reset 0x%x\= n", Status)); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 if (Status !=3D EFI_SUCCESS) { @@ -184,7 +184,7 @@ OnEndOfFirmware ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware requested reset 0x%= x\n", Status)); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 if (Status !=3D EFI_SUCCESS) { diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelF= sp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c index 047c2965a3..ac27524d08 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c @@ -43,16 +43,15 @@ extern EFI_GUID gFspHobGuid; =20 @return FSP-M UPD Data Address **/ - UINTN GetFspmUpdDataAddress ( VOID ) { if (PcdGet64 (PcdFspmUpdDataAddress64) !=3D 0) { - return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64); + return (UINTN)PcdGet64 (PcdFspmUpdDataAddress64); } else { - return (UINTN) PcdGet32 (PcdFspmUpdDataAddress); + return (UINTN)PcdGet32 (PcdFspmUpdDataAddress); } } =20 @@ -97,7 +96,7 @@ PeiFspMemoryInit ( // // External UPD is ready, get the buffer from PCD pointer. // - FspmUpdDataPtr =3D (VOID *) GetFspmUpdDataAddress(); + FspmUpdDataPtr =3D (VOID *)GetFspmUpdDataAddress (); ASSERT (FspmUpdDataPtr !=3D NULL); } =20 @@ -115,6 +114,7 @@ PeiFspMemoryInit ( DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMO= N *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize)); DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", ((FSPM_UPD_COMMO= N *)FspmUpdDataPtr)->FspmArchUpd.BootMode)); } + DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", &FspHobListPtr)); =20 TimeStampCounterStart =3D AsmReadTsc (); @@ -129,7 +129,7 @@ PeiFspMemoryInit ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status)= ); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 if (EFI_ERROR (Status)) { diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelF= sp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index fadadd40e6..ee48dd69d3 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -96,7 +96,7 @@ S3EndOfPeiNotify ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested r= eset 0x%x\n", Status)); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 NotifyPhaseParams.Phase =3D EnumInitPhaseReadyToBoot; @@ -108,7 +108,7 @@ S3EndOfPeiNotify ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%= x\n", Status)); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 NotifyPhaseParams.Phase =3D EnumInitPhaseEndOfFirmware; @@ -120,7 +120,7 @@ S3EndOfPeiNotify ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0= x%x\n", Status)); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 return EFI_SUCCESS; @@ -186,16 +186,15 @@ FspSiliconInitDoneGetFspHobList ( =20 @return FSP-S UPD Data Address **/ - UINTN GetFspsUpdDataAddress ( VOID ) { if (PcdGet64 (PcdFspsUpdDataAddress64) !=3D 0) { - return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64); + return (UINTN)PcdGet64 (PcdFspsUpdDataAddress64); } else { - return (UINTN) PcdGet32 (PcdFspsUpdDataAddress); + return (UINTN)PcdGet32 (PcdFspsUpdDataAddress); } } =20 @@ -310,7 +309,7 @@ PeiMemoryDiscoveredNotify ( SourceData =3D (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)Fsps= HeaderPtr->CfgRegionOffset); CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSi= ze); } else { - FspsUpdDataPtr =3D (FSPS_UPD_COMMON *) GetFspsUpdDataAddress(); + FspsUpdDataPtr =3D (FSPS_UPD_COMMON *)GetFspsUpdDataAddress (); ASSERT (FspsUpdDataPtr !=3D NULL); } =20 @@ -327,7 +326,7 @@ PeiMemoryDiscoveredNotify ( // if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) { DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status= )); - CallFspWrapperResetSystem ((UINT32)Status); + CallFspWrapperResetSystem (Status); } =20 if (EFI_ERROR (Status)) { diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchE= xecute.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExe= cute.c index 591a5c7a55..22e009ace3 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c @@ -121,6 +121,10 @@ Execute32BitCode ( // AsmReadIdtr (&Idtr); Status =3D AsmExecute32BitCode (Function, Param1, Param2, &mGdt); + // + // Convert FSP Status code from 32bit to 64bit to match caller expectati= on. + // + Status =3D (Status & ~(BIT31 + BIT30)) | LShiftU64 (Status & (BIT31 + BI= T30), 32); AsmWriteIdtr (&Idtr); =20 return Status; @@ -150,4 +154,3 @@ Execute64BitCode ( =20 return Status; } - diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/Fs= pWrapperPlatformLibSample.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperPla= tformLibSample/FspWrapperPlatformLibSample.c index fa7d60c292..00b4799fb4 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrappe= rPlatformLibSample.c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrappe= rPlatformLibSample.c @@ -86,7 +86,7 @@ GetS3MemoryInfo ( VOID EFIAPI CallFspWrapperResetSystem ( - IN UINT32 FspStatusResetType + IN EFI_STATUS FspStatusResetType ) { // diff --git a/IntelFsp2WrapperPkg/Include/Library/FspWrapperPlatformLib.h b/= IntelFsp2WrapperPkg/Include/Library/FspWrapperPlatformLib.h index a6ade2551e..fe9f0d7408 100644 --- a/IntelFsp2WrapperPkg/Include/Library/FspWrapperPlatformLib.h +++ b/IntelFsp2WrapperPkg/Include/Library/FspWrapperPlatformLib.h @@ -74,7 +74,7 @@ GetS3MemoryInfo ( VOID EFIAPI CallFspWrapperResetSystem ( - IN UINT32 FspStatusResetType + IN EFI_STATUS FspStatusResetType ); =20 #endif --=20 2.35.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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