From nobody Sat May 18 13:16:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+91432+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91432+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1658047074; cv=none; d=zohomail.com; s=zohoarc; b=FYBPsEoKMfhbpNtVWMi6urwoGI9goH4OKPNNprEAmmYL5SaabEu7dQg6cS6Hwdgs216rKVlTWbxDPp3KFc8h/DN/J9wIQ1CQe3ULk+1tnjzGNUiJhrwLOXSW4saWuTEu/rcudUjJwdDG01T1EvgMjVSXwqSOcntwv+82ZKGPl2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658047074; h=Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=CsoV/ZNy5r7y0UgXiiizdG954S+rIVxKffnD8riw61U=; b=jFjN0XWlSS/ZJazKFwk37dzKsxXqjB1o9JeEPDgCbP2IqEzcrAWHRF+gym3W0KMPYxympWmKmiRVRZHM1KE0ckJG+7K7cXTyFRJuXO0UnxDcyosoY35riT0cH/n9bXMSsAN9eVhPha5NqSOip893vd6AtJSbITw/Aa9+FxNx+Lo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+91432+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1658047074449674.2613152145303; Sun, 17 Jul 2022 01:37:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MREIYY1788612xvpTbv9WGnW; Sun, 17 Jul 2022 01:37:54 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.13984.1658047073141422457 for ; Sun, 17 Jul 2022 01:37:53 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10410"; a="266448200" X-IronPort-AV: E=Sophos;i="5.92,278,1650956400"; d="scan'208";a="266448200" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2022 01:37:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,278,1650956400"; d="scan'208";a="624356383" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.79]) by orsmga008.jf.intel.com with ESMTP; 17 Jul 2022 01:37:51 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni Subject: [edk2-devel] [PATCH v1] UefiCpuPkg: Dynamic check SMRR enable & SmmFeatureControl capability Date: Sun, 17 Jul 2022 16:37:47 +0800 Message-Id: <20220717083747.21076-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: QkRakU31INGE1lB1uR8qcATyx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1658047074; bh=qSxFUQMmf0R9jEwcF+5nTk8CeAjg7MoginzjtOWF8xc=; h=Cc:Date:From:Reply-To:Subject:To; b=qGBpMs2XEYSINssFNc1URpP2+L+K9ZeXo/bRGlcECBwCmRbyPlPeoOzol3G+dPEAKGQ rIdDOuiD6N6alFyCqrmTqIB7VjmerNjcJQKBBORWIznd/ct/8WAn1MTI7clcolj4e5u/x 3PXAE+a1AHljEaRjxWuqx1loiAaybv3vbNE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1658047075153100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3962 Two SMM variables (mSmrrSupported & mSmmFeatureControlSupported) are global variables, they control whether the SMRR and SMM Feature Control MSR will be restored respectively. To avoid the TOCTOU, dynamic check SMRR enable & SmmFeatureControl capabili= ty. Change-Id: I6835e4b0e12c5e6f52effb60fd9224e3eb97fc0d Cc: Eric Dong Cc: Ray Ni Signed-off-by: Jiaxin Wu --- .../SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c | 248 ++++++++++++-----= ---- 1 file changed, 141 insertions(+), 107 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c= b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c index 78de7f8407..b2f31c993f 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c @@ -35,26 +35,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // MSRs required for configuration of SMM Code Access Check // #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D #define SMM_CODE_ACCESS_CHK_BIT BIT58 =20 -// -// Set default value to assume SMRR is not supported -// -BOOLEAN mSmrrSupported =3D FALSE; - -// -// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported -// -BOOLEAN mSmmFeatureControlSupported =3D FALSE; - -// -// Set default value to assume IA-32 Architectural MSRs are used -// -UINT32 mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; -UINT32 mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; - // // Set default value to assume MTRRs need to be configured on each SMI // BOOLEAN mNeedConfigureMtrrs =3D TRUE; =20 @@ -62,26 +46,39 @@ BOOLEAN mNeedConfigureMtrrs =3D TRUE; // Array for state of SMRR enable on all CPUs // BOOLEAN *mSmrrEnabled; =20 /** - Performs library initialization. + Return if SMRR is supported =20 - This initialization function contains common functionality shared betwen= all - library instance constructors. + @param[in] SmrrPhysBaseMsr Pointer to SmrrPhysBaseMsr. + @param[in] SmrrPhysMaskMsr Pointer to SmrrPhysMaskMsr. + + @retval TRUE SMRR is supported. + @retval FALSE SMRR is not supported. =20 **/ -VOID -CpuFeaturesLibInitialization ( - VOID +BOOLEAN +IsSmrrSupported ( + IN UINT32 *SmrrPhysBaseMsr OPTIONAL, + IN UINT32 *SmrrPhysMaskMsr OPTIONAL ) { + BOOLEAN ReturnValue; + UINT32 RegEax; UINT32 RegEdx; UINTN FamilyId; UINTN ModelId; =20 + UINT64 FeatureControl; + + // + // Set default value to assume SMRR is not supported + // + ReturnValue =3D FALSE; + // // Retrieve CPU Family and Model // AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); FamilyId =3D (RegEax >> 8) & 0xf; @@ -96,11 +93,11 @@ CpuFeaturesLibInitialization ( if ((RegEdx & BIT12) !=3D 0) { // // Check MTRR_CAP MSR bit 11 for SMRR support // if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) !=3D 0) { - mSmrrSupported =3D TRUE; + ReturnValue =3D TRUE; } } =20 // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual @@ -109,28 +106,79 @@ CpuFeaturesLibInitialization ( // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then // SMRR Physical Base and SMM Physical Mask MSRs are not available. // if (FamilyId =3D=3D 0x06) { if ((ModelId =3D=3D 0x1C) || (ModelId =3D=3D 0x26) || (ModelId =3D=3D = 0x27) || (ModelId =3D=3D 0x35) || (ModelId =3D=3D 0x36)) { - mSmrrSupported =3D FALSE; + ReturnValue =3D FALSE; } } =20 - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily - // - // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2 - // Processor Family MSRs - // - if (FamilyId =3D=3D 0x06) { - if ((ModelId =3D=3D 0x17) || (ModelId =3D=3D 0x0f)) { - mSmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE; - mSmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK; + if (ReturnValue) { + // + // Return the SmrrPhysBaseMsr & SmrrPhysMaskMsr if required & Smrr Sup= ported + // + if (SmrrPhysBaseMsr !=3D NULL) { + *SmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; + } + + if (SmrrPhysBaseMsr !=3D NULL) { + *SmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; + } + + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor F= amily + // + // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2 + // Processor Family MSRs + // + if (FamilyId =3D=3D 0x06) { + if ((ModelId =3D=3D 0x17) || (ModelId =3D=3D 0x0f)) { + if (SmrrPhysBaseMsr !=3D NULL) { + *SmrrPhysBaseMsr =3D SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE; + } + + if (SmrrPhysMaskMsr !=3D NULL) { + *SmrrPhysMaskMsr =3D SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK; + } + + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Process= or Family + // + // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being= used, then + // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is= set before + // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CO= NTROL MSR(0x3A) + // is set, then the MSR is locked and can not be modified. + // + + FeatureControl =3D AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CON= TROL); + if (((FeatureControl & BIT3) =3D=3D 0) && ((FeatureControl & BIT0)= =3D=3D 1)) { + ReturnValue =3D FALSE; + } + } } } =20 + return ReturnValue; +} + +/** + Performs library initialization. + + This initialization function contains common functionality shared betwen= all + library instance constructors. + +**/ +VOID +CpuFeaturesLibInitialization ( + VOID + ) +{ + UINT32 RegEax; + UINT32 RegEdx; + // // Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Volume 3C, Section 34.4.2 SMRAM Caching // An IA-32 processor does not automatically write back and invalidate= its // caches before entering SMM or before exiting SMM. Because of this b= ehavior, @@ -193,50 +241,27 @@ SmmCpuFeaturesInitializeProcessor ( IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, IN CPU_HOT_PLUG_DATA *CpuHotPlugData ) { SMRAM_SAVE_STATE_MAP *CpuState; - UINT64 FeatureControl; - UINT32 RegEax; - UINT32 RegEdx; - UINTN FamilyId; - UINTN ModelId; + UINT32 SmrrPhysBaseMsr; + UINT32 SmrrPhysMaskMsr; =20 // // Configure SMBASE. // CpuState =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET); CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; =20 - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Fam= ily - // - // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used,= then - // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set b= efore - // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL = MSR(0x3A) - // is set, then the MSR is locked and can not be modified. - // - if (mSmrrSupported && (mSmrrPhysBaseMsr =3D=3D SMM_FEATURES_LIB_IA32_COR= E_SMRR_PHYSBASE)) { - FeatureControl =3D AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL= ); - if ((FeatureControl & BIT3) =3D=3D 0) { - if ((FeatureControl & BIT0) =3D=3D 0) { - AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureContr= ol | BIT3); - } else { - mSmrrSupported =3D FALSE; - } - } - } - // // If SMRR is supported, then program SMRR base/mask MSRs. // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first norma= l SMI. // The code that initializes SMM environment is running in normal mode // from SMRAM region. If SMRR is enabled here, then the SMRAM region // is protected and the normal mode code execution will fail. // - if (mSmrrSupported) { + if (IsSmrrSupported (&SmrrPhysBaseMsr, &SmrrPhysMaskMsr)) { // // SMRR size cannot be less than 4-KBytes // SMRR size must be of length 2^n // SMRR base alignment cannot be less than SMRR length // @@ -250,50 +275,16 @@ SmmCpuFeaturesInitializeProcessor ( if (IsMonarch) { DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size r= equirement!\n")); CpuDeadLoop (); } } else { - AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CAC= HE_WRITE_BACK); - AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & = EFI_MSR_SMRR_MASK)); + AsmWriteMsr64 (SmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACH= E_WRITE_BACK); + AsmWriteMsr64 (SmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & E= FI_MSR_SMRR_MASK)); mSmrrEnabled[CpuIndex] =3D FALSE; } } =20 - // - // Retrieve CPU Family and Model - // - AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); - FamilyId =3D (RegEax >> 8) & 0xf; - ModelId =3D (RegEax >> 4) & 0xf; - if ((FamilyId =3D=3D 0x06) || (FamilyId =3D=3D 0x0f)) { - ModelId =3D ModelId | ((RegEax >> 12) & 0xf0); - } - - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM) - // Processor Family. - // - // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation - // Intel(R) Core(TM) Processor Family MSRs. - // - if (FamilyId =3D=3D 0x06) { - if ((ModelId =3D=3D 0x3C) || (ModelId =3D=3D 0x45) || (ModelId =3D=3D = 0x46) || - (ModelId =3D=3D 0x3D) || (ModelId =3D=3D 0x47) || (ModelId =3D=3D = 0x4E) || (ModelId =3D=3D 0x4F) || - (ModelId =3D=3D 0x3F) || (ModelId =3D=3D 0x56) || (ModelId =3D=3D = 0x57) || (ModelId =3D=3D 0x5C) || - (ModelId =3D=3D 0x8C)) - { - // - // Check to see if the CPU supports the SMM Code Access Check feature - // Do not access this MSR unless the CPU supports the SmmRegFeatureC= ontrol - // - if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_= CHK_BIT) !=3D 0) { - mSmmFeatureControlSupported =3D TRUE; - } - } - } - // // Call internal worker function that completes the CPU initialization // FinishSmmCpuFeaturesInitializeProcessor (); } @@ -381,12 +372,14 @@ VOID EFIAPI SmmCpuFeaturesDisableSmrr ( VOID ) { - if (mSmrrSupported && mNeedConfigureMtrrs) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EF= I_MSR_SMRR_PHYS_MASK_VALID); + UINT32 SmrrPhysMaskMsr; + + if (IsSmrrSupported (NULL, &SmrrPhysMaskMsr) && mNeedConfigureMtrrs) { + AsmWriteMsr64 (SmrrPhysMaskMsr, AsmReadMsr64 (SmrrPhysMaskMsr) & ~EFI_= MSR_SMRR_PHYS_MASK_VALID); } } =20 /** Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigur= eMtrrs() @@ -396,12 +389,14 @@ VOID EFIAPI SmmCpuFeaturesReenableSmrr ( VOID ) { - if (mSmrrSupported && mNeedConfigureMtrrs) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI= _MSR_SMRR_PHYS_MASK_VALID); + UINT32 SmrrPhysMaskMsr; + + if (IsSmrrSupported (NULL, &SmrrPhysMaskMsr) && mNeedConfigureMtrrs) { + AsmWriteMsr64 (SmrrPhysMaskMsr, AsmReadMsr64 (SmrrPhysMaskMsr) | EFI_M= SR_SMRR_PHYS_MASK_VALID); } } =20 /** Processor specific hook point each time a CPU enters System Management M= ode. @@ -414,15 +409,17 @@ VOID EFIAPI SmmCpuFeaturesRendezvousEntry ( IN UINTN CpuIndex ) { + UINT32 SmrrPhysMaskMsr; + // // If SMRR is supported and this is the first normal SMI, then enable SM= RR // - if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI= _MSR_SMRR_PHYS_MASK_VALID); + if (!mSmrrEnabled[CpuIndex] && IsSmrrSupported (NULL, &SmrrPhysMaskMsr))= { + AsmWriteMsr64 (SmrrPhysMaskMsr, AsmReadMsr64 (SmrrPhysMaskMsr) | EFI_M= SR_SMRR_PHYS_MASK_VALID); mSmrrEnabled[CpuIndex] =3D TRUE; } } =20 /** @@ -458,12 +455,49 @@ EFIAPI SmmCpuFeaturesIsSmmRegisterSupported ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && (RegName =3D=3D SmmRegFeatureControl)= ) { - return TRUE; + UINT32 RegEax; + UINT32 RegEdx; + UINTN FamilyId; + UINTN ModelId; + + if (RegName =3D=3D SmmRegFeatureControl) { + // + // Retrieve CPU Family and Model + // + AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); + FamilyId =3D (RegEax >> 8) & 0xf; + ModelId =3D (RegEax >> 4) & 0xf; + if ((FamilyId =3D=3D 0x06) || (FamilyId =3D=3D 0x0f)) { + ModelId =3D ModelId | ((RegEax >> 12) & 0xf0); + } + + // + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM) + // Processor Family. + // + // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generati= on + // Intel(R) Core(TM) Processor Family MSRs. + // + if (FamilyId =3D=3D 0x06) { + if ((ModelId =3D=3D 0x3C) || (ModelId =3D=3D 0x45) || (ModelId =3D= =3D 0x46) || + (ModelId =3D=3D 0x3D) || (ModelId =3D=3D 0x47) || (ModelId =3D= =3D 0x4E) || (ModelId =3D=3D 0x4F) || + (ModelId =3D=3D 0x3F) || (ModelId =3D=3D 0x56) || (ModelId =3D= =3D 0x57) || (ModelId =3D=3D 0x5C) || + (ModelId =3D=3D 0x8C)) + { + // + // Check to see if the CPU supports the SMM Code Access Check feat= ure + // Do not access this MSR unless the CPU supports the SmmRegFeatur= eControl + // + if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCES= S_CHK_BIT) !=3D 0) { + return TRUE; + } + } + } } =20 return FALSE; } =20 @@ -484,11 +518,11 @@ EFIAPI SmmCpuFeaturesGetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && (RegName =3D=3D SmmRegFeatureControl)= ) { + if (SmmCpuFeaturesIsSmmRegisterSupported (CpuIndex, RegName)) { return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); } =20 return 0; } @@ -510,11 +544,11 @@ SmmCpuFeaturesSetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName, IN UINT64 Value ) { - if (mSmmFeatureControlSupported && (RegName =3D=3D SmmRegFeatureControl)= ) { + if (SmmCpuFeaturesIsSmmRegisterSupported (CpuIndex, RegName)) { AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); } } =20 /** --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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