https://bugzilla.tianocore.org/show_bug.cgi?id=3860

This is the project having rework on UefiCpuPkg in order to support a variety
of processor architectures. Some modules under UefiCpuPkg are required to be
abstract for the different archs.

In V2:
- I moved two RISC-V OpenSBI header files to under
  MdePkg/Include/IndustryStandard (5/8). However I am not sure if that is proper
  having those files there.
- Fixed some CI errors.

In V1:
The first step is to classify UefiCpuPkg modules to IA32 and X64 sections in
DSC file (Patch 1/6). Move the module to Common section later if more than one
archs can leverage the same module (such as Patch 3/6 for BaseUefiCpuLib).

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Chao Li <lichao@loongson.cn>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Abner Chang (8):
  [RFC] UefiCpuPkg: Classify IA32/X64 modules in DSC file
  [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor
    architecture
  [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace
  [RFC] UefiCpuPkg/RiscVOpensbLib: Add opensbi submodule
  [RFC] MdePkg/Include: Add RISC-V OpenSBI header files
  [RFC] BaseTools/Conf: Relocate RiscVOpensbiTypes.h
  [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib
  [RFC] UefiCpuPkg: Update YAML file for RISC-V arch

 UefiCpuPkg/UefiCpuPkg.dec                     |  26 ++-
 UefiCpuPkg/UefiCpuPkg.dsc                     |  45 +++--
 .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf |   8 +-
 .../RiscVOpensbiLib/RiscVOpensbiLib.inf       |  89 ++++++++++
 .../Include/IndustryStandard/RiscVOpensbi.h   |  62 +++++++
 .../IndustryStandard/RiscVOpensbiTypes.h      |  82 +++++++++
 .../Include/IndustryStandard/RISC-V/RiscV.h   | 162 ++++++++++++++++++
 .../Include/Library/RISC-V/RiscVCpuLib.h      | 118 +++++++++++++
 UefiCpuPkg/Include/RISC-V/RiscVImpl.h         |  87 ++++++++++
 .gitmodules                                   |  45 ++---
 BaseTools/Conf/tools_def.template             |   2 +-
 MdePkg/MdePkg.ci.yaml                         |   2 +
 .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni |   5 +-
 .../Library/BaseUefiCpuLib/RISCV64/Cpu.S      | 143 ++++++++++++++++
 .../Library/RISC-V/RiscVOpensbiLib/opensbi    |   1 +
 UefiCpuPkg/UefiCpuPkg.ci.yaml                 |  60 ++++++-
 16 files changed, 888 insertions(+), 49 deletions(-)
 create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf
 create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbi.h
 create mode 100644 MdePkg/Include/IndustryStandard/RiscVOpensbiTypes.h
 create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h
 create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h
 create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h
 create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S
 create mode 160000 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi

-- 
2.31.1



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