From nobody Thu May 16 03:19:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87739+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87739+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1647586143; cv=none; d=zohomail.com; s=zohoarc; b=cVtUe7adtwS02Gmqny/NgrVn2Fhe1Xbz8qGTdax6sOiciypviGiS5V8hJhUT7dkyIfztNx7eDaibb6+JBMxRMbttsw6mxVl/hFI1OXDjaRTPwNk5VLOkCugpg+tVzWSYc5WX8XQsJqh2DISOwvFr28tKSMRD0qD8oDUHTpB1y2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647586143; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8e6c7qoa7ZWpwXBItiOJI3HoP5NoXoqwWjxC4FKE8lM=; b=DXjiQCCs2aLOoBNzDzBxTuMCDJbXnh7YJVjr+/+sjm3GkVjQ1zwt/mo8NBuRrBnoMwpjxzMzAiFPlQvvkSaL6D17ekIC+btzyE3Hok4X5jSed/XZgUvxQctoMObrXmRxsEWpEtfeAFm6Xw58QkH7EQdMj0M9nITWz4UB2ObOgvE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87739+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1647586143524918.8377953277311; Thu, 17 Mar 2022 23:49:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id KjP4YY1788612x985MZo0mdH; Thu, 17 Mar 2022 23:49:03 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.6938.1647586142497680816 for ; Thu, 17 Mar 2022 23:49:02 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I4uMrC020862; Fri, 18 Mar 2022 06:47:00 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3evkg78r5t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:00 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 6EFA3A1; Fri, 18 Mar 2022 06:46:59 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 8B4244E; Fri, 18 Mar 2022 06:46:56 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 1/6] [RFC] UefiCpuPkg: Classify IA32/X64 modules in DSC file Date: Fri, 18 Mar 2022 13:43:17 +0800 Message-Id: <20220318054322.11520-2-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: I8WHMFI7eogonRO9vnpBcsqAMmZQCL4P X-Proofpoint-GUID: I8WHMFI7eogonRO9vnpBcsqAMmZQCL4P X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: F5jDqgvKjpxTMwNhhWVe8sJFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586143; bh=DvgtuQbeBdgb124ZJU/XtTgsRWi6oXbdLB8BG04ezsE=; h=Cc:Date:From:Reply-To:Subject:To; b=vmmdBeCAMqERl0k0MP1N3XPFr9lGAod6jMjLcGGw56Qyrtx/pDIHfS0lXVIHv8t5+70 VF/6vM+g75mJW7qMF6etAlGip59D6Os+5F4UAQ7VBFjtdpZbF548cYZtyBa+tYFyCwZd8 a9bizMIYPT0E0vNHeYGQJ4Zuje1Jiw+fmB8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1647586144376100002 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 This is the first step of reworking on UefiCpuPkg in order to accommodating all processor architectures in UEfiCpuPkg. Classify UefiCpuPkg modules to IA32 and X64 sections in DSC file. Move the module to Common section if more than one archs can leverage the same module. Such as the patch 3/6 for BaseUefiCpuLib. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dsc | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index a0bbde9985..6b43ff6822 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -2,6 +2,7 @@ # UefiCpuPkg Package # # Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All right= s reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,7 +24,7 @@ =20 !include MdePkg/MdeLibs.dsc.inc =20 -[LibraryClasses] +[LibraryClasses.common] BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -31,9 +32,7 @@ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf @@ -47,48 +46,56 @@ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf - LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf - SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf - SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib= .inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + +[LibraryClasses.IA32, LibraryClasses.X64] + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf + LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib= .inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezv= ousLib.inf =20 [LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + +[LibraryClasses.IA32.SEC, LibraryClasses.X64.SEC] PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf !if $(TOOL_CHAIN_TAG) =3D=3D "XCODE5" CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5S= ecPeiCpuExceptionHandlerLib.inf !else CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiC= puExceptionHandlerLib.inf !endif - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf =20 [LibraryClasses.common.PEIM] MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf - MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf - RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegi= sterCpuFeaturesLib.inf - CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf =20 [LibraryClasses.IA32.PEIM, LibraryClasses.X64.PEIM] PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuE= xceptionHandlerLib.inf + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf + RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegi= sterCpuFeaturesLib.inf + CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf =20 [LibraryClasses.common.DXE_DRIVER] MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[LibraryClasses.IA32.DXE_DRIVER, LibraryClasses.X64.DXE_DRIVER] CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegi= sterCpuFeaturesLib.inf @@ -99,6 +106,8 @@ MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.= inf MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAlloc= ationLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[LibraryClasses.IA32.DXE_SMM_DRIVER, LibraryClasses.X64.DXE_SMM_DRIVER] CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuE= xceptionHandlerLib.inf =20 [LibraryClasses.common.MM_STANDALONE] @@ -112,7 +121,7 @@ # Drivers/Libraries within this package # =20 -[Components] +[Components.IA32, Components.X64] UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuIoPei/CpuIoPei.inf UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf @@ -122,7 +131,6 @@ UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf =20 -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87739): https://edk2.groups.io/g/devel/message/87739 Mute This Topic: https://groups.io/mt/89863245/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 03:19:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87735+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87735+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1647586026; cv=none; d=zohomail.com; s=zohoarc; b=Ms2inGdLRhTbslgLs8u4wJXP46e+BILe9K3GMmxvOGG0B/9hNVIcRHL2lypefycgTV1FvuZCS+3+0C1YNgoHyUNN7MwE451NKtYCveGKoiENDyfoomG8kWwEFp8WWQ50wrbrpJkmLD5mMelJqSa1ru8XME/FKBzuaw7FBLR04+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647586026; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xFfx//x6gx3Zl+oGnLXQyvShbPYnjRdU6i3QmpeQAxI=; b=Zi5wdPVCzC46KrFDzWh+spbv1nuAHx/EJZWx6WFov1mbW2P7wCB3zMoilArykts+CaGgyc6R89+mO1yWNDcP5lFa9+sPRwQKAr+M/aMbxntxGqDE3tN2J/g/V2guXR2Qlt+ekR5+B6INkp4rBaTMLQ+d/zylMQnpLVhJY7V10jU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87735+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1647586026453947.521096762699; Thu, 17 Mar 2022 23:47:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id wkERYY1788612x6pbq7uxExJ; Thu, 17 Mar 2022 23:47:05 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.6932.1647586024983816877 for ; Thu, 17 Mar 2022 23:47:05 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I5OMbQ029101; Fri, 18 Mar 2022 06:47:03 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3ev99adp6m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:03 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 3FBBB6A; Fri, 18 Mar 2022 06:47:02 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id C34ED4A; Fri, 18 Mar 2022 06:46:59 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 2/6] [RFC] UefiCpuPkg/Include: Add header files of RISC-V processor architecture Date: Fri, 18 Mar 2022 13:43:18 +0800 Message-Id: <20220318054322.11520-3-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: nJVzLQUQR0THJhf_4HuVf_PQpiKnkZRs X-Proofpoint-GUID: nJVzLQUQR0THJhf_4HuVf_PQpiKnkZRs X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 9qycCFhfMhxveg85gmQL801qx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586025; bh=N+HDB78biRgG2QhGbEb/4qtfS3jbyF6e3BiX01KxPp8=; h=Cc:Date:From:Reply-To:Subject:To; b=tfqnfY/J15OLkBM+DLWrhMP6G3hQF1xxoCmMLyw6DYvnM7/7owF2LzKUWKJrLTmtKII qqTon7tqrVJF6+7wkLC/neAu7UzIEmSCc8ZuJSfWoExh93NYx/pL9r35GrziQPCf0ooTw 04j4mXRQGxiFfDPDPMuNWJIEMYfZ6rNVei8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1647586027746100001 Content-Type: text/plain; charset="utf-8" (This is migrated from edk2-platforms:Silicon/RISC-V) https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 RISC-V processor architecture definitions. Signed-off-by: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- .../Include/IndustryStandard/RISC-V/RiscV.h | 162 ++++++++++++++++++ UefiCpuPkg/Include/RISC-V/RiscVImpl.h | 87 ++++++++++ 2 files changed, 249 insertions(+) create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h create mode 100644 UefiCpuPkg/Include/RISC-V/RiscVImpl.h diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h b/UefiCpuPk= g/Include/IndustryStandard/RISC-V/RiscV.h new file mode 100644 index 0000000000..3edd1e6263 --- /dev/null +++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscV.h @@ -0,0 +1,162 @@ +/** @file + RISC-V processor architecture definitions. + + Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights= reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_INDUSTRY_STANDARD_H_ +#define RISCV_INDUSTRY_STANDARD_H_ + +#if defined (MDE_CPU_RISCV64) +#define RISC_V_XLEN_BITS 64 +#else +#endif + +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 = << 0) +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 = << 1) +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 = << 2) +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 = << 3) +#define RISC_V_ISA_RV32E_ISA (0x00000001 = << 4) +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 = << 5) +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 = << 6) +#define RISC_V_ISA_RESERVED_1 (0x00000001 = << 7) +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 = << 8) +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 = << 9) +#define RISC_V_ISA_RESERVED_2 (0x00000001 = << 10) +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 = << 11) +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 = << 12) +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 = << 13) +#define RISC_V_ISA_RESERVED_3 (0x00000001 = << 14) +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 = << 15) +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 = << 16) +#define RISC_V_ISA_RESERVED_4 (0x00000001 = << 17) +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 = << 18) +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 = << 19) +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 = << 20) +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 = << 21) +#define RISC_V_ISA_RESERVED_5 (0x00000001 = << 22) +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 = << 23) +#define RISC_V_ISA_RESERVED_6 (0x00000001 = << 24) +#define RISC_V_ISA_RESERVED_7 (0x00000001 = << 25) + +// +// RISC-V CSR definitions. +// +// +// Machine information +// +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 +#define RISCV_CSR_MACHINE_MARCHID 0xF12 +#define RISCV_CSR_MACHINE_MIMPID 0xF13 +#define RISCV_CSR_MACHINE_HARRID 0xF14 +// +// Machine Trap Setup. +// +#define RISCV_CSR_MACHINE_MSTATUS 0x300 +#define RISCV_CSR_MACHINE_MISA 0x301 +#define RISCV_CSR_MACHINE_MEDELEG 0x302 +#define RISCV_CSR_MACHINE_MIDELEG 0x303 +#define RISCV_CSR_MACHINE_MIE 0x304 +#define RISCV_CSR_MACHINE_MTVEC 0x305 + +#define RISCV_TIMER_COMPARE_BITS 32 +// +// Machine Timer and Counter. +// +// #define RISCV_CSR_MACHINE_MTIME 0x701 +// #define RISCV_CSR_MACHINE_MTIMEH 0x741 +// +// Machine Trap Handling. +// +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 +#define RISCV_CSR_MACHINE_MEPC 0x341 +#define RISCV_CSR_MACHINE_MCAUSE 0x342 +#define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f +#define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) +#define RISCV_CSR_MACHINE_MBADADDR 0x343 +#define RISCV_CSR_MACHINE_MIP 0x344 + +// +// Machine Protection and Translation. +// +#define RISCV_CSR_MACHINE_MBASE 0x380 +#define RISCV_CSR_MACHINE_MBOUND 0x381 +#define RISCV_CSR_MACHINE_MIBASE 0x382 +#define RISCV_CSR_MACHINE_MIBOUND 0x383 +#define RISCV_CSR_MACHINE_MDBASE 0x384 +#define RISCV_CSR_MACHINE_MDBOUND 0x385 + +// +// Supervisor mode CSR. +// +#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100 +#define SSTATUS_SIE_BIT_POSITION 1 +#define SSTATUS_SPP_BIT_POSITION 8 +#define RISCV_CSR_SUPERVISOR_SIE 0x104 +#define RISCV_CSR_SUPERVISOR_STVEC 0x105 +#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140 +#define RISCV_CSR_SUPERVISOR_SEPC 0x141 +#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142 +#define SCAUSE_USER_SOFTWARE_INT 0 +#define SCAUSE_SUPERVISOR_SOFTWARE_INT 1 +#define SCAUSE_USER_TIMER_INT 4 +#define SCAUSE_SUPERVISOR_TIMER_INT 5 +#define SCAUSE_USER_EXTERNAL_INT 8 +#define SCAUSE_SUPERVISOR_EXTERNAL_INT 9 +#define RISCV_CSR_SUPERVISOR_STVAL 0x143 +#define RISCV_CSR_SUPERVISOR_SIP 0x144 +#define RISCV_CSR_SUPERVISOR_SATP 0x180 + +#if defined (MDE_CPU_RISCV64) +#define RISCV_SATP_MODE_MASK 0xF000000000000000 +#define RISCV_SATP_MODE_BIT_POSITION 60 +#endif +#define RISCV_SATP_MODE_OFF 0 +#define RISCV_SATP_MODE_SV32 1 +#define RISCV_SATP_MODE_SV39 8 +#define RISCV_SATP_MODE_SV48 9 +#define RISCV_SATP_MODE_SV57 10 +#define RISCV_SATP_MODE_SV64 11 + +#define SATP64_ASID_MASK 0x0FFFF00000000000 +#define SATP64_PPN_MASK 0x00000FFFFFFFFFFF + +#define RISCV_CAUSE_MISALIGNED_FETCH 0x0 +#define RISCV_CAUSE_FETCH_ACCESS 0x1 +#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define RISCV_CAUSE_BREAKPOINT 0x3 +#define RISCV_CAUSE_MISALIGNED_LOAD 0x4 +#define RISCV_CAUSE_LOAD_ACCESS 0x5 +#define RISCV_CAUSE_MISALIGNED_STORE 0x6 +#define RISCV_CAUSE_STORE_ACCESS 0x7 +#define RISCV_CAUSE_USER_ECALL 0x8 +#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9 +#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa +#define RISCV_CAUSE_MACHINE_ECALL 0xb +#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc +#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd +#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf +#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +// +// Machine Read-Write Shadow of Hypervisor Read-Only Registers +// +#define RISCV_CSR_HTIMEW 0xB01 +#define RISCV_CSR_HTIMEHW 0xB81 +// +// Machine Host-Target Interface (Non-Standard Berkeley Extension) +// +#define RISCV_CSR_MTOHOST 0x780 +#define RISCV_CSR_MFROMHOST 0x781 + +// +// User mode CSR +// +#define RISCV_CSR_CYCLE 0xc00 +#define RISCV_CSR_TIME 0xc01 +#endif diff --git a/UefiCpuPkg/Include/RISC-V/RiscVImpl.h b/UefiCpuPkg/Include/RIS= C-V/RiscVImpl.h new file mode 100644 index 0000000000..e49095de3d --- /dev/null +++ b/UefiCpuPkg/Include/RISC-V/RiscVImpl.h @@ -0,0 +1,87 @@ +/** @file + RISC-V processor implementation definitions. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_H_ +#define RISCV_H_ + +#include +#include + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) + +#if defined (MDE_CPU_RISCV64) +typedef UINT64 RISC_V_REGS_PROTOTYPE; +#else +#endif + +// +// Structure for 128-bit value +// +typedef struct { + UINT64 Value64_L; + UINT64 Value64_H; +} RISCV_UINT128; + +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _EXCEPTION_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; + EFI_PHYSICAL_ADDRESS IllegalInstHander; + EFI_PHYSICAL_ADDRESS BreakpointHander; + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; +} EXCEPTION_HANDLER_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _INTERRUPT_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; + EFI_PHYSICAL_ADDRESS TimerIntHandler; +} INTERRUPT_HANDLER_CONTEXT; + +/// +/// Interrupt handlers in context. +/// +typedef struct _TRAP_HANDLER_CONTEXT { + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; +} TRAP_HANDLER_CONTEXT; + +/// +/// Machine mode context used for saveing hart-local context. +/// +typedef struct _RISCV_MACHINE_MODE_CONTEXT { + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap= handler. + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode t= rap handler. + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode t= rap handler. + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap ha= ndler. + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machi= ne mode. +} RISCV_MACHINE_MODE_CONTEXT; + +#endif --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87735): https://edk2.groups.io/g/devel/message/87735 Mute This Topic: https://groups.io/mt/89863232/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 03:19:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87736+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87736+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1647586027133851.8051539386165; Thu, 17 Mar 2022 23:47:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id sJh1YY1788612xf7mVsh23mA; Thu, 17 Mar 2022 23:47:08 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.6846.1647586027432021580 for ; Thu, 17 Mar 2022 23:47:07 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I5OxwD031962; Fri, 18 Mar 2022 06:47:05 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com (PPS) with ESMTPS id 3ev99adp6t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:05 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 029729A; Fri, 18 Mar 2022 06:47:05 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 8C65B48; Fri, 18 Mar 2022 06:47:02 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 3/6] [RFC] UefiCpuPkg/BaseUefiCpuLib: Add RISC-V RISCV64 instace Date: Fri, 18 Mar 2022 13:43:19 +0800 Message-Id: <20220318054322.11520-4-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: ttEXWDjnIFQy3J7qE_GnhX4atS-K18bp X-Proofpoint-GUID: ttEXWDjnIFQy3J7qE_GnhX4atS-K18bp X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: w43eUbBd7qAki3uJ6BhTkB0Ox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586028; bh=Bctk/VTdPZxkzUyy7d7VJl6GOuCD9NE9BqvyKqeuh4w=; h=Cc:Date:From:Reply-To:Subject:To; b=Edw23TRI83/W8ogmC3+qmJK4K2shI+Ul2vdhIf75hrT32kCJS2wM85uPywfoy60229d g+MBRJsfKGKVkzSb3gp3fDVTFNrSj7CzWUIDP8FxhzLizRGITJ7EENglX4E+FSSffsrQ3 dvwBv7ZTidI75GzzfkMTq56ONE15PVyaCRE= X-ZohoMail-DKIM: fail (Signature date is -1 seconds in the future.) X-ZM-MESSAGEID: 1647586046432100004 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 Add BaseUefiCpuLib instance for RISC-V RISCV64 arch. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dsc | 7 +- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +- .../Include/Library/RISC-V/RiscVCpuLib.h | 118 +++++++++++++++ .../Library/BaseUefiCpuLib/BaseUefiCpuLib.uni | 5 +- .../Library/BaseUefiCpuLib/RISCV64/Cpu.S | 143 ++++++++++++++++++ 5 files changed, 274 insertions(+), 7 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 6b43ff6822..50c9fc294c 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -14,7 +14,7 @@ PLATFORM_VERSION =3D 0.90 DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/UefiCpu - SUPPORTED_ARCHITECTURES =3D IA32|X64 + SUPPORTED_ARCHITECTURES =3D IA32|X64|RISCV64 BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT =20 @@ -55,9 +55,9 @@ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf =20 [LibraryClasses.IA32, LibraryClasses.X64] - UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf @@ -120,6 +120,8 @@ # # Drivers/Libraries within this package # +[Components.common] + UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf =20 [Components.IA32, Components.X64] UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf @@ -144,7 +146,6 @@ UefiCpuPkg/CpuIo2Smm/CpuIo2StandaloneMm.inf UefiCpuPkg/CpuMpPei/CpuMpPei.inf UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf - UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf index 34d3a7bb43..f43498e9b4 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf @@ -5,6 +5,7 @@ # # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2020, AMD Inc. All rights reserved.
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -21,7 +22,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64 # =20 [Sources.IA32] @@ -30,9 +31,12 @@ [Sources.X64] X64/InitializeFpu.nasm =20 -[Sources] +[Sources.IA32, Sources.X64] BaseUefiCpuLib.c =20 +[Sources.RISCV64] + RISCV64/Cpu.S + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h b/UefiCpuPkg/I= nclude/Library/RISC-V/RiscVCpuLib.h new file mode 100644 index 0000000000..610456d0be --- /dev/null +++ b/UefiCpuPkg/Include/Library/RISC-V/RiscVCpuLib.h @@ -0,0 +1,118 @@ +/** @file + RISC-V CPU library definitions. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RISCV_CPU_LIB_H_ +#define RISCV_CPU_LIB_H_ + +#include "RiscVImpl.h" + +/** + RISCV_TRAP_HANDLER +**/ +typedef +VOID +(EFIAPI *RISCV_TRAP_HANDLER)( + VOID + ); + +VOID +RiscVSetMachineScratch ( + RISCV_MACHINE_MODE_CONTEXT *RiscvContext + ); + +UINT32 +RiscVGetMachineScratch ( + VOID + ); + +UINT32 +RiscVGetMachineTrapCause ( + VOID + ); + +UINT64 +RiscVReadMachineTimer ( + VOID + ); + +UINT64 +RiscVReadMachineTimerInterface ( + VOID + ); + +VOID + RiscVSetMachineTimerCmp (UINT64); + +UINT64 +RiscVReadMachineTimerCmp ( + VOID + ); + +UINT64 +RiscVReadMachineInterruptEnable ( + VOID + ); + +UINT64 +RiscVReadMachineInterruptPending ( + VOID + ); + +UINT64 +RiscVReadMachineStatus ( + VOID + ); + +VOID + RiscVWriteMachineStatus (UINT64); + +UINT64 +RiscVReadMachineTrapVector ( + VOID + ); + +UINT64 +RiscVReadMachineIsa ( + VOID + ); + +UINT64 +RiscVReadMachineVendorId ( + VOID + ); + +UINT64 +RiscVReadMachineArchitectureId ( + VOID + ); + +UINT64 +RiscVReadMachineImplementId ( + VOID + ); + +VOID + RiscVSetSupervisorAddressTranslationRegister (UINT64); + +VOID + RiscVSetSupervisorScratch (UINT64); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + +VOID + RiscVSetSupervisorStvec (UINT64); + +UINT64 +RiscVGetSupervisorStvec ( + VOID + ); + +#endif diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni b/UefiCpu= Pkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni index 83c96cea67..a94bbef53e 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni @@ -4,13 +4,14 @@ // The library routines are UEFI specification compliant. // // Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+// Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // // **/ =20 =20 -#string STR_MODULE_ABSTRACT #language en-US "Defines generic r= outines for IA32 family CPUs." +#string STR_MODULE_ABSTRACT #language en-US "Base CPU library." =20 -#string STR_MODULE_DESCRIPTION #language en-US "The library routi= nes comply with the UEFI Specification." +#string STR_MODULE_DESCRIPTION #language en-US "Base CPU library = provides generic routines for specific CPU architecture." =20 diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S b/UefiCpuPkg/L= ibrary/BaseUefiCpuLib/RISCV64/Cpu.S new file mode 100644 index 0000000000..5bc31744db --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/RISCV64/Cpu.S @@ -0,0 +1,143 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V CPU functions. +// +// Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All right= s reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include +#include + +.data + +.text +.align 3 + +// +// Set machine mode scratch. +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_FUNC (RiscVSetMachineScratch) + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0 + ret + +// +// Get machine mode scratch. +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_FUNC (RiscVGetMachineScratch) + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0 + ret + +// +// Get machine trap cause CSR. +// +ASM_FUNC (RiscVGetMachineTrapCause) + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0 + ret + +// +// Get machine interrupt enable +// +ASM_FUNC (RiscVReadMachineInterruptEnable) + csrr a0, RISCV_CSR_MACHINE_MIE + ret + +// +// Get machine interrupt pending +// +ASM_FUNC (RiscVReadMachineInterruptPending) + csrr a0, RISCV_CSR_MACHINE_MIP + ret + +// +// Get machine status +// +ASM_FUNC (RiscVReadMachineStatus) + csrr a0, RISCV_CSR_MACHINE_MSTATUS + ret + +// +// Set machine status +// +ASM_FUNC (RiscVWriteMachineStatus) + csrw RISCV_CSR_MACHINE_MSTATUS, a0 + ret + +// +// Get machine trap vector +// +ASM_FUNC (RiscVReadMachineTrapVector) + csrr a0, RISCV_CSR_MACHINE_MTVEC + ret + +// +// Read machine ISA +// +ASM_FUNC (RiscVReadMachineIsa) + csrr a0, RISCV_CSR_MACHINE_MISA + ret + +// +// Read machine vendor ID +// +ASM_FUNC (RiscVReadMachineVendorId) + csrr a0, RISCV_CSR_MACHINE_MVENDORID + ret + +// +// Read machine architecture ID +// +ASM_FUNC (RiscVReadMachineArchitectureId) + csrr a0, RISCV_CSR_MACHINE_MARCHID + ret + +// +// Read machine implementation ID +// +ASM_FUNC (RiscVReadMachineImplementId) + csrr a0, RISCV_CSR_MACHINE_MIMPID + ret + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH + ret + +// +// Set Supervisor mode trap vector. +// @param a0 : Value set to Supervisor mode trap vector +// +ASM_FUNC (RiscVSetSupervisorStvec) + csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode trap vector +// +ASM_FUNC (RiscVGetSupervisorStvec) + csrr a0, RISCV_CSR_SUPERVISOR_STVEC + ret + +// +// Set Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) + csrw RISCV_CSR_SUPERVISOR_SATP, a0 + ret + --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 17 Mar 2022 23:47:11 -0700 X-Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I5W2Oh002635; Fri, 18 Mar 2022 06:47:09 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3evkfrrpas-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:09 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id F2EFD63; Fri, 18 Mar 2022 06:47:07 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 59D8F4B; Fri, 18 Mar 2022 06:47:05 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 4/6] [RFC] UefiCpuPkg/RiscVOpensbLib: Add opensbi submodule Date: Fri, 18 Mar 2022 13:43:20 +0800 Message-Id: <20220318054322.11520-5-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: R2VquEaogJ4b0cPdIcfx7kvMwyLxhfsM X-Proofpoint-GUID: R2VquEaogJ4b0cPdIcfx7kvMwyLxhfsM X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: o2xuwlrcASjiChThZC6Sg5Lyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586037; bh=sxU2SKAy6WlAsilgToSCpXe7kvrhUb/SZY+O66mvWmM=; h=Cc:Date:From:Reply-To:Subject:To; b=Y3aJbNDc5McwB1tJSBR3n7tiu+iujhymjl04B8Qhw3r45Y2b8zDDqH09gxym1aVSx05 QAo3dzC1JLfb0pi9m9Km+VTwWv/t44ZE+8UyWI2CtL19DuMKI4rpEWFgEJE9sIdH57NpI 1uyiqMJq8weoDLao00wUbdMmvkK5d58ToLA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1647586039623100002 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 (This is migrated from edk2-platforms:Silicon/RISC-V) Add RISC-V opensbi as the submoudle under UefiCpuPkg/Library/RISC-V Signed-off-by: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- .gitmodules | 45 ++++++++++--------- .../Library/RISC-V/RiscVOpensbiLib/opensbi | 1 + 2 files changed, 25 insertions(+), 21 deletions(-) create mode 160000 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi diff --git a/.gitmodules b/.gitmodules index b845c9ee3f..365bcd94bd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,22 +1,25 @@ -[submodule "CryptoPkg/Library/OpensslLib/openssl"] - path =3D CryptoPkg/Library/OpensslLib/openssl - url =3D https://github.com/openssl/openssl -[submodule "SoftFloat"] - path =3D ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3 - url =3D https://github.com/ucb-bar/berkeley-softfloat-3.git -[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"] - path =3D UnitTestFrameworkPkg/Library/CmockaLib/cmocka - url =3D https://github.com/tianocore/edk2-cmocka.git -[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"] - path =3D MdeModulePkg/Universal/RegularExpressionDxe/oniguruma - url =3D https://github.com/kkos/oniguruma -[submodule "MdeModulePkg/Library/BrotliCustomDecompressLib/brotli"] - path =3D MdeModulePkg/Library/BrotliCustomDecompressLib/brotli - url =3D https://github.com/google/brotli -[submodule "BaseTools/Source/C/BrotliCompress/brotli"] - path =3D BaseTools/Source/C/BrotliCompress/brotli - url =3D https://github.com/google/brotli +[submodule "CryptoPkg/Library/OpensslLib/openssl"] + path =3D CryptoPkg/Library/OpensslLib/openssl + url =3D https://github.com/openssl/openssl +[submodule "SoftFloat"] + path =3D ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3 + url =3D https://github.com/ucb-bar/berkeley-softfloat-3.git +[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"] + path =3D UnitTestFrameworkPkg/Library/CmockaLib/cmocka + url =3D https://github.com/tianocore/edk2-cmocka.git +[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"] + path =3D MdeModulePkg/Universal/RegularExpressionDxe/oniguruma + url =3D https://github.com/kkos/oniguruma +[submodule "MdeModulePkg/Library/BrotliCustomDecompressLib/brotli"] + path =3D MdeModulePkg/Library/BrotliCustomDecompressLib/brotli + url =3D https://github.com/google/brotli +[submodule "BaseTools/Source/C/BrotliCompress/brotli"] + path =3D BaseTools/Source/C/BrotliCompress/brotli + url =3D https://github.com/google/brotli ignore =3D untracked -[submodule "RedfishPkg/Library/JsonLib/jansson"] - path =3D RedfishPkg/Library/JsonLib/jansson - url =3D https://github.com/akheron/jansson +[submodule "RedfishPkg/Library/JsonLib/jansson"] + path =3D RedfishPkg/Library/JsonLib/jansson + url =3D https://github.com/akheron/jansson +[submodule "UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi"] + path =3D UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi + url =3D https://github.com/riscv/opensbi diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi b/UefiCpuPkg= /Library/RISC-V/RiscVOpensbiLib/opensbi new file mode 160000 index 0000000000..a731c7e369 --- /dev/null +++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi @@ -0,0 +1 @@ +Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490 --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87737): https://edk2.groups.io/g/devel/message/87737 Mute This Topic: https://groups.io/mt/89863234/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 03:19:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87738+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87738+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1647586034; cv=none; d=zohomail.com; s=zohoarc; b=RGtM71jpTDeTNnvci5kb60qx1NNfPzBvOebstRuOmVj0bPF+UPbnvMuBQUyKlHgRxlo9HdWKBvR2J0ScgLeGHlCKNWpaUTxFUeTjOiFQdEdxmIjamwLPfMyKPyeDXV8aPiryApBv3cWncYTE7Tc3kOY/kPLay1TVZU5NQP8A5LY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647586034; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3VKeWUjnsNLuF4X6wl0Ools4vwfZQUSD0VKaLE5T+I8=; b=IRKQpBA4krdCbPyq5PPppYMt45VrQ+xKu2k3J8i/AL/fDPkms1nfjQTXq+XKWSD3T9265kL0zz94toPcjpbA+t0d4tdUU0sIgubHefYUjXNTxnn+eTJcmGF2sl4Cm2WZp59vmClJINAsntckzu9xG7aEqYuuP00rDSbIet4sNMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87738+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1647586034841231.15449683728082; Thu, 17 Mar 2022 23:47:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LiJoYY1788612x4TikkdHThP; Thu, 17 Mar 2022 23:47:14 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.6742.1647586033467642544 for ; Thu, 17 Mar 2022 23:47:13 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22I0WSE9017538; Fri, 18 Mar 2022 06:47:11 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3eve38u9kd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:11 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id B94D58D; Fri, 18 Mar 2022 06:47:10 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 524B04B; Fri, 18 Mar 2022 06:47:08 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 5/6] [RFC] UefiCpuPkg/Library: Add RiscVOpensbiLib Date: Fri, 18 Mar 2022 13:43:21 +0800 Message-Id: <20220318054322.11520-6-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: mOXCWNG3gSpD7LGUpgl4koH25k_f2Cu_ X-Proofpoint-GUID: mOXCWNG3gSpD7LGUpgl4koH25k_f2Cu_ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: r7p7gR3G4kdOQvN7uPIAih8Rx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586034; bh=AAPZig6gsyRZkyNVYa9XhUBiWBp0kd06EfVMFUNbz/s=; h=Cc:Date:From:Reply-To:Subject:To; b=RvA7ojRN7ejpSgXBqjyc3FjZVuX9SkwTk/b81Ur6SGcGW0InWn+GXUptnxIXIoo1eQy yrOUFVMmbKceCdP+OQ1VFYH0I8vmZA3YUqdnqAwoI7erUmhXRT7PzScrWbTI+xhYxAjtj gEZao32KmY+0XVT1a4HC2b12tAvNM3roFII= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1647586035619100002 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 (This is migrated from edk2-platforms:Silicon/RISC-V) EDK2 RISC-V OpenSBI library which pull in external source files under UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/opensbi to the build process. Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.dec | 12 ++- UefiCpuPkg/UefiCpuPkg.dsc | 6 ++ .../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 +++++++++++++++++++ .../IndustryStandard/RISC-V/RiscVOpensbi.h | 62 +++++++++++++ UefiCpuPkg/Include/RISC-V/OpensbiTypes.h | 82 +++++++++++++++++ BaseTools/Conf/tools_def.template | 2 +- 6 files changed, 250 insertions(+), 3 deletions(-) create mode 100644 UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiL= ib.inf create mode 100644 UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi= .h create mode 100644 UefiCpuPkg/Include/RISC-V/OpensbiTypes.h diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 525cde4634..8e85d242a3 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -1,7 +1,8 @@ ## @file UefiCpuPkg.dec # This Package provides UEFI compatible CPU modules and libraries. # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,9 +15,16 @@ PACKAGE_GUID =3D 2171df9b-0d39-45aa-ac37-2de190010d23 PACKAGE_VERSION =3D 0.90 =20 -[Includes] +[Includes.common] Include =20 +[Includes.RISCV64] + Include/Library + Library/RISC-V/RiscVOpensbiLib/opensbi # OpenSBI header file ref= erence ("include/sbi/...") + Library/RISC-V/RiscVOpensbiLib/opensbi/include # Header file reference f= rom opensbi files, ("sbi/...") + Library/RISC-V/RiscVOpensbiLib/opensbi/platform/generic/include # Header= file reference from opensbi files, ("sbi/...") + + [LibraryClasses] ## @libraryclass Defines some routines that are generic for IA32 famil= y CPU ## to be UEFI specification compliant. diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 50c9fc294c..374e951f29 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -66,6 +66,9 @@ MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezv= ousLib.inf =20 +[LibraryClasses.RISCV64] + RiscVOpensbiLib|UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLi= b.inf + [LibraryClasses.common.SEC] HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf @@ -185,5 +188,8 @@ UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf =20 +[Components.RISCV64] + UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf + [BuildOptions] *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf = b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf new file mode 100644 index 0000000000..54eed050d4 --- /dev/null +++ b/UefiCpuPkg/Library/RISC-V/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -0,0 +1,89 @@ +## @file +# RISC-V Opensbi Library Instance. +# +# Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D RiscVOpensbiLib + FILE_GUID =3D 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVOpensbiLib + +[Sources] + opensbi/lib/sbi/riscv_asm.c + opensbi/lib/sbi/riscv_atomic.c + opensbi/lib/sbi/riscv_hardfp.S + opensbi/lib/sbi/riscv_locks.c + opensbi/lib/sbi/sbi_bitmap.c + opensbi/lib/sbi/sbi_bitops.c + opensbi/lib/sbi/sbi_console.c + opensbi/lib/sbi/sbi_domain.c + opensbi/lib/sbi/sbi_ecall.c + opensbi/lib/sbi/sbi_ecall_base.c + opensbi/lib/sbi/sbi_ecall_hsm.c + opensbi/lib/sbi/sbi_ecall_legacy.c + opensbi/lib/sbi/sbi_ecall_replace.c + opensbi/lib/sbi/sbi_ecall_vendor.c + opensbi/lib/sbi/sbi_emulate_csr.c + opensbi/lib/sbi/sbi_fifo.c + opensbi/lib/sbi/sbi_hart.c + opensbi/lib/sbi/sbi_math.c + opensbi/lib/sbi/sbi_hfence.S + opensbi/lib/sbi/sbi_hsm.c + opensbi/lib/sbi/sbi_illegal_insn.c + opensbi/lib/sbi/sbi_init.c + opensbi/lib/sbi/sbi_ipi.c + opensbi/lib/sbi/sbi_misaligned_ldst.c + opensbi/lib/sbi/sbi_platform.c + opensbi/lib/sbi/sbi_scratch.c + opensbi/lib/sbi/sbi_string.c + opensbi/lib/sbi/sbi_system.c + opensbi/lib/sbi/sbi_timer.c + opensbi/lib/sbi/sbi_tlb.c + opensbi/lib/sbi/sbi_trap.c + opensbi/lib/sbi/sbi_unpriv.c + opensbi/lib/sbi/sbi_expected_trap.S + + opensbi/lib/utils/fdt/fdt_helper.c + opensbi/lib/utils/fdt/fdt_fixup.c + opensbi/lib/utils/fdt/fdt_domain.c + opensbi/lib/utils/ipi/fdt_ipi.c + opensbi/lib/utils/ipi/aclint_mswi.c + opensbi/lib/utils/ipi/fdt_ipi_mswi.c + opensbi/lib/utils/irqchip/fdt_irqchip.c + opensbi/lib/utils/irqchip/fdt_irqchip_plic.c + opensbi/lib/utils/irqchip/plic.c + opensbi/lib/utils/reset/fdt_reset.c + opensbi/lib/utils/reset/fdt_reset_htif.c + opensbi/lib/utils/reset/fdt_reset_sifive.c + opensbi/lib/utils/reset/fdt_reset_thead.c + opensbi/lib/utils/reset/fdt_reset_thead_asm.S + opensbi/lib/utils/serial/fdt_serial.c + opensbi/lib/utils/serial/fdt_serial_htif.c + opensbi/lib/utils/serial/fdt_serial_shakti.c + opensbi/lib/utils/serial/fdt_serial_sifive.c + opensbi/lib/utils/serial/fdt_serial_uart8250.c + opensbi/lib/utils/serial/fdt_serial_gaisler.c + opensbi/lib/utils/serial/gaisler-uart.c + opensbi/lib/utils/serial/shakti-uart.c + opensbi/lib/utils/serial/sifive-uart.c + opensbi/lib/utils/serial/uart8250.c + opensbi/lib/utils/sys/htif.c + opensbi/lib/utils/sys/sifive_test.c + opensbi/lib/utils/timer/fdt_timer.c + opensbi/lib/utils/timer/aclint_mtimer.c + opensbi/lib/utils/timer/fdt_timer_mtimer.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec # For libfdt. + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[BuildOptions] + GCC:*_*_*_PP_FLAGS =3D -D__ASSEMBLY__ diff --git a/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h b/Ue= fiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h new file mode 100644 index 0000000000..db57aeeb37 --- /dev/null +++ b/UefiCpuPkg/Include/IndustryStandard/RISC-V/RiscVOpensbi.h @@ -0,0 +1,62 @@ +/** @file + SBI inline function calls. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EDK2_SBI_H_ +#define EDK2_SBI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS + +typedef +VOID +(EFIAPI *RISCV_HART_SWITCH_MODE)( + IN UINTN FuncArg0, + IN UINTN FuncArg1, + IN UINTN NextAddr, + IN UINTN NextMode, + IN BOOLEAN NextVirt + ); + +// +// Keep the structure member in 64-bit alignment. +// +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension th= is core supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture= ID + RISCV_UINT128 MachineImplId; // Machine Implementati= on ID + RISCV_HART_SWITCH_MODE HartSwitchMode; // OpenSBI's function t= o switch the mode of a hart +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 8) // This is the size = of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC + // structure. Referr= ed by both C code and assembly code. + +typedef struct { + UINT64 BootHartId; + VOID *PeiServiceTable; // PEI = Service table + UINT64 FlattenedDeviceTree; // Poin= ter to Flattened Device tree + UINT64 SecPeiHandOffData; // This= is EFI_SEC_PEI_HAND_OFF passed to PEI Core. + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HAR= T_SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +// +// Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines +// +typedef struct sbi_scratch SBI_SCRATCH; +typedef struct sbi_platform SBI_PLATFORM; + +#endif diff --git a/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h b/UefiCpuPkg/Include/= RISC-V/OpensbiTypes.h new file mode 100644 index 0000000000..918cf686fc --- /dev/null +++ b/UefiCpuPkg/Include/RISC-V/OpensbiTypes.h @@ -0,0 +1,82 @@ +/** @file + RISC-V OpenSBI header file reference. + + Copyright (c) 2022, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EDK2_SBI_TYPES_H_ +#define EDK2_SBI_TYPES_H_ + +#include + +typedef INT8 s8; +typedef UINT8 u8; +typedef UINT8 uint8_t; + +typedef INT16 s16; +typedef UINT16 u16; +typedef INT16 int16_t; +typedef UINT16 uint16_t; + +typedef INT32 s32; +typedef UINT32 u32; +typedef INT32 int32_t; +typedef UINT32 uint32_t; + +typedef INT64 s64; +typedef UINT64 u64; +typedef INT64 int64_t; +typedef UINT64 uint64_t; + +// PRILX is not used in EDK2 but we need to define it here because when +// defining our own types, this constant is not defined but used by OpenSB= I. +#define PRILX "016lx" + +typedef BOOLEAN bool; +typedef unsigned long ulong; +typedef UINT64 uintptr_t; +typedef UINT64 size_t; +typedef INT64 ssize_t; +typedef UINT64 virtual_addr_t; +typedef UINT64 virtual_size_t; +typedef UINT64 physical_addr_t; +typedef UINT64 physical_size_t; + +#define true TRUE +#define false FALSE + +#define __packed __attribute__((packed)) +#define __noreturn __attribute__((noreturn)) +#define __aligned(x) __attribute__((aligned(x))) + +#if defined (__GNUC__) || defined (__clang__) +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) +#else +#define likely(x) (x) +#define unlikely(x) (x) +#endif + +#undef offsetof +#ifdef __compiler_offsetof +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER) +#else +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#endif + +#define container_of(ptr, type, member) ({ \ + const typeof(((type *)0)->member) * __mptr =3D (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) + +#define array_size(x) (sizeof(x) / sizeof((x)[0])) + +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) +#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) +#define ROUNDDOWN(a, b) ((a) / (b) * (b)) + +/* clang-format on */ + +#endif diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 9c310cf23d..32af0bd15e 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -1978,7 +1978,7 @@ DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS =3D= -Wl,--defsym=3DPECOFF_HEADER_S DEFINE GCC5_RISCV_ALL_ASM_FLAGS =3D -c -x assembler -ima= cros $(DEST_DIR_DEBUG)/AutoGen.h DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE =3D -Wno-tautological-co= mpare -Wno-pointer-compare =20 -DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DOpensbiTypes.h +DEFINE GCC5_RISCV_OPENSBI_TYPES =3D -DOPENSBI_EXTERNAL_S= BI_TYPES=3DRISC-V/OpensbiTypes.h =20 DEFINE GCC5_RISCV64_ARCH =3D rv64imafdc DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_CO= MMON) -Wl,--entry,ReferenceAcpiTable -u ReferenceAcpiTable --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87738): https://edk2.groups.io/g/devel/message/87738 Mute This Topic: https://groups.io/mt/89863236/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 16 03:19:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87740+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87740+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164758616118989.16128566257021; Thu, 17 Mar 2022 23:49:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2QigYY1788612xpaEkrJ0JOI; Thu, 17 Mar 2022 23:49:22 -0700 X-Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.6939.1647586156507775380 for ; Thu, 17 Mar 2022 23:49:16 -0700 X-Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22HMlvDn010013; Fri, 18 Mar 2022 06:47:14 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3eve38u9ks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Mar 2022 06:47:14 +0000 X-Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 8C7734E; Fri, 18 Mar 2022 06:47:13 +0000 (UTC) X-Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 1C3834B; Fri, 18 Mar 2022 06:47:10 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Eric Dong , Ray Ni , Rahul Kumar , Sunil V L , Andrew Fish , Leif Lindholm , Michael D Kinney , Chao Li Subject: [edk2-devel] [PATCH 6/6] [RFC] UefiCpuPkg: Update YAML file for RISC-V arch Date: Fri, 18 Mar 2022 13:43:22 +0800 Message-Id: <20220318054322.11520-7-abner.chang@hpe.com> In-Reply-To: <20220318054322.11520-1-abner.chang@hpe.com> References: <20220318054322.11520-1-abner.chang@hpe.com> X-Proofpoint-ORIG-GUID: OAXNQv-WbcJEFUU_OXsqrEa9fS_DvWpZ X-Proofpoint-GUID: OAXNQv-WbcJEFUU_OXsqrEa9fS_DvWpZ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@hpe.com X-Gm-Message-State: 4bPj5h1RqTgIStNYXsPda2Jyx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1647586162; bh=OdwLhPpxyOxFTkVGI2rwS5Gn5NVH8TR3QDEqAIOqMJM=; h=Cc:Date:From:Reply-To:Subject:To; b=DRh9JCoF1IFfc/UH3utkmvrnpl+GMxLMo/thMorsCga1QnQToy5ntPZRbL03r8irPw3 Arv5FR01YhTJPH9JTGJVfIxkoMi3Vk8Gy8sG7kiaOzKpXrm4ch/GnaHVobjw6HCSalpkB T+Y2vWpA5W052AT1Kbvd9Uqsbqdfwm+h9Ng= X-ZohoMail-DKIM: fail (Signature date is -1 seconds in the future.) X-ZM-MESSAGEID: 1647586167011100001 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D3860 Signed-off-by: Abner Chang Co-authored-by: Daniel Schaefer Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Sunil V L Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Cc: Chao Li --- UefiCpuPkg/UefiCpuPkg.ci.yaml | 61 +++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index 6e0ab95fd8..3ead943e8e 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -3,6 +3,7 @@ # # Copyright (c) Microsoft Corporation # Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2022 Hewlett Packard Enterprise Development LP. All rights= reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent ## { @@ -18,6 +19,11 @@ ], ## Both file path and directory path are accepted. "IgnoreFiles": [ + ## Below source files incorporate with open source + ## RISC-V OpenSBI project, in which some coding style is + ## not able to pass the ECC. + "Library/RISC-V/RiscVOpensbiLib/opensbi", + "Include/RISC-V/OpensbiTypes.h" ] }, "CompilerPlugin": { @@ -69,8 +75,59 @@ ## options defined ci/Plugin/SpellCheck "SpellCheck": { "AuditOnly": True, # Fails test but run in AuditOnly mod= e to collect log - "IgnoreFiles": [], # use gitignore syntax to ignore erro= rs in matching files - "ExtendWords": [], # words to extend to the dictionary f= or this package + "IgnoreFiles": [ # use gitignore syntax to ignore erro= rs in matching files + "Library/RISC-V/RiscVOpensbiLib/opensbi/**" + ], + "ExtendWords": [ # words to extend to the dictionary fo= r this package + "aclint", + "dmdepkg", + "ecall", + "ecalls", + "efifstub", + "excep", + "execption", + "gaisler", + "hardfp", + "hfence", + "htimehw", + "htimew", + "impid", + "irqchip", + "keepexceptiontable", + "libfdt", + "mbase", + "mbound", + "mcause", + "mdbase", + "mdbound", + "memeory", + "mfromhost", + "mhartid", + "mibase", + "mibound", + "mideleg", + "mscratch", + "mstatus", + "mtimeh", + "mtimer", + "mtohost", + "mtvec", + "mvendorid", + "opensbi", + "prilx", + "rfence", + "scasue", + "scause", + "sfence", + "sifive", + "smode", + "sramt", + "sscratch", + "sstatus", + "stval", + "stvec", + "transational" + ], "IgnoreStandardPaths": [], # Standard Plugin defined paths that = should be ignore "AdditionalIncludePaths": [] # Additional paths to spell check (wi= ldcards supported) } --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87740): https://edk2.groups.io/g/devel/message/87740 Mute This Topic: https://groups.io/mt/89863248/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-