From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87407+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87407+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915770; cv=none; d=zohomail.com; s=zohoarc; b=Z6TsgwPEr0KhoeV7dUhtUBaMeLXeKuCaKK5Mjdu6wT3nZgAbAsGdOchfvckLzsIdkNB7Jzkv0AJeweKckS4AAPgLT0aQQnYZp0Jw7BSV/0I5V7RZPASfgFzdNL6YZC5BNYl5We8S8zcODtmAKQucykGXxQbUtPDudPSJ9m3UCEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915770; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=U49ybBJQi8MRYWVsTcCzccLcz/WwfYf9ZvDH8hixO/U=; b=b/WKRUk9sdlKZoRpz2tKdqTy18jJtdqmHi8/qZkQ47hi7t/9bN8MmLDMugcmZDOBmcG+R7MUBwSBBuF+X+Uyg1zPpMg+1hTde2F59PoALt3OQflqq30d/mPD4NDUVvhwPMmld/2/MlyIRM/yxWmsJ1ETa6wtgON226tWxSSDD2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87407+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164691577091960.03420963552253; Thu, 10 Mar 2022 04:36:10 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZK6OYY1788612xKkLIt2O8WI; Thu, 10 Mar 2022 04:36:10 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.8737.1646915769372788783 for ; Thu, 10 Mar 2022 04:36:09 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA6181691; Thu, 10 Mar 2022 04:36:08 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2DA793FA27; Thu, 10 Mar 2022 04:36:06 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 1/9] Platform/Sgi: Update ACPI version to v6.4 Date: Thu, 10 Mar 2022 18:05:51 +0530 Message-Id: <20220310123559.18945-2-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: OqKgx2xKOmnbzOvw8ethD64Vx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915770; bh=p5DUz2R9yQXdreUGD61F5c6z3XMVTfLBcdG8VRl/1UQ=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=VPboBMEHKyXY/pk3AFMhsKkvG6BaqFpO8uxqsi7eeoVn2YxuSOtc7zxi9g9ffBewidH Sabauu+5YjZ10C2twVx1NsF4cnL3KXlgWVtpEIuXcweMR8eTqxutsOdkq2piDVjy3l4Wp A4An8hV1ttIviGL9a4VmfniQCGEK9as9Dm4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915771374100005 Content-Type: text/plain; charset="utf-8" Update the common ACPI tables used by all the Neoverse Reference Design platforms to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 221 ++++++++++---------- Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc | 30 +-- Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc | 38 ++-- Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc | 69 +++--- Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc | 26 +-- Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc | 29 ++- 6 files changed, 220 insertions(+), 193 deletions(-) diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/Sgi= Pkg/Include/SgiAcpiHeader.h index d75d54055436..69af1df276a8 100644 --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2018-2021, ARM Limited. All rights reserved. +* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -44,133 +44,134 @@ #pragma pack(1) // PPTT processor core structure typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core; UINT32 ResourceOffset[2]; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache; } RD_PPTT_CORE; =20 // PPTT processor cluster structure typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster; UINT32 ResourceOffset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache; RD_PPTT_CORE Core[CORE_COUNT]; } RD_PPTT_CLUSTER; =20 // PPTT processor cluster structure without cache typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster; RD_PPTT_CORE Core[CORE_COUNT]; } RD_PPTT_MINIMAL_CLUSTER; =20 // PPTT processor package structure typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; UINT32 ResourceOffset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE Slc; RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; } RD_PPTT_SLC_PACKAGE; #pragma pack () =20 // // PPTT processor structure flags for different SoC components as defined = in -// ACPI 6.3 specification +// ACPI 6.4 specification // =20 // Processor structure flags for SoC package #define PPTT_PROCESSOR_PACKAGE_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL = \ } =20 // Processor structure flags for cluster #define PPTT_PROCESSOR_CLUSTER_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL = \ } =20 // Processor structure flags for cluster with multi-thread core #define PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL = \ } =20 // Processor structure flags for single-thread core #define PPTT_PROCESSOR_CORE_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ - EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ + EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_4_PPTT_NODE_IS_LEAF = \ } =20 // Processor structure flags for multi-thread core #define PPTT_PROCESSOR_CORE_THREADED_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, = \ - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, = \ - EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL = \ + EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD, = \ + EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF, = \ + EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL = \ } =20 // Processor structure flags for CPU thread #define PPTT_PROCESSOR_THREAD_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, = \ - EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, = \ - EFI_ACPI_6_3_PPTT_NODE_IS_LEAF = \ + EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID, = \ + EFI_ACPI_6_4_PPTT_PROCESSOR_IS_THREAD, = \ + EFI_ACPI_6_4_PPTT_NODE_IS_LEAF = \ } =20 -// PPTT cache structure flags as defined in ACPI 6.3 Specification +// PPTT cache structure flags as defined in ACPI 6.4 Specification #define PPTT_CACHE_STRUCTURE_FLAGS = \ { = \ - EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, = \ - EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, = \ - EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, = \ - EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, = \ - EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, = \ - EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, = \ - EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID = \ + EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID, = \ + EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID, = \ + EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID, = \ + EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID, = \ + EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID, = \ + EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID, = \ + EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID, = \ + EFI_ACPI_6_4_PPTT_CACHE_ID_VALID = \ } =20 // PPTT cache attributes for data cache #define PPTT_DATA_CACHE_ATTR = \ { = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ } =20 // PPTT cache attributes for instruction cache #define PPTT_INST_CACHE_ATTR = \ { = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ, = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ } =20 // PPTT cache attributes for unified cache #define PPTT_UNIFIED_CACHE_ATTR = \ { = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ - EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK = \ } =20 // A macro to initialise the common header part of EFI ACPI tables as defi= ned by @@ -187,12 +188,13 @@ typedef struct { EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ } =20 -// EFI_ACPI_6_2_GIC_STRUCTURE -#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, = \ - PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) = \ +// EFI_ACPI_6_4_GIC_STRUCTURE +#define EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, = \ + PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency, = \ + SpeOverflowInterrupt) = \ { = \ - EFI_ACPI_6_2_GIC, /* Type */ = \ - sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ = \ + EFI_ACPI_6_4_GIC, /* Type */ = \ + sizeof (EFI_ACPI_6_4_GIC_STRUCTURE), /* Length */ = \ EFI_ACPI_RESERVED_WORD, /* Reserved */ = \ GicId, /* CPUInterfaceNumber */ = \ AcpiCpuUid, /* AcpiProcessorUid */ = \ @@ -207,19 +209,16 @@ typedef struct { GicRBase, /* GICRBaseAddress */ = \ Mpidr, /* MPIDR */ = \ Efficiency, /* ProcessorPowerEfficiencyClass= */ \ - { = \ - EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ = \ - EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ = \ - EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ = \ - } = \ + EFI_ACPI_RESERVED_BYTE, /* Reserved2 */ = \ + SpeOverflowInterrupt /* SpeOverflowInterrupt */ = \ } =20 -// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE -#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, = \ +// EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE +#define EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, = \ GicDistVector, GicVersion) = \ { = \ - EFI_ACPI_6_2_GICD, /* Type */ = \ - sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), = \ + EFI_ACPI_6_4_GICD, /* Type */ = \ + sizeof (EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE), = \ EFI_ACPI_RESERVED_WORD, /* Reserved1 */ = \ GicDistHwId, /* GicId */ = \ GicDistBase, /* PhysicalBaseAddress */ = \ @@ -232,43 +231,43 @@ typedef struct { } = \ } =20 -// EFI_ACPI_6_2_GICR_STRUCTURE -#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLeng= th) \ +// EFI_ACPI_6_4_GICR_STRUCTURE +#define EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLeng= th) \ { = \ - EFI_ACPI_6_2_GICR, /* Type */ = \ - sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ = \ + EFI_ACPI_6_4_GICR, /* Type */ = \ + sizeof (EFI_ACPI_6_4_GICR_STRUCTURE), /* Length */ = \ EFI_ACPI_RESERVED_WORD, /* Reserved */ = \ RedisRegionAddr, /* DiscoveryRangeBaseAddress */ = \ RedisDiscLength /* DiscoveryRangeLength */ = \ } =20 -// EFI_ACPI_6_2_GIC_ITS_STRUCTURE -#define EFI_ACPI_6_2_GIC_ITS_INIT(GicItsId, GicItsBase) = \ +// EFI_ACPI_6_4_GIC_ITS_STRUCTURE +#define EFI_ACPI_6_4_GIC_ITS_INIT(GicItsId, GicItsBase) = \ { = \ - EFI_ACPI_6_2_GIC_ITS, /* Type */ = \ - sizeof (EFI_ACPI_6_2_GIC_ITS_STRUCTURE), = \ + EFI_ACPI_6_4_GIC_ITS, /* Type */ = \ + sizeof (EFI_ACPI_6_4_GIC_ITS_STRUCTURE), = \ EFI_ACPI_RESERVED_WORD, /* Reserved */ = \ GicItsId, /* GicItsId */ = \ GicItsBase, /* PhysicalBaseAddress */ = \ EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ = \ } =20 -// EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE -#define EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT( = \ +// EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE +#define EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT( = \ ProximityDomain, Base, Length, Flags) = \ { = \ - 1, sizeof (EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE), ProximityDomain, = \ + 1, sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE), ProximityDomain, = \ EFI_ACPI_RESERVED_WORD, (Base) & 0xffffffff, = \ (Base) >> 32, (Length) & 0xffffffff, = \ (Length) >> 32, EFI_ACPI_RESERVED_DWORD, Flags, = \ EFI_ACPI_RESERVED_QWORD = \ } =20 -// EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE -#define EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT( = \ +// EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE +#define EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT( = \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) = \ { = \ - 3, sizeof (EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE), ProximityDomain, = \ + 3, sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE), ProximityDomain, = \ ACPIProcessorUID, Flags, ClockDomain = \ } =20 @@ -276,16 +275,16 @@ typedef struct { // HMAT related structures // // Memory Proximity Domain Attributes Structure -// Refer Section 5.2.27.3 in ACPI Specification, Version 6.3 -#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INI= T( \ +// Refer Section 5.2.27.3 in ACPI Specification, Version 6.4 +#define EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INI= T( \ Flags, ProximityDomainForAttachedIntiator, ProximityDomainForMemory) = \ { = \ - EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, = \ + EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, = \ { = \ EFI_ACPI_RESERVED_BYTE, = \ EFI_ACPI_RESERVED_BYTE = \ }, = \ - sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES= ), \ + sizeof (EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES= ), \ { = \ Flags, = \ 0 = \ @@ -321,28 +320,27 @@ typedef struct { } =20 // System Locality Latency and Bandwidth Information Structure -// Refer Section 5.2.27.4 in ACPI Specification, Version 6.3 -#define EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_= INFO_INIT( \ - Flags, DataType, NumInitiatorProximityDomains, = \ +// Refer Section 5.2.27.4 in ACPI Specification, Version 6.4 +#define EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_= INFO_INIT( \ + Flags, DataType, MinTransferSize, NumInitiatorProximityDomains, = \ NumTargetProximityDomains, EntryBaseUnit) = \ { = \ - EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, = \ + EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, = \ { = \ EFI_ACPI_RESERVED_BYTE, = \ EFI_ACPI_RESERVED_BYTE = \ }, = \ - sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWI= DTH_INFO) + \ + sizeof (EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWI= DTH_INFO) + \ (4 * NumInitiatorProximityDomains) + (4 * NumTargetProximityDomains)= + \ (2 * NumInitiatorProximityDomains * NumTargetProximityDomains), = \ { = \ Flags, = \ + 0, = \ 0 = \ }, = \ + MinTransferSize, = \ DataType, = \ - { = \ - EFI_ACPI_RESERVED_BYTE, = \ - EFI_ACPI_RESERVED_BYTE = \ - }, = \ + EFI_ACPI_RESERVED_BYTE, = \ NumInitiatorProximityDomains, = \ NumTargetProximityDomains, = \ { = \ @@ -355,17 +353,17 @@ typedef struct { } =20 // Memory Side Cache Information Structure -// Refer Section 5.2.27.5 in ACPI Specification, Version 6.3 -#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT( = \ +// Refer Section 5.2.27.5 in ACPI Specification, Version 6.4 +#define EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT( = \ MemoryProximityDomain, MemorySideCacheSize, CacheAttributes, = \ NumberOfSmbiosHandles) = \ { = \ - EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO, = \ + EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO, = \ { = \ EFI_ACPI_RESERVED_BYTE, = \ EFI_ACPI_RESERVED_BYTE = \ }, = \ - sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO) + = \ + sizeof (EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO) + = \ (NumberOfSmbiosHandles * 2), = \ MemoryProximityDomain, = \ { = \ @@ -384,7 +382,7 @@ typedef struct { } =20 /** A macro to initialise the Memory Side Cache Information Attributes. - See Table 5.124 in ACPI Specification, Version 6.3 + See Table 5.130 in ACPI Specification, Version 6.4 =20 @param [in] TotalCacheLevels Total Cache Levels for this Memory Proxi= mity. @param [in] CacheLevel Cache Level described in this structure. @@ -399,11 +397,11 @@ typedef struct { TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLine= Size \ } =20 -// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR -#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, = \ +// EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR +#define EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, = \ ACPIProcessorID, NumberOfPrivateResource) = \ { = \ - EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ = \ + EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR, /* Type 0 */ = \ Length, /* Length */ = \ { = \ EFI_ACPI_RESERVED_BYTE, = \ @@ -415,12 +413,12 @@ typedef struct { NumberOfPrivateResource /* Resource count */= \ } =20 -// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE -#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size,= \ - NoOfSets, Associativity, Attributes, LineSize) = \ +// EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE +#define EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size,= \ + NoOfSets, Associativity, Attributes, LineSize, CacheId) = \ { = \ - EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ = \ - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ = \ + EFI_ACPI_6_4_PPTT_TYPE_CACHE, /* Type 1 */ = \ + sizeof (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE), /* Length */ = \ { = \ EFI_ACPI_RESERVED_BYTE, = \ EFI_ACPI_RESERVED_BYTE, = \ @@ -431,7 +429,8 @@ typedef struct { NoOfSets, /* Num of sets */ = \ Associativity, /* Num of ways */ = \ Attributes, /* Cache attributes = */ \ - LineSize /* Line size in byte= s */ \ + LineSize, /* Line size in byte= s */ \ + CacheId /* Cache id */ = \ } =20 /** Helper macro for CPPC _CPC object initialization. Use of this macro is diff --git a/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc b/Platform/ARM/SgiPkg= /AcpiTables/Dbg2.aslc index 279f847cce4c..b85e7272fd82 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc @@ -1,16 +1,22 @@ /** @file -* Debug Port Table 2 (DBG2) -* -* Copyright (c) 2018, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Debug Port Table 2 (DBPG2) + + Debug Port Table 2 is used in platform firmware to describe the debug + ports available on the system to the OS. The reference design platforms = use + the non-secure UART port in the compute subsystem as the debug port. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup + /acpi-debug-port-table **/ =20 -#include "SgiAcpiHeader.h" -#include -#include #include +#include +#include "SgiAcpiHeader.h" =20 #define SGI_DBG2_NUM_DEBUG_PORTS 1 #define SGI_DBG2_NUM_GAS 1 @@ -21,7 +27,7 @@ =20 typedef struct { EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; - EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; UINT32 AddressSize; UINT8 NameSpaceString[SGI_DBG2_N= S_STR_LENGTH]; } DBG2_DEBUG_DEVICE_INFORMATION; @@ -48,7 +54,7 @@ typedef struct { OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UIN= T16 BaseAddressRegister Offset */ \ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UIN= T16 AddressSize Offset */ \ }, = \ - ARM_GAS32 (UartBase), /* EFI_ACPI_6_2_GENERIC= _ADDRESS_STRUCTURE BaseAddressRegister */ \ + ARM_GAS32 (UartBase), /* EFI_ACPI_6_4_GENERIC= _ADDRESS_STRUCTURE BaseAddressRegister */ \ UartAddrLen, /* UINT32 AddressSize = */ \ UartNameStr /* UINT8 NameSpaceStr= ing[MAX_DBG2_NAME_LEN] */ \ } @@ -56,7 +62,7 @@ typedef struct { STATIC DBG2_TABLE Dbg2 =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_6_4_DEBUG_PORT_2_TABLE_SIGNATURE, DBG2_TABLE, EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION ), diff --git a/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc b/Platform/ARM/SgiPkg= /AcpiTables/Fadt.aslc index 9472aff2e054..5ad448d9c9d2 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc @@ -1,26 +1,32 @@ /** @file -* Fixed ACPI Description Table (FADT) -* -* Copyright (c) 2018, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Fixed ACPI Description Table (FADT) + + FADT defines various fixed hardware ACPI information vital to an ACPI + compatible OS. FADT also has a pointer to the DSDT that contains the + Differentiated Definition Block, which in turn provides variable informa= tion + to an ACPI-compatible OS concerning the base system design. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.9, Fixed ACPI Description Table **/ =20 -#include "SgiAcpiHeader.h" #include -#include +#include "SgiAcpiHeader.h" =20 -STATIC EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { +STATIC EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, = // UINT32 FirmwareCtrl 0, = // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, = // UINT8 Reserved0 - EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER, = // UINT8 PreferredPmProfile + EFI_ACPI_6_4_PM_PROFILE_ENTERPRISE_SERVER, = // UINT8 PreferredPmProfile 0, = // UINT16 SciInt 0, = // UINT32 SmiCmd 0, = // UINT8 AcpiEnable @@ -54,11 +60,11 @@ STATIC EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = =3D { 0, = // UINT8 Century 0, = // UINT16 IaPcBootArch 0, = // UINT8 Reserved1 - EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE, = // UINT32 Flags + EFI_ACPI_6_4_HW_REDUCED_ACPI | EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE, = // UINT32 Flags NULL_GAS, = // GAS ResetReg 0, = // UINT8 ResetValue - EFI_ACPI_6_2_ARM_PSCI_COMPLIANT, = // UINT16 ArmBootArchFlags - EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, = // UINT8 MinorRevision + EFI_ACPI_6_4_ARM_PSCI_COMPLIANT, = // UINT16 ArmBootArchFlags + EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, = // UINT8 MinorRevision 0, = // UINT64 XFirmwareCtrl 0, = // UINT64 XDsdt NULL_GAS, = // GAS XPm1aEvtBlk diff --git a/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc b/Platform/ARM/SgiPkg= /AcpiTables/Gtdt.aslc index b53cbb228f92..70765f87e537 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc @@ -1,16 +1,21 @@ /** @file -* Generic Timer Description Table (GTDT) -* -* Copyright (c) 2018, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Generic Timer Description Table (GTDT) + + GTDT provides OSPM with information about a system=E2=80=99s Generic Tim= ers + configuration. This table lists the watchdog and generic timer instances + available on the reference design platforms. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.24, Generic Timer Description Table **/ =20 -#include "SgiAcpiHeader.h" #include #include -#include +#include "SgiAcpiHeader.h" =20 #define SGI_PLATFORM_WATCHDOG_COUNT 2 #define SGI_PLATFORM_TIMER_COUNT (SGI_PLATFORM_WATCHDOG_COUNT + 1) @@ -18,7 +23,7 @@ =20 #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF #define GTDT_GLOBAL_FLAGS 0 -#define GTDT_GTIMER_FLAGS EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIM= ER_INTERRUPT_POLARITY +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIM= ER_INTERRUPT_POLARITY =20 #define SGI_GT_BLOCK_CTL_BASE 0x2A810000 #define SGI_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000 @@ -30,18 +35,18 @@ #define SGI_GT_BLOCK_FRAME0_GSIV FixedPcdGet32 (PcdGtFrame0Gsiv) =20 #define SGI_GTX_TIMER_FLAGS 0 -#define GTX_TIMER_SECURE EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMO= N_FLAG_SECURE_TIMER +#define GTX_TIMER_SECURE EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMO= N_FLAG_SECURE_TIMER #define GTX_TIMER_NON_SECURE 0 -#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMO= N_FLAG_ALWAYS_ON_CAPABILITY +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMO= N_FLAG_ALWAYS_ON_CAPABILITY #define SGI_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | GTX_TI= MER_SECURE) #define SGI_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | GTX_TI= MER_NON_SECURE) =20 -#define EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( \ +#define EFI_ACPI_6_4_ARM_GENERIC_WATCHDOG_STRUCTURE_INIT( \ RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \ WatchdogTimerGSIV, WatchdogTimerFlags) \ { \ - EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, \ - sizeof (EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \ + EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG, \ + sizeof (EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE), \ EFI_ACPI_RESERVED_WORD, \ RefreshFramePhysicalAddress, \ ControlFramePhysicalAddress, \ @@ -52,20 +57,20 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE GtBlock; - EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[SGI_TIMER_FRAM= ES_COUNT]; - EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[SGI_PLATFOR= M_WATCHDOG_COUNT]; -} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE GtBlock; + EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[SGI_TIMER_FRAM= ES_COUNT]; + EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE Watchdogs[SGI_PLATFOR= M_WATCHDOG_COUNT]; +} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLES; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt =3D { +STATIC EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddre= ss 0, // UINT32 Reserved @@ -79,17 +84,19 @@ STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gt= dt =3D { GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2T= imerFlags 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePh= ysicalAddress SGI_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimer= Count - sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 Platfr= omTimerOffset + sizeof (EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE), // UINT32 Platf= romTimerOffset + 0, // UINT32 VirtualPL2Tim= erGSIV + 0 // UINT32 VirtualPL2Tim= erFlags }, { - EFI_ACPI_6_2_GTDT_GT_BLOCK, // UINT8 Type - sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE) + // UINT16 Length - sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE) * + EFI_ACPI_6_4_GTDT_GT_BLOCK, // UINT8 Type + sizeof (EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE) + // UINT16 Length + sizeof (EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE) * SGI_TIMER_FRAMES_COUNT, EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved SGI_GT_BLOCK_CTL_BASE, // UINT64 CntCtl= Base SGI_TIMER_FRAMES_COUNT, // UINT32 GTBloc= kTimerCount - sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBloc= kTimerOffset + sizeof (EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBloc= kTimerOffset }, { { @@ -124,17 +131,17 @@ STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES = Gtdt =3D { } }, { - EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT ( + EFI_ACPI_6_4_ARM_GENERIC_WATCHDOG_STRUCTURE_INIT ( FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), FixedPcdGet32 (PcdWdogWS0Gsiv), 0 ), - EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT ( + EFI_ACPI_6_4_ARM_GENERIC_WATCHDOG_STRUCTURE_INIT ( FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), FixedPcdGet32 (PcdWdogWS1Gsiv), - EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER + EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER ) } }; diff --git a/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc b/Platform/ARM/SgiPkg= /AcpiTables/Mcfg.aslc index 090297d9541a..96fb6281ea53 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc @@ -1,22 +1,24 @@ /** @file -* Memory mapped configuration space base address description table (MCFG) -* -* Copyright (c) 2018, ARM Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Memory mapped configuration space base address description table (MCFG) + + The MCFG table provides the address of the PCI configuration space, which + is required by the OS to perform the PCIe bus enumeration. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - http://www.pcisig.com/home **/ =20 -#include #include +#include +#include #include #include "SgiAcpiHeader.h" #include "SgiPlatform.h" =20 -#include -#include -#include - #pragma pack(1) typedef struct { @@ -28,7 +30,7 @@ typedef struct EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mc= fg =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TA= BLE, EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION ), diff --git a/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc b/Platform/ARM/SgiPkg= /AcpiTables/Spcr.aslc index 632144530076..6467fcdf4fd0 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc @@ -1,20 +1,27 @@ /** @file -* Serial Port Console Redirection Table (SPCR) -* -* Copyright (c) 2018, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Serial Port Console Redirection Table (SPCR) + + SPCR table provides information about the configuration and use of the s= erial + port or non-legacy UART interface. This table list the non-secure UART + instance in the compute subsystem on the reference design platforms as t= he + available serial port. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/ + serial-port-console-redirection-table **/ =20 -#include "SgiAcpiHeader.h" -#include -#include #include +#include +#include "SgiAcpiHeader.h" =20 STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION ), @@ -26,7 +33,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spc= r =3D { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, - // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress; + // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE BaseAddress; ARM_GAS32 (FixedPcdGet64 (PcdSerialDbgRegisterBase)), // UINT8 InterruptType; EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87407): https://edk2.groups.io/g/devel/message/87407 Mute This Topic: https://groups.io/mt/89684943/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87408+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87408+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915772; cv=none; d=zohomail.com; s=zohoarc; b=kSyBBD0Z0T12ECAc0tpU5TdLsRepQObzh2DRjEaMP61QYXqDwa8SJT6IWacBrwtzjcAoFLy7IpgVrZ430wd7ZK53YLmkfj8/wSKd5Unm4w8jOWwqwrFt5w70i4ohfhiTFpM5oklAHKixq1bVsGUrHSs4UYVom8nKUKJ/BPjB/Ws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915772; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=iNC2wgAK5CRf4ORqZEPoInua+Gs+evr9m4iKVNl7Hso=; b=KinV6+sInyU1ZtO40pXPFAPLqWudQcKW5XBvXmo5pAYCFZQCMEvaSI4jbRPgC0jOo0d/Sp8yvUvIDHALgarV1jazj4KZz8K5zleNwy75EPT+SzOLGzaeajOKSJ+UmKDXZmfmYOK2Pkwo1iY8RyuFewS8AS/IcHubg403hCWC0YA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87408+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915772643872.1038030918888; Thu, 10 Mar 2022 04:36:12 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2jkOYY1788612xLNhUvHo2yp; Thu, 10 Mar 2022 04:36:12 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.8989.1646915771043927458 for ; Thu, 10 Mar 2022 04:36:11 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3F041692; Thu, 10 Mar 2022 04:36:10 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 72EE73FA27; Thu, 10 Mar 2022 04:36:09 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform Date: Thu, 10 Mar 2022 18:05:52 +0530 Message-Id: <20220310123559.18945-3-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: iqxTUrhUD4qsq4REdTkgUlRpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915772; bh=IEVxxvEumsYmUJe9c6Gk8S3o7Crqpe3ngJW7mwsP+F4=; h=Cc:Date:From:Reply-To:Subject:To; b=kBFmwri31PFtGyPvCQqCamGysGWp3KXRY1It/uT/QAx3Uqh2acoMAIs/0/gPf3AGQO8 lXDxQBJgCz+VxfcDelW9UIny90wbo8VuN+5GjeGMSlY3oeEns3qOgbVI926Nmv2No5WxI 9Z2XZRv9GMZU+T0hn+StEwxnwhTokqRyl7I= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915773605100010 Content-Type: text/plain; charset="utf-8" Update the SGI-575 platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++++++++++--------- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 86 ++++++++-------- 2 files changed, 100 insertions(+), 91 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/Sgi575/Madt.aslc index f04b77929d71..d3d7d946655f 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2018, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the SGI-575 + platform is included in this table. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORES (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -21,75 +27,76 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE= S]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= S]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0, // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1 - 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1 + 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2 - 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2 + 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-3 - 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-3 + 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-4 - 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-4 + 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-5 - 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-5 + 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-6 - 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-6 + 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-7 - 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-7 + 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), SIZE_1MB), // GIC ITS - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), }; =20 // diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/Sgi575/Pptt.aslc index a1b351379c9e..a0e958ceea7d 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc @@ -1,27 +1,25 @@ /** @file -* Processor Properties Topology Table (PPTT) for SGI-575 platform -* -* This file describes the topological structure of the processor block on = the -* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575 -* platform includes two clusters with four single-thread CPUS. Each of the= CPUs -* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. -* Each cluster includes a 2MB L3 cache. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for SGI-575 platform + + This file describes the topological structure of the processor block on = the + SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575 + platform includes two clusters with four single-thread CPUS. Each of the= CPUs + include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. + Each cluster includes a 2MB L3 cache. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 /** Define helper macro for populating processor core information. =20 @@ -32,10 +30,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -43,47 +41,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 64, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_512KB, /* Size */ = \ 1024, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ } =20 @@ -95,29 +96,30 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), = \ /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ ((PackageId << 1) | ClusterId), /* ACPI Id */ = \ 1 /* Num of private resource */ = \ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].L3Cache), = \ = \ /* L3 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_2MB, /* Size */ = \ 2048, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 1) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* Initialize child cores */ = \ @@ -131,7 +133,7 @@ =20 #pragma pack(1) typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } SGI575_PPTT_PACKAGE; =20 @@ -139,22 +141,22 @@ typedef struct { * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; SGI575_PPTT_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]), PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0 ), --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87408): https://edk2.groups.io/g/devel/message/87408 Mute This Topic: https://groups.io/mt/89684944/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87409+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87409+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915774; cv=none; d=zohomail.com; s=zohoarc; b=Xe40zRUslvGTltxrMRvypMnlQ2Lhc6OlG0kyiWoKOb/NN5U8vgUA5AOvl4Uw5MoqJU1I7o3Mu9NmVekOimqvsePTlae0DowTqzp7cUW3TP507OsTqPBXYC44YAbRA+GobxupTlA7L9dtC0cNXPI3Rlt+3yQwxl7wu9t2wIT0mNU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915774; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1K/qcTBXAjNFoHALBvwzoOyj7zcUdxfJ/DtvbkLay5M=; b=AubFIaiKNc7lDabyloP88LUnfA5Zfm2QO4j/cdRUCSKfFy0WF8YFpWIyxHWi31/z5dcnv1XJSPcJl3JOrnmHK36Dir+WSBW3CC5pQKgxKLlvVT+xZVu/X8sYHGADwXatOfqcnHkE+xwz2iSAW8AP1mju7Fnw3JHvZbBMi5P2QP0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87409+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915774180151.51859582138832; Thu, 10 Mar 2022 04:36:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id KyIqYY1788612xIXrvAW3aVN; Thu, 10 Mar 2022 04:36:13 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.8944.1646915772984691195 for ; Thu, 10 Mar 2022 04:36:13 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D5531691; Thu, 10 Mar 2022 04:36:12 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3C4F53FA27; Thu, 10 Mar 2022 04:36:10 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 3/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform Date: Thu, 10 Mar 2022 18:05:53 +0530 Message-Id: <20220310123559.18945-4-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: eMmemAgpOgNyYxcLjCisQsGIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915773; bh=dqwWM9ZPjdCeUvYyQu53m+PQ2DgpbTx+AzyIrd3iwn0=; h=Cc:Date:From:Reply-To:Subject:To; b=J+bUqdrAVs9s0ExdNQPAAEF7IyPybmteUDNXiE58Ioc4VeNIaJvZ4aQjSHKDW1o0uU4 4FOFjCqbSRP0jDTuj9pWtTqKxPBfE3g+qKa63I8E1RKwLsTQxgptarQFnmXuRPoD0co3D zFujBY45GAE0k+IHos+rylY2fteLJ0bv9P0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915775804100001 Content-Type: text/plain; charset="utf-8" Update the Rd-N1-Edge platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 +++++++++++-------= -- Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 97 +++++++++--------- 2 files changed, 106 insertions(+), 96 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc index 05eb78c5616a..df2576e1d9b7 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Ed= ge + platform is included in this table. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -21,75 +27,76 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1 - 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1 + 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2 - 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2 + 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3 - 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-3 + 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4 - 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-4 + 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5 - 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-5 + 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6 - 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-6 + 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7 - 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-7 + 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */) + 0x2c020000, 0x2c010000, 25, 0, 0, 0) }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), SIZE_1MB), // GIC ITS - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000) + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000) }; =20 // diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc index 63056939a868..50bfcabd7e94 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc @@ -1,28 +1,26 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip pl= atform -* -* This file describes the topological structure of the processor block on = the -* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT tabl= e. The -* RD-N1-Edge platform includes two clusters with four single-thread CPUS. = Each -* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 51= 2KB L2 -* cache. Each cluster includes a 2MB L3 cache. The platform also includes a -* system level cache of 8MB. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip pl= atform + + This file describes the topological structure of the processor block on = the + RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT tabl= e. The + RD-N1-Edge platform includes two clusters with four single-thread CPUS. = Each + of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 51= 2KB L2 + cache. Each cluster includes a 2MB L3 cache. The platform also includes a + system level cache of 8MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 /** Define helper macro for populating processor core information. =20 @@ -33,10 +31,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -44,47 +42,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_512KB, /* Size */ = \ 1024, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ } =20 @@ -96,28 +97,29 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ ((PackageId << 1) | ClusterId), /* ACPI Id */ = \ 1 /* Num of private resource */ = \ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].L3Cache), = \ = \ /* L3 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_2MB, /* Size */ = \ 2048, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 1) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* Initialize child cores */ = \ @@ -131,9 +133,9 @@ =20 #pragma pack(1) typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE Slc; RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDN1EDGE_PPTT_PACKAGE ; =20 @@ -141,36 +143,37 @@ typedef struct { * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RDN1EDGE_PPTT_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc), PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), =20 - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, Package.Slc), =20 - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ 0, /* Next level of cache */ SIZE_8MB, /* Size */ 8192, /* Num of sets */ 16, /* Associativity */ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ + 64, /* Line size */ + 1 /* Cache id */ ), { PPTT_CLUSTER_INIT (0, 0), --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87409): https://edk2.groups.io/g/devel/message/87409 Mute This Topic: https://groups.io/mt/89684946/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87410+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87410+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915776; cv=none; d=zohomail.com; s=zohoarc; b=EcEe5jCbUXfFu1I47pxxZOUIj3IGPzVrvq2dqOYq9mhqagrHkdLRWdpgsPxLbNkNa1+5s/krfGLRQeUaBsjD7IhQH/DIXwjUi6dLhXyMpZiVulOfBv+YVwYYuQznpK1joRHszkSzV/lehiLQYFqX7HDV4kBfhW2lsFtruIzKeu4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915776; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=j3ntIqSQyNoE3nH8Sh8LqeTFvi6ge/elFiV41+ZnrsE=; b=WHTCqA733/TAoz4U9GGnBbwTfPhqeGyB+H7tY/B/eAi1Kx0UwIxZt1dlmgrqpO/d3HEMsygZMyFfe6R71JaxW8bJU8fhkeolXCQwtkjR2XJ5hTCFdKCmJYE3Ey1hPWaV1rLFysu8OZQhzN0CpfWfbxqXzQPlT1CePbfPCmyvl7Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87410+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915776419974.7638429238051; Thu, 10 Mar 2022 04:36:16 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Yx8KYY1788612xuSpg9mWvrV; Thu, 10 Mar 2022 04:36:16 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.8945.1646915774985708701 for ; Thu, 10 Mar 2022 04:36:15 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84E7B1692; Thu, 10 Mar 2022 04:36:14 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 05D543FA27; Thu, 10 Mar 2022 04:36:12 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 4/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform Date: Thu, 10 Mar 2022 18:05:54 +0530 Message-Id: <20220310123559.18945-5-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: S41PfzPg9EfB3YHdmNeICzNTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915776; bh=Aayfwa9IdgiI8NKtqD3e+poB3wAsfBAp5a3sjZkrOVA=; h=Cc:Date:From:Reply-To:Subject:To; b=xb62sS1FxrZBz4goPZ5knLAQnP5qaYmyPDFpqyKpOjJ0wvaOY9Z+T0cfwj2wIw9le+j Aldp3QEZIkYYV4CHgSlBVCXsqrS2f6cjlEE+jXrDgl85OWpoBJOxHL1qDGRsYFkTJ5LkF prg590f5HIqvcr7AXSqmMssTWXeo46Hf6qQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915778173100002 Content-Type: text/plain; charset="utf-8" Update the Rd-N1-Edge multichip platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ++++--- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++++++++++------= ---- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 101 ++++++------- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +++++----- 4 files changed, 201 insertions(+), 177 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc index 704708f94baf..4a55c33396b6 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc @@ -1,17 +1,25 @@ /** @file -* Heterogeneous Memory Attribute Table (HMAT) -* -* Copyright (c) 2020-2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Heterogeneous Memory Attribute Table (HMAT) + + The (HMAT) describes the memory attributes, such as memory side cache + attributes and bandwidth and latency details, related to Memory Proximity + Domains. The software is expected to use this information as a hint for + optimization, or when the system has heterogeneous memory. The attribute= s of + the memory connected to the two chips on this platform are listed in this + table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute = Table **/ =20 -#include #include #include -#include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CHIP_CNT FixedPcdGet32 (PcdChipCount) #define INITATOR_PROXIMITY_DOMAIN_CNT 2 @@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix { } INITIATOR_TARGET_PROXIMITY_MATRIX; =20 typedef struct { - EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER = Header; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES = Proximity[CHIP_CNT]; - EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO = LatencyInfo; + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER = Header; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES = Proximity[CHIP_CNT]; + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO = LatencyInfo; INITIATOR_TARGET_PROXIMITY_MATRIX = Matrix; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache0; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache1; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache0; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache1; } EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE; =20 #pragma pack () @@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { // Header { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE, + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE, EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE, - EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION ), { EFI_ACPI_RESERVED_BYTE, @@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { =20 // Memory Proximity Domain { - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( 1, 0x0, 0x0), - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( 1, 0x1, 0x1), }, =20 // Latency Info - EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_I= NIT ( - 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100), + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_I= NIT ( + 0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 1= 00), { {0, 1}, {0, 1}, @@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { }, =20 // Memory Side Cache - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( 0x0, SIZE_8MB, HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( @@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { ), 0), =20 - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( 0x1, SIZE_8MB, HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc index f9210cc6226a..ecf444028e2e 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2019-2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Ed= ge + dual chip platform is included in this table. + + Copyright (c) 2019 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -23,114 +29,115 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_= CNT * CHIP_CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CH= IP_CNT]; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_= CNT * CHIP_CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[CH= IP_CNT]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). =20 // Chip - 0 CPUs =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1 - 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1 + 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2 - 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2 + 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-3 - 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-3 + 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-4 - 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-4 + 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-5 - 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-5 + 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-6 - 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-6 + 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-7 - 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-7 + 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 // Chip - 1 CPUs =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-8 - 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-8 + 0, 8, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-9 - 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-9 + 0, 9, GET_MPID(0x01000000ULL, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-10 - 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-10 + 0, 10, GET_MPID(0x01000000ULL, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-11 - 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-11 + 0, 11, GET_MPID(0x01000000ULL, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-12 - 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_2_GIC_ENABLED, 2= 3, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-12 + 0, 12, GET_MPID(0x01000100ULL, 0x00ULL), EFI_ACPI_6_4_GIC_ENABLED, 2= 3, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-13 - 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-13 + 0, 13, GET_MPID(0x01000100ULL, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-14 - 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-14 + 0, 14, GET_MPID(0x01000100ULL, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-15 - 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-15 + 0, 15, GET_MPID(0x01000100ULL, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */) + 0x2c020000, 0x2c010000, 25, 0, 0, 0) }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), { // GIC Redistributor for Chip 0 - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), SIZE_1MB), // GIC Redistributor for Chip 1 - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_1MB) } diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc index fa80544b61aa..f9daa4c30187 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc @@ -1,30 +1,28 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip plat= form -* -* This file describes the topological structure of the processor block on = the -* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table.= The -* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platfo= rms -* connected over cache coherent interconnect. Each of the RD-N1-Edge singl= e-chip -* platform includes two clusters with four single-thread CPUS. Each of the= CPUs -* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache= . Each -* cluster includes a 2MB L3 cache. Each instance of the chip includes a sy= stem -* level cache of 8MB. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip plat= form + + This file describes the topological structure of the processor block on = the + RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table.= The + RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platfo= rms + connected over cache coherent interconnect. Each of the RD-N1-Edge singl= e-chip + platform includes two clusters with four single-thread CPUS. Each of the= CPUs + include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache= . Each + cluster includes a 2MB L3 cache. Each instance of the chip includes a sy= stem + level cache of 8MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CHIP_COUNT FixedPcdGet32 (PcdChipCount) =20 @@ -37,10 +35,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -48,47 +46,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_512KB, /* Size */ = \ 1024, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ } =20 @@ -100,28 +101,29 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId]), /* Parent */ = \ ((PackageId << 1) | ClusterId), /* ACPI Id */ = \ 1 /* Num of private resource */ = \ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].L3Cache), = \ = \ /* L3 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_2MB, /* Size */ = \ 2048, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 1) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* Initialize child cores */ = \ @@ -139,7 +141,7 @@ **/ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ = \ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ 0, /* Parent */ = \ @@ -148,18 +150,19 @@ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Slc), = \ = \ /* SLC parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_8MB, /* Size */ = \ 8192, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (PackageId + 1) /* Cache id */ = \ ), = \ = \ { = \ @@ -170,9 +173,9 @@ =20 #pragma pack(1) typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE Slc; RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDN1EDGEX2_PPTT_PACKAGE; =20 @@ -180,17 +183,17 @@ typedef struct { * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_CO= UNT]; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc b/Platform= /ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc index 361db7506845..9be3f3f9b527 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc @@ -1,17 +1,23 @@ /** @file -* Static Resource Affinity Table (SRAT) -* -* Copyright (c) 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Static Resource Affinity Table (SRAT) + + SRAT table provides information that allows OSPM to associate devices su= ch as + processors with system locality / proximity domains and clock domains. T= he + memory attached to the two chips on this platform and its affinity to the + CPUs on its respective chips is listed in this table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table **/ =20 -#include "SgiAcpiHeader.h" -#include "SgiPlatform.h" -#include #include #include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 // // Static Resource Affinity Table @@ -19,9 +25,9 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[4]; - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16]; + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[4]; + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16]; } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; =20 #pragma pack () @@ -30,9 +36,9 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D { // Header { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE, - EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION ), 0x00000001, EFI_ACPI_RESERVED_QWORD @@ -40,54 +46,54 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D { // Memory Affinity { // Chip 0 (2GB and 6GB) - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x0, FixedPcdGet64 (PcdSystemMemoryBase), FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x0, FixedPcdGet64 (PcdDramBlock2Base), FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), =20 // Chip 1 (2GB and 6GB) - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x1, SYSTEM_MEMORY_BASE_REMOTE(1), FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x1, DRAM_BLOCK2_BASE_REMOTE(1), FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), }, // Processor Affinity { - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000000, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000001, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000002, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000003, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000004, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000005, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000006, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000007, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x00000008, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x00000009, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x0000000A, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x0000000B, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x0000000C, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x0000000D, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x0000000E, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x0000000F, 0x00000001, 0x00000000), }, }; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87410): https://edk2.groups.io/g/devel/message/87410 Mute This Topic: https://groups.io/mt/89684947/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87411+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87411+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915777; cv=none; d=zohomail.com; s=zohoarc; b=DqMMp7BGXNWu6eXKW+0jXK6i15oJzFMxdGXs7e/DB9cEGGrctNMdoOjpcaM9YuRNHdGr8eqYsE0qq4wzEGaTaFycwuaR1Sm1hdl4F7m+yMfzs7kYv6YIQZ4+a7y0kT8tploZYEFRH7Vg7zHW6CE1igmaoti5CUhLjx6Q/QgLoa0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915777; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=hhn1nmm/27yJXOZScgOBapm7U+DCdzS1S5d3NUpSpP4=; b=NGnKyY8dB+3h8TzzRk0+EGUdB0zrNsISj+D3/B/ib0FlIZFlcdBfMuXcwNFFaQ+ayq+ZCbusefso9/vwkiqUXJ/WJW1TyhAxEXod1cmqKWp7D+n0Pi2s1MX32bqmme8qAj4Bd/VDiXZVZ9AbwRICkGZkNRvQJZDZ7fWlukmV+Lc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87411+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16469157770381007.7644626185903; Thu, 10 Mar 2022 04:36:17 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id yzWsYY1788612xjmocGFErbh; Thu, 10 Mar 2022 04:36:17 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.8900.1646915776668291790 for ; Thu, 10 Mar 2022 04:36:17 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E55B1691; Thu, 10 Mar 2022 04:36:16 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0D6353FA27; Thu, 10 Mar 2022 04:36:14 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 5/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform Date: Thu, 10 Mar 2022 18:05:55 +0530 Message-Id: <20220310123559.18945-6-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: sGpkU6fZEfiINmGKnLmHOp4Jx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915777; bh=TdwGsee21tEwsQU47VQ4/P4TAEEvfYjj+WGpkiHl9CE=; h=Cc:Date:From:Reply-To:Subject:To; b=MtBtdtXM24ycoG1G4OyZ5RM6rpKsCnE2zTuKV6YMNVzF3jcikn1HwLNsEa79AKEm6bB MUkrTecRUeFcO055g9WR/t/jsHQ/gX/diTXdIXBaijhV8yCJ4EhpNuDF2Icz0FTumPCb2 cdAs4yNl3bQckkne4/ale3LHjswaCbRmBWM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915798289100001 Content-Type: text/plain; charset="utf-8" Update the Rd-E1-Edge platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++++++++++--------= -- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 115 ++++----- 2 files changed, 186 insertions(+), 176 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc index cb70394bfe91..0b2bba575bf5 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2018-2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Ed= ge + platform is included in this table. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -21,173 +27,174 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0 - 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0 + 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0 - 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0 + 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1 - 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1 + 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0 - 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0 + 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1 - 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1 + 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0 - 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0 + 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1 - 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1 + 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0 - 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0 + 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1 - 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1 + 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0 - 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0 + 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1 - 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1 + 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0 - 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0 + 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1 - 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1 + 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 //Cluster 1 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0 - 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0 + 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0 - 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0 + 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 - 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0 - 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-0 + 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1 - 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-2 Thread-1 + 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0 - 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-0 + 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1 - 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-3 Thread-1 + 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0 - 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-0 + 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1 - 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-4 Thread-1 + 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0 - 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-0 + 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1 - 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-5 Thread-1 + 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0 - 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-0 + 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1 - 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-6 Thread-1 + 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0 - 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-0 + 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1 - 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-7 Thread-1 + 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), SIZE_8MB), // GIC ITS - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000) + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000) }; =20 // diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc index 3615a11d75b0..043b85b31bbe 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc @@ -1,28 +1,26 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform -* -* This file describes the topological structure of the processor block on = the -* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1= -Edge -* platform includes two clusters with eight dual-thread CPUS. Each of the = CPUs -* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. -* Each cluster includes a 2MB L3 cache. The platform also includes a system -* level cache of 8MB. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-E1-Edge platform + + This file describes the topological structure of the processor block on = the + RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1= -Edge + platform includes two clusters with eight dual-thread CPUS. Each of the = CPUs + include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache. + Each cluster includes a 2MB L3 cache. The platform also includes a system + level cache of 8MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define THREAD_PER_CORE_E1 2 =20 @@ -35,10 +33,10 @@ **/ #define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) = \ { = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ = \ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ = \ ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), = \ /* ACPI Id */ = \ @@ -55,10 +53,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ 0, /* ACPI Id */ = \ 2 /* Num of private resource= */ \ @@ -66,47 +64,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_32KB, /* Size */ = \ 128, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_32KB, /* Size */ = \ 128, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_256KB, /* Size */ = \ 1024, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 3) | (ClusterId << 2) | CpuId) + 1) /* Cache id */= \ ), = \ = \ /* Thread Initialization */ = \ @@ -124,28 +125,29 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ 0, /* ACPI Id */ = \ 1 /* Num of private resource */ = \ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].L3Cache), = \ = \ /* L3 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_2MB, /* Size */ = \ 2048, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 1) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* Initialize child cores */ = \ @@ -167,7 +169,7 @@ **/ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), = \ PPTT_PROCESSOR_PACKAGE_FLAGS, = \ 0, = \ @@ -176,18 +178,19 @@ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Slc), = \ = \ /* SLC parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_8MB, /* Size */ = \ 8192, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + 1 /* Cache id */ = \ ), = \ = \ { = \ @@ -198,29 +201,29 @@ =20 #pragma pack(1) typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Thread; } RDE1EDGE_PPTT_THREAD; =20 typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core; UINT32 Offset[2]; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache; RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1]; } RDE1EDGE_PPTT_CORE; =20 typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster; UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache; RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE= _E1]; } RDE1EDGE_PPTT_CLUSTER; =20 typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; UINT32 Offset; - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE Slc; RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } RDE1EDGE_PPTT_PACKAGE; =20 @@ -228,17 +231,17 @@ typedef struct { * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RDE1EDGE_PPTT_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87411): https://edk2.groups.io/g/devel/message/87411 Mute This Topic: https://groups.io/mt/89684948/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87412+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87412+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915779; cv=none; d=zohomail.com; s=zohoarc; b=g7NUvba3H+xD8xpjY40FpkAxpPKAoZDPNrasUHVlF5sVCmuqqmwyza3KqtJ8S4GqddWPza4ZTR1VE0I1J4I/Dr3Su7UCXpdAPsNpT68iwBDs+t6MfEN/6o0mQU+JKgRHK875gK//2Je+w3zOOl/x4oJkPxEz8xQFAhud2hb/rSc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915779; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OD+qBLXAZgRDB0ckldjvAUBNTTbZ7NrPaI/wm8d+YJc=; b=JZqk4VJYzKd6MYxkCdSdY8QgwYxP2a/CotjBuxTVKTRXH344gVvPgNnBcO4dPhS8Z40nGDg/v0YoLWig9xJTPD5VCS1Ih2VNugTLJJ/wohXbLARo/kXtr2h8NDdCKVZGta4Fc4sr0FyoGUXt3D7zB9crXCDVw/OdpnISx9rLdOQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87412+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915779614333.9705334728476; Thu, 10 Mar 2022 04:36:19 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id TZwsYY1788612xR6MYOh5AIP; Thu, 10 Mar 2022 04:36:19 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.8946.1646915778398334613 for ; Thu, 10 Mar 2022 04:36:18 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 182021692; Thu, 10 Mar 2022 04:36:18 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CB1E73FA27; Thu, 10 Mar 2022 04:36:16 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 6/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform Date: Thu, 10 Mar 2022 18:05:56 +0530 Message-Id: <20220310123559.18945-7-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: Ycfi4PtgEY3jH5MEvfd804Shx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915779; bh=o8IYN+N4rD78Bka3DzxkAVJLpB9Mw0gN3qKcztEx5Bc=; h=Cc:Date:From:Reply-To:Subject:To; b=j8KYHDJJkUcbJZryF34y7oTX2sfYXcqtKt6Q6DLEQ+m55J42IJbvLcn1BCZEe2GOU6F SfCMCfBqEJc7/6JW0fKuWVaFuX0nqPuQDaou7UFYT0obX4L8wJ7NVtLnCetSzxQbWEmj1 +Q38fbx6f0iFbK8OIP2D8VumRFinebMHcgY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915780547100001 Content-Type: text/plain; charset="utf-8" Update the Rd-V1 platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++++++++++---------- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 84 ++++++----- 2 files changed, 126 insertions(+), 117 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdV1/Madt.aslc index c4551e92c0f2..374b0e2bddbf 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2020, Arm Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-V1 pl= atform + is included in this table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -21,110 +27,111 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[4]; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[4]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1 - 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2 - 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3 - 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core4 - 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core4 + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core5 - 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core5 + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core6 - 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core6 + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core7 - 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core7 + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core8 - 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core8 + 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core9 - 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core9 + 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core10 - 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core10 + 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core11 - 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core11 + 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core12 - 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core12 + 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core13 - 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core13 + 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core14 - 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core14 + 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core15 - 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core15 + 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), SIZE_16MB), // GIC ITS { - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000), - EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000), - EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000), - EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), }, }; =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdV1/Pptt.aslc index 06f059810fb2..fce71845121b 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc @@ -1,27 +1,25 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform -* -* This file describes the topological structure of the processor block on = the -* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The -* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of = the -* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 ca= che. -* The platform also includes a system level cache of 16MB. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform + + This file describes the topological structure of the processor block on = the + RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The + RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of = the + CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 ca= che. + The platform also includes a system level cache of 16MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 /** Define helper macro for populating processor core information. =20 @@ -32,10 +30,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -43,47 +41,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_1MB, /* Size */ = \ 2048, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ } =20 @@ -95,10 +96,10 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ 0 /* Num of private resource */ = \ @@ -115,36 +116,37 @@ * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RD_PPTT_SLC_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), =20 - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, Package.Slc), =20 - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ 0, /* Next level of cache */ SIZE_16MB, /* Size */ 16384, /* Num of sets */ 16, /* Associativity */ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ + 64, /* Line size */ + 1 /* Cache id */ ), =20 { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87412): https://edk2.groups.io/g/devel/message/87412 Mute This Topic: https://groups.io/mt/89684950/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87413+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87413+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915781; cv=none; d=zohomail.com; s=zohoarc; b=HVmD3Jsr9MNdKup1oOWDJzW4NylrXjoRC92+8W8y/7OVwG3yxlEAWgF8IzaKuQIZKJenAJL5vFy+C+Cvlmyiy7NnTJD87U8rIcSluZVU3HPKnpwd6NdcWqBdVvBvWpwlbcnsJGF7wOw/SLZYP8shR4A7IGOTi4mItHu/RwQm35A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915781; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9w4rzs5EpujXW3UPBxwwUVq3dme68JWG2fKaBKrq22s=; b=XWNLkhiK9RKh5tO/FwmVwp9pCpQgc3Z9pl3RKu+39qEJp3CUFAVtep7ko6+jdZc3BetZlrMciXZ81fn6Xx/Mtor81EGsXG4fkqpAcfRgHCB6z5RqotGsTWjzD3M09pPUfpvwB/Ps4vzSZdbd3cK+tmnHLDXMoe7tU6X1qPvAtdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87413+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915781414636.8629492271335; Thu, 10 Mar 2022 04:36:21 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5BrtYY1788612xVkP5HSjwbK; Thu, 10 Mar 2022 04:36:21 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.8903.1646915780200967024 for ; Thu, 10 Mar 2022 04:36:20 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5AFE1691; Thu, 10 Mar 2022 04:36:19 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 94C193FA27; Thu, 10 Mar 2022 04:36:18 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 7/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform Date: Thu, 10 Mar 2022 18:05:57 +0530 Message-Id: <20220310123559.18945-8-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: rfLz9yfBKcBG67vE9QqVx0uSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915781; bh=if41J8lUkOL14abvGGxs+dAxybhYvcbgZCDoetKgY+g=; h=Cc:Date:From:Reply-To:Subject:To; b=fCqZ4zqs+fp2IG/MPRspXCMrCgQO6hGbRgFxAd0pa3DagNeOhKRDybJNLO2MmeMLKaz GxFi4S5oWgBv2g/y1hkc+izo07mN1gyatn5qUiVp0hK92k3IBTrRrM8LYwOLuHiqG1v1H EVryVOFcxS5+3jw1mH/0Pd3AwY0x3HhtxS0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915782795100001 Content-Type: text/plain; charset="utf-8" Update the Rd-V1 multichip platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64 ++++---- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++++++++++---------- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 88 ++++++----- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +++++----- 4 files changed, 211 insertions(+), 188 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc index c2dad0e137d5..b8485cd98ea4 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc @@ -1,17 +1,25 @@ /** @file -* Heterogeneous Memory Attribute Table (HMAT) -* -* Copyright (c) 2020-2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Heterogeneous Memory Attribute Table (HMAT) + + The (HMAT) describes the memory attributes, such as memory side cache + attributes and bandwidth and latency details, related to Memory Proximity + Domains. The software is expected to use this information as a hint for + optimization, or when the system has heterogeneous memory. The attribute= s of + the memory connected to the two chips on this platform are listed in this + table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute = Table **/ =20 -#include #include #include -#include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CHIP_CNT FixedPcdGet32 (PcdChipCount) #define INITATOR_PROXIMITY_DOMAIN_CNT 4 @@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix { } INITIATOR_TARGET_PROXIMITY_MATRIX; =20 typedef struct { - EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER = Header; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES = Proximity[CHIP_CNT]; - EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO = LatencyInfo; + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER = Header; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES = Proximity[CHIP_CNT]; + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO = LatencyInfo; INITIATOR_TARGET_PROXIMITY_MATRIX = Matrix; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache0; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache1; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache2; - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache3; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache0; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache1; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache2; + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO = MemSideCache3; } EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE; =20 #pragma pack () @@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { // Header { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE, + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE, EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE, - EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION ), { EFI_ACPI_RESERVED_BYTE, @@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { =20 // Memory Proximity Domain { - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( 1, 0x0, 0x0), - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( 1, 0x1, 0x1), - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( 1, 0x2, 0x2), - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT ( 1, 0x3, 0x3), }, =20 // Latency Info - EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_I= NIT ( - 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100), + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_I= NIT ( + 0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 1= 00), { {0, 1, 2, 3}, {0, 1, 2, 3}, @@ -90,7 +98,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { }, =20 // Memory Side Cache - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( 0x0, SIZE_1GB, HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( @@ -102,7 +110,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { ), 0), =20 - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( 0x1, SIZE_1GB, HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( @@ -114,7 +122,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { ), 0), =20 - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( 0x2, SIZE_1GB, HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( @@ -126,7 +134,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D { ), 0), =20 - EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( + EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT ( 0x3, SIZE_1GB, HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT ( diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Madt.aslc index 9b3e4f2be370..67687d627670 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2020, Arm Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-V1 + multichip platform is included in this table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -22,125 +28,126 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_= CNT * CHIP_CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CH= IP_CNT]; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[4]; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE_= CNT * CHIP_CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[CH= IP_CNT]; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[4]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). //Chip 0 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1 - 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2 - 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3 - 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 // Chip 1 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0 - 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0 + 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1 - 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1 + 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2 - 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2 + 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3 - 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3 + 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 // Chip 2 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0 - 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0 + 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1 - 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1 + 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2 - 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2 + 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3 - 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3 + 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 // Chip 3 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0 - 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0 + 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1 - 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1 + 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2 - 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2 + 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3 - 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3 + 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), { // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + SGI_REMOTE_CHIP_MEM_OFFSET(0), SIZE_16MB), - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_16MB), - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + SGI_REMOTE_CHIP_MEM_OFFSET(2), SIZE_16MB), - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase) + SGI_REMOTE_CHIP_MEM_OFFSET(3), SIZE_16MB) }, // GIC ITS { - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000), - EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000), - EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000), - EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), }, }; =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc index 607a9eac9dc0..704cb743b528 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc @@ -1,29 +1,27 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform -* -* This file describes the topological structure of the processor block on = the -* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The = RD-V1 -* quad-chip platform is composed of four identical chips connected over ca= che -* coherent interconnect. Each of the chip on the platform includes four si= ngle -* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instru= ction -* cache and 1MB L2 cache. The platform also includes a system level cache = of -* 16MB per chip. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform + + This file describes the topological structure of the processor block on = the + RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The = RD-V1 + quad-chip platform is composed of four identical chips connected over ca= che + coherent interconnect. Each of the chip on the platform includes four si= ngle + thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instru= ction + cache and 1MB L2 cache. The platform also includes a system level cache = of + 16MB per chip. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CHIP_COUNT FixedPcdGet32 (PcdChipCount) =20 @@ -36,10 +34,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 2) | ClusterId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -47,47 +45,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 2) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 2) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_1MB, /* Size */ = \ 2048, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 2) | ClusterId) + 1) /* Cache id */ = \ ), = \ } =20 @@ -99,10 +100,10 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId]), /* Parent */ = \ ((PackageId << 2) | ClusterId), /* ACPI Id */ = \ 0 /* Num of private resource */ = \ @@ -120,7 +121,7 @@ **/ #define PPTT_PACKAGE_INIT(PackageId) = \ { = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ = \ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ = \ 0, /* Parent */ = \ @@ -129,17 +130,18 @@ ), = \ = \ /* Offsets of the private resources */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package[PackageId].Slc), = \ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_16MB, /* Size */ = \ 16384, /* Num of sets */ = \ 16, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (PackageId + 1) /* Cache id */ = \ ), = \ = \ { = \ @@ -155,17 +157,17 @@ * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RD_PPTT_SLC_PACKAGE Package[CHIP_CO= UNT]; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc b/Platform/ARM= /SgiPkg/AcpiTables/RdV1Mc/Srat.aslc index 2ad72e3878c2..b12db67dfe3f 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc @@ -1,17 +1,23 @@ /** @file -* Static Resource Affinity Table (SRAT) -* -* Copyright (c) 2020, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Static Resource Affinity Table (SRAT) + + SRAT table provides information that allows OSPM to associate devices su= ch as + processors with system locality / proximity domains and clock domains. T= he + memory attached to the two chips on this platform and its affinity to the + CPUs on its respective chips is listed in this table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Table **/ =20 -#include "SgiAcpiHeader.h" -#include "SgiPlatform.h" -#include #include #include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 // // Static Resource Affinity Table @@ -19,9 +25,9 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[8]; - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16]; + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[8]; + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16]; } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; =20 #pragma pack () @@ -30,9 +36,9 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D { // Header { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE, - EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION ), 0x00000001, EFI_ACPI_RESERVED_QWORD @@ -40,70 +46,70 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D { // Memory Affinity { // Chip 0 (2GB and 6GB) - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x0, FixedPcdGet64 (PcdSystemMemoryBase), FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x0, FixedPcdGet64 (PcdDramBlock2Base), FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), =20 // Chip 1 (2GB and 6GB) - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x1, SYSTEM_MEMORY_BASE_REMOTE(1), FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x1, DRAM_BLOCK2_BASE_REMOTE(1), FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), =20 // Chip 2 (2GB and 6GB) - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x2, SYSTEM_MEMORY_BASE_REMOTE(2), FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT ( 0x2, DRAM_BLOCK2_BASE_REMOTE(2), FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), =20 // Chip 3 (2GB and 6GB) - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT( 0x3, SYSTEM_MEMORY_BASE_REMOTE(3), FixedPcdGet64 (PcdSystemMemorySize), 0x00000001), - EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT( + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT( 0x3, DRAM_BLOCK2_BASE_REMOTE(3), FixedPcdGet64 (PcdDramBlock2Size), 0x00000001), }, // Processor Affinity { - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000000, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000001, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000002, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x0, 0x00000003, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x00000004, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x00000005, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x00000006, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x1, 0x00000007, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x2, 0x00000008, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x2, 0x00000009, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x2, 0x0000000A, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x2, 0x0000000B, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x3, 0x0000000C, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x3, 0x0000000D, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x3, 0x0000000E, 0x00000001, 0x00000000), - EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT ( + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT ( 0x3, 0x0000000F, 0x00000001, 0x00000000), }, }; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87413): https://edk2.groups.io/g/devel/message/87413 Mute This Topic: https://groups.io/mt/89684952/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87414+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87414+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915783; cv=none; d=zohomail.com; s=zohoarc; b=WMTbEMJzhE1hfEL34JhVbv+v6Q8fhTba8c52D1uSXWTOWi5iLf1no7FYVV3iNEdRN6KXwoCzbwi3zBlPqAjyHi3FAenDlMof2n+Ns9o+JCtKyLOU9EN9GQIxS98rmBIcF0rNt9LjMbF8GuTc9BDCaVYGSiph5y6iOgTsSiQn+r0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915783; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=H1Rui8mXW5cP1zYmokj8GzMCAdzM2MYUdbE4EEroJpE=; b=B536qhotQiMKhIv4PYHTsdKfXvR2Eyg59Fy+ncsD8Spv7i4oYfL9qHvcfXleCIXOEYLWEdE2O9ffz8DDut42F4ek6qmykX7mUKOR/wd2clOUysWtK3vgJGavi9Bl3DptbPHyO7TfRFbwhYvqc+rBBbjVnxMvBOng+2DAD0Na2FQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87414+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915783105393.3155847034602; Thu, 10 Mar 2022 04:36:23 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZIWRYY1788612xFEef3lHpXT; Thu, 10 Mar 2022 04:36:22 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.8904.1646915781994245355 for ; Thu, 10 Mar 2022 04:36:22 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F17B1692; Thu, 10 Mar 2022 04:36:21 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5E2623FA27; Thu, 10 Mar 2022 04:36:20 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 8/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform Date: Thu, 10 Mar 2022 18:05:58 +0530 Message-Id: <20220310123559.18945-9-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: UbOSjlh8GYR4ta5kYFm7yRZEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915782; bh=NXXsd2e4T6N8zso+EZuSVsiCDEoVWCKH8JGSwZaXgPA=; h=Cc:Date:From:Reply-To:Subject:To; b=K7AwDovaA2WXgzwhTEpRWanS8sxv0/79Hzfz/evV0XG0RQdL+M507Z3tyBRipTM8mzg DHh8BqPSzX+E79P62ujAiBDynqs/E2/XRgOOmYFEgpGFGtheHjBLNVPYPSv6dVZ6DM5LQ EHg21vrpECzHmXVpXCYar/KYxHALPRx2dA4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915785089100001 Content-Type: text/plain; charset="utf-8" Update the Rd-N2 platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++++++++++---------- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 84 +++++----- 2 files changed, 128 insertions(+), 119 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdN2/Madt.aslc index dbb23683113a..cdf8b3f2e953 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2020, Arm Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-N2 pl= atform + is included in this table. + + Copyright (c) 2020 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include #include #include -#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ FixedPcdGet32 (PcdCoreCount)) @@ -21,112 +27,113 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[6]; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1 - 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2 - 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3 - 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4 - 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core4 + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5 - 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core5 + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6 - 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core6 + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7 - 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core7 + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core8 - 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core8 + 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core9 - 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core9 + 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core10 - 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core10 + 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core11 - 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core11 + 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core12 - 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core12 + 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core13 - 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core13 + 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core14 - 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core14 + 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core15 - 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core15 + 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), SIZE_16MB), // GIC ITS { - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000), - EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000), - EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000), - EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000), - EFI_ACPI_6_2_GIC_ITS_INIT(4, 0x30140000), - EFI_ACPI_6_2_GIC_ITS_INIT(5, 0x30180000), + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), + EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000), + EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000), }, }; =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/S= giPkg/AcpiTables/RdN2/Pptt.aslc index b70d583ba90c..a1c90fa864ed 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -1,27 +1,25 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-N2 platform -* -* This file describes the topological structure of the processor block on = the -* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 plat= form -* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Da= ta -* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also inc= ludes -* system level cache of 32MB. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-N2 platform + + This file describes the topological structure of the processor block on = the + RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 plat= form + includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Da= ta + cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also inc= ludes + system level cache of 32MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 /** Define helper macro for populating processor core information. =20 @@ -32,10 +30,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -43,47 +41,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_1MB, /* Size */ = \ 2048, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ } =20 @@ -95,10 +96,10 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ 0 /* Num of private resource */ = \ @@ -115,36 +116,37 @@ * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RD_PPTT_SLC_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), =20 - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, Package.Slc), =20 - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ 0, /* Next level of cache */ SIZE_32MB, /* Size */ 32768, /* Num of sets */ 16, /* Associativity */ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ + 64, /* Line size */ + 1 /* Cache id */ ), =20 { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87414): https://edk2.groups.io/g/devel/message/87414 Mute This Topic: https://groups.io/mt/89684953/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 08:26:05 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87415+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87415+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1646915784; cv=none; d=zohomail.com; s=zohoarc; b=KySK5aPbbLMDuROAP3ClLPyyCd/eKEI2v9sVDibQRsf2+og++xqbEg3W98HRbLevnWiOHbkmkQE4M4K5LPrtO48pO4PpOzHF4m5fg8rR1GUucOi4xQJg+WZq0Txl1Yo8OV2FyJgOe04G2tvbuH1KJtITCX/2xwm0iHdHQgFm7tY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646915784; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5MhQ9BhxldHrhKSx5DvEhGpS/8TQPAM0iSaXUDxJKy4=; b=g151kycSOsjyzaQnw3/zSZb7P2Bn1N+M+gE1ww8jg93BsASgNTJG7phlDrSHDUEyemJui2A4uPtJajqZewwHqJ1fwqxnNoNoJZrdlKGpm656ZM+EUHmvZMQskomralyDYOCemUeJvAOEY4+AVqgIAfIyBJYeG7P9YgErIrPrbKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87415+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646915784929950.4365671043079; Thu, 10 Mar 2022 04:36:24 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id QAt8YY1788612xqLkGT7bNe7; Thu, 10 Mar 2022 04:36:24 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.8905.1646915783693360237 for ; Thu, 10 Mar 2022 04:36:23 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6904E16A3; Thu, 10 Mar 2022 04:36:23 -0800 (PST) X-Received: from usa.arm.com (a074742.blr.arm.com [10.162.16.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 278DA3FA27; Thu, 10 Mar 2022 04:36:21 -0800 (PST) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [edk2-platforms][PATCH V1 9/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform Date: Thu, 10 Mar 2022 18:05:59 +0530 Message-Id: <20220310123559.18945-10-pranav.madhu@arm.com> In-Reply-To: <20220310123559.18945-1-pranav.madhu@arm.com> References: <20220310123559.18945-1-pranav.madhu@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pranav.madhu@arm.com X-Gm-Message-State: 0qwrIm8udgtAlB0qPu0Ue8Tzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646915784; bh=6Fruy/zk12HnrW4/8Z8BRJvkjW45B3bJVOzRLSh7CGE=; h=Cc:Date:From:Reply-To:Subject:To; b=qJfngsE+cuxUUOjEE4Hlc5vawbRka6YdNTnSujJSlb5xr0MZBZecfqakOOtcsDH2e5T 7LiIO3Ol/XVo9bT4Sf/IGcnUHm8EQjCqvUPYg0iiWYv18YdGnzzca3CEeZvnNliS4yGnU ewsKDcAtFSvQrlDsy+mQrqUMjWnT3YnhCTs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646915785448100003 Content-Type: text/plain; charset="utf-8" Update the Rd-N2-Cfg1 platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++++++++++--------= -- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 80 +++++++------- 2 files changed, 97 insertions(+), 95 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc index c6bb29a25c61..65926027eadf 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc @@ -1,23 +1,22 @@ /** @file -* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform -* -* This file lists all the processors available on the platform that the OS= PM -* can enumerate and boot. It also lists all the interrupt controllers avai= lable -* in the system. -* -* Copyright (c) 2021, Arm Ltd. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table + Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform + + The MADT table provides OSPM with information necessary for operation on + systems with Generic interrupt controller (GIC). The information about t= he GIC + CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-Cf= g1 + platform is included in this table. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table **/ =20 #include #include #include -#include - #include "SgiAcpiHeader.h" #include "SgiPlatform.h" =20 @@ -28,69 +27,70 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3]; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CORE= _CNT]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[3]; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0 // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, = Flags, // PmuIrq, GicBase, GicVBase, // GicHBase, GsivId, GicRBase, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entry - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1 - 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2 - 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3 - 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4 - 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5 - 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6 - 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7 - 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, - 0, 0, 0, 25, 0, 0), + // (see chapter 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1 + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2 + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3 + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core4 + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core5 + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core6 + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core7 + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, + 0, 0, 0, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsB= ase), SIZE_16MB), // GIC ITS { - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000), - EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000), - EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000), + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), }, }; =20 diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc index 5890544c0b92..52be70f5b170 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc @@ -1,24 +1,22 @@ /** @file -* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform -* -* This file describes the topological structure of the processor block on = the -* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2= -Cfg1 -* platform includes eight single-thread CPUS. Each of the CPUs include 64KB -* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform = also -* includes system level cache of 8MB. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology T= able + Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform + + This file describes the topological structure of the processor block on = the + RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2= -Cfg1 + platform includes eight single-thread CPUS. Each of the CPUs include 64KB + L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform = also + includes system level cache of 8MB. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology T= able **/ =20 -#include #include #include #include - #include "SgiAcpiHeader.h" #include "SgiPlatform.h" =20 @@ -31,10 +29,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), /* Parent */ = \ ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ 2 /* Num of private resource */ = \ @@ -42,47 +40,50 @@ = \ /* Offsets of the private resources */ = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ /* L1 data cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L1 instruction cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ /* Next level of cache */ = \ SIZE_64KB, /* Size */ = \ 256, /* Num of sets */ = \ 4, /* Associativity */ = \ PPTT_INST_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ = \ /* L2 cache parameters */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ 0, /* Next level of cache */ = \ SIZE_1MB, /* Size */ = \ 2048, /* Num of sets */ = \ 8, /* Associativity */ = \ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ - 64 /* Line size */ = \ + 64, /* Line size */ = \ + (((PackageId << 4) | ClusterId) + 1) /* Cache id */ = \ ), = \ } =20 @@ -94,10 +95,10 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ /* Parameters for Cluster */ = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), /* Parent */ = \ ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ 0 /* Num of private resource */ = \ @@ -114,36 +115,37 @@ * Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; RD_PPTT_SLC_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), =20 - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, Package.Slc), =20 - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ 0, /* Next level of cache */ SIZE_8MB, /* Size */ 8192, /* Num of sets */ 16, /* Associativity */ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ - 64 /* Line size */ + 64, /* Line size */ + 1 /* Cache id */ ), =20 { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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