From nobody Fri May 17 05:49:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86707+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86707+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=9elements.com ARC-Seal: i=1; a=rsa-sha256; t=1645023705; cv=none; d=zohomail.com; s=zohoarc; b=g5XOK7LWik7B4b0ODZPsgTf8oyh9VRRxIuWyNps64i1/PGXpMOkZj+P4j3fhi0F654CQqsGy07zc5GSoKr4sWcu4PlPr/8krqn7LPGyG8VeXy4TuBmLTz96N5aEqk9Xcv0Q47U8WKlmUlCpyf1LbndL0CWN9UARawSv0xCX4naA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1645023705; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=FDWeKvnmS+n3ObwD9qMcz2k06GU9L3Zt/vWXeNkD1jk=; b=kzUpeHdXlmM+891up37CB/k1cR8cuOp0xiUZCDKIgsC2GWvFudfnxr4ws/swm5ql7u4TjDJl4wn0kS5bUTZuvAZFE/vcDgbPQKiTQztz6N3dNLLEnk6tIbnyv7qZ5U0CNnkrY355x4MZFrBJNe0jBZ3gqTq1ooe4z5RL8dXb0a0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86707+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1645023705084440.5200625025027; Wed, 16 Feb 2022 07:01:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id rcnHYY1788612xKCY5T7aZwS; Wed, 16 Feb 2022 07:01:44 -0800 X-Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by mx.groups.io with SMTP id smtpd.web09.14.1645023268857703339 for ; Wed, 16 Feb 2022 06:54:29 -0800 X-Received: by mail-ed1-f42.google.com with SMTP id m17so4278036edc.13 for ; Wed, 16 Feb 2022 06:54:28 -0800 (PST) X-Gm-Message-State: qn8xrwAb8Ne766jU0Db7V2nAx1787277AA= X-Google-Smtp-Source: ABdhPJzouct3xpHLipAjiuv0zk//L6Cr4dBxuK8CYh5HxmgiApAAW4qA08uapgVYhgcXQquI0l9LEg== X-Received: by 2002:a50:9d8a:0:b0:410:d303:8af5 with SMTP id w10-20020a509d8a000000b00410d3038af5mr3303537ede.371.1645023267365; Wed, 16 Feb 2022 06:54:27 -0800 (PST) X-Received: from fedora.sec.9e.network (ip-088-153-139-166.um27.pools.vodafone-ip.de. [88.153.139.166]) by smtp.gmail.com with ESMTPSA id 5sm4176420ejq.131.2022.02.16.06.54.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 06:54:26 -0800 (PST) From: "Patrick Rudolph" To: devel@edk2.groups.io Cc: ray.ni@intel.com, benjamin.you@intel.com, maurice.ma@intel.com, guo.dong@intel.com Subject: [edk2-devel][PATCH] UefiPayloadPkg: Fix PciHostBridgeLib Date: Wed, 16 Feb 2022 15:54:25 +0100 Message-Id: <20220216145425.284473-1-patrick.rudolph@9elements.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,patrick.rudolph@9elements.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1645023704; bh=Pp5zVFnHFXXgOJtrPnqRyktbDi3e7KqX7wGqMz2IvlU=; h=Cc:Date:From:Reply-To:Subject:To; b=hPLhuGhX9EowANJ9m38AqZTT5pwc9twfzjEPlJjcCs7i+IZL2ESOM2+wdnzo++4Y17M tVSDzrgtn1K8tMoYi09XEuxE7RwGKgNRgDIDWyYGYXH1NlatnkXjT2Y3UjKXDGkyGv1ux mGpoRM3ztHa7UEGGylEupgbxNT0XZHJikuU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1645023712290100004 Content-Type: text/plain; charset="utf-8" On modern platforms with TBT devices the coreboot resource allocator opens large PCI bridge MMIO windows above 4GiB to place hotplugable PCI BARs there as they won't fit below 4GiB. In addition modern GPGPU devices have very big PCI bars that doesn't fit below 4GiB. The PciHostBridgeLib made lots of assumptions about the coreboot resource allocator that were not verified at runtime and are no longer true. Remove all of the 'coreboot specific' code and implement the same logic as OvmfPkg's ScanForRootBridges. Fixes assertion "ASSERT [PciHostBridgeDxe] Bridge->Mem.Limit < 0x0000000100000000ULL". Tested with coreboot as bootloader on platforms that have PCI resources above 4GiB and on platforms that don't have resources above 4GiB. Signed-off-by: Patrick Rudolph Reviewed-by: Guo Dong --- UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 137 +++--= --------------- 1 file changed, 18 insertions(+), 119 deletions(-) diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c= b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index bf2d10f4bf..8a890b6b53 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -18,92 +18,6 @@ #include #include "PciHostBridge.h" =20 -/** - Adjust the collected PCI resource. - - @param[in] Io IO aperture. - - @param[in] Mem MMIO aperture. - - @param[in] MemAbove4G MMIO aperture above 4G. - - @param[in] PMem Prefetchable MMIO aperture. - - @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G. -**/ -VOID -AdjustRootBridgeResource ( - IN PCI_ROOT_BRIDGE_APERTURE *Io, - IN PCI_ROOT_BRIDGE_APERTURE *Mem, - IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, - IN PCI_ROOT_BRIDGE_APERTURE *PMem, - IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G - ) -{ - UINT64 Mask; - - // - // For now try to downgrade everything into MEM32 since - // - coreboot does not assign resource above 4GB - // - coreboot might allocate interleaved MEM32 and PMEM32 resource - // in some cases - // - if (PMem->Base < Mem->Base) { - Mem->Base =3D PMem->Base; - } - - if (PMem->Limit > Mem->Limit) { - Mem->Limit =3D PMem->Limit; - } - - PMem->Base =3D MAX_UINT64; - PMem->Limit =3D 0; - - if (MemAbove4G->Base < 0x100000000ULL) { - if (MemAbove4G->Base < Mem->Base) { - Mem->Base =3D MemAbove4G->Base; - } - - if (MemAbove4G->Limit > Mem->Limit) { - Mem->Limit =3D MemAbove4G->Limit; - } - - MemAbove4G->Base =3D MAX_UINT64; - MemAbove4G->Limit =3D 0; - } - - if (PMemAbove4G->Base < 0x100000000ULL) { - if (PMemAbove4G->Base < Mem->Base) { - Mem->Base =3D PMemAbove4G->Base; - } - - if (PMemAbove4G->Limit > Mem->Limit) { - Mem->Limit =3D PMemAbove4G->Limit; - } - - PMemAbove4G->Base =3D MAX_UINT64; - PMemAbove4G->Limit =3D 0; - } - - // - // Align IO resource at 4K boundary - // - Mask =3D 0xFFFULL; - Io->Limit =3D ((Io->Limit + Mask) & ~Mask) - 1; - if (Io->Base !=3D MAX_UINT64) { - Io->Base &=3D ~Mask; - } - - // - // Align MEM resource at 1MB boundary - // - Mask =3D 0xFFFFFULL; - Mem->Limit =3D ((Mem->Limit + Mask) & ~Mask) - 1; - if (Mem->Base !=3D MAX_UINT64) { - Mem->Base &=3D ~Mask; - } -} - /** Probe a bar is existed or not. =20 @@ -114,28 +28,24 @@ AdjustRootBridgeResource ( STATIC VOID PcatPciRootBridgeBarExisted ( - IN UINT64 Address, + IN UINTN Address, OUT UINT32 *OriginalValue, OUT UINT32 *Value ) { - UINTN PciAddress; - - PciAddress =3D (UINTN)Address; - // // Preserve the original value // - *OriginalValue =3D PciRead32 (PciAddress); + *OriginalValue =3D PciRead32 (Address); =20 // // Disable timer interrupt while the BAR is probed // DisableInterrupts (); =20 - PciWrite32 (PciAddress, 0xFFFFFFFF); - *Value =3D PciRead32 (PciAddress); - PciWrite32 (PciAddress, *OriginalValue); + PciWrite32 (Address, 0xFFFFFFFF); + *Value =3D PciRead32 (Address); + PciWrite32 (Address, *OriginalValue); =20 // // Enable interrupt @@ -179,9 +89,7 @@ PcatPciRootBridgeParseBars ( IN UINTN BarOffsetEnd, IN PCI_ROOT_BRIDGE_APERTURE *Io, IN PCI_ROOT_BRIDGE_APERTURE *Mem, - IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, - IN PCI_ROOT_BRIDGE_APERTURE *PMem, - IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G =20 ) { @@ -246,11 +154,7 @@ PcatPciRootBridgeParseBars ( // Length =3D ((~Length) + 1) & 0xffffffff; =20 - if ((Value & BIT3) =3D=3D BIT3) { - MemAperture =3D PMem; - } else { - MemAperture =3D Mem; - } + MemAperture =3D Mem; } else { // // 64bit @@ -269,8 +173,8 @@ PcatPciRootBridgeParseBars ( Length =3D LShiftU64 (1ULL, LowBit); } =20 - if ((Value & BIT3) =3D=3D BIT3) { - MemAperture =3D PMemAbove4G; + if (Base < BASE_4GB) { + MemAperture =3D Mem; } else { MemAperture =3D MemAbove4G; } @@ -291,6 +195,8 @@ PcatPciRootBridgeParseBars ( } } =20 +STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture =3D { MAX_UINT64, 0 }; + /** Scan for all root bridges in platform. =20 @@ -317,8 +223,6 @@ ScanForRootBridges ( PCI_ROOT_BRIDGE_APERTURE Io; PCI_ROOT_BRIDGE_APERTURE Mem; PCI_ROOT_BRIDGE_APERTURE MemAbove4G; - PCI_ROOT_BRIDGE_APERTURE PMem; - PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; PCI_ROOT_BRIDGE_APERTURE *MemAperture; PCI_ROOT_BRIDGE *RootBridges; UINTN BarOffsetEnd; @@ -338,9 +242,7 @@ ScanForRootBridges ( ZeroMem (&Io, sizeof (Io)); ZeroMem (&Mem, sizeof (Mem)); ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); - ZeroMem (&PMem, sizeof (PMem)); - ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); - Io.Base =3D Mem.Base =3D MemAbove4G.Base =3D PMem.Base =3D PMemAbove4G= .Base =3D MAX_UINT64; + Io.Base =3D Mem.Base =3D MemAbove4G.Base =3D MAX_UINT64; // // Scan all the PCI devices on the primary bus of the PCI root bridge // @@ -446,16 +348,17 @@ ScanForRootBridges ( =20 // // Get the Prefetchable Memory range that the PPB is decoding + // and merge it into Memory range // Value =3D Pci.Bridge.PrefetchableMemoryBase & 0x0f; Base =3D ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) <= < 16; Limit =3D (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0) << 16) | 0xfffff; - MemAperture =3D &PMem; + MemAperture =3D &Mem; if (Value =3D=3D BIT0) { Base |=3D LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32,= 32); Limit |=3D LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32= , 32); - MemAperture =3D &PMemAbove4G; + MemAperture =3D &MemAbove4G; } =20 if ((Base > 0) && (Base < Limit)) { @@ -513,9 +416,7 @@ ScanForRootBridges ( BarOffsetEnd, &Io, &Mem, - &MemAbove4G, - &PMem, - &PMemAbove4G + &MemAbove4G ); =20 // @@ -593,8 +494,6 @@ ScanForRootBridges ( ); ASSERT (RootBridges !=3D NULL); =20 - AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4= G); - InitRootBridge ( Attributes, Attributes, @@ -604,8 +503,8 @@ ScanForRootBridges ( &Io, &Mem, &MemAbove4G, - &PMem, - &PMemAbove4G, + &mNonExistAperture, + &mNonExistAperture, &RootBridges[*NumberOfRootBridges] ); RootBridges[*NumberOfRootBridges].ResourceAssigned =3D TRUE; --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86707): https://edk2.groups.io/g/devel/message/86707 Mute This Topic: https://groups.io/mt/89186676/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-