From nobody Tue Apr 30 00:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1534299284945114.33516629923429; Tue, 14 Aug 2018 19:14:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BB8FC210F16B0; Tue, 14 Aug 2018 19:14:42 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ECE8F210ED792 for ; Tue, 14 Aug 2018 19:14:39 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2018 19:14:38 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 14 Aug 2018 19:14:38 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,241,1531810800"; d="scan'208";a="81837402" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 15 Aug 2018 10:14:31 +0800 Message-Id: <20180815021435.13748-2-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180815021435.13748-1-eric.dong@intel.com> References: <20180815021435.13748-1-eric.dong@intel.com> Subject: [edk2] [Patch v4 1/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use GDT/IDT saved in Smram. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Laszlo Ersek MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current implementation will copy GDT/IDT at SmmReadyToLock point from ACPI NVS memory to Smram. Later at S3 resume phase, it restore the memory saved in Smram to ACPI NVS. It can directly use GDT/IDT saved in Smram instead of restore the original ACPI NVS memory. This patch do this change. V4 changes: 1. Remove global variables mGdtForAp/mIdtForAp/mMachineCheckHandlerForAp. Test Done: Do the OS boot and S3 resume test. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek Reviewed-by: Ruiyu Ni Tested-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 0b8ef70359..abd8a5a07b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -66,9 +66,6 @@ ACPI_CPU_DATA mAcpiCpuData; volatile UINT32 mNumberToFinish; MP_CPU_EXCHANGE_INFO *mExchangeInfo; BOOLEAN mRestoreSmmConfigurationInS3 =3D FALSE; -VOID *mGdtForAp =3D NULL; -VOID *mIdtForAp =3D NULL; -VOID *mMachineCheckHandlerForAp =3D NULL; MP_MSR_LOCK *mMsrSpinLocks =3D NULL; UINTN mMsrSpinLockCount; UINTN mMsrCount =3D 0; @@ -448,13 +445,6 @@ PrepareApStartupVector ( CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) = mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR)); CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) = mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR)); =20 - // - // Copy AP's GDT, IDT and Machine Check handler from SMRAM to ACPI NVS m= emory - // - CopyMem ((VOID *) mExchangeInfo->GdtrProfile.Base, mGdtForAp, mExchangeI= nfo->GdtrProfile.Limit + 1); - CopyMem ((VOID *) mExchangeInfo->IdtrProfile.Base, mIdtForAp, mExchangeI= nfo->IdtrProfile.Limit + 1); - CopyMem ((VOID *)(UINTN) mAcpiCpuData.ApMachineCheckHandlerBase, mMachin= eCheckHandlerForAp, mAcpiCpuData.ApMachineCheckHandlerSize); - mExchangeInfo->StackStart =3D (VOID *) (UINTN) mAcpiCpuData.StackAddres= s; mExchangeInfo->StackSize =3D mAcpiCpuData.StackSize; mExchangeInfo->BufferStart =3D (UINT32) StartupVector; @@ -831,6 +821,9 @@ GetAcpiCpuData ( ACPI_CPU_DATA *AcpiCpuData; IA32_DESCRIPTOR *Gdtr; IA32_DESCRIPTOR *Idtr; + VOID *GdtForAp; + VOID *IdtForAp; + VOID *MachineCheckHandlerForAp; =20 if (!mAcpiS3Enable) { return; @@ -893,14 +886,18 @@ GetAcpiCpuData ( Gdtr =3D (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile; Idtr =3D (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile; =20 - mGdtForAp =3D AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAc= piCpuData.ApMachineCheckHandlerSize); - ASSERT (mGdtForAp !=3D NULL); - mIdtForAp =3D (VOID *) ((UINTN)mGdtForAp + (Gdtr->Limit + 1)); - mMachineCheckHandlerForAp =3D (VOID *) ((UINTN)mIdtForAp + (Idtr->Limit = + 1)); + GdtForAp =3D AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcp= iCpuData.ApMachineCheckHandlerSize); + ASSERT (GdtForAp !=3D NULL); + IdtForAp =3D (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1)); + MachineCheckHandlerForAp =3D (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + = 1)); + + CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1); + CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1); + CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachine= CheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize); =20 - CopyMem (mGdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1); - CopyMem (mIdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1); - CopyMem (mMachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachin= eCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize); + Gdtr->Base =3D (UINTN)GdtForAp; + Idtr->Base =3D (UINTN)IdtForAp; + mAcpiCpuData.ApMachineCheckHandlerBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)= MachineCheckHandlerForAp; } =20 /** --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 00:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15342992863091008.7563141421094; Tue, 14 Aug 2018 19:14:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ED5A0210F16B9; Tue, 14 Aug 2018 19:14:42 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D423210EFB15 for ; Tue, 14 Aug 2018 19:14:41 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2018 19:14:39 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 14 Aug 2018 19:14:39 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,241,1531810800"; d="scan'208";a="81837415" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 15 Aug 2018 10:14:32 +0800 Message-Id: <20180815021435.13748-3-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180815021435.13748-1-eric.dong@intel.com> References: <20180815021435.13748-1-eric.dong@intel.com> MIME-Version: 1.0 Subject: [edk2] [Patch v4 2/5] UefiCpuPkg/AcpiCpuData.h: Remove AcpiNVS and Below 4G limitation. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Ruiyu Ni Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 ACPI_CPU_DATA structure first introduced to save data in normal boot phase. Also this data will be used in S3 phase by one PEI driver. So in first phase, this data is been defined to use ACPI NVS memory type and must below 4G. Later in order to fix potential security issue, PiSmmCpuDxeSmm driver added logic to copy ACPI_CPU_DATA (except ResetVector and Stack buffer) to smram at smm ready to lock point. ResetVector must below 1M and Stack buffer is write only in S3 phase, so these two fields not copy to smram. Also PiSmmCpuDxeSmm driver owned the task to restore the CPU setting and it's a SMM driver. After above change, the acpi nvs memory type and below 4G limitation is no longer needed. This change remove the limitation in the comments for ACPI_CPU_DATA definition. Cc: Marvin H=C3=A4user Cc: Fan Jeff Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek Reviewed-by: Ruiyu Ni Tested-by: Laszlo Ersek --- UefiCpuPkg/Include/AcpiCpuData.h | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD= ata.h index ec092074ce..9e51145c08 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -1,7 +1,7 @@ /** @file Definitions for CPU S3 data. =20 -Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -57,15 +57,13 @@ typedef struct { // UINT32 InitialApicId; // - // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer= must be - // allocated below 4GB from memory of type EfiACPIMemoryNVS. + // Physical address of CPU_REGISTER_TABLE_ENTRY structures. // EFI_PHYSICAL_ADDRESS RegisterTableEntry; } CPU_REGISTER_TABLE; =20 // -// Data structure that is required for ACPI S3 resume. This structure mus= t be -// allocated below 4GB from memory of type EfiACPIMemoryNVS. The PCD +// Data structure that is required for ACPI S3 resume. The PCD // PcdCpuS3DataAddress must be set to the physical address where this stru= cture // is allocated // @@ -78,21 +76,17 @@ typedef struct { // EFI_PHYSICAL_ADDRESS StartupVector; // - // Physical address of structure of type IA32_DESCRIPTOR. This structur= e must - // be allocated below 4GB from memory of type EfiACPIMemoryNVS. The + // Physical address of structure of type IA32_DESCRIPTOR. The // IA32_DESCRIPTOR structure provides the base address and length of a G= DT - // The buffer for GDT must also be allocated below 4GB from memory of ty= pe - // EfiACPIMemoryNVS. The GDT must be filled in with the GDT contents th= at are + // The GDT must be filled in with the GDT contents that are // used during an ACPI S3 resume. This is typically the contents of the= GDT // used by the boot processor when the platform is booted. // EFI_PHYSICAL_ADDRESS GdtrProfile; // - // Physical address of structure of type IA32_DESCRIPTOR. This structur= e must - // be allocated below 4GB from memory of type EfiACPIMemoryNVS. The + // Physical address of structure of type IA32_DESCRIPTOR. The // IA32_DESCRIPTOR structure provides the base address and length of an = IDT. - // The buffer for IDT must also be allocated below 4GB from memory of ty= pe - // EfiACPIMemoryNVS. The IDT must be filled in with the IDT contents th= at are + // The IDT must be filled in with the IDT contents that are // used during an ACPI S3 resume. This is typically the contents of the= IDT // used by the boot processor when the platform is booted. // @@ -100,7 +94,7 @@ typedef struct { // // Physical address of a buffer that is used as stacks during ACPI S3 re= sume. // The total size of this buffer, in bytes, is NumberOfCpus * StackSize.= This - // structure must be allocated below 4GB from memory of type EfiACPIMemo= ryNVS. + // structure must be allocated from memory of type EfiACPIMemoryNVS. // EFI_PHYSICAL_ADDRESS StackAddress; // @@ -118,14 +112,12 @@ typedef struct { // Physical address of structure of type MTRR_SETTINGS that contains a c= opy // of the MTRR settings that are compatible with the MTRR settings used = by // the boot processor when the platform was booted. These MTRR settings= are - // used during an ACPI S3 resume. This structure must be allocated belo= w 4GB - // from memory of type EfiACPIMemoryNVS. + // used during an ACPI S3 resume. // EFI_PHYSICAL_ADDRESS MtrrTable; // // Physical address of an array of CPU_REGISTER_TABLE structures, with - // NumberOfCpus entries. This array must be allocated below 4GB from me= mory - // of type EfiACPIMemoryNVS. If a register table is not required, then = the + // NumberOfCpus entries. If a register table is not required, then the // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to= 0. // If TableLength is > 0, then elements of RegisterTableEntry are used to // initialize the CPU that matches InitialApicId, during an ACPI S3 resu= me, @@ -134,8 +126,7 @@ typedef struct { EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable; // // Physical address of an array of CPU_REGISTER_TABLE structures, with - // NumberOfCpus entries. This array must be allocated below 4GB from me= mory - // of type EfiACPIMemoryNVS. If a register table is not required, then = the + // NumberOfCpus entries. If a register table is not required, then the // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to= 0. // If TableLength is > 0, then elements of RegisterTableEntry are used to // initialize the CPU that matches InitialApicId, during an ACPI S3 resu= me, @@ -144,8 +135,7 @@ typedef struct { EFI_PHYSICAL_ADDRESS RegisterTable; // // Physical address of a buffer that contains the machine check handler = that - // is used during an ACPI S3 Resume. This buffer must be allocated belo= w 4GB - // from memory of type EfiACPIMemoryNVS. In order for this machine check + // is used during an ACPI S3 Resume. In order for this machine check // handler to be active on an AP during an ACPI S3 resume, the machine c= heck // vector in the IDT provided by IdtrProfile must be initialized to tran= sfer // control to this physical address. --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 00:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1534299289064946.3264670390274; Tue, 14 Aug 2018 19:14:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2A9A3210F16A0; Tue, 14 Aug 2018 19:14:44 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B1B60210F16A0 for ; Tue, 14 Aug 2018 19:14:42 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2018 19:14:41 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 14 Aug 2018 19:14:41 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,241,1531810800"; d="scan'208";a="81837425" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 15 Aug 2018 10:14:33 +0800 Message-Id: <20180815021435.13748-4-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180815021435.13748-1-eric.dong@intel.com> References: <20180815021435.13748-1-eric.dong@intel.com> MIME-Version: 1.0 Subject: [edk2] [Patch v4 3/5] UefiCpuPkg/CpuS3DataDxe: Change Memory Type and address limitation. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Ruiyu Ni Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 Because CpuS3Data memory will be copy to smram at SmmReadyToLock point, the memory type no need to be ACPI NVS type, also the address not limit to below 4G. This change remove the limit of ACPI NVS memory type and below 4G. V4 Changes: 1. Create AllocateZeroPages and use it. It's easy to use than gBS->Allocate= Pages. Pass OS boot and resume from S3 test. Cc: Marvin H=C3=A4user Cc: Fan Jeff Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek Reviewed-by: Ruiyu Ni Tested-by: Laszlo Ersek --- UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 34 +++++++++++++++++++++++++---= ---- UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf | 1 + 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/= CpuS3Data.c index dccb406b8d..3e8c8b383c 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c @@ -31,6 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include =20 #include #include @@ -81,6 +82,28 @@ AllocateAcpiNvsMemoryBelow4G ( return Buffer; } =20 +/** + Allocate memory and clean it with zero. + + @param[in] Size Size of memory to allocate. + + @return Allocated address for output. + +**/ +VOID * +AllocateZeroPages ( + IN UINTN Size + ) +{ + VOID *Buffer; + + Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (Size)); + if (Buffer !=3D NULL) { + ZeroMem (Buffer, Size); + } + + return Buffer; +} /** Callback function executed when the EndOfDxe event group is signaled. =20 @@ -171,10 +194,7 @@ CpuS3DataInitialize ( // OldAcpiCpuData =3D (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddre= ss); =20 - // - // Allocate ACPI NVS memory below 4G memory for use on ACPI S3 resume. - // - AcpiCpuDataEx =3D AllocateAcpiNvsMemoryBelow4G (sizeof (ACPI_CPU_DATA_EX= )); + AcpiCpuDataEx =3D AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX)); ASSERT (AcpiCpuDataEx !=3D NULL); AcpiCpuData =3D &AcpiCpuDataEx->AcpiCpuData; =20 @@ -223,11 +243,11 @@ CpuS3DataInitialize ( AsmReadIdtr (&AcpiCpuDataEx->IdtrProfile); =20 // - // Allocate GDT and IDT in ACPI NVS and copy current GDT and IDT contents + // Allocate GDT and IDT and copy current GDT and IDT contents // GdtSize =3D AcpiCpuDataEx->GdtrProfile.Limit + 1; IdtSize =3D AcpiCpuDataEx->IdtrProfile.Limit + 1; - Gdt =3D AllocateAcpiNvsMemoryBelow4G (GdtSize + IdtSize); + Gdt =3D AllocateZeroPages (GdtSize + IdtSize); ASSERT (Gdt !=3D NULL); Idt =3D (VOID *)((UINTN)Gdt + GdtSize); CopyMem (Gdt, (VOID *)AcpiCpuDataEx->GdtrProfile.Base, GdtSize); @@ -243,7 +263,7 @@ CpuS3DataInitialize ( // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable= for all CPUs // TableSize =3D 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE); - RegisterTable =3D (CPU_REGISTER_TABLE *)AllocateAcpiNvsMemoryBelow4G (= TableSize); + RegisterTable =3D (CPU_REGISTER_TABLE *)AllocateZeroPages (TableSize); ASSERT (RegisterTable !=3D NULL); =20 for (Index =3D 0; Index < NumberOfCpus; Index++) { diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf b/UefiCpuPkg/CpuS3Dat= aDxe/CpuS3DataDxe.inf index 480c98ebcd..c16731529c 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf @@ -51,6 +51,7 @@ DebugLib BaseLib MtrrLib + MemoryAllocationLib =20 [Guids] gEfiEndOfDxeEventGroupGuid ## CONSUMES ## Event --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 00:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1534299292511305.419968307188; Tue, 14 Aug 2018 19:14:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5E70C210F16CE; Tue, 14 Aug 2018 19:14:44 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BF55D210F16A0 for ; Tue, 14 Aug 2018 19:14:43 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2018 19:14:42 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 14 Aug 2018 19:14:42 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,241,1531810800"; d="scan'208";a="81837430" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 15 Aug 2018 10:14:34 +0800 Message-Id: <20180815021435.13748-5-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180815021435.13748-1-eric.dong@intel.com> References: <20180815021435.13748-1-eric.dong@intel.com> Subject: [edk2] [Patch v4 4/5] UefiCpuPkg/CpuS3DataDxe: Remove below 4G limitation. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Laszlo Ersek MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Because PrepareApStartupVector() stores StackAddress to "mExchangeInfo->StackStart" (which has type (VOID*)), and because "UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm" reads the latter with: add edi, StackStartAddressLocation add rax, qword [edi] mov rsp, rax mov qword [edi], rax in long-mode code. So code can remove below 4G limitation. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek Reviewed-by: Ruiyu Ni Tested-by: Laszlo Ersek --- UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/= CpuS3Data.c index 3e8c8b383c..ef98239844 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c @@ -47,9 +47,7 @@ typedef struct { } ACPI_CPU_DATA_EX; =20 /** - Allocate EfiACPIMemoryNVS below 4G memory address. - - This function allocates EfiACPIMemoryNVS below 4G memory address. + Allocate EfiACPIMemoryNVS memory. =20 @param[in] Size Size of memory to allocate. =20 @@ -57,7 +55,7 @@ typedef struct { =20 **/ VOID * -AllocateAcpiNvsMemoryBelow4G ( +AllocateAcpiNvsMemory ( IN UINTN Size ) { @@ -65,9 +63,8 @@ AllocateAcpiNvsMemoryBelow4G ( EFI_STATUS Status; VOID *Buffer; =20 - Address =3D BASE_4GB - 1; Status =3D gBS->AllocatePages ( - AllocateMaxAddress, + AllocateAnyPages, EfiACPIMemoryNVS, EFI_SIZE_TO_PAGES (Size), &Address @@ -230,9 +227,13 @@ CpuS3DataInitialize ( AcpiCpuData->MtrrTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataE= x->MtrrTable; =20 // - // Allocate stack space for all CPUs + // Allocate stack space for all CPUs. + // Use ACPI NVS memory type because this data will be directly used by A= Ps + // in S3 resume phase in long mode. Also during S3 resume, the stack buf= fer + // will only be used as scratch space. i.e. we won't read anything from = it + // before we write to it, in PiSmmCpuDxeSmm. // - Stack =3D AllocateAcpiNvsMemoryBelow4G (NumberOfCpus * AcpiCpuData->Stac= kSize); + Stack =3D AllocateAcpiNvsMemory (NumberOfCpus * AcpiCpuData->StackSize); ASSERT (Stack !=3D NULL); AcpiCpuData->StackAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Stack; =20 --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 00:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1534299307804121.95354034944285; Tue, 14 Aug 2018 19:15:07 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 94866210F16AD; Tue, 14 Aug 2018 19:15:06 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CE610210ED792 for ; Tue, 14 Aug 2018 19:15:05 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2018 19:15:04 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 14 Aug 2018 19:14:43 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,241,1531810800"; d="scan'208";a="81837435" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 15 Aug 2018 10:14:35 +0800 Message-Id: <20180815021435.13748-6-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180815021435.13748-1-eric.dong@intel.com> References: <20180815021435.13748-1-eric.dong@intel.com> MIME-Version: 1.0 Subject: [edk2] [Patch v4 5/5] UefiCpuPkg/RegisterCpuFeaturesLib: Combine implementation. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Ruiyu Ni Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 V1 changes: > Current code logic can't confirm CpuS3DataDxe driver start before > CpuFeaturesDxe driver. So the assumption in CpuFeaturesDxe not valid. > Add implementation for AllocateAcpiCpuData function to remove this > assumption. V2 changes: > Because CpuS3Data memory will be copy to smram at SmmReadToLock point, > so the memory type no need to be ACPI NVS type, also the address not > limit to below 4G. > This change remove the limit of ACPI NVS memory type and below 4G. V3 changes: > Remove function definition in header file. > Add STATIC in function implementation. Pass OS boot and resume from S3 test. Bugz: https://bugzilla.tianocore.org/show_bug.cgi?id=3D959 Reported-by: Marvin H=C3=A4user Suggested-by: Fan Jeff Cc: Marvin H=C3=A4user Cc: Fan Jeff Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek Reviewed-by: Ruiyu Ni Tested-by: Laszlo Ersek --- .../DxeRegisterCpuFeaturesLib.c | 67 ----------- .../PeiRegisterCpuFeaturesLib.c | 131 -----------------= ---- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 20 ---- .../RegisterCpuFeaturesLib.c | 92 +++++++++++++++ 4 files changed, 92 insertions(+), 218 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeatur= esLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesL= ib.c index 902a339529..1f34a3f489 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c @@ -197,70 +197,3 @@ GetNumberOfProcessor ( ASSERT_EFI_ERROR (Status); } =20 -/** - Allocates ACPI NVS memory to save ACPI_CPU_DATA. - - @return Pointer to allocated ACPI_CPU_DATA. -**/ -ACPI_CPU_DATA * -AllocateAcpiCpuData ( - VOID - ) -{ - // - // CpuS3DataDxe will do it. - // - ASSERT (FALSE); - return NULL; -} - -/** - Enlarges CPU register table for each processor. - - @param[in, out] RegisterTable Pointer processor's CPU register table -**/ -VOID -EnlargeRegisterTable ( - IN OUT CPU_REGISTER_TABLE *RegisterTable - ) -{ - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Address; - UINTN AllocatePages; - - Address =3D BASE_4GB - 1; - AllocatePages =3D RegisterTable->AllocatedSize / EFI_PAGE_SIZE; - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiACPIMemoryNVS, - AllocatePages + 1, - &Address - ); - ASSERT_EFI_ERROR (Status); - - // - // If there are records existing in the register table, then copy its co= ntents - // to new region and free the old one. - // - if (RegisterTable->AllocatedSize > 0) { - CopyMem ( - (VOID *) (UINTN) Address, - (VOID *) (UINTN) RegisterTable->RegisterTableEntry, - RegisterTable->AllocatedSize - ); - // - // RegisterTableEntry is allocated by gBS->AllocatePages() service. - // So, gBS->FreePages() service is used to free it. - // - gBS->FreePages ( - RegisterTable->RegisterTableEntry, - AllocatePages - ); - } - - // - // Adjust the allocated size and register table base address. - // - RegisterTable->AllocatedSize +=3D EFI_PAGE_SIZE; - RegisterTable->RegisterTableEntry =3D Address; -} diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeatur= esLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesL= ib.c index 6804eddf65..82fe268812 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c @@ -257,134 +257,3 @@ GetNumberOfProcessor ( ); ASSERT_EFI_ERROR (Status); } - -/** - Allocates ACPI NVS memory to save ACPI_CPU_DATA. - - @return Pointer to allocated ACPI_CPU_DATA. -**/ -ACPI_CPU_DATA * -AllocateAcpiCpuData ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_MP_SERVICES_PPI *CpuMpPpi; - UINTN NumberOfCpus; - UINTN NumberOfEnabledProcessors; - ACPI_CPU_DATA *AcpiCpuData; - EFI_PHYSICAL_ADDRESS Address; - UINTN TableSize; - CPU_REGISTER_TABLE *RegisterTable; - UINTN Index; - EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; - - Status =3D PeiServicesAllocatePages ( - EfiACPIMemoryNVS, - EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA)), - &Address - ); - ASSERT_EFI_ERROR (Status); - AcpiCpuData =3D (ACPI_CPU_DATA *) (UINTN) Address; - ASSERT (AcpiCpuData !=3D NULL); - - // - // Get MP Services Protocol - // - Status =3D PeiServicesLocatePpi ( - &gEfiPeiMpServicesPpiGuid, - 0, - NULL, - (VOID **)&CpuMpPpi - ); - ASSERT_EFI_ERROR (Status); - - // - // Get the number of CPUs - // - Status =3D CpuMpPpi->GetNumberOfProcessors ( - GetPeiServicesTablePointer (), - CpuMpPpi, - &NumberOfCpus, - &NumberOfEnabledProcessors - ); - ASSERT_EFI_ERROR (Status); - AcpiCpuData->NumberOfCpus =3D (UINT32)NumberOfCpus; - - // - // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable f= or all CPUs - // - TableSize =3D 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE); - Status =3D PeiServicesAllocatePages ( - EfiACPIMemoryNVS, - EFI_SIZE_TO_PAGES (TableSize), - &Address - ); - ASSERT_EFI_ERROR (Status); - RegisterTable =3D (CPU_REGISTER_TABLE *) (UINTN) Address; - - for (Index =3D 0; Index < NumberOfCpus; Index++) { - Status =3D CpuMpPpi->GetProcessorInfo ( - GetPeiServicesTablePointer (), - CpuMpPpi, - Index, - &ProcessorInfoBuffer - ); - ASSERT_EFI_ERROR (Status); - - RegisterTable[Index].InitialApicId =3D (UINT32)ProcessorInfoBuffe= r.ProcessorId; - RegisterTable[Index].TableLength =3D 0; - RegisterTable[Index].AllocatedSize =3D 0; - RegisterTable[Index].RegisterTableEntry =3D 0; - - RegisterTable[NumberOfCpus + Index].InitialApicId =3D (UINT32)Pro= cessorInfoBuffer.ProcessorId; - RegisterTable[NumberOfCpus + Index].TableLength =3D 0; - RegisterTable[NumberOfCpus + Index].AllocatedSize =3D 0; - RegisterTable[NumberOfCpus + Index].RegisterTableEntry =3D 0; - } - AcpiCpuData->RegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Re= gisterTable; - AcpiCpuData->PreSmmInitRegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(R= egisterTable + NumberOfCpus); - - return AcpiCpuData; -} - -/** - Enlarges CPU register table for each processor. - - @param[in, out] RegisterTable Pointer processor's CPU register table -**/ -VOID -EnlargeRegisterTable ( - IN OUT CPU_REGISTER_TABLE *RegisterTable - ) -{ - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS Address; - UINTN AllocatePages; - - AllocatePages =3D RegisterTable->AllocatedSize / EFI_PAGE_SIZE; - Status =3D PeiServicesAllocatePages ( - EfiACPIMemoryNVS, - AllocatePages + 1, - &Address - ); - ASSERT_EFI_ERROR (Status); - - // - // If there are records existing in the register table, then copy its co= ntents - // to new region and free the old one. - // - if (RegisterTable->AllocatedSize > 0) { - CopyMem ( - (VOID *) (UINTN) Address, - (VOID *) (UINTN) RegisterTable->RegisterTableEntry, - RegisterTable->AllocatedSize - ); - } - - // - // Adjust the allocated size and register table base address. - // - RegisterTable->AllocatedSize +=3D EFI_PAGE_SIZE; - RegisterTable->RegisterTableEntry =3D Address; -} diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.= h b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h index 69b412172a..edd266934f 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h @@ -87,26 +87,6 @@ GetCpuFeaturesData ( VOID ); =20 -/** - Enlarges CPU register table for each processor. - - @param[in, out] RegisterTable Pointer processor's CPU register table -**/ -VOID -EnlargeRegisterTable ( - IN OUT CPU_REGISTER_TABLE *RegisterTable - ); - -/** - Allocates ACPI NVS memory to save ACPI_CPU_DATA. - - @return Pointer to allocated ACPI_CPU_DATA. -**/ -ACPI_CPU_DATA * -AllocateAcpiCpuData ( - VOID - ); - /** Worker function to return processor index. =20 diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL= ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index dd6a82be7a..4143ee4bb1 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -488,6 +488,98 @@ RegisterCpuFeature ( return RETURN_SUCCESS; } =20 +/** + Allocates boot service data to save ACPI_CPU_DATA. + + @return Pointer to allocated ACPI_CPU_DATA. +**/ +STATIC +ACPI_CPU_DATA * +AllocateAcpiCpuData ( + VOID + ) +{ + EFI_STATUS Status; + UINTN NumberOfCpus; + UINTN NumberOfEnabledProcessors; + ACPI_CPU_DATA *AcpiCpuData; + UINTN TableSize; + CPU_REGISTER_TABLE *RegisterTable; + UINTN Index; + EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; + + AcpiCpuData =3D AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA= ))); + ASSERT (AcpiCpuData !=3D NULL); + + GetNumberOfProcessor (&NumberOfCpus, &NumberOfEnabledProcessors); + AcpiCpuData->NumberOfCpus =3D (UINT32)NumberOfCpus; + + // + // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable f= or all CPUs + // =20 + TableSize =3D 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE); + RegisterTable =3D AllocatePages (EFI_SIZE_TO_PAGES (TableSize)); + ASSERT (RegisterTable !=3D NULL); + + for (Index =3D 0; Index < NumberOfCpus; Index++) { + Status =3D GetProcessorInformation (Index, &ProcessorInfoBuffer); + ASSERT_EFI_ERROR (Status); + + RegisterTable[Index].InitialApicId =3D (UINT32)ProcessorInfoBuffe= r.ProcessorId; + RegisterTable[Index].TableLength =3D 0; + RegisterTable[Index].AllocatedSize =3D 0; + RegisterTable[Index].RegisterTableEntry =3D 0; + + RegisterTable[NumberOfCpus + Index].InitialApicId =3D (UINT32)Pro= cessorInfoBuffer.ProcessorId; + RegisterTable[NumberOfCpus + Index].TableLength =3D 0; + RegisterTable[NumberOfCpus + Index].AllocatedSize =3D 0; + RegisterTable[NumberOfCpus + Index].RegisterTableEntry =3D 0; + } + AcpiCpuData->RegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Re= gisterTable; + AcpiCpuData->PreSmmInitRegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(R= egisterTable + NumberOfCpus); + + return AcpiCpuData; +} + +/** + Enlarges CPU register table for each processor. + + @param[in, out] RegisterTable Pointer processor's CPU register table +**/ +STATIC +VOID +EnlargeRegisterTable ( + IN OUT CPU_REGISTER_TABLE *RegisterTable + ) +{ + EFI_PHYSICAL_ADDRESS Address; + UINTN UsedPages; + + UsedPages =3D RegisterTable->AllocatedSize / EFI_PAGE_SIZE; + Address =3D (UINTN)AllocatePages (UsedPages + 1); + ASSERT (Address !=3D 0); + + // + // If there are records existing in the register table, then copy its co= ntents + // to new region and free the old one. + // + if (RegisterTable->AllocatedSize > 0) { + CopyMem ( + (VOID *) (UINTN) Address, + (VOID *) (UINTN) RegisterTable->RegisterTableEntry, + RegisterTable->AllocatedSize + ); + + FreePages ((VOID *)(UINTN)RegisterTable->RegisterTableEntry, UsedPages= ); + } + + // + // Adjust the allocated size and register table base address. + // + RegisterTable->AllocatedSize +=3D EFI_PAGE_SIZE; + RegisterTable->RegisterTableEntry =3D Address; +} + /** Add an entry in specified register table. =20 --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel