From nobody Tue Apr 30 09:12:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531392572841348.25351241733233; Thu, 12 Jul 2018 03:49:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 587D82097FA88; Thu, 12 Jul 2018 03:49:31 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9688820972151 for ; Thu, 12 Jul 2018 03:49:30 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jul 2018 03:49:29 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.24]) by orsmga001.jf.intel.com with ESMTP; 12 Jul 2018 03:49:29 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,342,1526367600"; d="scan'208";a="72147226" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 18:49:25 +0800 Message-Id: <20180712104927.12220-2-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180712104927.12220-1-eric.dong@intel.com> References: <20180712104927.12220-1-eric.dong@intel.com> Subject: [edk2] [Patch v2 1/3] UefiCpuPkg/MpInitLib: Relocate uCode to memory to save time. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Laszlo Ersek MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Read uCode from memory has better performance than from flash. But it needs extra effort to let BSP copy uCode from flash to memory. Also BSP already enable cache in SEC phase, so it use less time to relocate uCode from flash to memory. After verification, if system has more than one processor, it will reduce some time if load uCode from memory. This change enable this optimization. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 34 ++++++++++++++++++++++++++++++++= +- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 108eea0a6f..c3cd6d7d51 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1520,6 +1520,7 @@ MpInitLibInitialize ( UINTN ApResetVectorSize; UINTN BackupBufferAddr; UINTN ApIdtBase; + VOID *MicrocodePatchInRam; =20 OldCpuMpData =3D GetCpuMpDataFromGuidedHob (); if (OldCpuMpData =3D=3D NULL) { @@ -1587,8 +1588,39 @@ MpInitLibInitialize ( CpuMpData->SwitchBspFlag =3D FALSE; CpuMpData->CpuData =3D (CPU_AP_DATA *) (CpuMpData + 1); CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); - CpuMpData->MicrocodePatchAddress =3D PcdGet64 (PcdCpuMicrocodePatchAd= dress); CpuMpData->MicrocodePatchRegionSize =3D PcdGet64 (PcdCpuMicrocodePatchRe= gionSize); + // + // If platform has more than one CPU, relocate microcode to memory to re= duce + // loading microcode time. + // + MicrocodePatchInRam =3D NULL; + if (MaxLogicalProcessorNumber > 1) { + MicrocodePatchInRam =3D AllocatePages ( + EFI_SIZE_TO_PAGES ( + (UINTN)CpuMpData->MicrocodePatchRegionSize + ) + ); + ASSERT (MicrocodePatchInRam !=3D NULL); + } + if (MicrocodePatchInRam =3D=3D NULL) { + // + // there is only one processor, or no microcode patch is available, or + // memory allocation failed + // + CpuMpData->MicrocodePatchAddress =3D PcdGet64 (PcdCpuMicrocodePatchAdd= ress); + } else { + // + // there are multiple processors, and a microcode patch is available, = and + // memory allocation succeeded + // + CopyMem ( + MicrocodePatchInRam, + (VOID *)(UINTN)PcdGet64 (PcdCpuMicrocodePatchAddress), + (UINTN)CpuMpData->MicrocodePatchRegionSize + ); + CpuMpData->MicrocodePatchAddress =3D (UINTN)MicrocodePatchInRam; + } + InitializeSpinLock(&CpuMpData->MpLock); =20 // --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 09:12:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531392575632686.9729472406626; Thu, 12 Jul 2018 03:49:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 87B952097FA8B; Thu, 12 Jul 2018 03:49:32 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A6ABF2097E25B for ; Thu, 12 Jul 2018 03:49:31 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jul 2018 03:49:30 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.24]) by orsmga001.jf.intel.com with ESMTP; 12 Jul 2018 03:49:30 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,342,1526367600"; d="scan'208";a="72147234" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 18:49:26 +0800 Message-Id: <20180712104927.12220-3-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180712104927.12220-1-eric.dong@intel.com> References: <20180712104927.12220-1-eric.dong@intel.com> Subject: [edk2] [Patch v2 2/3] UefiCpuPkg/MpInitLib: Use BSP uCode for APs if possible. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Laszlo Ersek MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Search uCode costs much time, if AP has same processor type with BSP, AP can use BSP saved uCode info to get better performance. This change enables this solution. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Acked-by: Laszlo Ersek --- UefiCpuPkg/Library/MpInitLib/Microcode.c | 34 ++++++++++++++++++++++++++++= +--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 4 ++-- UefiCpuPkg/Library/MpInitLib/MpLib.h | 11 +++++++++-- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index e47f9f4f8f..351975e2a2 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -35,11 +35,13 @@ GetCurrentMicrocodeSignature ( /** Detect whether specified processor can find matching microcode patch and= load it. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] IsBspCallIn Indicate whether the caller is BSP or not. **/ VOID MicrocodeDetect ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData, + IN BOOLEAN IsBspCallIn ) { UINT32 ExtendedTableLength; @@ -58,6 +60,7 @@ MicrocodeDetect ( BOOLEAN CorrectMicrocode; VOID *MicrocodeData; MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; + UINT32 ProcessorFlags; =20 if (CpuMpData->MicrocodePatchRegionSize =3D=3D 0) { // @@ -67,7 +70,7 @@ MicrocodeDetect ( } =20 CurrentRevision =3D GetCurrentMicrocodeSignature (); - if (CurrentRevision !=3D 0) { + if (CurrentRevision !=3D 0 && !IsBspCallIn) { // // Skip loading microcode if it has been loaded successfully // @@ -87,6 +90,19 @@ MicrocodeDetect ( PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); PlatformId =3D (UINT8) PlatformIdMsr.Bits.PlatformId; =20 + // + // Check whether AP has same processor with BSP. + // If yes, direct use microcode info saved by BSP. + // + if (!IsBspCallIn) { + if ((CpuMpData->ProcessorSignature =3D=3D Eax.Uint32) && + (CpuMpData->ProcessorFlags & (1 << PlatformId)) !=3D 0) { + MicrocodeData =3D (VOID *)(UINTN) CpuMpData->MicrocodeDataAddress; + LatestRevision =3D CpuMpData->MicrocodeRevision; + goto Done; + } + } + LatestRevision =3D 0; MicrocodeData =3D NULL; MicrocodeEnd =3D (UINTN) (CpuMpData->MicrocodePatchAddress + CpuMpData->= MicrocodePatchRegionSize); @@ -117,6 +133,7 @@ MicrocodeDetect ( } if (CheckSum32 =3D=3D 0) { CorrectMicrocode =3D TRUE; + ProcessorFlags =3D MicrocodeEntryPoint->ProcessorFlags; } } else if ((MicrocodeEntryPoint->DataSize !=3D 0) && (MicrocodeEntryPoint->UpdateRevision > LatestRevision)) { @@ -151,6 +168,7 @@ MicrocodeDetect ( // Find one // CorrectMicrocode =3D TRUE; + ProcessorFlags =3D ExtendedTable->ProcessorFlag; break; } } @@ -188,6 +206,7 @@ MicrocodeDetect ( MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEn= tryPoint) + TotalSize); } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); =20 +Done: if (LatestRevision > CurrentRevision) { // // BIOS only authenticate updates that contain a numerically larger re= vision @@ -211,4 +230,13 @@ MicrocodeDetect ( ReleaseSpinLock(&CpuMpData->MpLock); } } + + if (IsBspCallIn && (LatestRevision !=3D 0)) { + CpuMpData->ProcessorSignature =3D Eax.Uint32; + CpuMpData->ProcessorFlags =3D ProcessorFlags; + CpuMpData->MicrocodeDataAddress =3D (UINTN) MicrocodeData; + CpuMpData->MicrocodeRevision =3D LatestRevision; + DEBUG ((DEBUG_INFO, "BSP Microcode:: signature [0x%08x], ProcessorFlag= s [0x%08x], \ + MicroData [0x%08x], Revision [0x%08x]\n", Eax.Uint32, ProcessorFlag= s, (UINTN) MicrocodeData, LatestRevision)); + } } diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index c3cd6d7d51..3a7bdfa00b 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -410,7 +410,7 @@ ApInitializeSync ( // // Load microcode on AP // - MicrocodeDetect (CpuMpData); + MicrocodeDetect (CpuMpData, FALSE); // // Sync BSP's MTRR table to AP // @@ -1659,7 +1659,7 @@ MpInitLibInitialize ( // // Load Microcode on BSP // - MicrocodeDetect (CpuMpData); + MicrocodeDetect (CpuMpData, TRUE); // // Store BSP's MTRR setting // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 9aedb52636..6958080ac1 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -245,6 +245,11 @@ struct _CPU_MP_DATA { BOOLEAN TimerInterruptState; UINT64 MicrocodePatchAddress; UINT64 MicrocodePatchRegionSize; + + UINT32 ProcessorSignature; + UINT32 ProcessorFlags; + UINT64 MicrocodeDataAddress; + UINT32 MicrocodeRevision; }; =20 extern EFI_GUID mCpuInitMpLibHobGuid; @@ -546,11 +551,13 @@ CheckAndUpdateApsStatus ( /** Detect whether specified processor can find matching microcode patch and= load it. =20 - @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] IsBspCallIn Indicate whether the caller is BSP or not. **/ VOID MicrocodeDetect ( - IN CPU_MP_DATA *CpuMpData + IN CPU_MP_DATA *CpuMpData, + IN BOOLEAN IsBspCallIn ); =20 /** --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 09:12:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531392578331233.04862881879035; Thu, 12 Jul 2018 03:49:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B83822097FA8F; Thu, 12 Jul 2018 03:49:33 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B5C412097E25B for ; Thu, 12 Jul 2018 03:49:32 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jul 2018 03:49:31 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.24]) by orsmga001.jf.intel.com with ESMTP; 12 Jul 2018 03:49:31 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,342,1526367600"; d="scan'208";a="72147241" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 18:49:27 +0800 Message-Id: <20180712104927.12220-4-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180712104927.12220-1-eric.dong@intel.com> References: <20180712104927.12220-1-eric.dong@intel.com> Subject: [edk2] [Patch v2 3/3] UefiCpuPkg/MpInitLib: Load uCode once for each core. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Laszlo Ersek MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The SDM requires only one thread per core to load the microcode. This change enables this solution. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Acked-by: Laszlo Ersek --- UefiCpuPkg/Library/MpInitLib/Microcode.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 351975e2a2..122c23469d 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -61,6 +61,7 @@ MicrocodeDetect ( VOID *MicrocodeData; MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; UINT32 ProcessorFlags; + UINT32 ThreadId; =20 if (CpuMpData->MicrocodePatchRegionSize =3D=3D 0) { // @@ -77,6 +78,14 @@ MicrocodeDetect ( return; } =20 + GetProcessorLocationByApicId (GetInitialApicId (), NULL, NULL, &ThreadId= ); + if (ThreadId !=3D 0) { + // + // Skip loading microcode if it is not the first thread in one core. + // + return; + } + ExtendedTableLength =3D 0; // // Here data of CPUID leafs have not been collected into context buffer,= so --=20 2.15.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel