From nobody Thu Apr 18 00:21:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1530690690395997.0655508279825; Wed, 4 Jul 2018 00:51:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AA0D6210C125E; Wed, 4 Jul 2018 00:51:29 -0700 (PDT) Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 20D8A210C0F74 for ; Wed, 4 Jul 2018 00:51:29 -0700 (PDT) Received: by mail-pf0-x242.google.com with SMTP id v9-v6so2269985pff.9 for ; Wed, 04 Jul 2018 00:51:29 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2GIue/aybt5tZzjD+BhxHrMBA1bf79ztpczv1tK7EQA=; b=hZB1uZWY2RxkUlvkXmkFz/wuD77L/jx2Tzsw1wKnwn76suQGu7SYfrsJxurs4K1AVg 6fPf61V8CHYfxGhPe7/aKzQSvEeSdYJsm5NDlw77rpcHHh/zG9ncn6AIgqp3SdoRPqQ5 gWG3CzItt41MUmvN1emJgBYKdsALhmRPmmKUI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2GIue/aybt5tZzjD+BhxHrMBA1bf79ztpczv1tK7EQA=; b=SZvQGnoWMBsKal3h7RdVYnWUbbMsDWF+ROyaLgAX/OforeEU3Rp9LZQSAGbDBIKo4Q wNUrKC6+dGMYufP8x8d07MUi3HkYKnHIZ34Ts4QQPhtC7fg2rmrDasfJ3sL0E7TEKDxE 1FuA6tGqBQqD7u/g5Iwpwh30ukn0qfU/n/iiZSci/0YHt/melBEhzrJhJRSSJEo34UyW g2gfjGwb3tIx0Sio83t0NfFisRkCI2h2LwoOUwd8UHPeCIEkwefwsR9ys+H21f9Ay44H s6ivGBturrSIEYa+P4T7CUzxgZyRMa/XC5hmDMyoNx4UMQsBUWxp7xWG8vZv9MTanmaK 2FbQ== X-Gm-Message-State: APt69E1rKhFAgpbKt7PiAefzmwOv2SPoHfTIYMOYIIO0znYegMKWuq8g 1uVM6zf9LbrKXX62m0s5nMCG1g== X-Google-Smtp-Source: AAOMgpcKB7uMR+JDFNyevBRZOs+cp7xSV5R8Ppd0wVF3cFoiV19IrailgvgOPH0pLjfvebcDbS5k7g== X-Received: by 2002:a65:4b0f:: with SMTP id r15-v6mr928232pgq.103.1530690688881; Wed, 04 Jul 2018 00:51:28 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:12 +0800 Message-Id: <20180704075117.7427-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The edk2 commit bacfd6e let CpuDxe running latter. CpuDxe is needed by gDS->SetMemorySpaceAttributes, and gDS->SetMemorySpaceAttributes is invoked by some drivers. This issue can solve by adding Depex on gEfiCpuArchProtocolGuid to RealTimeClockLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.fdf = | 4 ++++ Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockL= ib.inf | 2 ++ 2 files changed, 6 insertions(+) diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 1383aa1091..73e2b7e958 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -146,6 +146,10 @@ READ_STATUS =3D TRUE READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE =20 + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + INF MdeModulePkg/Core/Dxe/DxeMain.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf =20 diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231Re= alTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/= DS3231RealTimeClockLib.inf index 319c35c724..ae7116dc31 100644 --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeC= lockLib.inf +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeC= lockLib.inf @@ -46,3 +46,5 @@ =20 [Pcd] =20 +[Depex] + gEfiCpuArchProtocolGuid --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 18 00:21:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 04 Jul 2018 00:51:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=aDN19AlqtSnaYjhijcH06XJ3M4U8eCUzLKvXX2B7yt+FLpHjEHqxud324YXKmx5mka BssYTY3Ak87vWJILkJyGaojsKMmzcZFwyc678N/BgHQQnD+x5sJVBWFqtyDigK/xouep nfQz9XDn/B1HLkc4CJD3X0WY9KOHzMNYrF8/w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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charset="utf-8" From: Jason Zhang 1. During test PCIe mcs9922 UART card, the card can't work because the IO ATU config is overlap by Cfg0/Cfg1 ATU address. 2. After adjust the ATU windows, Cfg0/Cfg1 config as below: Cfg0 is equal to "ECAM + (BusBase, 0, 0)" Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Heyi Guo Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++--= --- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 55b80aa4e4..e5f66eaa4a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -640,11 +640,12 @@ void SetAtuConfig0RW ( { UINTN RbPciBase =3D Private->RbPciBar; UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= + 1, 1, 0, 0) - 1; + UINT64 Cfg0Base =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= , 0, 0, 0); =20 =20 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= ((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= Cfg0Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= (Cfg0Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= ) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); @@ -666,12 +667,12 @@ void SetAtuConfig1RW ( { UINTN RbPciBase =3D Private->RbPciBar; UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusLimi= t + 1, 0, 0, 0) - 1; - + UINT64 Cfg1Base =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= + 2, 0, 0, 0); =20 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= ((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= Cfg1Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= (Cfg1Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= ) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 18 00:21:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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Wed, 04 Jul 2018 00:51:35 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:14 +0800 Message-Id: <20180704075117.7427-4-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The MemLimit is wrong when the Private->BusLimit equal 0xFF. This patch fix enumerating device plug in switch cart failed issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index e5f66eaa4a..3f894e8eec 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -666,7 +666,7 @@ void SetAtuConfig1RW ( ) { UINTN RbPciBase =3D Private->RbPciBar; - UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusLimi= t + 1, 0, 0, 0) - 1; + UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusLimi= t, 0x1F, 0x07, 0xFFF); UINT64 Cfg1Base =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= + 2, 0, 0, 0); =20 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 18 00:21:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 04 Jul 2018 00:51:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::243; helo=mail-pg0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0sRNz9lxXBn4Ds0xXco2Q9Ksha2Xik1Bw4rce6YWnMg=; b=X11TnKQupmt+xF+kSvdDuRJHgcmE4JK54b7sy6Wy0fsTFQt/oVq1hoW95QxTsqKXS8 7v7xDV0AOzGUi+M/Ch9V69yFUwEBMKLTtMbm/QFIS+oOY89Dc3ZnudDypoRY0RuHrv9i 2mbWgW1LpYjlh6HG+SSy1LaOha2n7ikGPWqGg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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charset="utf-8" Fix the issue of onboard Nic not work kerenl with AMD GPU and NVME SSD in board. The GPU don't support 64 MSI, so need to allocate INTx, but the default interrupt number 255 is invalid, so Change all the PCI Device interrupt number to 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++= ++++++++++++++++++ Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++= ++++++++ 4 files changed, 148 insertions(+) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d98a..0e6d5912a0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -629,6 +629,7 @@ =20 =20 Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassD= xe.inf + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf =20 # # Memory test diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 4503776d63..61e8d907f9 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -354,6 +354,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf =20 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf =20 diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe= .c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c new file mode 100644 index 0000000000..8519b7139d --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +VOID +SetIntLine ( + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 INTLine; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Fun; + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); + gBS->FreePool ((VOID *)HandleBuffer); + return; + } + + for (HandleIndex =3D 0; HandleIndex < HandleCount; HandleIndex++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[HandleIndex], + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + continue; + } + + INTLine =3D 0; + (VOID)PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_INT_LINE_OFFSET, + 1, + &INTLine); + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device,= Fun)); + } + + gBS->FreePool ((VOID *)HandleBuffer); + return; +} + +EFI_STATUS +EFIAPI +PlatformMiscDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SetIntLine, + NULL, + &gEfiEventReadyToBootGuid, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe= .inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf new file mode 100644 index 0000000000..0b365e7a53 --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformMiscDxe + FILE_GUID =3D a48f7a09-253f-468b-87c6-caf78baf47bb + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformMiscDxeEntry + +[Sources.common] + PlatformMiscDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[Guids] + gEfiEventReadyToBootGuid + +[Protocols] + gEfiPciIoProtocolGuid + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + +[Depex] + TRUE --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 18 00:21:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 04 Jul 2018 00:51:41 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A+M5+sAEB/cNqK92kBnSQlZCLUxo1R5kCvkAL13vgDY=; b=LCwwortIoepSJqK/uqM+34GgCphx4m+M67t6YHYaslMhvmEllwS5W2LdniuzO79kux vTLQh2a+VTUGgY8MSAQhYkBZiH/915Rv5mIIbpFDaiD9CvUMFC8yeo4poEX89ys/1ujz THHv03HWdRqNpu7xOFAdiZtuWaE3EKvIPNu3s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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charset="utf-8" Optimize pcie space for promoting usage rate.Change regions order of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion can satisfy the requirement of larger address alignment. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 12 ++++--= -- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 ++++++= ++++---------- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0e6d5912a0..ab7c5caf86 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -305,13 +305,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 @@ -336,10 +336,10 @@ =20 gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 @@ -353,10 +353,10 @@ =20 gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c= b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1053..ed6c4ac321 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_= HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLi= mit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MA= X_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLi= mit (PCI_HB0RB5_IO_BASE), //IoBase diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/H= isilicon/Hi1616/D05AcpiTables/D05Iort.asl index 50ccac1b06..9955f6dbeb 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -412,9 +412,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 =20 -[0004] Input base : 00008000 +[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 +[0004] Output Base : 0000f800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -469,9 +469,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 =20 -[0004] Input base : 00000000 +[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 +[0004] Output Base : 00007800 [0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/= Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index b47cfec7bd..64807b1714 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE M= cfg=3D { 0xa0000000, //Base Address 0x2, //Segment Group = Number - 0x80, //Start Bus Numb= er - 0x87, //End Bus Number + 0xF8, //Start Bus Numb= er + 0xFF, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe0 @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE M= cfg=3D { 0x8b0000000, //Base Address 0x5, //Segment Group = Number - 0x0, //Start Bus Numb= er - 0x7, //End Bus Number + 0x78, //Start Bus Num= ber + 0x7F, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe2 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 122e4f072c..3f09e5e568 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -89,15 +89,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number + Name(_BBN, 0xF8) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x87, // AddressMaximum - Maximum Bus Number + 0xF8, // AddressMinimum - Minimum Bus Number + 0xFF, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -109,8 +109,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xa8800000, // Min Base Address - 0xaffeffff, // Max Base Address + 0xa8000000, // Min Base Address + 0xaf7effff, // Max Base Address 0x0, // Translate 0x77f0000 // Length ) @@ -123,7 +123,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0xafff0000, // Translate + 0xaf7f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -165,7 +165,7 @@ Scope(_SB) { Name (_HID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [b= us 80-87] + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [b= us f8-ff] }) Method (_STA, 0x0, NotSerialized) { @@ -280,15 +280,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x0) // Base Bus Number + Name(_BBN, 0x78) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x7, // AddressMaximum - Maximum Bus Number + 0x78, // AddressMinimum - Minimum Bus Number + 0x7f, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -300,8 +300,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xb0800000, // Min Base Address - 0xb7feffff, // Max Base Address + 0xb0000000, // Min Base Address + 0xb77effff, // Max Base Address 0x800000000, // Translate 0x77f0000 // Length ) @@ -314,7 +314,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0x8b7ff0000, // Translate + 0x8b77f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -593,7 +593,7 @@ Scope(_SB) 0x0, // Translate 0x800000 // Length ) - QwordMemory ( //ECAM space for [bus 0-7] + QwordMemory ( //ECAM space for [bus 78-7f] ResourceConsumer, PosDecode, MinFixed, @@ -601,8 +601,8 @@ Scope(_SB) NonCacheable, ReadWrite, 0x0, // Granularity - 0x8b0000000, // Min Base Address - 0x8b07fffff, // Max Base Address + 0x8b7800000, // Min Base Address + 0x8b7ffffff, // Max Base Address 0x0, // Translate 0x800000 // Length ) --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 18 00:21:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1530690708160991.9349428384716; Wed, 4 Jul 2018 00:51:48 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ABECF210D93B7; Wed, 4 Jul 2018 00:51:45 -0700 (PDT) Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07403210C0F74 for ; Wed, 4 Jul 2018 00:51:45 -0700 (PDT) Received: by mail-pf0-x244.google.com with SMTP id j17-v6so2272699pfn.5 for ; Wed, 04 Jul 2018 00:51:45 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xWLk29EGw3s9NQWq/MONaz7B4FkrWLi4cB3eyEnsuv8=; b=JydfNG8Bcr4r/y5A6JYof5J6x1tq2r76ct85iyR3xMf4oiQy17QTtE3e8XZQGNJAOC cUU0NMaWZjftc0uRQkcS1LbpaDIMM4t7Yv6x7zhew8C14i6vA0Oeg1ALIni7xMhzmZ1q qJpRPNy9PLE/i/wCb+0vwwWGIUhDWyg2Xc748= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xWLk29EGw3s9NQWq/MONaz7B4FkrWLi4cB3eyEnsuv8=; b=jjZbCuKTHgwyhtjWY7Rmne9YsD9Hy5Od1QOzSPacRkTFUNqT6ojQ4uV3Q6gzwSA3Rp jw2JtTUYT7Q0SM2Z36YKutR8Wk99bVu2TRqfsCRpOR0c5orGCiHMhSAhKL8MM5n91Jdn ecdIc6038DaAV8lda7JUxYEB9jsbSqoXhLP9QwXGEUgEbBU2i5NPjiGJt+RIBXZBuf+B 1iVixjkgwC77A6NiK0zkDS8Lm9f8dL9zWiwQkg23NtOA9f1fGsZnHQywqA6ByUaynNG3 n+3s8bwcdwXLYhFVo6NDGTcr2wVNAwPo7PmoyBHZ1KAKlIl2IbVr5RDJrIP+q0mJDxlW FNAQ== X-Gm-Message-State: APt69E0huHeo3iLtbTgTtD7ID0hZQmjAroD8H23M6GtGi9ca7AYRGc/Q 7BFc95Fa82aTWfuTACGbKFFFow== X-Google-Smtp-Source: AAOMgpfyXV3OaB46e4kmcxNvbqYP0Z7avlr6yOKYDQvEAMj2DGbR0pvnKKNvXvRbIsrb1VH8BjB59Q== X-Received: by 2002:a63:2d45:: with SMTP id t66-v6mr889120pgt.381.1530690704788; Wed, 04 Jul 2018 00:51:44 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:17 +0800 Message-Id: <20180704075117.7427-7-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 6/6] Hisilicon/D0x: Correct smbios product name X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The product name getting from BMC is not suitable. It may cause ambiguity. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufactur= erFunction.c | 1 - 1 file changed, 1 deletion(-) diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSyst= emManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/T= ype01/MiscSystemManufacturerFunction.c index fcefe2442c..5e965c996c 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManuf= acturerFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManuf= acturerFunction.c @@ -86,7 +86,6 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) TokenToUpdate =3D STRING_TOKEN (STR_MISC_SYSTEM_VERSION); HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL); } - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAM= E), ProductNameType01); UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMB= ER), SerialNumType01); UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURE= R), SystemManufacturerType01); =20 --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel