From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527106890078476.4735550158757; Wed, 23 May 2018 13:21:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 18C2F207E4E10; Wed, 23 May 2018 13:21:27 -0700 (PDT) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 58C842063D755 for ; Wed, 23 May 2018 13:21:26 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 96F2F406E897; Wed, 23 May 2018 20:21:25 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-208.rdu2.redhat.com [10.10.120.208]) by smtp.corp.redhat.com (Postfix) with ESMTP id 96CA263F35; Wed, 23 May 2018 20:21:24 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:15 +0200 Message-Id: <20180523202121.8125-2-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:25 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:25 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 1/7] OvmfPkg: introduce PciCapLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a library class, and a BASE lib instance, to work more easily with PCI capabilities in PCI config space. Functions are provided to parse capabilities lists, and to locate, describe, read and write capabilities. PCI config space access is abstracted away. Cc: Ard Biesheuvel Cc: Jordan Justen Suggested-by: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - move library from MdePkg to OvmfPkg, for initial introduction OvmfPkg/OvmfPkg.dec | 4 + OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf | 38 + OvmfPkg/Include/Library/PciCapLib.h | 429 +++++++++ OvmfPkg/Library/BasePciCapLib/BasePciCapLib.h | 60 ++ OvmfPkg/Library/BasePciCapLib/BasePciCapLib.c | 1007 ++++++++++++++++++++ 5 files changed, 1538 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index c01a2ca7219a..74818a2e2a19 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -31,6 +31,10 @@ [LibraryClasses] # NvVarsFileLib|Include/Library/NvVarsFileLib.h =20 + ## @libraryclass Provides services to work with PCI capabilities in PCI + # config space. + PciCapLib|Include/Library/PciCapLib.h + ## @libraryclass Access QEMU's firmware configuration interface # QemuFwCfgLib|Include/Library/QemuFwCfgLib.h diff --git a/OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf b/OvmfPkg/Libr= ary/BasePciCapLib/BasePciCapLib.inf new file mode 100644 index 000000000000..9a7428a589c2 --- /dev/null +++ b/OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf @@ -0,0 +1,38 @@ +## @file +# Work with PCI capabilities in PCI config space. +# +# Provides functions to parse capabilities lists, and to locate, describe,= read +# and write capabilities. PCI config space access is abstracted away. +# +# Copyright (C) 2018, Red Hat, Inc. +# +# This program and the accompanying materials are licensed and made availa= ble +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +## + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D BasePciCapLib + FILE_GUID =3D 6957540D-F7B5-4D5B-BEE4-FC14114DCD3C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciCapLib + +[Sources] + BasePciCapLib.h + BasePciCapLib.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + MemoryAllocationLib + OrderedCollectionLib diff --git a/OvmfPkg/Include/Library/PciCapLib.h b/OvmfPkg/Include/Library/= PciCapLib.h new file mode 100644 index 000000000000..22a1ad624bd3 --- /dev/null +++ b/OvmfPkg/Include/Library/PciCapLib.h @@ -0,0 +1,429 @@ +/** @file + Library class to work with PCI capabilities in PCI config space. + + Provides functions to parse capabilities lists, and to locate, describe,= read + and write capabilities. PCI config space access is abstracted away. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __PCI_CAP_LIB_H__ +#define __PCI_CAP_LIB_H__ + +#include + +// +// Base structure for representing a PCI device -- down to the PCI function +// level -- for the purposes of this library class. This is a forward +// declaration that is completed below. Concrete implementations are suppo= sed +// to inherit and extend this type. +// +typedef struct PCI_CAP_DEV PCI_CAP_DEV; + +/** + Read the config space of a given PCI device (both normal and extended). + + PCI_CAP_DEV_READ_CONFIG performs as few config space accesses as possible + (without attempting 64-bit wide accesses). + + PCI_CAP_DEV_READ_CONFIG returns an unspecified error if accessing Size b= ytes + from SourceOffset exceeds the config space limit of the PCI device. Fewer + than Size bytes may have been read in this case. + + @param[in] PciDevice Implementation-specific unique representa= tion + of the PCI device in the PCI hierarchy. + + @param[in] SourceOffset Source offset in the config space of the = PCI + device to start reading from. + + @param[out] DestinationBuffer Buffer to store the read data to. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from config spa= ce to + DestinationBuffer. + + @return Unspecified error codes. Fewer than Size bytes m= ay + have been read. +**/ +typedef +RETURN_STATUS +(EFIAPI *PCI_CAP_DEV_READ_CONFIG) ( + IN PCI_CAP_DEV *PciDevice, + IN UINT16 SourceOffset, + OUT VOID *DestinationBuffer, + IN UINT16 Size + ); + +/** + Write the config space of a given PCI device (both normal and extended). + + PCI_CAP_DEV_WRITE_CONFIG performs as few config space accesses as possib= le + (without attempting 64-bit wide accesses). + + PCI_CAP_DEV_WRITE_CONFIG returns an unspecified error if accessing Size = bytes + at DestinationOffset exceeds the config space limit of the PCI device. F= ewer + than Size bytes may have been written in this case. + + @param[in] PciDevice Implementation-specific unique representat= ion + of the PCI device in the PCI hierarchy. + + @param[in] DestinationOffset Destination offset in the config space of = the + PCI device to start writing at. + + @param[in] SourceBuffer Buffer to read the data to be stored from. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from SourceBuff= er to + config space. + + @return Unspecified error codes. Fewer than Size bytes m= ay + have been written. +**/ +typedef +RETURN_STATUS +(EFIAPI *PCI_CAP_DEV_WRITE_CONFIG) ( + IN PCI_CAP_DEV *PciDevice, + IN UINT16 DestinationOffset, + IN VOID *SourceBuffer, + IN UINT16 Size + ); + +// +// Complete the PCI_CAP_DEV type here. The base abstraction only requires +// config space accessors. +// +struct PCI_CAP_DEV { + PCI_CAP_DEV_READ_CONFIG ReadConfig; + PCI_CAP_DEV_WRITE_CONFIG WriteConfig; +}; + +// +// Opaque data structure representing parsed PCI Capabilities Lists. +// +typedef struct PCI_CAP_LIST PCI_CAP_LIST; + +// +// Opaque data structure representing a PCI Capability in a parsed Capabil= ity +// List. +// +typedef struct PCI_CAP PCI_CAP; + +// +// Distinguishes whether a Capability ID is 8-bit wide and interpreted in +// normal config space, or 16-bit wide and interpreted in extended config +// space. Capability ID definitions are relative to domain. +// +typedef enum { + PciCapNormal, + PciCapExtended +} PCI_CAP_DOMAIN; + +// +// Public data structure that PciCapGetInfo() fills in about a PCI_CAP obj= ect. +// +typedef struct { + PCI_CAP_DOMAIN Domain; + UINT16 CapId; + // + // The capability identified by Domain and CapId may have multiple insta= nces + // in config space. NumInstances provides the total count of occurrences= of + // the capability. It is always positive. + // + UINT16 NumInstances; + // + // Instance is the serial number, in capabilities list traversal order (= not + // necessarily config space offset order), of the one capability instance + // that PciCapGetInfo() is reporting about. Instance is always smaller t= han + // NumInstances. + // + UINT16 Instance; + // + // The offset in config space at which the capability header of the + // capability instance starts. + // + UINT16 Offset; + // + // The deduced maximum size of the capability instance, including the + // capability header. This hint is an upper bound, calculated -- without + // regard to the internal structure of the capability -- from (a) the ne= xt + // lowest offset in configuration space that is known to be used by anot= her + // capability, and (b) from the end of the config space identified by Do= main, + // whichever is lower. + // + UINT16 MaxSizeHint; + // + // The version number of the capability instance. Always zero when Domai= n is + // PciCapNormal. + // + UINT8 Version; +} PCI_CAP_INFO; + + +/** + Parse the capabilities lists (both normal and extended, as applicable) o= f a + PCI device. + + If the PCI device has no capabilities, that per se will not fail + PciCapListInit(); an empty capabilities list will be represented. + + If the PCI device is found to be PCI Express, then an attempt will be ma= de to + parse the extended capabilities list as well. If the first extended conf= ig + space access -- via PciDevice->ReadConfig() with SourceOffset=3D0x100 and + Size=3D4 -- fails, that per se will not fail PciCapListInit(); the devic= e will + be assumed to have no extended capabilities. + + @param[in] PciDevice Implementation-specific unique representation of t= he + PCI device in the PCI hierarchy. + + @param[out] CapList Opaque data structure that holds an in-memory + representation of the parsed capabilities lists of + PciDevice. + + @retval RETURN_SUCCESS The capabilities lists have been parsed= from + config space. + + @retval RETURN_OUT_OF_RESOURCES Memory allocation failed. + + @retval RETURN_DEVICE_ERROR A loop or some other kind of invalid po= inter + was detected in the capabilities lists = of + PciDevice. + + @return Error codes propagated from + PciDevice->ReadConfig(). +**/ +RETURN_STATUS +EFIAPI +PciCapListInit ( + IN PCI_CAP_DEV *PciDevice, + OUT PCI_CAP_LIST **CapList + ); + + +/** + Free the resources used by CapList. + + @param[in] CapList The PCI_CAP_LIST object to free, originally produced= by + PciCapListInit(). +**/ +VOID +EFIAPI +PciCapListUninit ( + IN PCI_CAP_LIST *CapList + ); + + +/** + Locate a capability instance in the parsed capabilities lists. + + @param[in] CapList The PCI_CAP_LIST object produced by PciCapListInit(= ). + + @param[in] Domain Distinguishes whether CapId is 8-bit wide and + interpreted in normal config space, or 16-bit wide = and + interpreted in extended config space. Capability ID + definitions are relative to domain. + + @param[in] CapId Capability identifier to look up. + + @param[in] Instance Domain and CapId may identify a multi-instance + capability. When Instance is zero, the first instan= ce of + the capability is located (in list traversal order = -- + which may not mean increasing config space offset + order). Higher Instance values locate subsequent + instances of the same capability (in list traversal + order). + + @param[out] Cap The capability instance that matches the search + criteria. Cap is owned by CapList and becomes inval= id + when CapList is freed with PciCapListUninit(). + PciCapListFindCap() may be called with Cap set to N= ULL, + in order to test the existence of a specific capabi= lity + instance. + + @retval RETURN_SUCCESS The capability instance identified by (Domain, + CapId, Instance) has been found. + + @retval RETURN_NOT_FOUND The requested (Domain, CapId, Instance) capabi= lity + instance does not exist. +**/ +RETURN_STATUS +EFIAPI +PciCapListFindCap ( + IN PCI_CAP_LIST *CapList, + IN PCI_CAP_DOMAIN Domain, + IN UINT16 CapId, + IN UINT16 Instance, + OUT PCI_CAP **Cap OPTIONAL + ); + + +/** + Locate the first instance of the capability given by (Domain, CapId) such + that the instance's Version is greater than or equal to MinVersion. + + This is a convenience function that may save client code calls to + PciCapListFindCap() and PciCapGetInfo(). + + @param[in] CapList The PCI_CAP_LIST object produced by PciCapListIni= t(). + + @param[in] Domain Distinguishes whether CapId is 8-bit wide and + interpreted in normal config space, or 16-bit wid= e and + interpreted in extended config space. Capability = ID + definitions are relative to domain. + + @param[in] CapId Capability identifier to look up. + + @param[in] MinVersion The minimum version that the capability instance = is + required to have. Note that all capability instan= ces + in Domain=3DPciCapNormal have Version=3D0. + + @param[out] Cap The first capability instance that matches the se= arch + criteria. Cap is owned by CapList and becomes inv= alid + when CapList is freed with PciCapListUninit(). + PciCapListFindCapVersion() may be called with Cap= set + to NULL, in order just to test whether the search + criteria are satisfiable. + + @retval RETURN_SUCCESS The first capability instance matching (Domain, + CapId, MinVersion) has been located. + + @retval RETURN_NOT_FOUND No capability instance matches (Domain, CapId, + MinVersion). +**/ +RETURN_STATUS +EFIAPI +PciCapListFindCapVersion ( + IN PCI_CAP_LIST *CapList, + IN PCI_CAP_DOMAIN Domain, + IN UINT16 CapId, + IN UINT8 MinVersion, + OUT PCI_CAP **Cap OPTIONAL + ); + + +/** + Get information about a PCI Capability instance. + + @param[in] Cap The capability instance to get info about, located with + PciCapListFindCap*(). + + @param[out] Info A PCI_CAP_INFO structure that describes the properties= of + Cap. + + @retval RETURN_SUCCESS Fields of Info have been set. + + @return Unspecified error codes, if filling in Info fail= ed + for some reason. +**/ +RETURN_STATUS +EFIAPI +PciCapGetInfo ( + IN PCI_CAP *Cap, + OUT PCI_CAP_INFO *Info + ); + + +/** + Read a slice of a capability instance. + + The function performs as few config space accesses as possible (without + attempting 64-bit wide accesses). PciCapRead() performs bounds checking = on + SourceOffsetInCap and Size, and only invokes PciDevice->ReadConfig() if = the + requested transfer falls within Cap. + + @param[in] PciDevice Implementation-specific unique representa= tion + of the PCI device in the PCI hierarchy. + + @param[in] Cap The capability instance to read, located = with + PciCapListFindCap*(). + + @param[in] SourceOffsetInCap Source offset relative to the capability + header to start reading from. A zero value + refers to the first byte of the capability + header. + + @param[out] DestinationBuffer Buffer to store the read data to. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from Ca= p to + DestinationBuffer. + + @retval RETURN_BAD_BUFFER_SIZE Reading Size bytes starting from + SourceOffsetInCap would not (entirely) be + contained within Cap, as suggested by + PCI_CAP_INFO.MaxSizeHint. No bytes have = been + read. + + @return Error codes propagated from + PciDevice->ReadConfig(). Fewer than Size + bytes may have been read. +**/ +RETURN_STATUS +EFIAPI +PciCapRead ( + IN PCI_CAP_DEV *PciDevice, + IN PCI_CAP *Cap, + IN UINT16 SourceOffsetInCap, + OUT VOID *DestinationBuffer, + IN UINT16 Size + ); + + +/** + Write a slice of a capability instance. + + The function performs as few config space accesses as possible (without + attempting 64-bit wide accesses). PciCapWrite() performs bounds checking= on + DestinationOffsetInCap and Size, and only invokes PciDevice->WriteConfig= () if + the requested transfer falls within Cap. + + @param[in] PciDevice Implementation-specific unique + representation of the PCI device in t= he + PCI hierarchy. + + @param[in] Cap The capability instance to write, loc= ated + with PciCapListFindCap*(). + + @param[in] DestinationOffsetInCap Destination offset relative to the + capability header to start writing at= . A + zero value refers to the first byte o= f the + capability header. + + @param[in] SourceBuffer Buffer to read the data to be stored = from. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from + SourceBuffer to Cap. + + @retval RETURN_BAD_BUFFER_SIZE Writing Size bytes starting at + DestinationOffsetInCap would not (entire= ly) + be contained within Cap, as suggested by + PCI_CAP_INFO.MaxSizeHint. No bytes have = been + written. + + @return Error codes propagated from + PciDevice->WriteConfig(). Fewer than Size + bytes may have been written. +**/ +RETURN_STATUS +EFIAPI +PciCapWrite ( + IN PCI_CAP_DEV *PciDevice, + IN PCI_CAP *Cap, + IN UINT16 DestinationOffsetInCap, + IN VOID *SourceBuffer, + IN UINT16 Size + ); + +#endif // __PCI_CAP_LIB_H__ diff --git a/OvmfPkg/Library/BasePciCapLib/BasePciCapLib.h b/OvmfPkg/Librar= y/BasePciCapLib/BasePciCapLib.h new file mode 100644 index 000000000000..e631745834d9 --- /dev/null +++ b/OvmfPkg/Library/BasePciCapLib/BasePciCapLib.h @@ -0,0 +1,60 @@ +/** @file + Work with PCI capabilities in PCI config space -- internal type definiti= ons. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __BASE_PCI_CAP_LIB_H__ +#define __BASE_PCI_CAP_LIB_H__ + +#include + +#include + +// +// Structure that uniquely identifies a capability instance and serves as = key +// for insertion and lookup. +// +typedef struct { + PCI_CAP_DOMAIN Domain; + UINT16 CapId; + UINT16 Instance; +} PCI_CAP_KEY; + +// +// In Instance=3D=3D0 PCI_CAP objects, store NumInstances directly. In Ins= tance>0 +// PCI_CAP objects, link Instance#0 of the same (Domain, CapId). This way +// NumInstances needs maintenance in one object only, per (Domain, CapId) = pair. +// +typedef union { + UINT16 NumInstances; + PCI_CAP *InstanceZero; +} PCI_CAP_NUM_INSTANCES; + +// +// Complete the incomplete PCI_CAP structure here. +// +struct PCI_CAP { + PCI_CAP_KEY Key; + PCI_CAP_NUM_INSTANCES NumInstancesUnion; + UINT16 Offset; + UINT16 MaxSizeHint; + UINT8 Version; +}; + +// +// Complete the incomplete PCI_CAP_LIST structure here. +// +struct PCI_CAP_LIST { + ORDERED_COLLECTION *Capabilities; +}; + +#endif // __BASE_PCI_CAP_LIB_H__ diff --git a/OvmfPkg/Library/BasePciCapLib/BasePciCapLib.c b/OvmfPkg/Librar= y/BasePciCapLib/BasePciCapLib.c new file mode 100644 index 000000000000..6789359f0a54 --- /dev/null +++ b/OvmfPkg/Library/BasePciCapLib/BasePciCapLib.c @@ -0,0 +1,1007 @@ +/** @file + Work with PCI capabilities in PCI config space. + + Provides functions to parse capabilities lists, and to locate, describe,= read + and write capabilities. PCI config space access is abstracted away. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include + +#include +#include +#include + +#include "BasePciCapLib.h" + + +/** + Compare a standalone PCI_CAP_KEY against a PCI_CAP containing an embedded + PCI_CAP_KEY. + + @param[in] PciCapKey Pointer to the bare PCI_CAP_KEY. + + @param[in] PciCap Pointer to the PCI_CAP with the embedded PCI_CAP_K= EY. + + @retval <0 If PciCapKey compares less than PciCap->Key. + + @retval 0 If PciCapKey compares equal to PciCap->Key. + + @retval >0 If PciCapKey compares greater than PciCap->Key. +**/ +STATIC +INTN +EFIAPI +ComparePciCapKey ( + IN CONST VOID *PciCapKey, + IN CONST VOID *PciCap + ) +{ + CONST PCI_CAP_KEY *Key1; + CONST PCI_CAP_KEY *Key2; + + Key1 =3D PciCapKey; + Key2 =3D &((CONST PCI_CAP *)PciCap)->Key; + + if (Key1->Domain < Key2->Domain) { + return -1; + } + if (Key1->Domain > Key2->Domain) { + return 1; + } + if (Key1->CapId < Key2->CapId) { + return -1; + } + if (Key1->CapId > Key2->CapId) { + return 1; + } + if (Key1->Instance < Key2->Instance) { + return -1; + } + if (Key1->Instance > Key2->Instance) { + return 1; + } + return 0; +} + + +/** + Compare two PCI_CAP objects based on PCI_CAP.Key. + + @param[in] PciCap1 Pointer to the first PCI_CAP. + + @param[in] PciCap2 Pointer to the second PCI_CAP. + + @retval <0 If PciCap1 compares less than PciCap2. + + @retval 0 If PciCap1 compares equal to PciCap2. + + @retval >0 If PciCap1 compares greater than PciCap2. +**/ +STATIC +INTN +EFIAPI +ComparePciCap ( + IN CONST VOID *PciCap1, + IN CONST VOID *PciCap2 + ) +{ + CONST PCI_CAP_KEY *PciCap1Key; + + PciCap1Key =3D &((CONST PCI_CAP *)PciCap1)->Key; + return ComparePciCapKey (PciCap1Key, PciCap2); +} + + +/** + Compare the standalone UINT16 config space offset of a capability header + against a PCI_CAP containing an embedded Offset. + + @param[in] CapHdrOffset Pointer to the bare UINT16 config space offset. + + @param[in] PciCap Pointer to the PCI_CAP with the embedded Offset. + + @retval <0 If CapHdrOffset compares less than PciCap->Offset. + + @retval 0 If CapHdrOffset compares equal to PciCap->Offset. + + @retval >0 If CapHdrOffset compares greater than PciCap->Offset. +**/ +STATIC +INTN +EFIAPI +ComparePciCapOffsetKey ( + IN CONST VOID *CapHdrOffset, + IN CONST VOID *PciCap + ) +{ + UINT16 Offset1; + UINT16 Offset2; + + Offset1 =3D *(CONST UINT16 *)CapHdrOffset; + Offset2 =3D ((CONST PCI_CAP *)PciCap)->Offset; + // + // Note: both Offset1 and Offset2 are promoted to INT32 below, and the + // subtraction takes place between INT32 values. + // + return Offset1 - Offset2; +} + + +/** + Compare two PCI_CAP objects based on PCI_CAP.Offset. + + @param[in] PciCap1 Pointer to the first PCI_CAP. + + @param[in] PciCap2 Pointer to the second PCI_CAP. + + @retval <0 If PciCap1 compares less than PciCap2. + + @retval 0 If PciCap1 compares equal to PciCap2. + + @retval >0 If PciCap1 compares greater than PciCap2. +**/ +STATIC +INTN +EFIAPI +ComparePciCapOffset ( + IN CONST VOID *PciCap1, + IN CONST VOID *PciCap2 + ) +{ + UINT16 Offset1; + UINT16 Offset2; + + Offset1 =3D ((CONST PCI_CAP *)PciCap1)->Offset; + Offset2 =3D ((CONST PCI_CAP *)PciCap2)->Offset; + // + // Note: both Offset1 and Offset2 are promoted to INT32 below, and the + // subtraction takes place between INT32 values. + // + return Offset1 - Offset2; +} + + +/** + Insert a new instance of the PCI capability given by (Domain, CapId) in + CapList. + + @param[in,out] CapList The PCI_CAP_LIST into which the new PCI_CAP + should be inserted. CapList will own the n= ew + PCI_CAP structure. + + @param[in,out] CapHdrOffsets Link the new PCI_CAP structure into the + (non-owning) CapHdrOffsets collection as w= ell. + CapHdrOffsets orders the PCI_CAP structures + based on the PCI_CAP.Offset member, and en= ables + the calculation of PCI_CAP.MaxSizeHint. + + @param[in] Domain Whether the capability is normal or extend= ed. + + @param[in] CapId Capability ID (specific to Domain). + + @param[in] Offset Config space offset at which the standard + header of the capability starts. The calle= r is + responsible for ensuring that Offset be DW= ORD + aligned. The caller is also responsible for + ensuring that Offset be within the config = space + identified by Domain. + + @param[in] Version The version number of the capability. The + caller is responsible for passing 0 as Ver= sion + if Domain is PciCapNormal. + + @retval RETURN_SUCCESS Insertion successful. + + @retval RETURN_OUT_OF_RESOURCES Memory allocation failed. + + @retval RETURN_DEVICE_ERROR A PCI_CAP with Offset is already linked= by + CapHdrOffsets. This indicates a loop in= the + capabilities list being parsed. +**/ +STATIC +RETURN_STATUS +InsertPciCap ( + IN OUT PCI_CAP_LIST *CapList, + IN OUT ORDERED_COLLECTION *CapHdrOffsets, + IN PCI_CAP_DOMAIN Domain, + IN UINT16 CapId, + IN UINT16 Offset, + IN UINT8 Version + ) +{ + PCI_CAP *PciCap; + RETURN_STATUS Status; + ORDERED_COLLECTION_ENTRY *PciCapEntry; + PCI_CAP *InstanceZero; + + ASSERT ((Offset & 0x3) =3D=3D 0); + ASSERT (Offset < (Domain =3D=3D PciCapNormal ? + PCI_MAX_CONFIG_OFFSET : PCI_EXP_MAX_CONFIG_OFFSET)); + ASSERT (Domain =3D=3D PciCapExtended || Version =3D=3D 0); + + // + // Set InstanceZero to suppress incorrect compiler/analyzer warnings. + // + InstanceZero =3D NULL; + + // + // Allocate PciCap, and populate it assuming it is the first occurrence = of + // (Domain, CapId). Note that PciCap->MaxSizeHint is not assigned the fi= nal + // value just yet. + // + PciCap =3D AllocatePool (sizeof *PciCap); + if (PciCap =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + PciCap->Key.Domain =3D Domain; + PciCap->Key.CapId =3D CapId; + PciCap->Key.Instance =3D 0; + PciCap->NumInstancesUnion.NumInstances =3D 1; + PciCap->Offset =3D Offset; + PciCap->MaxSizeHint =3D 0; + PciCap->Version =3D Version; + + // + // Add PciCap to CapList. + // + Status =3D OrderedCollectionInsert (CapList->Capabilities, &PciCapEntry, + PciCap); + if (RETURN_ERROR (Status)) { + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + goto FreePciCap; + } + ASSERT (Status =3D=3D RETURN_ALREADY_STARTED); + // + // PciCap is not the first instance of (Domain, CapId). Add it as a new + // instance, taking the current instance count from Instance#0. Note t= hat + // we don't bump the instance count maintained in Instance#0 just yet,= to + // keep rollback on errors simple. + // + InstanceZero =3D OrderedCollectionUserStruct (PciCapEntry); + PciCap->Key.Instance =3D InstanceZero->NumInstancesUnion.NumInstances; + PciCap->NumInstancesUnion.InstanceZero =3D InstanceZero; + + ASSERT (PciCap->Key.Instance > 0); + Status =3D OrderedCollectionInsert (CapList->Capabilities, &PciCapEntr= y, + PciCap); + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + goto FreePciCap; + } + } + // + // At this point, PciCap has been inserted in CapList->Capabilities, eit= her + // with Instance=3D=3D0 or with Instance>0. PciCapEntry is the iterator = that + // links PciCap. + // + ASSERT_RETURN_ERROR (Status); + + // + // Link PciCap into CapHdrOffsets too, to order it globally based on con= fig + // space offset. Note that partial overlaps between capability headers i= s not + // possible: Offset is DWORD aligned, normal capability headers are 16-b= it + // wide, and extended capability headers are 32-bit wide. Therefore any = two + // capability headers either are distinct or start at the same offset + // (implying a loop in the respective capabilities list). + // + Status =3D OrderedCollectionInsert (CapHdrOffsets, NULL, PciCap); + if (RETURN_ERROR (Status)) { + if (Status =3D=3D RETURN_ALREADY_STARTED) { + // + // Loop found; map return status accordingly. + // + Status =3D RETURN_DEVICE_ERROR; + } + goto DeletePciCapFromCapList; + } + + // + // Now we can bump the instance count maintained in Instance#0, if PciCa= p is + // not the first instance of (Domain, CapId). + // + if (PciCap->Key.Instance > 0) { + InstanceZero->NumInstancesUnion.NumInstances++; + } + return RETURN_SUCCESS; + +DeletePciCapFromCapList: + OrderedCollectionDelete (CapList->Capabilities, PciCapEntry, NULL); + +FreePciCap: + FreePool (PciCap); + + return Status; +} + + +/** + Calculate the MaxSizeHint member for a PCI_CAP object. + + CalculatePciCapMaxSizeHint() may only be called once all capability inst= ances + have been successfully processed by InsertPciCap(). + + @param[in,out] PciCap The PCI_CAP object for which to calculate the + MaxSizeHint member. The caller is responsible for + passing a PCI_CAP object that has been created by= a + successful invocation of InsertPciCap(). + + @param[in] NextPciCap If NextPciCap is NULL, then the caller is respons= ible + for PciCap to represent the capability instance w= ith + the highest header offset in all config space. If + NextPciCap is not NULL, then the caller is respon= sible + for (a) having created NextPciCap with a successf= ul + invocation of InsertPciCap(), and (b) NextPciCap = being + the direct successor of PciCap in config space of= fset + order, as ordered by ComparePciCapOffset(). +**/ +STATIC +VOID +CalculatePciCapMaxSizeHint ( + IN OUT PCI_CAP *PciCap, + IN PCI_CAP *NextPciCap OPTIONAL + ) +{ + UINT16 ConfigSpaceSize; + + ConfigSpaceSize =3D (PciCap->Key.Domain =3D=3D PciCapNormal ? + PCI_MAX_CONFIG_OFFSET : PCI_EXP_MAX_CONFIG_OFFSET); + // + // The following is guaranteed by the interface contract on + // CalculatePciCapMaxSizeHint(). + // + ASSERT (NextPciCap =3D=3D NULL || PciCap->Offset < NextPciCap->Offset); + // + // The following is guaranteed by the interface contract on InsertPciCap= (). + // + ASSERT (PciCap->Offset < ConfigSpaceSize); + // + // Thus we can safely subtract PciCap->Offset from either of + // - ConfigSpaceSize + // - and NextPciCap->Offset (if NextPciCap is not NULL). + // + // PciCap extends from PciCap->Offset to NextPciCap->Offset (if any), ex= cept + // it cannot cross config space boundary. + // + if (NextPciCap =3D=3D NULL || NextPciCap->Offset >=3D ConfigSpaceSize) { + PciCap->MaxSizeHint =3D ConfigSpaceSize - PciCap->Offset; + return; + } + PciCap->MaxSizeHint =3D NextPciCap->Offset - PciCap->Offset; +} + + +/** + Debug dump a PCI_CAP_LIST object at the DEBUG_VERBOSE level. + + @param[in] CapList The PCI_CAP_LIST object to dump. +**/ +STATIC +VOID +EFIAPI +DebugDumpPciCapList ( + IN PCI_CAP_LIST *CapList + ) +{ + DEBUG_CODE_BEGIN (); + ORDERED_COLLECTION_ENTRY *PciCapEntry; + + for (PciCapEntry =3D OrderedCollectionMin (CapList->Capabilities); + PciCapEntry !=3D NULL; + PciCapEntry =3D OrderedCollectionNext (PciCapEntry)) { + PCI_CAP *PciCap; + RETURN_STATUS Status; + PCI_CAP_INFO Info; + + PciCap =3D OrderedCollectionUserStruct (PciCapEntry); + Status =3D PciCapGetInfo (PciCap, &Info); + // + // PciCapGetInfo() cannot fail in this library instance. + // + ASSERT_RETURN_ERROR (Status); + + DEBUG ((DEBUG_VERBOSE, + "%a:%a: %a 0x%04x %03u/%03u v0x%x @0x%03x+0x%03x\n", gEfiCallerBaseN= ame, + __FUNCTION__, (Info.Domain =3D=3D PciCapNormal ? "Norm" : "Extd"), + Info.CapId, Info.Instance, Info.NumInstances, Info.Version, Info.Off= set, + Info.MaxSizeHint)); + } + DEBUG_CODE_END (); +} + + +/** + Empty a collection of PCI_CAP structures, optionally releasing the refer= enced + PCI_CAP structures themselves. Release the collection at last. + + @param[in,out] PciCapCollection The collection to empty and release. + + @param[in] FreePciCap TRUE if the PCI_CAP structures linked by + PciCapCollection should be released. Wh= en + FALSE, the caller is responsible for + retaining at least one reference to each + PCI_CAP structure originally linked by + PciCapCollection. +**/ +STATIC +VOID +EmptyAndUninitPciCapCollection ( + IN OUT ORDERED_COLLECTION *PciCapCollection, + IN BOOLEAN FreePciCap + ) +{ + ORDERED_COLLECTION_ENTRY *PciCapEntry; + ORDERED_COLLECTION_ENTRY *NextEntry; + + for (PciCapEntry =3D OrderedCollectionMin (PciCapCollection); + PciCapEntry !=3D NULL; + PciCapEntry =3D NextEntry) { + PCI_CAP *PciCap; + + NextEntry =3D OrderedCollectionNext (PciCapEntry); + OrderedCollectionDelete (PciCapCollection, PciCapEntry, (VOID **)&PciC= ap); + if (FreePciCap) { + FreePool (PciCap); + } + } + OrderedCollectionUninit (PciCapCollection); +} + + +/** + Parse the capabilities lists (both normal and extended, as applicable) o= f a + PCI device. + + If the PCI device has no capabilities, that per se will not fail + PciCapListInit(); an empty capabilities list will be represented. + + If the PCI device is found to be PCI Express, then an attempt will be ma= de to + parse the extended capabilities list as well. If the first extended conf= ig + space access -- via PciDevice->ReadConfig() with SourceOffset=3D0x100 and + Size=3D4 -- fails, that per se will not fail PciCapListInit(); the devic= e will + be assumed to have no extended capabilities. + + @param[in] PciDevice Implementation-specific unique representation of t= he + PCI device in the PCI hierarchy. + + @param[out] CapList Opaque data structure that holds an in-memory + representation of the parsed capabilities lists of + PciDevice. + + @retval RETURN_SUCCESS The capabilities lists have been parsed= from + config space. + + @retval RETURN_OUT_OF_RESOURCES Memory allocation failed. + + @retval RETURN_DEVICE_ERROR A loop or some other kind of invalid po= inter + was detected in the capabilities lists = of + PciDevice. + + @return Error codes propagated from + PciDevice->ReadConfig(). +**/ +RETURN_STATUS +EFIAPI +PciCapListInit ( + IN PCI_CAP_DEV *PciDevice, + OUT PCI_CAP_LIST **CapList + ) +{ + PCI_CAP_LIST *OutCapList; + RETURN_STATUS Status; + ORDERED_COLLECTION *CapHdrOffsets; + UINT16 PciStatusReg; + BOOLEAN DeviceIsExpress; + ORDERED_COLLECTION_ENTRY *OffsetEntry; + + // + // Allocate the output structure. + // + OutCapList =3D AllocatePool (sizeof *OutCapList); + if (OutCapList =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + // + // The OutCapList->Capabilities collection owns the PCI_CAP structures a= nd + // orders them based on PCI_CAP.Key. + // + OutCapList->Capabilities =3D OrderedCollectionInit (ComparePciCap, + ComparePciCapKey); + if (OutCapList->Capabilities =3D=3D NULL) { + Status =3D RETURN_OUT_OF_RESOURCES; + goto FreeOutCapList; + } + + // + // The (temporary) CapHdrOffsets collection only references PCI_CAP + // structures, and orders them based on PCI_CAP.Offset. + // + CapHdrOffsets =3D OrderedCollectionInit (ComparePciCapOffset, + ComparePciCapOffsetKey); + if (CapHdrOffsets =3D=3D NULL) { + Status =3D RETURN_OUT_OF_RESOURCES; + goto FreeCapabilities; + } + + // + // Whether the device is PCI Express depends on the normal capability wi= th + // identifier EFI_PCI_CAPABILITY_ID_PCIEXP. + // + DeviceIsExpress =3D FALSE; + + // + // Check whether a normal capabilities list is present. If there's none, + // that's not an error; we'll just return OutCapList->Capabilities empty. + // + Status =3D PciDevice->ReadConfig (PciDevice, PCI_PRIMARY_STATUS_OFFSET, + &PciStatusReg, sizeof PciStatusReg); + if (RETURN_ERROR (Status)) { + goto FreeCapHdrOffsets; + } + if ((PciStatusReg & EFI_PCI_STATUS_CAPABILITY) !=3D 0) { + UINT8 NormalCapHdrOffset; + + // + // Fetch the start offset of the normal capabilities list. + // + Status =3D PciDevice->ReadConfig (PciDevice, PCI_CAPBILITY_POINTER_OFF= SET, + &NormalCapHdrOffset, sizeof NormalCapHdrOffset); + if (RETURN_ERROR (Status)) { + goto FreeCapHdrOffsets; + } + + // + // Traverse the normal capabilities list. + // + NormalCapHdrOffset &=3D 0xFC; + while (NormalCapHdrOffset > 0) { + EFI_PCI_CAPABILITY_HDR NormalCapHdr; + + Status =3D PciDevice->ReadConfig (PciDevice, NormalCapHdrOffset, + &NormalCapHdr, sizeof NormalCapHdr); + if (RETURN_ERROR (Status)) { + goto FreeCapHdrOffsets; + } + + Status =3D InsertPciCap (OutCapList, CapHdrOffsets, PciCapNormal, + NormalCapHdr.CapabilityID, NormalCapHdrOffset, 0); + if (RETURN_ERROR (Status)) { + goto FreeCapHdrOffsets; + } + + if (NormalCapHdr.CapabilityID =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP) { + DeviceIsExpress =3D TRUE; + } + NormalCapHdrOffset =3D NormalCapHdr.NextItemPtr & 0xFC; + } + } + + // + // If the device has been found PCI Express, attempt to traverse the ext= ended + // capabilities list. It starts right after the normal config space. + // + if (DeviceIsExpress) { + UINT16 ExtendedCapHdrOffset; + + ExtendedCapHdrOffset =3D PCI_MAX_CONFIG_OFFSET; + while (ExtendedCapHdrOffset > 0) { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER ExtendedCapHdr; + + Status =3D PciDevice->ReadConfig (PciDevice, ExtendedCapHdrOffset, + &ExtendedCapHdr, sizeof ExtendedCapHdr); + // + // If the first extended config space access fails, assume the devic= e has + // no extended capabilities. If the first extended config space acce= ss + // succeeds but we read an "all bits zero" extended capability heade= r, + // that means (by spec) the device has no extended capabilities. + // + if (ExtendedCapHdrOffset =3D=3D PCI_MAX_CONFIG_OFFSET && + (RETURN_ERROR (Status) || + IsZeroBuffer (&ExtendedCapHdr, sizeof ExtendedCapHdr))) { + break; + } + if (RETURN_ERROR (Status)) { + goto FreeCapHdrOffsets; + } + + Status =3D InsertPciCap (OutCapList, CapHdrOffsets, PciCapExtended, + ExtendedCapHdr.CapabilityId, ExtendedCapHdrOffset, + ExtendedCapHdr.CapabilityVersion); + if (RETURN_ERROR (Status)) { + goto FreeCapHdrOffsets; + } + + ExtendedCapHdrOffset =3D ExtendedCapHdr.NextCapabilityOffset & 0xFFC; + if (ExtendedCapHdrOffset > 0 && + ExtendedCapHdrOffset < PCI_MAX_CONFIG_OFFSET) { + // + // Invalid capability pointer. + // + Status =3D RETURN_DEVICE_ERROR; + goto FreeCapHdrOffsets; + } + } + } + + // + // Both capabilities lists have been parsed; compute the PCI_CAP.MaxSize= Hint + // members if at least one capability has been found. In parallel, evacu= ate + // the CapHdrOffsets collection. + // + // At first, set OffsetEntry to the iterator of the PCI_CAP object with = the + // lowest Offset (if such exists). + // + OffsetEntry =3D OrderedCollectionMin (CapHdrOffsets); + if (OffsetEntry !=3D NULL) { + ORDERED_COLLECTION_ENTRY *NextOffsetEntry; + PCI_CAP *PciCap; + + // + // Initialize NextOffsetEntry to the iterator of the PCI_CAP object wi= th + // the second lowest Offset (if such exists). + // + NextOffsetEntry =3D OrderedCollectionNext (OffsetEntry); + // + // Calculate MaxSizeHint for all PCI_CAP objects except the one with t= he + // highest Offset. + // + while (NextOffsetEntry !=3D NULL) { + PCI_CAP *NextPciCap; + + OrderedCollectionDelete (CapHdrOffsets, OffsetEntry, (VOID **)&PciCa= p); + NextPciCap =3D OrderedCollectionUserStruct (NextOffsetEntry); + CalculatePciCapMaxSizeHint (PciCap, NextPciCap); + + OffsetEntry =3D NextOffsetEntry; + NextOffsetEntry =3D OrderedCollectionNext (OffsetEntry); + } + // + // Calculate MaxSizeHint for the PCI_CAP object with the highest Offse= t. + // + OrderedCollectionDelete (CapHdrOffsets, OffsetEntry, (VOID **)&PciCap); + CalculatePciCapMaxSizeHint (PciCap, NULL); + } + ASSERT (OrderedCollectionIsEmpty (CapHdrOffsets)); + OrderedCollectionUninit (CapHdrOffsets); + + DebugDumpPciCapList (OutCapList); + *CapList =3D OutCapList; + return RETURN_SUCCESS; + +FreeCapHdrOffsets: + EmptyAndUninitPciCapCollection (CapHdrOffsets, FALSE); + +FreeCapabilities: + EmptyAndUninitPciCapCollection (OutCapList->Capabilities, TRUE); + +FreeOutCapList: + FreePool (OutCapList); + + ASSERT (RETURN_ERROR (Status)); + DEBUG ((DEBUG_ERROR, "%a:%a: %r\n", gEfiCallerBaseName, __FUNCTION__, + Status)); + return Status; +} + + +/** + Free the resources used by CapList. + + @param[in] CapList The PCI_CAP_LIST object to free, originally produced= by + PciCapListInit(). +**/ +VOID +EFIAPI +PciCapListUninit ( + IN PCI_CAP_LIST *CapList + ) +{ + EmptyAndUninitPciCapCollection (CapList->Capabilities, TRUE); + FreePool (CapList); +} + + +/** + Locate a capability instance in the parsed capabilities lists. + + @param[in] CapList The PCI_CAP_LIST object produced by PciCapListInit(= ). + + @param[in] Domain Distinguishes whether CapId is 8-bit wide and + interpreted in normal config space, or 16-bit wide = and + interpreted in extended config space. Capability ID + definitions are relative to domain. + + @param[in] CapId Capability identifier to look up. + + @param[in] Instance Domain and CapId may identify a multi-instance + capability. When Instance is zero, the first instan= ce of + the capability is located (in list traversal order = -- + which may not mean increasing config space offset + order). Higher Instance values locate subsequent + instances of the same capability (in list traversal + order). + + @param[out] Cap The capability instance that matches the search + criteria. Cap is owned by CapList and becomes inval= id + when CapList is freed with PciCapListUninit(). + PciCapListFindCap() may be called with Cap set to N= ULL, + in order to test the existence of a specific capabi= lity + instance. + + @retval RETURN_SUCCESS The capability instance identified by (Domain, + CapId, Instance) has been found. + + @retval RETURN_NOT_FOUND The requested (Domain, CapId, Instance) capabi= lity + instance does not exist. +**/ +RETURN_STATUS +EFIAPI +PciCapListFindCap ( + IN PCI_CAP_LIST *CapList, + IN PCI_CAP_DOMAIN Domain, + IN UINT16 CapId, + IN UINT16 Instance, + OUT PCI_CAP **Cap OPTIONAL + ) +{ + PCI_CAP_KEY Key; + ORDERED_COLLECTION_ENTRY *PciCapEntry; + + Key.Domain =3D Domain; + Key.CapId =3D CapId; + Key.Instance =3D Instance; + + PciCapEntry =3D OrderedCollectionFind (CapList->Capabilities, &Key); + if (PciCapEntry =3D=3D NULL) { + return RETURN_NOT_FOUND; + } + if (Cap !=3D NULL) { + *Cap =3D OrderedCollectionUserStruct (PciCapEntry); + } + return RETURN_SUCCESS; +} + + +/** + Locate the first instance of the capability given by (Domain, CapId) such + that the instance's Version is greater than or equal to MinVersion. + + This is a convenience function that may save client code calls to + PciCapListFindCap() and PciCapGetInfo(). + + @param[in] CapList The PCI_CAP_LIST object produced by PciCapListIni= t(). + + @param[in] Domain Distinguishes whether CapId is 8-bit wide and + interpreted in normal config space, or 16-bit wid= e and + interpreted in extended config space. Capability = ID + definitions are relative to domain. + + @param[in] CapId Capability identifier to look up. + + @param[in] MinVersion The minimum version that the capability instance = is + required to have. Note that all capability instan= ces + in Domain=3DPciCapNormal have Version=3D0. + + @param[out] Cap The first capability instance that matches the se= arch + criteria. Cap is owned by CapList and becomes inv= alid + when CapList is freed with PciCapListUninit(). + PciCapListFindCapVersion() may be called with Cap= set + to NULL, in order just to test whether the search + criteria are satisfiable. + + @retval RETURN_SUCCESS The first capability instance matching (Domain, + CapId, MinVersion) has been located. + + @retval RETURN_NOT_FOUND No capability instance matches (Domain, CapId, + MinVersion). +**/ +RETURN_STATUS +EFIAPI +PciCapListFindCapVersion ( + IN PCI_CAP_LIST *CapList, + IN PCI_CAP_DOMAIN Domain, + IN UINT16 CapId, + IN UINT8 MinVersion, + OUT PCI_CAP **Cap OPTIONAL + ) +{ + PCI_CAP_KEY Key; + ORDERED_COLLECTION_ENTRY *PciCapEntry; + + // + // Start the version checks at Instance#0 of (Domain, CapId). + // + Key.Domain =3D Domain; + Key.CapId =3D CapId; + Key.Instance =3D 0; + + for (PciCapEntry =3D OrderedCollectionFind (CapList->Capabilities, &Key); + PciCapEntry !=3D NULL; + PciCapEntry =3D OrderedCollectionNext (PciCapEntry)) { + PCI_CAP *PciCap; + + PciCap =3D OrderedCollectionUserStruct (PciCapEntry); + // + // PCI_CAP.Key ordering keeps instances of the same (Domain, CapId) + // adjacent to each other, so stop searching if either Domain or CapId + // changes. + // + if (PciCap->Key.Domain !=3D Domain || PciCap->Key.CapId !=3D CapId) { + break; + } + if (PciCap->Version >=3D MinVersion) { + // + // Match found. + // + if (Cap !=3D NULL) { + *Cap =3D PciCap; + } + return RETURN_SUCCESS; + } + } + return RETURN_NOT_FOUND; +} + + +/** + Get information about a PCI Capability instance. + + @param[in] Cap The capability instance to get info about, located with + PciCapListFindCap*(). + + @param[out] Info A PCI_CAP_INFO structure that describes the properties= of + Cap. + + @retval RETURN_SUCCESS Fields of Info have been set. + + @return Unspecified error codes, if filling in Info fail= ed + for some reason. +**/ +RETURN_STATUS +EFIAPI +PciCapGetInfo ( + IN PCI_CAP *Cap, + OUT PCI_CAP_INFO *Info + ) +{ + PCI_CAP *InstanceZero; + + InstanceZero =3D (Cap->Key.Instance =3D=3D 0 ? Cap : + Cap->NumInstancesUnion.InstanceZero); + + Info->Domain =3D Cap->Key.Domain; + Info->CapId =3D Cap->Key.CapId; + Info->NumInstances =3D InstanceZero->NumInstancesUnion.NumInstances; + Info->Instance =3D Cap->Key.Instance; + Info->Offset =3D Cap->Offset; + Info->MaxSizeHint =3D Cap->MaxSizeHint; + Info->Version =3D Cap->Version; + + return RETURN_SUCCESS; +} + + +/** + Read a slice of a capability instance. + + The function performs as few config space accesses as possible (without + attempting 64-bit wide accesses). PciCapRead() performs bounds checking = on + SourceOffsetInCap and Size, and only invokes PciDevice->ReadConfig() if = the + requested transfer falls within Cap. + + @param[in] PciDevice Implementation-specific unique representa= tion + of the PCI device in the PCI hierarchy. + + @param[in] Cap The capability instance to read, located = with + PciCapListFindCap*(). + + @param[in] SourceOffsetInCap Source offset relative to the capability + header to start reading from. A zero value + refers to the first byte of the capability + header. + + @param[out] DestinationBuffer Buffer to store the read data to. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from Ca= p to + DestinationBuffer. + + @retval RETURN_BAD_BUFFER_SIZE Reading Size bytes starting from + SourceOffsetInCap would not (entirely) be + contained within Cap, as suggested by + PCI_CAP_INFO.MaxSizeHint. No bytes have = been + read. + + @return Error codes propagated from + PciDevice->ReadConfig(). Fewer than Size + bytes may have been read. +**/ +RETURN_STATUS +EFIAPI +PciCapRead ( + IN PCI_CAP_DEV *PciDevice, + IN PCI_CAP *Cap, + IN UINT16 SourceOffsetInCap, + OUT VOID *DestinationBuffer, + IN UINT16 Size + ) +{ + // + // Note: all UINT16 values are promoted to INT32 below, and addition and + // comparison take place between INT32 values. + // + if (SourceOffsetInCap + Size > Cap->MaxSizeHint) { + return RETURN_BAD_BUFFER_SIZE; + } + return PciDevice->ReadConfig (PciDevice, Cap->Offset + SourceOffsetInCap, + DestinationBuffer, Size); +} + + +/** + Write a slice of a capability instance. + + The function performs as few config space accesses as possible (without + attempting 64-bit wide accesses). PciCapWrite() performs bounds checking= on + DestinationOffsetInCap and Size, and only invokes PciDevice->WriteConfig= () if + the requested transfer falls within Cap. + + @param[in] PciDevice Implementation-specific unique + representation of the PCI device in t= he + PCI hierarchy. + + @param[in] Cap The capability instance to write, loc= ated + with PciCapListFindCap*(). + + @param[in] DestinationOffsetInCap Destination offset relative to the + capability header to start writing at= . A + zero value refers to the first byte o= f the + capability header. + + @param[in] SourceBuffer Buffer to read the data to be stored = from. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from + SourceBuffer to Cap. + + @retval RETURN_BAD_BUFFER_SIZE Writing Size bytes starting at + DestinationOffsetInCap would not (entire= ly) + be contained within Cap, as suggested by + PCI_CAP_INFO.MaxSizeHint. No bytes have = been + written. + + @return Error codes propagated from + PciDevice->WriteConfig(). Fewer than Size + bytes may have been written. +**/ +RETURN_STATUS +EFIAPI +PciCapWrite ( + IN PCI_CAP_DEV *PciDevice, + IN PCI_CAP *Cap, + IN UINT16 DestinationOffsetInCap, + IN VOID *SourceBuffer, + IN UINT16 Size + ) +{ + // + // Note: all UINT16 values are promoted to INT32 below, and addition and + // comparison take place between INT32 values. + // + if (DestinationOffsetInCap + Size > Cap->MaxSizeHint) { + return RETURN_BAD_BUFFER_SIZE; + } + return PciDevice->WriteConfig (PciDevice, + Cap->Offset + DestinationOffsetInCap, SourceBuffer, + Size); +} --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 152710689362057.41675154228528; Wed, 23 May 2018 13:21:33 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 479C6207E4E1A; Wed, 23 May 2018 13:21:29 -0700 (PDT) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4A15C21BADAB6 for ; Wed, 23 May 2018 13:21:28 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8FCA5406E974; Wed, 23 May 2018 20:21:27 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-208.rdu2.redhat.com [10.10.120.208]) by smtp.corp.redhat.com (Postfix) with ESMTP id D54F46B592; Wed, 23 May 2018 20:21:26 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:16 +0200 Message-Id: <20180523202121.8125-3-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:27 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:27 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 2/7] OvmfPkg: introduce PciCapPciSegmentLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a library class, and a BASE lib instance, that are layered on top of PciCapLib, and allow clients to plug a PciSegmentLib backend into PciCapLib, for config space access. (Side note: The "MaxDomain" parameter is provided because, in practice, platforms exist where a PCI Express device may show up on a root bridge such that the root bridge doesn't support access to extended config space. Earlier the same issue was handled for MdeModulePkg/PciHostBridgeDxe in commit 014b472053ae3. However, that solution does not apply to the PciSegmentLib class, because: (1) The config space accessor functions of the PciSegmentLib class, such as PciSegmentReadBuffer(), have no way of informing the caller whether access to extended config space actually succeeds. (For example, in the UefiPciSegmentLibPciRootBridgeIo instace, which could in theory benefit from commit 014b472053ae3, the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() status code is explicitly ignored, because there's no way for the lib instance to propagate it to the PciSegmentLib caller. If the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() call fails, then DxePciSegmentLibPciRootBridgeIoReadWorker() returns Data with indeterminate value.) (2) There is no *general* way for any firmware platform to provide, or use, a PciSegmentLib instance in which access to extended config space always succeeds. In brief, on a platform where config space may be limited to 256 bytes, access to extended config space through PciSegmentLib may invoke undefined behavior; therefore PciCapPciSegmentLib must give platforms a way to prevent such access.) Cc: Ard Biesheuvel Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - move library from MdePkg to OvmfPkg, for initial introduction OvmfPkg/OvmfPkg.dec | 5 + OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf | 35 = +++ OvmfPkg/Include/Library/PciCapPciSegmentLib.h | 82 = +++++++ OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.h | 47 = ++++ OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.c | 226 = ++++++++++++++++++++ 5 files changed, 395 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 74818a2e2a19..fbec1cfe4a8e 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -35,6 +35,11 @@ [LibraryClasses] # config space. PciCapLib|Include/Library/PciCapLib.h =20 + ## @libraryclass Layered on top of PciCapLib, allows clients to plug a + # PciSegmentLib backend into PciCapLib, for config space + # access. + PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h + ## @libraryclass Access QEMU's firmware configuration interface # QemuFwCfgLib|Include/Library/QemuFwCfgLib.h diff --git a/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLi= b.inf b/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf new file mode 100644 index 000000000000..e3cf5de49b15 --- /dev/null +++ b/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf @@ -0,0 +1,35 @@ +## @file +# Plug a PciSegmentLib backend into PciCapLib, for config space access. +# +# Copyright (C) 2018, Red Hat, Inc. +# +# This program and the accompanying materials are licensed and made availa= ble +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +## + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D BasePciCapPciSegmentLib + FILE_GUID =3D ED011855-AA31-43B9-ACC0-BF45A05C5985 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciCapPciSegmentLib + +[Sources] + BasePciCapPciSegmentLib.h + BasePciCapPciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + MemoryAllocationLib + PciSegmentLib diff --git a/OvmfPkg/Include/Library/PciCapPciSegmentLib.h b/OvmfPkg/Includ= e/Library/PciCapPciSegmentLib.h new file mode 100644 index 000000000000..6b6930288d16 --- /dev/null +++ b/OvmfPkg/Include/Library/PciCapPciSegmentLib.h @@ -0,0 +1,82 @@ +/** @file + Library class layered on top of PciCapLib that allows clients to plug a + PciSegmentLib backend into PciCapLib, for config space access. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __PCI_CAP_PCI_SEGMENT_LIB_H__ +#define __PCI_CAP_PCI_SEGMENT_LIB_H__ + +#include + + +/** + Create a PCI_CAP_DEV object from the PCI Segment:Bus:Device.Function + quadruplet. The config space accessors are based upon PciSegmentLib. + + @param[in] MaxDomain If MaxDomain is PciCapExtended, then + PciDevice->ReadConfig() and PciDevice->WriteConfi= g() + will delegate extended config space accesses too = to + PciSegmentReadBuffer() and PciSegmentWriteBuffer(= ), + respectively. Otherwise, PciDevice->ReadConfig() = and + PciDevice->WriteConfig() will reject accesses to + extended config space with RETURN_UNSUPPORTED, wi= thout + calling PciSegmentReadBuffer() or + PciSegmentWriteBuffer(). By setting MaxDomain to + PciCapNormal, the platform can prevent undefined + PciSegmentLib behavior when the PCI root bridge u= nder + the PCI device at Segment:Bus:Device.Function doe= sn't + support extended config space. + + @param[in] Segment 16-bit wide segment number. + + @param[in] Bus 8-bit wide bus number. + + @param[in] Device 5-bit wide device number. + + @param[in] Function 3-bit wide function number. + + @param[out] PciDevice The PCI_CAP_DEV object constructed as described a= bove. + PciDevice can be passed to the PciCapLib APIs. + + @retval RETURN_SUCCESS PciDevice has been constructed and out= put. + + @retval RETURN_INVALID_PARAMETER Device or Function does not fit in the + permitted number of bits. + + @retval RETURN_OUT_OF_RESOURCES Memory allocation failed. +**/ +RETURN_STATUS +EFIAPI +PciCapPciSegmentDeviceInit ( + IN PCI_CAP_DOMAIN MaxDomain, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + OUT PCI_CAP_DEV **PciDevice + ); + + +/** + Free the resources used by PciDevice. + + @param[in] PciDevice The PCI_CAP_DEV object to free, originally produce= d by + PciCapPciSegmentDeviceInit(). +**/ +VOID +EFIAPI +PciCapPciSegmentDeviceUninit ( + IN PCI_CAP_DEV *PciDevice + ); + +#endif // __PCI_CAP_PCI_SEGMENT_LIB_H__ diff --git a/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLi= b.h b/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.h new file mode 100644 index 000000000000..3ce15fe0fb57 --- /dev/null +++ b/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.h @@ -0,0 +1,47 @@ +/** @file + Plug a PciSegmentLib backend into PciCapLib, for config space access -- + internal macro and type definitions. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __BASE_PCI_CAP_PCI_SEGMENT_LIB_H__ +#define __BASE_PCI_CAP_PCI_SEGMENT_LIB_H__ + +#include + +#include + +#define SEGMENT_DEV_SIG SIGNATURE_64 ('P', 'C', 'P', 'S', 'G', 'M', 'N', '= T') + +typedef struct { + // + // Signature identifying the derived class. + // + UINT64 Signature; + // + // Members added by the derived class, specific to the use of PciSegment= Lib. + // + PCI_CAP_DOMAIN MaxDomain; + UINT16 SegmentNr; + UINT8 BusNr; + UINT8 DeviceNr; + UINT8 FunctionNr; + // + // Base class. + // + PCI_CAP_DEV BaseDevice; +} SEGMENT_DEV; + +#define SEGMENT_DEV_FROM_PCI_CAP_DEV(PciDevice) \ + CR (PciDevice, SEGMENT_DEV, BaseDevice, SEGMENT_DEV_SIG) + +#endif // __BASE_PCI_CAP_PCI_SEGMENT_LIB_H__ diff --git a/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLi= b.c b/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.c new file mode 100644 index 000000000000..57eb6b625b56 --- /dev/null +++ b/OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.c @@ -0,0 +1,226 @@ +/** @file + Plug a PciSegmentLib backend into PciCapLib, for config space access. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include + +#include +#include +#include + +#include "BasePciCapPciSegmentLib.h" + + +/** + Read the config space of a given PCI device (both normal and extended). + + SegmentDevReadConfig() performs as few config space accesses as possible + (without attempting 64-bit wide accesses). + + @param[in] PciDevice Implementation-specific unique representa= tion + of the PCI device in the PCI hierarchy. + + @param[in] SourceOffset Source offset in the config space of the = PCI + device to start reading from. + + @param[out] DestinationBuffer Buffer to store the read data to. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from config + space to DestinationBuffer. + + @retval RETURN_UNSUPPORTED Accessing Size bytes from SourceOffset excee= ds + the config space limit of the PCI device. + Although PCI_CAP_DEV_READ_CONFIG allows read= ing + fewer than Size bytes in this case, + SegmentDevReadConfig() will read none. +**/ +STATIC +RETURN_STATUS +EFIAPI +SegmentDevReadConfig ( + IN PCI_CAP_DEV *PciDevice, + IN UINT16 SourceOffset, + OUT VOID *DestinationBuffer, + IN UINT16 Size + ) +{ + SEGMENT_DEV *SegmentDev; + UINT16 ConfigSpaceSize; + UINT64 SourceAddress; + + SegmentDev =3D SEGMENT_DEV_FROM_PCI_CAP_DEV (PciDevice); + ConfigSpaceSize =3D (SegmentDev->MaxDomain =3D=3D PciCapNormal ? + PCI_MAX_CONFIG_OFFSET : PCI_EXP_MAX_CONFIG_OFFSET); + // + // Note that all UINT16 variables below are promoted to INT32, and the + // addition and the comparison is carried out in INT32. + // + if (SourceOffset + Size > ConfigSpaceSize) { + return RETURN_UNSUPPORTED; + } + SourceAddress =3D PCI_SEGMENT_LIB_ADDRESS (SegmentDev->SegmentNr, + SegmentDev->BusNr, SegmentDev->DeviceNr, + SegmentDev->FunctionNr, SourceOffset); + PciSegmentReadBuffer (SourceAddress, Size, DestinationBuffer); + return RETURN_SUCCESS; +} + + +/** + Write the config space of a given PCI device (both normal and extended). + + SegmentDevWriteConfig() performs as few config space accesses as possible + (without attempting 64-bit wide accesses). + + @param[in] PciDevice Implementation-specific unique representat= ion + of the PCI device in the PCI hierarchy. + + @param[in] DestinationOffset Destination offset in the config space of = the + PCI device to start writing at. + + @param[in] SourceBuffer Buffer to read the data to be stored from. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from + SourceBuffer to config space. + + @retval RETURN_UNSUPPORTED Accessing Size bytes at DestinationOffset ex= ceeds + the config space limit of the PCI device. + Although PCI_CAP_DEV_WRITE_CONFIG allows wri= ting + fewer than Size bytes in this case, + SegmentDevWriteConfig() will write none. +**/ +STATIC +RETURN_STATUS +EFIAPI +SegmentDevWriteConfig ( + IN PCI_CAP_DEV *PciDevice, + IN UINT16 DestinationOffset, + IN VOID *SourceBuffer, + IN UINT16 Size + ) +{ + SEGMENT_DEV *SegmentDev; + UINT16 ConfigSpaceSize; + UINT64 DestinationAddress; + + SegmentDev =3D SEGMENT_DEV_FROM_PCI_CAP_DEV (PciDevice); + ConfigSpaceSize =3D (SegmentDev->MaxDomain =3D=3D PciCapNormal ? + PCI_MAX_CONFIG_OFFSET : PCI_EXP_MAX_CONFIG_OFFSET); + // + // Note that all UINT16 variables below are promoted to INT32, and the + // addition and the comparison is carried out in INT32. + // + if (DestinationOffset + Size > ConfigSpaceSize) { + return RETURN_UNSUPPORTED; + } + DestinationAddress =3D PCI_SEGMENT_LIB_ADDRESS (SegmentDev->SegmentNr, + SegmentDev->BusNr, SegmentDev->DeviceNr, + SegmentDev->FunctionNr, DestinationOffset); + PciSegmentWriteBuffer (DestinationAddress, Size, SourceBuffer); + return RETURN_SUCCESS; +} + + +/** + Create a PCI_CAP_DEV object from the PCI Segment:Bus:Device.Function + quadruplet. The config space accessors are based upon PciSegmentLib. + + @param[in] MaxDomain If MaxDomain is PciCapExtended, then + PciDevice->ReadConfig() and PciDevice->WriteConfi= g() + will delegate extended config space accesses too = to + PciSegmentReadBuffer() and PciSegmentWriteBuffer(= ), + respectively. Otherwise, PciDevice->ReadConfig() = and + PciDevice->WriteConfig() will reject accesses to + extended config space with RETURN_UNSUPPORTED, wi= thout + calling PciSegmentReadBuffer() or + PciSegmentWriteBuffer(). By setting MaxDomain to + PciCapNormal, the platform can prevent undefined + PciSegmentLib behavior when the PCI root bridge u= nder + the PCI device at Segment:Bus:Device.Function doe= sn't + support extended config space. + + @param[in] Segment 16-bit wide segment number. + + @param[in] Bus 8-bit wide bus number. + + @param[in] Device 5-bit wide device number. + + @param[in] Function 3-bit wide function number. + + @param[out] PciDevice The PCI_CAP_DEV object constructed as described a= bove. + PciDevice can be passed to the PciCapLib APIs. + + @retval RETURN_SUCCESS PciDevice has been constructed and out= put. + + @retval RETURN_INVALID_PARAMETER Device or Function does not fit in the + permitted number of bits. + + @retval RETURN_OUT_OF_RESOURCES Memory allocation failed. +**/ +RETURN_STATUS +EFIAPI +PciCapPciSegmentDeviceInit ( + IN PCI_CAP_DOMAIN MaxDomain, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + OUT PCI_CAP_DEV **PciDevice + ) +{ + SEGMENT_DEV *SegmentDev; + + if (Device > PCI_MAX_DEVICE || Function > PCI_MAX_FUNC) { + return RETURN_INVALID_PARAMETER; + } + + SegmentDev =3D AllocatePool (sizeof *SegmentDev); + if (SegmentDev =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + + SegmentDev->Signature =3D SEGMENT_DEV_SIG; + SegmentDev->MaxDomain =3D MaxDomain; + SegmentDev->SegmentNr =3D Segment; + SegmentDev->BusNr =3D Bus; + SegmentDev->DeviceNr =3D Device; + SegmentDev->FunctionNr =3D Function; + SegmentDev->BaseDevice.ReadConfig =3D SegmentDevReadConfig; + SegmentDev->BaseDevice.WriteConfig =3D SegmentDevWriteConfig; + + *PciDevice =3D &SegmentDev->BaseDevice; + return RETURN_SUCCESS; +} + + +/** + Free the resources used by PciDevice. + + @param[in] PciDevice The PCI_CAP_DEV object to free, originally produce= d by + PciCapPciSegmentDeviceInit(). +**/ +VOID +EFIAPI +PciCapPciSegmentDeviceUninit ( + IN PCI_CAP_DEV *PciDevice + ) +{ + SEGMENT_DEV *SegmentDev; + + SegmentDev =3D SEGMENT_DEV_FROM_PCI_CAP_DEV (PciDevice); + FreePool (SegmentDev); +} --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527106896684254.44351670649746; Wed, 23 May 2018 13:21:36 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 72E6F207E4E1D; Wed, 23 May 2018 13:21:30 -0700 (PDT) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4575F207E4E17 for ; Wed, 23 May 2018 13:21:29 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8BF5A77023; Wed, 23 May 2018 20:21:28 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-208.rdu2.redhat.com [10.10.120.208]) by smtp.corp.redhat.com (Postfix) with ESMTP id CEE3463F35; Wed, 23 May 2018 20:21:27 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:17 +0200 Message-Id: <20180523202121.8125-4-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Wed, 23 May 2018 20:21:28 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Wed, 23 May 2018 20:21:28 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 3/7] OvmfPkg: introduce PciCapPciIoLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a library class, and a UEFI_DRIVER lib instance, that are layered on top of PciCapLib, and allow clients to plug an EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config space access. (Side note: Although the UEFI spec says that EFI_PCI_IO_PROTOCOL_CONFIG() returns EFI_UNSUPPORTED if "[t]he address range specified by Offset, Width, and Count is not valid for the PCI configuration header of the PCI controller", this patch doesn't directly document the EFI_UNSUPPORTED error code, for ProtoDevTransferConfig() and its callers ProtoDevReadConfig() and ProtoDevWriteConfig(). Instead, the patch refers to "unspecified error codes". The reason is that in edk2, the PciIoConfigRead() and PciIoConfigWrite() functions [1] can also return EFI_INVALID_PARAMETER for the above situation. Namely, PciIoConfigRead() and PciIoConfigWrite() first call PciIoVerifyConfigAccess(), which indeed produces the standard EFI_UNSUPPORTED error code, if the device's config space is exceeded. However, if PciIoVerifyConfigAccess() passes, and we reach RootBridgeIoPciRead() and RootBridgeIoPciWrite() [2], then RootBridgeIoCheckParameter() can still fail, e.g. if the root bridge doesn't support extended config space (see commit 014b472053ae3). For all kinds of Limit violations in IO, MMIO, and config space, RootBridgeIoCheckParameter() returns EFI_INVALID_PARAMETER, not EFI_UNSUPPORTED. That error code is then propagated up to, and out of, PciIoConfigRead() and PciIoConfigWrite(). [1] MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c [2] MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c ) Cc: Ard Biesheuvel Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - move library from MdePkg to OvmfPkg, for initial introduction OvmfPkg/OvmfPkg.dec | 5 + OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf | 36 +++ OvmfPkg/Include/Library/PciCapPciIoLib.h | 58 +++++ OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.h | 44 ++++ OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.c | 243 ++++++++++= ++++++++++ 5 files changed, 386 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index fbec1cfe4a8e..dc5597db4136 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -35,6 +35,11 @@ [LibraryClasses] # config space. PciCapLib|Include/Library/PciCapLib.h =20 + ## @libraryclass Layered on top of PciCapLib, allows clients to plug an + # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config + # space access. + PciCapPciIoLib|Include/Library/PciCapPciIoLib.h + ## @libraryclass Layered on top of PciCapLib, allows clients to plug a # PciSegmentLib backend into PciCapLib, for config space # access. diff --git a/OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf b/Ov= mfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf new file mode 100644 index 000000000000..2e14acb0ab75 --- /dev/null +++ b/OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf @@ -0,0 +1,36 @@ +## @file +# Plug an EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config space acc= ess. +# +# Copyright (C) 2018, Red Hat, Inc. +# +# This program and the accompanying materials are licensed and made availa= ble +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +## + +[Defines] + INF_VERSION =3D 1.27 + BASE_NAME =3D UefiPciCapPciIoLib + FILE_GUID =3D 4102F4FE-DA10-4F0F-AC18-4982ED506154 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciCapPciIoLib + +[Sources] + UefiPciCapPciIoLib.h + UefiPciCapPciIoLib.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib + +[Protocols] + gEfiPciIoProtocolGuid ## CONSUMES diff --git a/OvmfPkg/Include/Library/PciCapPciIoLib.h b/OvmfPkg/Include/Lib= rary/PciCapPciIoLib.h new file mode 100644 index 000000000000..553715fd5080 --- /dev/null +++ b/OvmfPkg/Include/Library/PciCapPciIoLib.h @@ -0,0 +1,58 @@ +/** @file + Library class layered on top of PciCapLib that allows clients to plug an + EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config space access. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __PCI_CAP_PCI_IO_LIB_H__ +#define __PCI_CAP_PCI_IO_LIB_H__ + +#include + +#include + + +/** + Create a PCI_CAP_DEV object from an EFI_PCI_IO_PROTOCOL instance. The co= nfig + space accessors are based upon EFI_PCI_IO_PROTOCOL.Pci.Read() and + EFI_PCI_IO_PROTOCOL.Pci.Write(). + + @param[in] PciIo EFI_PCI_IO_PROTOCOL representation of the PCI dev= ice. + + @param[out] PciDevice The PCI_CAP_DEV object constructed as described a= bove. + PciDevice can be passed to the PciCapLib APIs. + + @retval EFI_SUCCESS PciDevice has been constructed and output. + + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. +**/ +EFI_STATUS +EFIAPI +PciCapPciIoDeviceInit ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT PCI_CAP_DEV **PciDevice + ); + + +/** + Free the resources used by PciDevice. + + @param[in] PciDevice The PCI_CAP_DEV object to free, originally produce= d by + PciCapPciIoDeviceInit(). +**/ +VOID +EFIAPI +PciCapPciIoDeviceUninit ( + IN PCI_CAP_DEV *PciDevice + ); + +#endif // __PCI_CAP_PCI_IO_LIB_H__ diff --git a/OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.h b/Ovmf= Pkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.h new file mode 100644 index 000000000000..a94f65e5a4e3 --- /dev/null +++ b/OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.h @@ -0,0 +1,44 @@ +/** @file + Plug an EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config space acc= ess + -- internal macro and type definitions. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __UEFI_PCI_CAP_PCI_IO_LIB_H__ +#define __UEFI_PCI_CAP_PCI_IO_LIB_H__ + +#include + +#include + +#define PROTO_DEV_SIG SIGNATURE_64 ('P', 'C', 'P', 'I', 'O', 'P', 'R', 'T') + +typedef struct { + // + // Signature identifying the derived class. + // + UINT64 Signature; + // + // Members added by the derived class, specific to the use of + // EFI_PCI_IO_PROTOCOL. + // + EFI_PCI_IO_PROTOCOL *PciIo; + // + // Base class. + // + PCI_CAP_DEV BaseDevice; +} PROTO_DEV; + +#define PROTO_DEV_FROM_PCI_CAP_DEV(PciDevice) \ + CR (PciDevice, PROTO_DEV, BaseDevice, PROTO_DEV_SIG) + +#endif // __UEFI_PCI_CAP_PCI_IO_LIB_H__ diff --git a/OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.c b/Ovmf= Pkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.c new file mode 100644 index 000000000000..84369e4dc3a8 --- /dev/null +++ b/OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.c @@ -0,0 +1,243 @@ +/** @file + Plug an EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config space acc= ess. + + Copyright (C) 2018, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include + +#include "UefiPciCapPciIoLib.h" + + +/** + Transfer bytes between the config space of a given PCI device and a memo= ry + buffer. + + ProtoDevTransferConfig() performs as few config space accesses as possib= le + (without attempting 64-bit wide accesses). + + @param[in] PciIo The EFI_PCI_IO_PROTOCOL representation of t= he + PCI device. + + @param[in] TransferFunction The EFI_PCI_IO_PROTOCOL_CONFIG function that + implements the transfer. The direction of t= he + transfer is inherent to TransferFunction. + TransferFunction() is required to return an + unspecified error if any sub-transfer within + Size bytes from ConfigOffset exceeds the co= nfig + space limit of the PCI device. + + @param[in] ConfigOffset The offset in the config space of the PCI d= evice + at which the transfer should commence. + + @param[in,out] Buffer The memory buffer where the transfer should + occur. + + @param[in] Size The number of bytes to transfer. + + @retval EFI_SUCCESS Size bytes have been transferred between config spa= ce + and Buffer. + + @return Error codes propagated from TransferFunction(). Few= er + than Size bytes may have been transferred. +**/ +STATIC +EFI_STATUS +ProtoDevTransferConfig ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN EFI_PCI_IO_PROTOCOL_CONFIG TransferFunction, + IN UINT16 ConfigOffset, + IN OUT UINT8 *Buffer, + IN UINT16 Size + ) +{ + while (Size > 0) { + EFI_PCI_IO_PROTOCOL_WIDTH Width; + UINT16 Count; + EFI_STATUS Status; + UINT16 Progress; + + // + // Pick the largest access size that is allowed by the remaining trans= fer + // Size and by the alignment of ConfigOffset. + // + // When the largest access size is available, transfer as many bytes as + // possible in one iteration of the loop. Otherwise, transfer only one + // unit, to improve the alignment. + // + if (Size >=3D BIT2 && (ConfigOffset & (BIT2 - 1)) =3D=3D 0) { + Width =3D EfiPciIoWidthUint32; + Count =3D Size >> Width; + } else if (Size >=3D BIT1 && (ConfigOffset & (BIT1 - 1)) =3D=3D 0) { + Width =3D EfiPciIoWidthUint16; + Count =3D 1; + } else { + Width =3D EfiPciIoWidthUint8; + Count =3D 1; + } + Status =3D TransferFunction (PciIo, Width, ConfigOffset, Count, Buffer= ); + if (EFI_ERROR (Status)) { + return Status; + } + Progress =3D Count << Width; + ConfigOffset +=3D Progress; + Buffer +=3D Progress; + Size -=3D Progress; + } + return EFI_SUCCESS; +} + + +/** + Read the config space of a given PCI device (both normal and extended). + + ProtoDevReadConfig() performs as few config space accesses as possible + (without attempting 64-bit wide accesses). + + ProtoDevReadConfig() returns an unspecified error if accessing Size bytes + from SourceOffset exceeds the config space limit of the PCI device. Fewer + than Size bytes may have been read in this case. + + @param[in] PciDevice Implementation-specific unique representa= tion + of the PCI device in the PCI hierarchy. + + @param[in] SourceOffset Source offset in the config space of the = PCI + device to start reading from. + + @param[out] DestinationBuffer Buffer to store the read data to. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from config spa= ce to + DestinationBuffer. + + @return Error codes propagated from + EFI_PCI_IO_PROTOCOL.Pci.Read(). Fewer than Size = bytes + may have been read. +**/ +STATIC +RETURN_STATUS +EFIAPI +ProtoDevReadConfig ( + IN PCI_CAP_DEV *PciDevice, + IN UINT16 SourceOffset, + OUT VOID *DestinationBuffer, + IN UINT16 Size + ) +{ + PROTO_DEV *ProtoDev; + + ProtoDev =3D PROTO_DEV_FROM_PCI_CAP_DEV (PciDevice); + return ProtoDevTransferConfig (ProtoDev->PciIo, ProtoDev->PciIo->Pci.Rea= d, + SourceOffset, DestinationBuffer, Size); +} + + +/** + Write the config space of a given PCI device (both normal and extended). + + ProtoDevWriteConfig() performs as few config space accesses as possible + (without attempting 64-bit wide accesses). + + ProtoDevWriteConfig() returns an unspecified error if accessing Size byt= es at + DestinationOffset exceeds the config space limit of the PCI device. Fewer + than Size bytes may have been written in this case. + + @param[in] PciDevice Implementation-specific unique representat= ion + of the PCI device in the PCI hierarchy. + + @param[in] DestinationOffset Destination offset in the config space of = the + PCI device to start writing at. + + @param[in] SourceBuffer Buffer to read the data to be stored from. + + @param[in] Size The number of bytes to transfer. + + @retval RETURN_SUCCESS Size bytes have been transferred from SourceBuff= er to + config space. + + @return Error codes propagated from + EFI_PCI_IO_PROTOCOL.Pci.Write(). Fewer than Size + bytes may have been written. +**/ +STATIC +RETURN_STATUS +EFIAPI +ProtoDevWriteConfig ( + IN PCI_CAP_DEV *PciDevice, + IN UINT16 DestinationOffset, + IN VOID *SourceBuffer, + IN UINT16 Size + ) +{ + PROTO_DEV *ProtoDev; + + ProtoDev =3D PROTO_DEV_FROM_PCI_CAP_DEV (PciDevice); + return ProtoDevTransferConfig (ProtoDev->PciIo, ProtoDev->PciIo->Pci.Wri= te, + DestinationOffset, SourceBuffer, Size); +} + + +/** + Create a PCI_CAP_DEV object from an EFI_PCI_IO_PROTOCOL instance. The co= nfig + space accessors are based upon EFI_PCI_IO_PROTOCOL.Pci.Read() and + EFI_PCI_IO_PROTOCOL.Pci.Write(). + + @param[in] PciIo EFI_PCI_IO_PROTOCOL representation of the PCI dev= ice. + + @param[out] PciDevice The PCI_CAP_DEV object constructed as described a= bove. + PciDevice can be passed to the PciCapLib APIs. + + @retval EFI_SUCCESS PciDevice has been constructed and output. + + @retval EFI_OUT_OF_RESOURCES Memory allocation failed. +**/ +EFI_STATUS +EFIAPI +PciCapPciIoDeviceInit ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT PCI_CAP_DEV **PciDevice + ) +{ + PROTO_DEV *ProtoDev; + + ProtoDev =3D AllocatePool (sizeof *ProtoDev); + if (ProtoDev =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ProtoDev->Signature =3D PROTO_DEV_SIG; + ProtoDev->PciIo =3D PciIo; + ProtoDev->BaseDevice.ReadConfig =3D ProtoDevReadConfig; + ProtoDev->BaseDevice.WriteConfig =3D ProtoDevWriteConfig; + + *PciDevice =3D &ProtoDev->BaseDevice; + return EFI_SUCCESS; +} + + +/** + Free the resources used by PciDevice. + + @param[in] PciDevice The PCI_CAP_DEV object to free, originally produce= d by + PciCapPciIoDeviceInit(). +**/ +VOID +EFIAPI +PciCapPciIoDeviceUninit ( + IN PCI_CAP_DEV *PciDevice + ) +{ + PROTO_DEV *ProtoDev; + + ProtoDev =3D PROTO_DEV_FROM_PCI_CAP_DEV (PciDevice); + FreePool (ProtoDev); +} --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527106900680548.3688006538315; Wed, 23 May 2018 13:21:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9DFD0207E4E19; Wed, 23 May 2018 13:21:31 -0700 (PDT) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2E998207E4E17 for ; Wed, 23 May 2018 13:21:30 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 803DC406E974; Wed, 23 May 2018 20:21:29 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-208.rdu2.redhat.com [10.10.120.208]) by smtp.corp.redhat.com (Postfix) with ESMTP id C78B983B83; Wed, 23 May 2018 20:21:28 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:18 +0200 Message-Id: <20180523202121.8125-5-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:29 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:29 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 4/7] OvmfPkg: resolve PciCapLib, PciCapPciSegmentLib, PciCapPciIoLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Resolve the PciCapLib, PciCapPciSegmentLib, and PciCapPciIoLib classes to their single respective instances. Later patches will use these lib classes in OvmfPkg drivers. Cc: Ard Biesheuvel Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - update references from MdePkg to OvmfPkg OvmfPkg/OvmfPkgIa32.dsc | 3 +++ OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++ OvmfPkg/OvmfPkgX64.dsc | 3 +++ 3 files changed, 9 insertions(+) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 251434a9ff7c..a2c995b910cd 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -127,6 +127,9 @@ [LibraryClasses] PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index ce247a59d61a..bc7db229d2d9 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -132,6 +132,9 @@ [LibraryClasses] PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 67f7e155ee3e..0767b34d1877 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -132,6 +132,9 @@ [LibraryClasses] PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527106904565138.55040807599084; Wed, 23 May 2018 13:21:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CFA76207E53F1; Wed, 23 May 2018 13:21:32 -0700 (PDT) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0E4212063E30E for ; Wed, 23 May 2018 13:21:31 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5766E818BAEF; Wed, 23 May 2018 20:21:30 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-208.rdu2.redhat.com [10.10.120.208]) by smtp.corp.redhat.com (Postfix) with ESMTP id C0F9463F35; Wed, 23 May 2018 20:21:29 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:19 +0200 Message-Id: <20180523202121.8125-6-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Wed, 23 May 2018 20:21:30 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Wed, 23 May 2018 20:21:30 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 5/7] ArmVirtPkg: resolve PciCapLib, PciCapPciSegmentLib, PciCapPciIoLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Resolve the PciCapLib, PciCapPciSegmentLib, and PciCapPciIoLib classes to their single respective instances under OvmfPkg. Later patches will use those lib classes in OvmfPkg drivers, some of which are included in ArmVirt platforms. Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - update references from MdePkg to OvmfPkg ArmVirtPkg/ArmVirt.dsc.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc index 35bccb3dc1f4..766e4f598a07 100644 --- a/ArmVirtPkg/ArmVirt.dsc.inc +++ b/ArmVirtPkg/ArmVirt.dsc.inc @@ -131,6 +131,9 @@ [LibraryClasses.common] # PCI Libraries PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPci= ExpressLib.inf + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf =20 # USB Libraries UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527106907915859.160298381051; Wed, 23 May 2018 13:21:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0A62F207E5403; Wed, 23 May 2018 13:21:34 -0700 (PDT) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07534207E53ED for ; Wed, 23 May 2018 13:21:32 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4FD53406F8B0; Wed, 23 May 2018 20:21:31 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-208.rdu2.redhat.com [10.10.120.208]) by smtp.corp.redhat.com (Postfix) with ESMTP id 96F2963F35; Wed, 23 May 2018 20:21:30 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:20 +0200 Message-Id: <20180523202121.8125-7-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:31 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Wed, 23 May 2018 20:21:31 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 6/7] OvmfPkg/PciHotPlugInitDxe: convert to PciCapLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Replace the manual capability list parsing in OvmfPkg/PciHotPlugInitDxe with PciCapLib and PciCapPciSegmentLib API calls. Cc: Ard Biesheuvel Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - no changes OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf | 5 + OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c | 267 +++++++------------- 2 files changed, 102 insertions(+), 170 deletions(-) diff --git a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf b/OvmfPkg/PciHotP= lugInitDxe/PciHotPlugInit.inf index 38043986eb67..cc2b60d44263 100644 --- a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf +++ b/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf @@ -35,6 +35,8 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + PciCapLib + PciCapPciSegmentLib PciLib UefiBootServicesTableLib UefiDriverEntryPoint @@ -42,5 +44,8 @@ [LibraryClasses] [Protocols] gEfiPciHotPlugInitProtocolGuid ## ALWAYS_PRODUCES =20 +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId ## CONSUMES + [Depex] TRUE diff --git a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c b/OvmfPkg/PciHotPlu= gInitDxe/PciHotPlugInit.c index 177e1a62120d..3449796878ef 100644 --- a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c +++ b/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c @@ -14,6 +14,7 @@ **/ =20 #include +#include #include =20 #include @@ -21,12 +22,20 @@ #include #include #include +#include +#include #include #include =20 #include #include =20 +// +// TRUE if the PCI platform supports extended config space, FALSE otherwis= e. +// +STATIC BOOLEAN mPciExtConfSpaceSupported; + + // // The protocol interface this driver produces. // @@ -248,91 +257,11 @@ HighBitSetRoundUp64 ( } =20 =20 -/** - Read a slice from conventional PCI config space at the given offset, then - advance the offset. - - @param[in] PciAddress The address of the PCI Device -- Bus, Device, Fun= ction - -- in UEFI (not PciLib) encoding. - - @param[in,out] Offset On input, the offset in conventional PCI config s= pace - to start reading from. On output, the offset of t= he - first byte that was not read. - - @param[in] Size The number of bytes to read. - - @param[out] Buffer On output, the bytes read from PCI config space a= re - stored in this object. -**/ -STATIC -VOID -ReadConfigSpace ( - IN CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciAddress, - IN OUT UINT8 *Offset, - IN UINT8 Size, - OUT VOID *Buffer - ) -{ - PciReadBuffer ( - PCI_LIB_ADDRESS ( - PciAddress->Bus, - PciAddress->Device, - PciAddress->Function, - *Offset - ), - Size, - Buffer - ); - *Offset +=3D Size; -} - - -/** - Convenience wrapper macro for ReadConfigSpace(). - - Given the following conditions: - - - HeaderField is the first field in the structure pointed-to by Struct, - - - Struct->HeaderField has been populated from the conventional PCI config - space of the PCI device identified by PciAddress, - - - *Offset points one past HeaderField in the conventional PCI config spa= ce of - the PCI device identified by PciAddress, - - populate the rest of *Struct from conventional PCI config space, startin= g at - *Offset. Finally, increment *Offset so that it point one past *Struct. - - @param[in] PciAddress The address of the PCI Device -- Bus, Device, Fun= ction - -- in UEFI (not PciLib) encoding. Type: pointer to - CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS. - - @param[in,out] Offset On input, the offset in conventional PCI config s= pace - to start reading from; one past Struct->HeaderFie= ld. - On output, the offset of the first byte that was = not - read; one past *Struct. Type: pointer to UINT8. - - @param[out] Struct The structure to complete. Type: pointer to struc= ture - object. - - @param[in] HeaderField The name of the first field in *Struct, after whi= ch - *Struct should be populated. Type: structure memb= er - identifier. -**/ -#define COMPLETE_CONFIG_SPACE_STRUCT(PciAddress, Offset, Struct, HeaderFie= ld) \ - ReadConfigSpace ( = \ - (PciAddress), = \ - (Offset), = \ - (UINT8)(sizeof *(Struct) - sizeof ((Struct)->HeaderField)), = \ - &((Struct)->HeaderField) + 1 = \ - ) - - /** Look up the QEMU-specific Resource Reservation capability in the convent= ional config space of a Hotplug Controller (that is, PCI Bridge). =20 - This function performs as few config space reads as possible. + On error, the contents of ReservationHint are indeterminate. =20 @param[in] HpcPciAddress The address of the PCI Bridge -- Bus, Devic= e, Function -- in UEFI (not PciLib) encoding. @@ -343,8 +272,9 @@ ReadConfigSpace ( @retval EFI_SUCCESS The capability has been found, ReservationHint has been populated. =20 - @retval EFI_NOT_FOUND The capability is missing. The contents of - ReservationHint are now indeterminate. + @retval EFI_NOT_FOUND The capability is missing. + + @return Error codes from PciCapPciSegmentLib and PciCapLi= b. **/ STATIC EFI_STATUS @@ -353,10 +283,12 @@ QueryReservationHint ( OUT QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION *ReservationHint ) { - UINT16 PciVendorId; - UINT16 PciStatus; - UINT8 PciCapPtr; - UINT8 Offset; + UINT16 PciVendorId; + EFI_STATUS Status; + PCI_CAP_DEV *PciDevice; + PCI_CAP_LIST *CapList; + UINT16 VendorInstance; + PCI_CAP *VendorCap; =20 // // Check the vendor identifier. @@ -374,108 +306,101 @@ QueryReservationHint ( } =20 // - // Check the Capabilities List bit in the PCI Status Register. + // Parse the capabilities lists. // - PciStatus =3D PciRead16 ( - PCI_LIB_ADDRESS ( - HpcPciAddress->Bus, - HpcPciAddress->Device, - HpcPciAddress->Function, - PCI_PRIMARY_STATUS_OFFSET - ) - ); - if ((PciStatus & EFI_PCI_STATUS_CAPABILITY) =3D=3D 0) { - return EFI_NOT_FOUND; + Status =3D PciCapPciSegmentDeviceInit ( + mPciExtConfSpaceSupported ? PciCapExtended : PciCapNormal, + 0, // Segment + HpcPciAddress->Bus, + HpcPciAddress->Device, + HpcPciAddress->Function, + &PciDevice + ); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D PciCapListInit (PciDevice, &CapList); + if (EFI_ERROR (Status)) { + goto UninitPciDevice; } =20 // - // Fetch the start of the Capabilities List. - // - PciCapPtr =3D PciRead8 ( - PCI_LIB_ADDRESS ( - HpcPciAddress->Bus, - HpcPciAddress->Device, - HpcPciAddress->Function, - PCI_CAPBILITY_POINTER_OFFSET - ) - ); - - // - // Scan the Capabilities List until we find the terminator element, or t= he - // Resource Reservation capability. + // Scan the vendor capability instances for the Resource Reservation + // capability. // - for (Offset =3D PciCapPtr & 0xFC; - Offset > 0; - Offset =3D ReservationHint->BridgeHdr.VendorHdr.Hdr.NextItemPtr & 0= xFC) { - BOOLEAN EnoughRoom; - - // - // Check if the Resource Reservation capability would fit into config = space - // at this offset. - // - EnoughRoom =3D (BOOLEAN)( - Offset <=3D PCI_MAX_CONFIG_OFFSET - sizeof *Reservation= Hint - ); + VendorInstance =3D 0; + for (;;) { + UINT8 VendorLength; + UINT8 BridgeCapType; =20 - // - // Read the standard capability header so we can check the capability = ID - // (if necessary) and advance to the next capability. - // - ReadConfigSpace ( - HpcPciAddress, - &Offset, - (UINT8)sizeof ReservationHint->BridgeHdr.VendorHdr.Hdr, - &ReservationHint->BridgeHdr.VendorHdr.Hdr - ); - if (!EnoughRoom || - (ReservationHint->BridgeHdr.VendorHdr.Hdr.CapabilityID !=3D - EFI_PCI_CAPABILITY_ID_VENDOR)) { - continue; + Status =3D PciCapListFindCap ( + CapList, + PciCapNormal, + EFI_PCI_CAPABILITY_ID_VENDOR, + VendorInstance++, + &VendorCap + ); + if (EFI_ERROR (Status)) { + goto UninitCapList; } =20 // - // Read the rest of the vendor capability header so we can check the - // capability length. + // Check the vendor capability length. // - COMPLETE_CONFIG_SPACE_STRUCT ( - HpcPciAddress, - &Offset, - &ReservationHint->BridgeHdr.VendorHdr, - Hdr - ); - if (ReservationHint->BridgeHdr.VendorHdr.Length !=3D - sizeof *ReservationHint) { + Status =3D PciCapRead ( + PciDevice, + VendorCap, + OFFSET_OF (EFI_PCI_CAPABILITY_VENDOR_HDR, Length), + &VendorLength, + sizeof VendorLength + ); + if (EFI_ERROR (Status)) { + goto UninitCapList; + } + if (VendorLength !=3D sizeof *ReservationHint) { continue; } =20 // - // Read the rest of the QEMU bridge capability header so we can check = the - // capability type. + // Check the vendor bridge capability type. // - COMPLETE_CONFIG_SPACE_STRUCT ( - HpcPciAddress, - &Offset, - &ReservationHint->BridgeHdr, - VendorHdr - ); - if (ReservationHint->BridgeHdr.Type !=3D + Status =3D PciCapRead ( + PciDevice, + VendorCap, + OFFSET_OF (QEMU_PCI_BRIDGE_CAPABILITY_HDR, Type), + &BridgeCapType, + sizeof BridgeCapType + ); + if (EFI_ERROR (Status)) { + goto UninitCapList; + } + if (BridgeCapType =3D=3D QEMU_PCI_BRIDGE_CAPABILITY_TYPE_RESOURCE_RESERVATION) { - continue; + // + // We have a match. + // + break; } - - // - // Read the body of the reservation hint. - // - COMPLETE_CONFIG_SPACE_STRUCT ( - HpcPciAddress, - &Offset, - ReservationHint, - BridgeHdr - ); - return EFI_SUCCESS; } =20 - return EFI_NOT_FOUND; + // + // Populate ReservationHint. + // + Status =3D PciCapRead ( + PciDevice, + VendorCap, + 0, // SourceOffsetInCap + ReservationHint, + sizeof *ReservationHint + ); + +UninitCapList: + PciCapListUninit (CapList); + +UninitPciDevice: + PciCapPciSegmentDeviceUninit (PciDevice); + + return Status; } =20 =20 @@ -870,6 +795,8 @@ DriverInitialize ( { EFI_STATUS Status; =20 + mPciExtConfSpaceSupported =3D (PcdGet16 (PcdOvmfHostBridgePciDevId) =3D= =3D + INTEL_Q35_MCH_DEVICE_ID); mPciHotPlugInit.GetRootHpcList =3D GetRootHpcList; mPciHotPlugInit.InitializeRootHpc =3D InitializeRootHpc; mPciHotPlugInit.GetResourcePadding =3D GetResourcePadding; --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 05:13:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527106911548635.8979745016006; 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envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Wed, 23 May 2018 22:21:21 +0200 Message-Id: <20180523202121.8125-8-lersek@redhat.com> In-Reply-To: <20180523202121.8125-1-lersek@redhat.com> References: <20180523202121.8125-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Wed, 23 May 2018 20:21:32 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Wed, 23 May 2018 20:21:32 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH v2 7/7] OvmfPkg/Virtio10Dxe: convert to PciCapLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Replace the manual capability list parsing in OvmfPkg/Virtio10Dxe with PciCapLib and PciCapPciIoLib API calls. The VIRTIO_PCI_CAP_LINK structure type is now superfluous. (Well, it always has been; we should have used EFI_PCI_CAPABILITY_HDR.) Also, EFI_PCI_CAPABILITY_VENDOR_HDR is now included at the front of VIRTIO_PCI_CAP. No driver other than Virtio10Dxe relies on VIRTIO_PCI_CAP. Cc: Ard Biesheuvel Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel --- Notes: v2: - no changes OvmfPkg/Virtio10Dxe/Virtio10.inf | 2 + OvmfPkg/Include/IndustryStandard/Virtio10.h | 7 +- OvmfPkg/Virtio10Dxe/Virtio10.c | 135 +++++++------------- 3 files changed, 52 insertions(+), 92 deletions(-) diff --git a/OvmfPkg/Virtio10Dxe/Virtio10.inf b/OvmfPkg/Virtio10Dxe/Virtio1= 0.inf index c4ef15d94bfc..db0cb1189a29 100644 --- a/OvmfPkg/Virtio10Dxe/Virtio10.inf +++ b/OvmfPkg/Virtio10Dxe/Virtio10.inf @@ -32,6 +32,8 @@ [LibraryClasses] BaseMemoryLib DebugLib MemoryAllocationLib + PciCapLib + PciCapPciIoLib UefiBootServicesTableLib UefiDriverEntryPoint UefiLib diff --git a/OvmfPkg/Include/IndustryStandard/Virtio10.h b/OvmfPkg/Include/= IndustryStandard/Virtio10.h index c5efb5cfcb8a..7d51aa36b326 100644 --- a/OvmfPkg/Include/IndustryStandard/Virtio10.h +++ b/OvmfPkg/Include/IndustryStandard/Virtio10.h @@ -16,6 +16,7 @@ #ifndef _VIRTIO_1_0_H_ #define _VIRTIO_1_0_H_ =20 +#include #include =20 // @@ -29,11 +30,7 @@ // #pragma pack (1) typedef struct { - UINT8 CapId; // Capability identifier (generic) - UINT8 CapNext; // Link to next capability (generic) -} VIRTIO_PCI_CAP_LINK; - -typedef struct { + EFI_PCI_CAPABILITY_VENDOR_HDR VendorHdr; UINT8 ConfigType; // Identifies the specific VirtIo 1.0 config structure UINT8 Bar; // The BAR that contains the structure UINT8 Padding[3]; diff --git a/OvmfPkg/Virtio10Dxe/Virtio10.c b/OvmfPkg/Virtio10Dxe/Virtio10.c index e9b50b6e437b..9ebb72c76bfd 100644 --- a/OvmfPkg/Virtio10Dxe/Virtio10.c +++ b/OvmfPkg/Virtio10Dxe/Virtio10.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #include #include =20 @@ -184,48 +186,6 @@ GetBarType ( } =20 =20 -/** - Read a slice from PCI config space at the given offset, then advance the - offset. - - @param [in] PciIo The EFI_PCI_IO_PROTOCOL instance that represents= the - device. - - @param [in,out] Offset On input, the offset in PCI config space to start - reading from. On output, the offset of the first= byte - that was not read. On error, Offset is not modif= ied. - - @param [in] Size The number of bytes to read. - - @param [out] Buffer On output, the bytes read from PCI config space = are - stored in this object. - - @retval EFI_SUCCESS Size bytes have been transferred from PCI config sp= ace - (from Offset) to Buffer, and Offset has been increm= ented - by Size. - - @return Error codes from PciIo->Pci.Read(). -**/ -STATIC -EFI_STATUS -ReadConfigSpace ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN OUT UINT32 *Offset, - IN UINTN Size, - OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - - Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, *Offset, Size, Bu= ffer); - if (EFI_ERROR (Status)) { - return Status; - } - *Offset +=3D (UINT32)Size; - return EFI_SUCCESS; -} - - /* Traverse the PCI capabilities list of a virtio-1.0 device, and capture t= he locations of the interesting virtio-1.0 register blocks. @@ -239,57 +199,51 @@ ReadConfigSpace ( will have been updated from the PCI capabilities found. =20 - @param[in] CapabilityPtr The offset of the first capability in PCI - config space, taken from the standard PCI - device header. - @retval EFI_SUCCESS Traversal successful. =20 - @return Error codes from the ReadConfigSpace() and GetBarTy= pe() - helper functions. + @return Error codes from PciCapPciIoLib, PciCapLib, and the + GetBarType() helper function. */ STATIC EFI_STATUS ParseCapabilities ( - IN OUT VIRTIO_1_0_DEV *Device, - IN UINT8 CapabilityPtr + IN OUT VIRTIO_1_0_DEV *Device ) { - UINT32 Offset; - VIRTIO_PCI_CAP_LINK CapLink; + EFI_STATUS Status; + PCI_CAP_DEV *PciDevice; + PCI_CAP_LIST *CapList; + UINT16 VendorInstance; + PCI_CAP *VendorCap; =20 - for (Offset =3D CapabilityPtr & 0xFC; - Offset > 0; - Offset =3D CapLink.CapNext & 0xFC - ) { - EFI_STATUS Status; + Status =3D PciCapPciIoDeviceInit (Device->PciIo, &PciDevice); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D PciCapListInit (PciDevice, &CapList); + if (EFI_ERROR (Status)) { + goto UninitPciDevice; + } + + for (VendorInstance =3D 0; + !EFI_ERROR (PciCapListFindCap (CapList, PciCapNormal, + EFI_PCI_CAPABILITY_ID_VENDOR, VendorInstance, + &VendorCap)); + VendorInstance++) { UINT8 CapLen; VIRTIO_PCI_CAP VirtIoCap; VIRTIO_1_0_CONFIG *ParsedConfig; =20 - // - // Read capability identifier and link to next capability. - // - Status =3D ReadConfigSpace (Device->PciIo, &Offset, sizeof CapLink, - &CapLink); - if (EFI_ERROR (Status)) { - return Status; - } - if (CapLink.CapId !=3D 0x09) { - // - // Not a vendor-specific capability, move to the next one. - // - continue; - } - // // Big enough to accommodate a VIRTIO_PCI_CAP structure? // - Status =3D ReadConfigSpace (Device->PciIo, &Offset, sizeof CapLen, &Ca= pLen); + Status =3D PciCapRead (PciDevice, VendorCap, + OFFSET_OF (EFI_PCI_CAPABILITY_VENDOR_HDR, Length), &CapLen, + sizeof CapLen); if (EFI_ERROR (Status)) { - return Status; + goto UninitCapList; } - if (CapLen < sizeof CapLink + sizeof CapLen + sizeof VirtIoCap) { + if (CapLen < sizeof VirtIoCap) { // // Too small, move to next. // @@ -299,11 +253,11 @@ ParseCapabilities ( // // Read interesting part of capability. // - Status =3D ReadConfigSpace (Device->PciIo, &Offset, sizeof VirtIoCap, - &VirtIoCap); + Status =3D PciCapRead (PciDevice, VendorCap, 0, &VirtIoCap, sizeof Vir= tIoCap); if (EFI_ERROR (Status)) { - return Status; + goto UninitCapList; } + switch (VirtIoCap.ConfigType) { case VIRTIO_PCI_CAP_COMMON_CFG: ParsedConfig =3D &Device->CommonConfig; @@ -326,7 +280,7 @@ ParseCapabilities ( // Status =3D GetBarType (Device->PciIo, VirtIoCap.Bar, &ParsedConfig->Ba= rType); if (EFI_ERROR (Status)) { - return Status; + goto UninitCapList; } ParsedConfig->Bar =3D VirtIoCap.Bar; ParsedConfig->Offset =3D VirtIoCap.Offset; @@ -337,19 +291,18 @@ ParseCapabilities ( // This capability has an additional field called NotifyOffsetMultip= lier; // parse it too. // - if (CapLen < sizeof CapLink + sizeof CapLen + sizeof VirtIoCap + - sizeof Device->NotifyOffsetMultiplier) { + if (CapLen < sizeof VirtIoCap + sizeof Device->NotifyOffsetMultiplie= r) { // // Too small, move to next. // continue; } =20 - Status =3D ReadConfigSpace (Device->PciIo, &Offset, - sizeof Device->NotifyOffsetMultiplier, - &Device->NotifyOffsetMultiplier); + Status =3D PciCapRead (PciDevice, VendorCap, sizeof VirtIoCap, + &Device->NotifyOffsetMultiplier, + sizeof Device->NotifyOffsetMultiplier); if (EFI_ERROR (Status)) { - return Status; + goto UninitCapList; } } =20 @@ -359,7 +312,15 @@ ParseCapabilities ( ParsedConfig->Exists =3D TRUE; } =20 - return EFI_SUCCESS; + ASSERT_EFI_ERROR (Status); + +UninitCapList: + PciCapListUninit (CapList); + +UninitPciDevice: + PciCapPciIoDeviceUninit (PciDevice); + + return Status; } =20 =20 @@ -1015,7 +976,7 @@ Virtio10BindingStart ( =20 Device->VirtIo.SubSystemDeviceId =3D Pci.Hdr.DeviceId - 0x1040; =20 - Status =3D ParseCapabilities (Device, Pci.Device.CapabilityPtr); + Status =3D ParseCapabilities (Device); if (EFI_ERROR (Status)) { goto ClosePciIo; } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel