From nobody Tue Apr 23 16:47:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1523876469296361.3577309773051; Mon, 16 Apr 2018 04:01:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 046A822497F56; Mon, 16 Apr 2018 04:01:08 -0700 (PDT) Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 64B5222497F2D for ; Mon, 16 Apr 2018 04:01:06 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id v24so7669221wra.8 for ; Mon, 16 Apr 2018 04:01:05 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id y100sm16931392wmh.2.2018.04.16.04.01.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Apr 2018 04:01:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=i3Ust7hvtFqvCbnMo6vHyF9WQORvirUcrm7FdXboVDE=; b=X5gtaESx4ppwZyiGvHVU9fri4U/01weynLWpDRdZrt5sp0CMxR/9f31x1CLiE7lhVQ AvQXSbYKFakmyAIAqy+iorEAJeG+AQfRWvNvvhCkdvZxGE73Zr+S1+kEVcLoV3aVpIgm Y/aEU6YJ6YzAdL0ua71kXvnxyMRDRiXPnga7Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=i3Ust7hvtFqvCbnMo6vHyF9WQORvirUcrm7FdXboVDE=; b=qidpoAFhZyn3pHNy8K0HjswenRsCjHfXGdN/B1pjZhhzLJIbtkbj4ICMiardDTwy4s lMQp+0/XtmEVJ3z6+5kD5CJAAT/0MEO5lx24iZWB6yoVar5/iayGb9iOrGULMzlJCXzC Xrv8ZSSl43g9OWW3L7uJvU3srcpwI4S8JNr2xJ4Ab0K0IH0D0+OgmxTBpojT9J2Vg1p1 alUr/8qP8n6PnY1Y1i9A18zH7BWSVUu4VdLT+BSCa2biqfxgBEtyyQl9vy7k5PSbW6Bw eWUqq/r+QDzwCQLtL04nNJK2Z2k7sLSt9anT2oAFjKmThZgqSkPY2ktNFUsZSrmDw7l6 BTUg== X-Gm-Message-State: ALQs6tA7UkbJUMFo5gKJ8QgbaCUbVqKBYmEs3TtUJpF5EVeGgxIoVh5b e4jkdDmC2fF5zlVWvtB7IYOjdfVfV0g= X-Google-Smtp-Source: AIpwx4+L1liFs9le02yOPhG5bEJEEgT+DJSpw4J8odwE+PoxRSWxxWWbAMywBOqlHTvkpx7oNZGQ4Q== X-Received: by 10.223.152.20 with SMTP id v20mr1404637wrb.93.1523876464299; Mon, 16 Apr 2018 04:01:04 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 16 Apr 2018 13:00:58 +0200 Message-Id: <20180416110058.16952-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 Subject: [edk2] [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaswinder.singh@linaro.org, Ard Biesheuvel , leif.lindholm@linaro.org, masahisa.kojima@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As reported by Kojima-san, the PHY reference clock value we use in our ACPI and DT descriptions is out of sync with the hardware. Replace 125 MHz with 250 MHz throughout. Cc: Masahisa Kojima Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Kojima-san, Please confirm that the modification to ogma_config.h is correct. Thanks, Ard. Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl = | 2 +- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi = | 4 ++-- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_con= fig.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Soci= onext/SynQuacer/AcpiTables/Dsdt.asl index b6f6c4360029..3f73c191d4d6 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SY= NQUACR", Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress)= }, Package (2) { "max-speed", 1000 }, Package (2) { "max-frame-size", 9000 }, - Package (2) { "socionext,phy-clock-frequency", 125000000 }, + Package (2) { "socionext,phy-clock-frequency", 250000000 }, } }) } diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 6e93c6ae16a8..f6887329f6c7 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -420,9 +420,9 @@ reg-shift =3D <2>; }; =20 - clk_netsec: refclk125mhz { + clk_netsec: refclk250mhz { compatible =3D "fixed-clock"; - clock-frequency =3D <125000000>; + clock-frequency =3D <250000000>; #clock-cells =3D <0>; }; =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/ogma_config.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netse= c_for_uefi/ogma_config.h index 1caf64e30623..f6ec9b30ec8e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogm= a_config.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogm= a_config.h @@ -16,8 +16,8 @@ #ifndef OGMA_CONFIG_H #define OGMA_CONFIG_H =20 -#define OGMA_CONFIG_CLK_HZ 125000000UL -#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL +#define OGMA_CONFIG_CLK_HZ 250000000UL +#define OGMA_CONFIG_GMAC_CLK_HZ 250000000UL #define OGMA_CONFIG_CHECK_CLK_SUPPLY =20 #define OGMA_CONFIG_USE_READ_GMAC_STAT --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel