From nobody Fri May 3 09:05:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1523431803936313.7769767095198; Wed, 11 Apr 2018 00:30:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 91A582270D341; Wed, 11 Apr 2018 00:30:02 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9697522618176 for ; Wed, 11 Apr 2018 00:30:00 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Apr 2018 00:29:59 -0700 Received: from shwdeopenpsi777.ccr.corp.intel.com ([10.239.158.27]) by fmsmga005.fm.intel.com with ESMTP; 11 Apr 2018 00:29:58 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,435,1517904000"; d="scan'208";a="219501954" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 11 Apr 2018 15:29:55 +0800 Message-Id: <20180411072955.6276-1-jian.j.wang@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 Subject: [edk2] [PATCH] MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Michael D Kinney , Jiewen Yao , Eric Dong , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch fixes an issue introduced by commit 5b91bf82c67b586b9588cbe4bbffa1588f6b5926 This issue will only happen if PcdDxeNxMemoryProtectionPolicy is enabled for reserved memory, which will mark SMM RAM as NX (non- executable) during DXE core initialization. SMM IPL driver will unset the NX attribute for SMM RAM to allow loading and running SMM core/drivers. But above commit will fail the unset operation of the NX attribute due to a fact that SMM RAM has zero cache attribute (MRC code always sets 0 attribute for reserved memory), which will cause GCD internal method ConverToCpuArchAttributes() to return 0 attribute which is taken as invalid CPU paging attribute and skip the calling of gCpu->SetMemoryAttributes(). Commit 0c9f2cb10b7ddec56a3440e77219fd3ab1725e5c tries to fix compatible issue but not this one. The solution is to make use of existing functionality in PiSmmIpl to make sure one cache attribute is set for SMM RAM. For performance consideration, PiSmmIpl will always try to set SMM RAM to write-back. But there's a hole in the code which will fail the setting write-back attribute because of no corresponding cache capabilities. This patch will add necessary cache capabilities before setting corresponding attributes. Cc: Star Zeng Cc: Eric Dong Cc: Jiewen Yao Cc: Ruiyu Ni Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang --- MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 32 ++++++++++++++++++++++++------= -- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiS= mmCore/PiSmmIpl.c index 94d671bd74..552220b4dd 100644 --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c @@ -1617,6 +1617,21 @@ SmmIplEntry ( =20 GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCache= Size); // + // Make sure we can change the cache attributes. + // + Status =3D gDS->GetMemorySpaceDescriptor ( + mSmramCacheBase, + &MemDesc + ); + if (!EFI_ERROR (Status) && + (MemDesc.Capabilities & (EFI_MEMORY_WB | EFI_MEMORY_UC)) !=3D (EFI= _MEMORY_WB | EFI_MEMORY_UC)) { + gDS->SetMemorySpaceCapabilities ( + mSmramCacheBase, + mSmramCacheSize, + MemDesc.Capabilities | EFI_MEMORY_WB | EFI_MEMORY_UC + ); + } + // // If CPU AP is present, attempt to set SMRAM cacheability to WB and c= lear // XP if it's set. // Note that it is expected that cacheability of SMRAM has been set to= WB if CPU AP @@ -1626,7 +1641,7 @@ SmmIplEntry ( Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID = **)&CpuArch); if (!EFI_ERROR (Status)) { Status =3D gDS->SetMemorySpaceAttributes( - mSmramCacheBase,=20 + mSmramCacheBase, mSmramCacheSize, EFI_MEMORY_WB ); @@ -1634,16 +1649,17 @@ SmmIplEntry ( DEBUG ((DEBUG_WARN, "SMM IPL failed to set SMRAM window to EFI_MEM= ORY_WB\n")); } =20 - Status =3D gDS->GetMemorySpaceDescriptor( - mCurrentSmramRange->PhysicalStart, + Status =3D gDS->GetMemorySpaceDescriptor ( + mSmramCacheBase, &MemDesc ); if (!EFI_ERROR (Status) && (MemDesc.Attributes & EFI_MEMORY_XP) !=3D= 0) { - gDS->SetMemorySpaceAttributes ( - mCurrentSmramRange->PhysicalStart, - mCurrentSmramRange->PhysicalSize, - MemDesc.Attributes & (~EFI_MEMORY_XP) - ); + Status =3D gDS->SetMemorySpaceAttributes ( + mSmramCacheBase, + mSmramCacheSize, + MemDesc.Attributes & (~EFI_MEMORY_XP) + ); + ASSERT_EFI_ERROR (Status); } } // --=20 2.16.2.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel