From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951712233641.6110205482191; Thu, 5 Apr 2018 11:08:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2B06122685240; Thu, 5 Apr 2018 11:08:15 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8FD5A226C7C45 for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qd027787; Thu, 5 Apr 2018 19:08:09 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:47 +0100 Message-Id: <20180405180803.33684-2-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 01/17] ARM/VExpressPkg: Fix MODULE_TYPE of HDLCD/PL111 platform libraries X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel This change fixes incorrect MODULE_TYPE of HDLCD and PL111 LcdPlatformLibs. Currently set MODUL_TYPE DXE_DRIVER is incorrect for these platform libraries. Hence set this to type BASE. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 4 ++-- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index fc51c781b45122eaf4f2269af61b44c8630cdfb8..5bbfb7eabb5d475a8c6ef21d0a3= f75490be47467 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -2,7 +2,7 @@ # # Component description file for HdLcdArmLib module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2018, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -18,7 +18,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D HdLcdArmVExpress FILE_GUID =3D 535a720e-06c0-4bb9-b563-452216abbed4 - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D LcdPlatformLib =20 diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index fd83d2412d4fd2dfa59204f21626c62e377e3c55..7ffd217a7d1eefb06b99042c2b2= a9ed0079f2bd3 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -2,7 +2,7 @@ # # Component description file for ArmVeGraphicsDxe module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2018, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -18,7 +18,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D PL111LcdArmVExpressLib FILE_GUID =3D b7f06f20-496f-11e0-a8e8-0002a5d5c51b - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D LcdPlatformLib =20 --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 152295171967416.73971327628874; Thu, 5 Apr 2018 11:08:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AEE2D2268524F; Thu, 5 Apr 2018 11:08:15 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8943E21F85E8C for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qe027787; Thu, 5 Apr 2018 19:08:09 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:48 +0100 Message-Id: <20180405180803.33684-3-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 02/17] ARM/VExpressPkg: Tidy HDLCD and PL11LCD platform Lib: Coding standard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 136 ++++++----- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 5 +- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 238 +++++++++++--------- 3 files changed, 218 insertions(+), 161 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index b1106ee19b98cebac01820924514eac79b97d0d5..36ea484bbceac51566bfeaf029b= 1aa0ede93dee1 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -1,6 +1,6 @@ -/** +/** @file =20 - Copyright (c) 2012, ARM Ltd. All rights reserved. + Copyright (c) 2012-2018, ARM Ltd. All rights reserved. =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -44,35 +44,40 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 - LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OS= C_FREQUENCY, + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVG= A_OSC_FREQUENCY, + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OS= C_FREQUENCY, + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SX= GA_OSC_FREQUENCY/2), + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UX= GA_OSC_FREQUENCY/2), + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_F= REQUENCY/2), + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH } @@ -95,19 +100,25 @@ LcdPlatformInitializeDisplay ( { EFI_STATUS Status; =20 - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { + // Set the FPGA multiplexer to select the video output from the + // motherboard or the daughterboard + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_MUXFPGA, + ARM_VE_DAUGHTERBOARD_1_SITE + ); + if (EFI_ERROR (Status)) { return Status; } =20 // Install the EDID Protocols Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); + &Handle, + &gEfiEdidDiscoveredProtocolGuid, + &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, + &mEdidActive, + NULL + ); =20 return Status; } @@ -132,16 +143,25 @@ LcdPlatformGetVram ( } else { AllocationType =3D AllocateAddress; } - Status =3D gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_= SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { + Status =3D gBS->AllocatePages ( + AllocationType, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { return Status; } =20 - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { + // Mark the VRAM as write-combining. + // The VRAM is inside the DRAM, which is cacheable. + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -150,15 +170,11 @@ LcdPlatformGetVram ( } =20 UINT32 -LcdPlatformGetMaxMode ( - VOID - ) +LcdPlatformGetMaxMode (VOID) { - // // The following line will report correctly the total number of graphics= modes - // that could be supported by the graphics driver: - // - return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION)); + // that could be supported by the graphics driver + return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); } =20 EFI_STATUS @@ -174,25 +190,35 @@ LcdPlatformSetMode ( =20 // Set the video mode oscillator do { - Status =3D ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(= PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq); + Status =3D ArmPlatformSysConfigSetDevice ( + SYS_CFG_OSC_SITE1, + PcdGet32 (PcdHdLcdVideoModeOscId), + mResolutions[ModeNumber].OscFreq + ); } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the DVI into the new mode do { - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mode= Number].Mode); + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_MUXFPGA, + ARM_VE_DAUGHTERBOARD_1_SITE + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -216,25 +242,25 @@ LcdPlatformQueryMode ( Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; =20 switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; =20 - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT(FALSE); - break; + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT (FALSE); + break; } =20 return EFI_SUCCESS; diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index 5bbfb7eabb5d475a8c6ef21d0a3f75490be47467..bedbaea3a296bea5184564c5826= 59381733d08a9 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -1,6 +1,6 @@ #/** @file # -# Component description file for HdLcdArmLib module +# Component description file for HdLcdArmVExpress module # # Copyright (c) 2011-2018, ARM Ltd. All rights reserved.
# @@ -23,8 +23,7 @@ [Defines] LIBRARY_CLASS =3D LcdPlatformLib =20 [Sources.common] - -HdLcdArmVExpress.c + HdLcdArmVExpress.c =20 [Packages] ArmPlatformPkg/ArmPlatformPkg.dec diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 18b7ef5cf57f1de8dbd9068731eb21d3f76cbf06..3ab9fe4abb15a41731a518a8500= cd414f670fd66 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -41,87 +41,102 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 - LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_= OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, S= VGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_= OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (SXGA_OSC_FREQUENCY/2), + SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, + SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (UXGA_OSC_FREQUENCY/2), + UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, + UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC= _FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (HD_OSC_FREQUENCY/2), + HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, + HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH }, { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = 63500000, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + 63500000, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH } }; =20 @@ -135,7 +150,6 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 - EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -143,16 +157,19 @@ LcdPlatformInitializeDisplay ( { EFI_STATUS Status; =20 - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard + // Set the FPGA multiplexer to select the video output from the motherbo= ard + // or the daughterboard Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); - if (!EFI_ERROR(Status)) { + if (!EFI_ERROR (Status)) { // Install the EDID Protocols - Status =3D gBS->InstallMultipleProtocolInterfaces( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, + &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, + &mEdidActive, + NULL + ); } =20 return Status; @@ -169,29 +186,38 @@ LcdPlatformGetVram ( Status =3D EFI_SUCCESS; =20 // Is it on the motherboard or on the daughterboard? - switch(PL111_CLCD_SITE) { + switch (PL111_CLCD_SITE) { =20 case ARM_VE_MOTHERBOARD_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOAR= D_BASE; + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; break; =20 case ARM_VE_DAUGHTERBOARD_1_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE; + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; *VramSize =3D LCD_VRAM_SIZE; =20 // Allocate the VRAM from the DRAM so that nobody else uses it. - Status =3D gBS->AllocatePages( AllocateAddress, EfiBootServicesData, E= FI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { + Status =3D gBS->AllocatePages ( + AllocateAddress, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { return Status; } =20 - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, whic= h is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { - gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); + // Mark the VRAM as write-combining. + // The VRAM is inside the DRAM, which is cacheable. + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } break; @@ -206,19 +232,18 @@ LcdPlatformGetVram ( } =20 UINT32 -LcdPlatformGetMaxMode ( - VOID - ) +LcdPlatformGetMaxMode (VOID) { - // The following line will report correctly the total number of graphics= modes - // supported by the PL111CLCD. - //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; + // The following line would correctly report the total number + // of graphics modes supported by the PL111CLCD. + // return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; =20 // However, on some platforms it is desirable to ignore some graphics mo= des. - // This could be because the specific implementation of PL111 has certai= n limitations. + // This could be because the specific implementation of PL111 has + // certain limitations. =20 // Set the maximum mode allowed - return (PcdGet32(PcdPL111LcdMaxMode)); + return (PcdGet32 (PcdPL111LcdMaxMode)); } =20 EFI_STATUS @@ -238,22 +263,26 @@ LcdPlatformSetMode ( =20 LcdSite =3D PL111_CLCD_SITE; =20 - switch(LcdSite) { + switch (LcdSite) { case ARM_VE_MOTHERBOARD_SITE: Function =3D SYS_CFG_OSC; OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; break; case ARM_VE_DAUGHTERBOARD_1_SITE: Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId); + OscillatorId =3D (UINT32)PcdGet32 (PcdPL111LcdVideoModeOscId); break; default: return EFI_UNSUPPORTED; } =20 // Set the video mode oscillator - Status =3D ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResol= utions[ModeNumber].OscFreq); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSetDevice ( + Function, + OscillatorId, + mResolutions[ModeNumber].OscFreq + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -267,8 +296,11 @@ LcdPlatformSetMode ( SysId &=3D ~(ARM_FVP_SYS_ID_VARIANT_MASK | ARM_FVP_SYS_ID_REV_MASK); if (SysId !=3D ARM_FVP_BASE_BOARD_SYS_ID) { // Set the DVI into the new mode - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mo= deNumber].Mode); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -277,7 +309,7 @@ LcdPlatformSetMode ( =20 // Set the multiplexer Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -301,25 +333,25 @@ LcdPlatformQueryMode ( Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; =20 switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; =20 - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT(FALSE); - break; + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT (FALSE); + break; } =20 return EFI_SUCCESS; --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951714586289.7879747704777; Thu, 5 Apr 2018 11:08:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5BE0922685245; Thu, 5 Apr 2018 11:08:15 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90A91226C7C48 for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qf027787; Thu, 5 Apr 2018 19:08:09 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:49 +0100 Message-Id: <20180405180803.33684-4-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 03/17] ARM/VExpressPkg: Tidy HdLcd/PL111Lcd code: Updated comments X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change. In this change some comments in HDLCD and PL111LCD platform library code are modified and a few new comments are added. This is to prevent mixing formatting changes with functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 74 ++++++++++++++++++++ Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 73 +++++++++++++++++++ Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 2 +- 3 files changed, 148 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 36ea484bbceac51566bfeaf029b1aa0ede93dee1..80603f04df3793b8b62196990c8= 46de9ba8f130d 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -44,6 +44,8 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 +/** The display modes supported by the platform. +**/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, @@ -93,6 +95,13 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 +/** HDLCD platform specific initialization function. + + @param[in] Handle Handle to the LCD device instance. + + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -123,6 +132,18 @@ LcdPlatformInitializeDisplay ( return Status; } =20 +/** Allocate VRAM memory in DRAM for the framebuffer + (unless it is reserved already). + + The allocated address can be used to set the framebuffer. + + @param[out] VramBaseAddress A pointer to the framebuffer address. + @param[out] VramSize A pointer to the size of the framebuffer + in bytes + + @retval EFI_SUCCESS Framebuffer memory allocated successfull= y. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, @@ -169,6 +190,13 @@ LcdPlatformGetVram ( return EFI_SUCCESS; } =20 +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode (VOID) { @@ -177,6 +205,14 @@ LcdPlatformGetMaxMode (VOID) return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); } =20 +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber @@ -226,6 +262,17 @@ LcdPlatformSetMode ( return Status; } =20 +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, @@ -266,6 +313,23 @@ LcdPlatformQueryMode ( return EFI_SUCCESS; } =20 +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] HRes Pointer to horizontal resolution. + @param[out] HSync Pointer to horizontal sync width. + @param[out] HBackPorch Pointer to horizontal back porch. + @param[out] HFrontPorch Pointer to horizontal front porch. + @param[out] VRes Pointer to vertical resolution. + @param[out] VSync Pointer to vertical sync width. + @param[out] VBackPorch Pointer to vertical back porch. + @param[out] VFrontPorch Pointer to vertical front porch. + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -295,6 +359,16 @@ LcdPlatformGetTimings ( return EFI_SUCCESS; } =20 +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to bits per pixel information. + + @retval EFI_SUCCESS Bits per pixel information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 3ab9fe4abb15a41731a518a8500cd414f670fd66..3e3102623ebc46cbe31b7f35000= 21f53f2281d1b 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -41,6 +41,8 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 +/** The display modes supported by the platform. +**/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, @@ -150,6 +152,12 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 +/** PL111 Platform specific initialization function. + + @param[in] Handle Handle to the LCD device instance. + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -175,6 +183,18 @@ LcdPlatformInitializeDisplay ( return Status; } =20 +/** Allocate VRAM memory in DRAM for the framebuffer + (unless it is reserved already). + + The allocated address can be used to set the framebuffer. + + @param[out] VramBaseAddress A pointer to the framebuffer address. + @param[out] VramSize A pointer to the size of the framebuffer + in bytes + + @retval EFI_SUCCESS Framebuffer memory allocated successfull= y. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, @@ -231,6 +251,13 @@ LcdPlatformGetVram ( return Status; } =20 +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode (VOID) { @@ -246,6 +273,15 @@ LcdPlatformGetMaxMode (VOID) return (PcdGet32 (PcdPL111LcdMaxMode)); } =20 +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval EFI_UNSUPPORTED PLL111 configuration not supported. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber @@ -317,6 +353,16 @@ LcdPlatformSetMode ( return Status; } =20 +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, @@ -357,6 +403,23 @@ LcdPlatformQueryMode ( return EFI_SUCCESS; } =20 +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] HRes Pointer to horizontal resolution. + @param[out] HSync Pointer to horizontal sync width. + @param[out] HBackPorch Pointer to horizontal back porch. + @param[out] HFrontPorch Pointer to horizontal front porch. + @param[out] VRes Pointer to vertical resolution. + @param[out] VSync Pointer to vertical sync width. + @param[out] VBackPorch Pointer to vertical back porch. + @param[out] VFrontPorch Pointer to vertical front porch. + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -386,6 +449,16 @@ LcdPlatformGetTimings ( return EFI_SUCCESS; } =20 +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to bits per pixel information. + + @retval EFI_SUCCESS Bits per pixel information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index 7ffd217a7d1eefb06b99042c2b2a9ed0079f2bd3..9ca2ace9594d21050c3e5370505= 4c25c69e238f4 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -1,6 +1,6 @@ #/** @file # -# Component description file for ArmVeGraphicsDxe module +# Component description file for PL111LcdArmVExpressLib module # # Copyright (c) 2011-2018, ARM Ltd. All rights reserved.
# --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951707256924.6443548694892; Thu, 5 Apr 2018 11:08:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C255922685237; Thu, 5 Apr 2018 11:08:14 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8E2F5226C7C3E for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qg027787; Thu, 5 Apr 2018 19:08:09 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:50 +0100 Message-Id: <20180405180803.33684-5-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 04/17] ARM/VExpressPkg: Remove unused PcdPL111LcdMaxMode from HDLCD inf X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" PCD PcdPL111LcdMaxMode is not used in HDLCD platform library. Presence of this PCD in HDLCD is probably due to copy/paste code from PL111 Lcd platform library. This change removes it from the HdLcdArmVExpressLib.inf file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index bedbaea3a296bea5184564c582659381733d08a9..34db24d4ee6162b0e963d500a8e= d1097bd8a5ceb 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -40,5 +40,4 @@ [Protocols] gEfiEdidActiveProtocolGuid # Produced =20 [Pcd] - gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951704794609.8070005187402; Thu, 5 Apr 2018 11:08:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8C7A922685233; Thu, 5 Apr 2018 11:08:14 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8D64F226C7C33 for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qh027787; Thu, 5 Apr 2018 19:08:09 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:51 +0100 Message-Id: <20180405180803.33684-6-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 05/17] ARM/VExpressPkg: Add and update debug ASSERTS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds some debug assertions e.g to catch NULL pointer errors missing in PL11Lcd and HdLcd platform libraries. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Notes: V3: - Use ASSERT_EFI_ERROR (Status) in place of ASSERT (FALSE) [Ard] =20 Done [Girish] Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 22 +++++++++++++++++- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 24 +++++++++++++++++++- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 80603f04df3793b8b62196990c846de9ba8f130d..5247b8e038ac45ba800d0f6c79f= 8718c99b951da 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -153,6 +153,9 @@ LcdPlatformGetVram ( EFI_STATUS Status; EFI_ALLOCATE_TYPE AllocationType; =20 + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + // Set the vram size *VramSize =3D LCD_VRAM_SIZE; =20 @@ -171,6 +174,7 @@ LcdPlatformGetVram ( VramBaseAddress ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } =20 @@ -181,8 +185,8 @@ LcdPlatformGetVram ( *VramSize, EFI_MEMORY_WC ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -221,6 +225,7 @@ LcdPlatformSetMode ( EFI_STATUS Status; =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -279,7 +284,10 @@ LcdPlatformQueryMode ( OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info ) { + ASSERT (Info !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -343,7 +351,18 @@ LcdPlatformGetTimings ( OUT UINT32* VFrontPorch ) { + // One of the pointers is NULL + ASSERT (HRes !=3D NULL); + ASSERT (HSync !=3D NULL); + ASSERT (HBackPorch !=3D NULL); + ASSERT (HFrontPorch !=3D NULL); + ASSERT (VRes !=3D NULL); + ASSERT (VSync !=3D NULL); + ASSERT (VBackPorch !=3D NULL); + ASSERT (VFrontPorch !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -376,6 +395,7 @@ LcdPlatformGetBpp ( ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 3e3102623ebc46cbe31b7f3500021f53f2281d1b..3d2ec7b1bf658a5fd644cd82fd1= 341245ba0f5d3 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -205,6 +205,9 @@ LcdPlatformGetVram ( =20 Status =3D EFI_SUCCESS; =20 + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + // Is it on the motherboard or on the daughterboard? switch (PL111_CLCD_SITE) { =20 @@ -225,6 +228,7 @@ LcdPlatformGetVram ( VramBaseAddress ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } =20 @@ -235,8 +239,8 @@ LcdPlatformGetVram ( *VramSize, EFI_MEMORY_WC ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -294,6 +298,7 @@ LcdPlatformSetMode ( UINT32 SysId; =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -369,7 +374,10 @@ LcdPlatformQueryMode ( OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info ) { + ASSERT (Info !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -433,7 +441,18 @@ LcdPlatformGetTimings ( OUT UINT32* VFrontPorch ) { + // One of the pointers is NULL + ASSERT (HRes !=3D NULL); + ASSERT (HSync !=3D NULL); + ASSERT (HBackPorch !=3D NULL); + ASSERT (HFrontPorch !=3D NULL); + ASSERT (VRes !=3D NULL); + ASSERT (VSync !=3D NULL); + ASSERT (VBackPorch !=3D NULL); + ASSERT (VFrontPorch !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -465,7 +484,10 @@ LcdPlatformGetBpp ( OUT LCD_BPP * Bpp ) { + ASSERT (Bpp !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951699886331.422005538176; Thu, 5 Apr 2018 11:08:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3080C226C7C5F; Thu, 5 Apr 2018 11:08:14 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8BB10224A9ECA for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qi027787; Thu, 5 Apr 2018 19:08:09 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:52 +0100 Message-Id: <20180405180803.33684-7-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 06/17] ARM/VExpressPkg: PL111Lcd/HdLcd plaform libs: Minor code cleanup X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This minor change removes some unecessary initializations and variables in PL111LcdArmVExpress.c and redudant return status checks in HdLcdArmVExpress.c Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 5 +---- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 16 ++++------------ 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 5247b8e038ac45ba800d0f6c79f8718c99b951da..6fe7360d55c85ab9137b245b2fa= 7abf661de270e 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -259,10 +259,7 @@ LcdPlatformSetMode ( SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } + ASSERT_EFI_ERROR (Status); =20 return Status; } diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 3d2ec7b1bf658a5fd644cd82fd1341245ba0f5d3..c229530ce8e7156d0b834abbe46= 1a4d3213afc79 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -203,8 +203,6 @@ LcdPlatformGetVram ( { EFI_STATUS Status; =20 - Status =3D EFI_SUCCESS; - ASSERT (VramBaseAddress !=3D NULL); ASSERT (VramSize !=3D NULL); =20 @@ -214,6 +212,7 @@ LcdPlatformGetVram ( case ARM_VE_MOTHERBOARD_SITE: *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; + Status =3D EFI_SUCCESS; break; =20 case ARM_VE_DAUGHTERBOARD_1_SITE: @@ -242,7 +241,6 @@ LcdPlatformGetVram ( if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); - return Status; } break; =20 @@ -292,7 +290,6 @@ LcdPlatformSetMode ( ) { EFI_STATUS Status; - UINT32 LcdSite; UINT32 OscillatorId; SYS_CONFIG_FUNCTION Function; UINT32 SysId; @@ -302,9 +299,7 @@ LcdPlatformSetMode ( return EFI_INVALID_PARAMETER; } =20 - LcdSite =3D PL111_CLCD_SITE; - - switch (LcdSite) { + switch (PL111_CLCD_SITE) { case ARM_VE_MOTHERBOARD_SITE: Function =3D SYS_CFG_OSC; OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; @@ -349,11 +344,8 @@ LcdPlatformSetMode ( } =20 // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); + ASSERT_EFI_ERROR (Status); =20 return Status; } --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:53 +0100 Message-Id: <20180405180803.33684-8-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 07/17] ARM/VExpressPkg: PL111 and HDLCD: Use FixedPcdGet32 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change replaces PcdGet32 with FixedPcdGet32 for the PCDs which are defined as fixed PCDs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 2 +- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 2 +- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 4 ++-- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 6fe7360d55c85ab9137b245b2fa7abf661de270e..d6d63295688f9aa5a6b24cee142= 760609439941d 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -233,7 +233,7 @@ LcdPlatformSetMode ( do { Status =3D ArmPlatformSysConfigSetDevice ( SYS_CFG_OSC_SITE1, - PcdGet32 (PcdHdLcdVideoModeOscId), + FixedPcdGet32 (PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq ); } while (Status =3D=3D EFI_TIMEOUT); diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index 34db24d4ee6162b0e963d500a8ed1097bd8a5ceb..eb2a3c94b80129a16bf9ae26b7c= 2a5403556dc71 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -39,5 +39,5 @@ [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced gEfiEdidActiveProtocolGuid # Produced =20 -[Pcd] +[FixedPcd] gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index c229530ce8e7156d0b834abbe461a4d3213afc79..c51540e1c00a1f46ca845d95306= e28e7ca6bfde5 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -272,7 +272,7 @@ LcdPlatformGetMaxMode (VOID) // certain limitations. =20 // Set the maximum mode allowed - return (PcdGet32 (PcdPL111LcdMaxMode)); + return (FixedPcdGet32 (PcdPL111LcdMaxMode)); } =20 /** Set the requested display mode. @@ -306,7 +306,7 @@ LcdPlatformSetMode ( break; case ARM_VE_DAUGHTERBOARD_1_SITE: Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32 (PcdPL111LcdVideoModeOscId); + OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); break; default: return EFI_UNSUPPORTED; diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index 9ca2ace9594d21050c3e53705054c25c69e238f4..f480000936f394accc98e8d031f= cd2900a6f4611 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -39,6 +39,6 @@ [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced gEfiEdidActiveProtocolGuid # Produced =20 -[Pcd] +[FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:54 +0100 Message-Id: <20180405180803.33684-9-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 08/17] ARM/VExpressPkg: HdLcdArmVExpressLib: Remove status check EFI_TIMEOUT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak None of the ArmPlatformSys* functions returns EFI_TIMEOUT. Hence checking this in the do {} while loop in LcdPlatformSetMode is wrong. Therefore remove this comparision and as a result remove the do {} while loop. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | = 22 ++++++++------------ 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index d6d63295688f9aa5a6b24cee142760609439941d..cd62cd61883dcd78c72aa614466= c6f714cc73fc4 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -230,25 +230,21 @@ LcdPlatformSetMode ( } =20 // Set the video mode oscillator - do { - Status =3D ArmPlatformSysConfigSetDevice ( - SYS_CFG_OSC_SITE1, - FixedPcdGet32 (PcdHdLcdVideoModeOscId), - mResolutions[ModeNumber].OscFreq - ); - } while (Status =3D=3D EFI_TIMEOUT); + Status =3D ArmPlatformSysConfigSetDevice ( + SYS_CFG_OSC_SITE1, + FixedPcdGet32 (PcdHdLcdVideoModeOscId), + mResolutions[ModeNumber].OscFreq + ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the DVI into the new mode - do { - Status =3D ArmPlatformSysConfigSet ( - SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode - ); - } while (Status =3D=3D EFI_TIMEOUT); + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951699566647.8425045696354; Thu, 5 Apr 2018 11:08:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 092EF226C7C5C; Thu, 5 Apr 2018 11:08:14 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8AE1522146740 for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88ql027787; Thu, 5 Apr 2018 19:08:10 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:55 +0100 Message-Id: <20180405180803.33684-10-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 09/17] ARM/VExpressPkg: HdLcdArmVExpressLib: Remove redundant Bpp X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: EvanLloyd Because of copy/paste effects, HdLcdArmVExpress.c contained a table entry "LCD_BPP Bpp;" specifying the Bits per Pixel for each mode. However, all modes are LCD_BITS_PER_PIXEL_24. This change removes the table entry and related use of the field. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | = 42 ++++++-------------- 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index cd62cd61883dcd78c72aa614466c6f714cc73fc4..97cbe77ee79f53d3430b0fdb057= a3bf262834849 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -32,7 +32,6 @@ typedef struct { UINT32 Mode; UINT32 HorizontalResolution; UINT32 VerticalResolution; - LCD_BPP Bpp; UINT32 OscFreq; =20 // These are used by HDLCD @@ -48,37 +47,37 @@ typedef struct { **/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH @@ -289,27 +288,12 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; =20 - switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; =20 return EFI_SUCCESS; } @@ -392,7 +376,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mResolutions[ModeNumber].Bpp; + *Bpp =3D LCD_BITS_PER_PIXEL_24; =20 return EFI_SUCCESS; } --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522954381363915.748095246282; Thu, 5 Apr 2018 11:53:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EBBEA226FAA75; Thu, 5 Apr 2018 11:52:59 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4E4AB226FAA63 for ; Thu, 5 Apr 2018 11:52:57 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qm027787; Thu, 5 Apr 2018 19:08:10 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:56 +0100 Message-Id: <20180405180803.33684-11-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 10/17] ARM/VExpressPkg: Redefine LcdPlatformGetTimings function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: EvanLloyd The LcdPlatformGetTimings interface function takes similar sets of multiple parameters for horizontal and vertical timings which can be aggregated in a common data type. This change defines a structure SCAN_TIMINGS for this which can be used to describe both horizontal and vertical scan timings, and accordingly redefines the LcdPlatformGetTiming interface, greatly reducing the amount of data passed about. Similarly the mode definition tables are also changed to use this data type and thus enable pass through access. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 106 +++++------- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 168 ++++++++------------ 2 files changed, 109 insertions(+), 165 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 97cbe77ee79f53d3430b0fdb057a3bf262834849..0c3a4efd6d8d1617965394f461c= 3f3e7bf70994d 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -30,57 +30,51 @@ =20 typedef struct { UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; UINT32 OscFreq; =20 // These are used by HDLCD - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; =20 /** The display modes supported by the platform. **/ -LCD_RESOLUTION mResolutions[] =3D { +STATIC DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, + VGA, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, + SVGA, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, + XGA, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, + SXGA, (SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, + UXGA, (UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH= }, + {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, + HD, (HD_OSC_FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} } }; =20 @@ -205,7 +199,7 @@ LcdPlatformGetMaxMode (VOID) { // The following line will report correctly the total number of graphics= modes // that could be supported by the graphics driver - return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); + return (sizeof (mDisplayModes) / sizeof (DISPLAY_MODE)); } =20 /** Set the requested display mode. @@ -232,7 +226,7 @@ LcdPlatformSetMode ( Status =3D ArmPlatformSysConfigSetDevice ( SYS_CFG_OSC_SITE1, FixedPcdGet32 (PcdHdLcdVideoModeOscId), - mResolutions[ModeNumber].OscFreq + mDisplayModes[ModeNumber].OscFreq ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -242,7 +236,7 @@ LcdPlatformSetMode ( // Set the DVI into the new mode Status =3D ArmPlatformSysConfigSet ( SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode + mDisplayModes[ModeNumber].Mode ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -284,9 +278,9 @@ LcdPlatformQueryMode ( } =20 Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; @@ -302,14 +296,10 @@ LcdPlatformQueryMode ( =20 @param[in] ModeNumber Mode Number. =20 - @param[out] HRes Pointer to horizontal resolution. - @param[out] HSync Pointer to horizontal sync width. - @param[out] HBackPorch Pointer to horizontal back porch. - @param[out] HFrontPorch Pointer to horizontal front porch. - @param[out] VRes Pointer to vertical resolution. - @param[out] VSync Pointer to vertical sync width. - @param[out] VBackPorch Pointer to vertical back porch. - @param[out] VFrontPorch Pointer to vertical front porch. + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) =20 @retval EFI_SUCCESS Display timing information for the reque= sted mode returned successfully. @@ -317,40 +307,22 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + IN UINT32 ModeNumber, + OUT SCAN_TIMINGS ** Horizontal, + OUT SCAN_TIMINGS ** Vertical ) { // One of the pointers is NULL - ASSERT (HRes !=3D NULL); - ASSERT (HSync !=3D NULL); - ASSERT (HBackPorch !=3D NULL); - ASSERT (HFrontPorch !=3D NULL); - ASSERT (VRes !=3D NULL); - ASSERT (VSync !=3D NULL); - ASSERT (VBackPorch !=3D NULL); - ASSERT (VFrontPorch !=3D NULL); + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; =20 return EFI_SUCCESS; } diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index c51540e1c00a1f46ca845d95306e28e7ca6bfde5..a6fab279e3e5959228259e6d477= 03a304ad372a7 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -28,117 +28,111 @@ =20 typedef struct { UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; LCD_BPP Bpp; UINT32 OscFreq; =20 - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; =20 /** The display modes supported by the platform. **/ -LCD_RESOLUTION mResolutions[] =3D { +STATIC DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH= }, + {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} }, { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + VGA, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + SVGA, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + XGA, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + VGA, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + SVGA, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA, LCD_BITS_PER_PIXEL_16_555, 63500000, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + VGA, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + SVGA, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + XGA, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} } }; =20 @@ -316,7 +310,7 @@ LcdPlatformSetMode ( Status =3D ArmPlatformSysConfigSetDevice ( Function, OscillatorId, - mResolutions[ModeNumber].OscFreq + mDisplayModes[ModeNumber].OscFreq ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -334,7 +328,7 @@ LcdPlatformSetMode ( // Set the DVI into the new mode Status =3D ArmPlatformSysConfigSet ( SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode + mDisplayModes[ModeNumber].Mode ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -374,11 +368,11 @@ LcdPlatformQueryMode ( } =20 Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mResolutions[ModeNumber].Bpp) { + switch (mDisplayModes[ModeNumber].Bpp) { case LCD_BITS_PER_PIXEL_24: Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; @@ -407,14 +401,10 @@ LcdPlatformQueryMode ( =20 @param[in] ModeNumber Mode Number. =20 - @param[out] HRes Pointer to horizontal resolution. - @param[out] HSync Pointer to horizontal sync width. - @param[out] HBackPorch Pointer to horizontal back porch. - @param[out] HFrontPorch Pointer to horizontal front porch. - @param[out] VRes Pointer to vertical resolution. - @param[out] VSync Pointer to vertical sync width. - @param[out] VBackPorch Pointer to vertical back porch. - @param[out] VFrontPorch Pointer to vertical front porch. + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) =20 @retval EFI_SUCCESS Display timing information for the reque= sted mode returned successfully. @@ -422,40 +412,22 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + IN UINT32 ModeNumber, + OUT SCAN_TIMINGS ** Horizontal, + OUT SCAN_TIMINGS ** Vertical ) { // One of the pointers is NULL - ASSERT (HRes !=3D NULL); - ASSERT (HSync !=3D NULL); - ASSERT (HBackPorch !=3D NULL); - ASSERT (HFrontPorch !=3D NULL); - ASSERT (VRes !=3D NULL); - ASSERT (VSync !=3D NULL); - ASSERT (VBackPorch !=3D NULL); - ASSERT (VFrontPorch !=3D NULL); + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; =20 return EFI_SUCCESS; } @@ -483,7 +455,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mResolutions[ModeNumber].Bpp; + *Bpp =3D mDisplayModes[ModeNumber].Bpp; =20 return EFI_SUCCESS; } --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951717021121.11084677284998; Thu, 5 Apr 2018 11:08:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 89EAB2268524A; Thu, 5 Apr 2018 11:08:15 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B10DE226C7C49 for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qn027787; Thu, 5 Apr 2018 19:08:10 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:57 +0100 Message-Id: <20180405180803.33684-12-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 11/17] ARM/VExpressPkg: PL111 and HDLCD: Add PCD to select pixel format X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Current HDLCD and PL111 platform libraries do not support display modes with PixelBlueGreenRedReserved8BitPerColor format, i.e. because of historical confusion, they do not support the UEFI default PixelBlueGreenRedReserved8BitPerColor LcdPlatformLib for PL111, LcdPlatformQueryMode function returns the pixel format as PixelRedGreenBlueReserved8BitPerColor which is wrong, because that does not match the display controller's pixel format which is set to BGR in PL111Lcd GOP driver. Also it is not possible to configure pixel format as RGB/BGR for the display modes for a platform at build time. This change adds PcdGopPixelFormat to configure pixel format as PixelRedGreenBlueReserved8BitPerColor or PixelBlueGreenRedReserved8BitPerColor or PixelBitMask. With this change, pixel format can be selected in the platform specific .dsc file for all supported display modes. Support for PixelBitMask is not implemented in PL111 or HDLCD GOP driver, hence HDLCD and PL111 platform libraries will return error EFI_UNSUPPORTED if PcdGopPixelFormat is set to PixelBitMask. Indeed, it is not clear what selecting PixelBitMask might mean, but the option is allowed as it might suit a custom platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Notes: v3: - Fix minor indentation [Ard] =20 - Done [Girish] Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 23 ++++++++---- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 1 + Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 38 +++++++++----------- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 1 + 4 files changed, 35 insertions(+), 28 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 0c3a4efd6d8d1617965394f461c3f3e7bf70994d..f7cae39c9cc9954ba4cad1bd597= ebfc8baf10f11 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -15,7 +15,6 @@ #include =20 #include -#include #include #include #include @@ -93,6 +92,10 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { @param[in] Handle Handle to the LCD device instance. =20 @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -101,6 +104,17 @@ LcdPlatformInitializeDisplay ( ) { EFI_STATUS Status; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor && + PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor || + PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } =20 // Set the FPGA multiplexer to select the video output from the // motherboard or the daughterboard @@ -282,12 +296,7 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); =20 return EFI_SUCCESS; } diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index eb2a3c94b80129a16bf9ae26b7c2a5403556dc71..9b0d358846bf367d7f9ff6f5d3f= dffc204864528 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -41,3 +41,4 @@ [Protocols] =20 [FixedPcd] gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index a6fab279e3e5959228259e6d47703a304ad372a7..2f4814a2adbf01517ba14d75ce5= 79ff35c362379 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -149,7 +149,12 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { /** PL111 Platform specific initialization function. =20 @param[in] Handle Handle to the LCD device instance. + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -158,6 +163,17 @@ LcdPlatformInitializeDisplay ( ) { EFI_STATUS Status; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor && + PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor || + PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } =20 // Set the FPGA multiplexer to select the video output from the motherbo= ard // or the daughterboard @@ -372,27 +388,7 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mDisplayModes[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); =20 return EFI_SUCCESS; } diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index f480000936f394accc98e8d031fcd2900a6f4611..2bf14f999e633a55abd572daaac= 1e80ae2e648eb 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -42,3 +42,4 @@ [Protocols] [FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951722446947.2194460550384; Thu, 5 Apr 2018 11:08:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D537722685254; Thu, 5 Apr 2018 11:08:15 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39E2E2210D9ED for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qo027787; Thu, 5 Apr 2018 19:08:10 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:58 +0100 Message-Id: <20180405180803.33684-13-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 12/17] ARM/VExpressPkg: Allocate framebuffer using EfiReservedMemoryType X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As per the UEFI specification(2.7) section 12.9, the GOP framebuffer memory can be accessed in the pre-boot and the post boot phase (by OS) Therefore the memory type EfiBootServicesData which may no longer exist after ExitBootServices is incorrect for the framebuffer memory allocation. Change EfiBootServicesData with EfiReservedMemoryType so that allocated memory can be accessed in the post boot phase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Notes: v4: - Use EfiReservedMemory [Ard] - Done [Girish] Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 2 +- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index f7cae39c9cc9954ba4cad1bd597ebfc8baf10f11..f1c497f4b3474e32626bcfce039= 8432319eae72f 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -176,7 +176,7 @@ LcdPlatformGetVram ( } Status =3D gBS->AllocatePages ( AllocationType, - EfiBootServicesData, + EfiReservedMemoryType, EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), VramBaseAddress ); diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 2f4814a2adbf01517ba14d75ce579ff35c362379..50a53d3fff5065b0fcec5a5332d= cc63e344328c3 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -232,7 +232,7 @@ LcdPlatformGetVram ( // Allocate the VRAM from the DRAM so that nobody else uses it. Status =3D gBS->AllocatePages ( AllocateAddress, - EfiBootServicesData, + EfiReservedMemoryType, EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), VramBaseAddress ); --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951725737730.7928905301544; Thu, 5 Apr 2018 11:08:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0734722685258; Thu, 5 Apr 2018 11:08:16 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39EE122146740 for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qp027787; Thu, 5 Apr 2018 19:08:10 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:07:59 +0100 Message-Id: <20180405180803.33684-14-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 13/17] ARM/VExpressPkg: Reserving framebuffer at build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change uses two PCDs, PcdArmLcdFrameBufferBase and PcdArmLcdFrameBufferSize introduced in correspondiong EDK2 patch to reserve framebuffer in DRAM if these values are defined in platform specific DSC file, avoiding the need to allocate dynamically. This allows the framebuffer to appear as "I/O memory" outside of the normal RAM map, which is similar to the "VRAM" case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Notes: v3: - Move PcdArmLcdDdrFrameBufferBase and PcdArmLcdDdrFrameBufferSize to VExpressPkg. [Ard] =20 These PCDs are also used for the Juno platform hence these PCDs are defined for the ArmPlatformPkg so that both platform can use it. [Girish] =20 - Could you please add an ASSERT() so that System Memory and PcdArmLcdDdrFrameBufferBase do not overlap [Ard] =20 Done [Girish] Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | = 4 +- Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 4= 1 ++++++++++++++------ 2 files changed, 32 insertions(+), 13 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpres= sLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf index 8c6291c42f8a599591d00d7afcb2ff3399417034..b025abd98b5e654323b7821ac35= 3ad920e2e6421 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf @@ -1,5 +1,5 @@ #/* @file -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2011-2018, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -54,6 +54,8 @@ [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore =20 gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 9fb0803d31ad0dbab59875bae99fd8a381d484b7..1d5fefc21726ba1b05d90e0e476= 77575d7fa2034 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* Copyright (c) 2011-2018, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -128,17 +128,34 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D 2 * ARM_VE_SMB_PERIPH_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; =20 - // VRAM - VirtualMemoryTable[++Index].PhysicalBase =3D PL111_CLCD_VRAM_MOTHERBOARD= _BASE; - VirtualMemoryTable[Index].VirtualBase =3D PL111_CLCD_VRAM_MOTHERBOARD_BA= SE; - VirtualMemoryTable[Index].Length =3D PL111_CLCD_VRAM_MOTHERBOARD_SIZE; - // - // Map the VRAM region as Normal Non-Cacheable memory and not device mem= ory, - // so that we can use the accelerated string routines that may use unali= gned - // accesses or DC ZVA instructions. The enum identifier is slightly awkw= ard - // here, but it maps to a memory type that allows buffering and reorderi= ng. - // - VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; + // Map region for the framebuffer in the system RAM if no VRAM present + if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferBase) =3D=3D 0) { + // VRAM + VirtualMemoryTable[++Index].PhysicalBase =3D PL111_CLCD_VRAM_MOTHERBOA= RD_BASE; + VirtualMemoryTable[Index].VirtualBase =3D PL111_CLCD_VRAM_MOTHERBOARD_= BASE; + VirtualMemoryTable[Index].Length =3D PL111_CLCD_VRAM_MOTHERBOARD_SIZE; + // + // Map the VRAM region as Normal Non-Cacheable memory and not device m= emory, + // so that we can use the accelerated string routines that may use una= ligned + // accesses or DC ZVA instructions. The enum identifier is slightly aw= kward + // here, but it maps to a memory type that allows buffering and reorde= ring. + // + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + } else { + ASSERT ((ARM_VE_DRAM_BASE + ARM_VE_DRAM_SZ - 1) < + FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase)); + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmLcdD= drFrameBufferBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmLcdDdrF= rameBufferBase); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmLcdDdrFrameB= ufferSize); + // Map as Normal Non-Cacheable memory, so that we can use the accelera= ted + // SetMem/CopyMem routines that may use unaligned accesses or + // DC ZVA instructions. If mapped as device memory, these routine may = cause + // alignment faults. + // NOTE: The attribute value is misleading, it indicates memory map ty= pe as + // an un-cached, un-buffered but allows buffering and reordering. + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + } =20 // Map sparse memory region if present if (HasSparseMemory) { --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 152295172826331.873842088217316; Thu, 5 Apr 2018 11:08:48 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2D7B62268525C; Thu, 5 Apr 2018 11:08:16 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3A1A6226C7C4A for ; Thu, 5 Apr 2018 11:08:12 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qq027787; Thu, 5 Apr 2018 19:08:10 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:08:00 +0100 Message-Id: <20180405180803.33684-15-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 14/17] ARM/VExpressPkg: Set EFI_MEMORY_XP flag on GOP framebuffer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The framebuffer memory is set with flag EFI_MEMORY_WC (uncached, unbuffered) which causes framebuffer memory with eXecute bit set. Framebuffer memory having executable bit set is a security hazard. This fix adds EFI_MEMORY_XP flag to avoid this. Unfortunately function gDS->SetMemorySpaceAttributes() causes assertion due to unsupported EFI_MEMORY_XP type. Therefore this fix replaces gDS->SetMemorySpaceAttributes() with Cpu->SetMemoryAttributes(). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 24 ++++++++++++++------ Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 1 - Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 24 ++++++++++++++------ Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 1 - 4 files changed, 34 insertions(+), 16 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index f1c497f4b3474e32626bcfce0398432319eae72f..711f036d74b6544e54ec073a354= e9fc6f36db5e2 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -17,11 +17,11 @@ #include #include #include -#include #include #include #include =20 +#include #include #include =20 @@ -159,6 +159,7 @@ LcdPlatformGetVram ( { EFI_STATUS Status; EFI_ALLOCATE_TYPE AllocationType; + EFI_CPU_ARCH_PROTOCOL *Cpu; =20 ASSERT (VramBaseAddress !=3D NULL); ASSERT (VramSize !=3D NULL); @@ -185,13 +186,22 @@ LcdPlatformGetVram ( return Status; } =20 - // Mark the VRAM as write-combining. - // The VRAM is inside the DRAM, which is cacheable. - Status =3D gDS->SetMemorySpaceAttributes ( - *VramBaseAddress, - *VramSize, - EFI_MEMORY_WC + // Ensure the Cpu architectural protocol is already installed + Status =3D gBS->LocateProtocol ( + &gEfiCpuArchProtocolGuid, + NULL, + (VOID **)&Cpu ); + if (!EFI_ERROR (Status)) { + // The VRAM is inside the DRAM, which is cacheable. + // Mark the VRAM as write-combining (uncached) and non-executable. + Status =3D Cpu->SetMemoryAttributes ( + Cpu, + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC | EFI_MEMORY_XP + ); + } if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index 9b0d358846bf367d7f9ff6f5d3fdffc204864528..c7b1b7fae77cbbf82b3a0768e76= 54a96719f5e7a 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -33,7 +33,6 @@ [Packages] [LibraryClasses] ArmPlatformSysConfigLib BaseLib - DxeServicesTableLib =20 [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 50a53d3fff5065b0fcec5a5332dcc63e344328c3..bcf4f6593c071b652695ec46368= 7ac2fe84ffa73 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -17,10 +17,10 @@ #include #include #include -#include #include #include =20 +#include #include #include =20 @@ -212,6 +212,7 @@ LcdPlatformGetVram ( ) { EFI_STATUS Status; + EFI_CPU_ARCH_PROTOCOL *Cpu; =20 ASSERT (VramBaseAddress !=3D NULL); ASSERT (VramSize !=3D NULL); @@ -241,13 +242,22 @@ LcdPlatformGetVram ( return Status; } =20 - // Mark the VRAM as write-combining. - // The VRAM is inside the DRAM, which is cacheable. - Status =3D gDS->SetMemorySpaceAttributes ( - *VramBaseAddress, - *VramSize, - EFI_MEMORY_WC + // Ensure the Cpu architectural protocol is already installed + Status =3D gBS->LocateProtocol ( + &gEfiCpuArchProtocolGuid, + NULL, + (VOID **)&Cpu ); + if (!EFI_ERROR (Status)) { + // The VRAM is inside the DRAM, which is cacheable. + // Mark the VRAM as write-combining (uncached) and non-executable. + Status =3D Cpu->SetMemoryAttributes ( + Cpu, + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC | EFI_MEMORY_XP + ); + } if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index 2bf14f999e633a55abd572daaac1e80ae2e648eb..b1fa100def0dd774fec50cb04a6= 38a89b95de575 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -33,7 +33,6 @@ [Packages] [LibraryClasses] ArmPlatformSysConfigLib BaseLib - DxeServicesTableLib =20 [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951733893631.6812244318268; Thu, 5 Apr 2018 11:08:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7D050226C7C52; Thu, 5 Apr 2018 11:08:16 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 98E23226C7C42 for ; Thu, 5 Apr 2018 11:08:13 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qr027787; Thu, 5 Apr 2018 19:08:11 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:08:01 +0100 Message-Id: <20180405180803.33684-16-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 15/17] ARM/VExpressPkg: New DP500/DP550/DP650 platform library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds LcdPlatformLib implementation for Arm Mali DP500/DP500/DP650 display processors for models (with DP550 support). NOTE: Versions for actual hardware are liable to require extra handling for clock input changes, etc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Notes: v3: - Please fix the funky indentation [Ard] =20 Done [Girish] =20 - Add EFI_MEMORY_XP [Ard] =20 Done [Girish] Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | = 3 +- Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c | 3= 87 ++++++++++++++++++++ Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf | = 43 +++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | = 3 + Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | = 12 +- 5 files changed, 446 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec b/Platform/ARM/VEx= pressPkg/ArmVExpressPkg.dec index 695553a94f7f7e963b5db995c5e54f1ae1559daf..ac77540362d0775bed45f517306= b98ea16bfb170 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec +++ b/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec @@ -1,7 +1,7 @@ #/** @file # Arm Versatile Express package. # -# Copyright (c) 2012-2015, ARM Limited. All rights reserved. +# Copyright (c) 2012-2018, ARM Limited. All rights reserved. # # This program and the accompanying materials are licensed and made avail= able # under the terms and conditions of the BSD License which accompanies this @@ -51,6 +51,7 @@ [PcdsFixedAtBuild.common] gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000003 =20 gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000005 + gArmVExpressTokenSpaceGuid.PcdArmMaliDpMaxMode|0|UINT32|0x00000008 =20 # # Device path of block device on which Fastboot will flash partitions diff --git a/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c b= /Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c new file mode 100644 index 0000000000000000000000000000000000000000..04ad341d14650b10b92a38a6ff6= 8108871feef9e --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c @@ -0,0 +1,387 @@ +/** @file + + The file contains Arm Mali DP platform specific implementation. + + Copyright (c) 2017-2018, Arm Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** Check an address is within 40 bits. + + The ARM Mali DP framebuffer address size can not be wider than 40 bits +**/ +#define DP_VALID_BASE_ADDR(Address) ((Address >> 40) =3D=3D 0) + +typedef struct { + UINT32 OscFreq; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; + +/** The display modes implemented by this driver. + + On Models, the OSC frequencies (listed for each mode below) are not used. + However these frequencies are useful on hardware plaforms where related + clock (or PLL) settings are based on these pixel clocks. + + Since the clock settings are defined externally, the driver must + communicate pixel clock frequencies to relevant modules + responsible for setting clocks. e.g. SCP. +**/ +STATIC DISPLAY_MODE mDisplayModes[] =3D { + { + // Mode 0 : VGA : 640 x 480 x 24 bpp. + VGA_OSC_FREQUENCY, + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} + }, + { + // Mode 1 : WVGA : 800 x 480 x 24 bpp. + WVGA_OSC_FREQUENCY, + {WVGA_H_RES_PIXELS, WVGA_H_SYNC, WVGA_H_BACK_PORCH, WVGA_H_FRONT_PORCH= }, + {WVGA_V_RES_PIXELS, WVGA_V_SYNC, WVGA_V_BACK_PORCH, WVGA_V_FRONT_PORCH} + }, + { + // Mode 2 : SVGA : 800 x 600 x 24 bpp. + SVGA_OSC_FREQUENCY, + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} + }, + { + // Mode 3 : QHD : 960 x 540 x 24 bpp. + QHD_OSC_FREQUENCY, + {QHD_H_RES_PIXELS, QHD_H_SYNC, QHD_H_BACK_PORCH, QHD_H_FRONT_PORCH}, + {QHD_V_RES_PIXELS, QHD_V_SYNC, QHD_V_BACK_PORCH, QHD_V_FRONT_PORCH} + }, + { + // Mode 4 : WSVGA : 1024 x 600 x 24 bpp. + WSVGA_OSC_FREQUENCY, + {WSVGA_H_RES_PIXELS, WSVGA_H_SYNC, WSVGA_H_BACK_PORCH, WSVGA_H_FRONT_P= ORCH}, + {WSVGA_V_RES_PIXELS, WSVGA_V_SYNC, WSVGA_V_BACK_PORCH, WSVGA_V_FRONT_P= ORCH} + }, + { + // Mode 5 : XGA : 1024 x 768 x 24 bpp. + XGA_OSC_FREQUENCY, + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} + }, + { + // Mode 6 : HD : 1280 x 720 x 24 bpp. + HD720_OSC_FREQUENCY, + {HD720_H_RES_PIXELS, HD720_H_SYNC, HD720_H_BACK_PORCH, HD720_H_FRONT_P= ORCH}, + {HD720_V_RES_PIXELS, HD720_V_SYNC, HD720_V_BACK_PORCH, HD720_V_FRONT_P= ORCH} + }, + { + // Mode 7 : WXGA : 1280 x 800 x 24 bpp. + WXGA_OSC_FREQUENCY, + {WXGA_H_RES_PIXELS, WXGA_H_SYNC, WXGA_H_BACK_PORCH, WXGA_H_FRONT_PORCH= }, + {WXGA_V_RES_PIXELS, WXGA_V_SYNC, WXGA_V_BACK_PORCH, WXGA_V_FRONT_PORCH} + }, + { // Mode 8 : SXGA : 1280 x 1024 x 24 bpp. + SXGA_OSC_FREQUENCY, + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} + }, + { // Mode 9 : WSXGA+ : 1680 x 1050 x 24 bpp. + WSXGA_OSC_FREQUENCY, + {WSXGA_H_RES_PIXELS, WSXGA_H_SYNC, WSXGA_H_BACK_PORCH, WSXGA_H_FRONT_P= ORCH}, + {WSXGA_V_RES_PIXELS,WSXGA_V_SYNC, WSXGA_V_BACK_PORCH, WSXGA_V_FRONT_PO= RCH} + }, + { + // Mode 10 : HD : 1920 x 1080 x 24 bpp. + HD_OSC_FREQUENCY, + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} + } +}; + +/** If PcdArmMaliDpMaxMode is 0, platform supports full range of modes + else platform supports modes from 0 to PcdArmMaliDpMaxMode - 1 +**/ +STATIC CONST UINT32 mMaxMode =3D ((FixedPcdGet32 (PcdArmMaliDpMaxMode) != =3D 0) + ? FixedPcdGet32 (PcdArmMaliDpMaxMode) + : sizeof (mDisplayModes) / sizeof (DISP= LAY_MODE)); + +/** Platform related initialization function. + + @param[in] Handle Handle to the instance of the device. + + @retval EFI_SUCCESS Initialization of platform library success= ful. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. +**/ +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ) +{ + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + (VOID)Handle; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor && + PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor || + PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/* Internal helper function to allocate memory if memory is not already + reserved for framebuffer + + @param[in] VramSize Requested framebuffer size in bytes. + @param[out] VramBaseAddress Pointer to memory allocated for framebuffe= r. + + @retval EFI_SUCCESS Framebuffer memory allocated successfully. + @retval EFI_UNSUPPORTED Allocated address wider than 40 bits. + @retval !EFI_SUCCESS Other errors. +**/ +STATIC +EFI_STATUS +GetVram ( + IN UINTN VramSize, + OUT EFI_PHYSICAL_ADDRESS * VramBaseAddress + ) +{ + EFI_STATUS Status; + EFI_CPU_ARCH_PROTOCOL *Cpu; + + *VramBaseAddress =3D FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase); + + // Check if memory is already reserved for the framebuffer. + if (*VramBaseAddress !=3D 0) { + // ARM Mali DP framebuffer base address can not be wider than 40 bits. + if (!DP_VALID_BASE_ADDR (*VramBaseAddress)) { + ASSERT (DP_VALID_BASE_ADDR (*VramBaseAddress)); + Status =3D EFI_UNSUPPORTED; + } else { + Status =3D EFI_SUCCESS; + } + } else { + // If not already reserved, attempt to allocate the VRAM from the DRAM. + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (VramSize), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ArmMaliDpLib: Failed to allocate framebuffer.\= n")); + ASSERT_EFI_ERROR (Status); + return Status; + } + + // ARM Mali DP framebuffer base address can not be wider than 40 bits. + if (!DP_VALID_BASE_ADDR (*VramBaseAddress)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (VramSize)); + ASSERT (DP_VALID_BASE_ADDR (*VramBaseAddress)); + return EFI_UNSUPPORTED; + } + + // Ensure the Cpu architectural protocol is already installed + Status =3D gBS->LocateProtocol ( + &gEfiCpuArchProtocolGuid, + NULL, + (VOID **)&Cpu + ); + if (!EFI_ERROR (Status)) { + // The VRAM is inside the DRAM, which is cacheable. + // Mark the VRAM as write-combining (uncached) and non-executable. + Status =3D Cpu->SetMemoryAttributes ( + Cpu, + *VramBaseAddress, + VramSize, + EFI_MEMORY_WC | EFI_MEMORY_XP + ); + } + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (VramSize)); + } + } + + return Status; +} + +/** Allocate VRAM memory in DRAM for the framebuffer + (unless it is reserved already). + + The allocated address can be used to set the framebuffer as a base buffer + address for any layer of the ARM Mali DP. + + @param[out] VramBaseAddress A pointer to the framebuffer address. + @param[out] VramSize A pointer to the size of the frame + buffer in bytes + + @retval EFI_SUCCESS Framebuffer memory allocation success. + @retval EFI_UNSUPPORTED Allocated address wider than 40 bits + @retval !EFI_SUCCESS Other errors. +**/ +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS * VramBaseAddress, + OUT UINTN * VramSize + ) +{ + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + + // Set the VRAM size. + *VramSize =3D (UINTN)FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize); + + return GetVram (*VramSize, VramBaseAddress); +} + +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ +UINT32 +LcdPlatformGetMaxMode (VOID) +{ + return mMaxMode; +} + +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successful. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ) +{ + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + // On models, platform specific clock/mux settings are not required. + // Display controller specific settings for Mali DP are done in LcdSetMo= de. + return EFI_SUCCESS; +} + +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Display mode information of the requested + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * Info + ) +{ + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Info !=3D NULL); + + Info->Version =3D 0; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; + + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + + return EFI_SUCCESS; +} + +/** Return the display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front porc= h) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front porc= h) + + @retval EFI_SUCCESS Display timing information of the reques= ted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT SCAN_TIMINGS ** Horizontal, + OUT SCAN_TIMINGS ** Vertical + ) +{ + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; + + return EFI_SUCCESS; +} + +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Bpp Pointer to bits per pixel information. + + @retval EFI_SUCCESS Bits per pixel information of the display + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP * Bpp + ) +{ + ASSERT (Bpp !=3D NULL); + // Check valid ModeNumber. + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D LCD_BITS_PER_PIXEL_24; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf= b/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..78f7d307b70701194b7121f1652= 9ab10a6d52835 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf @@ -0,0 +1,43 @@ +#/** @file +# Component description file for ArmMaliDpLib module +# +# Copyright (c) 2017-2018, Arm Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmMaliDpLib + FILE_GUID =3D 36C47FED-2F3F-49C7-89CE-31B13F0431D8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + ArmMaliDpLib.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + BaseLib + +[FixedPcd.common] + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat + + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # See Section 12.9 of the UEFI Specification 2.7 + gArmVExpressTokenSpaceGuid.PcdArmMaliDpMaxMode + diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpres= sLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf index b025abd98b5e654323b7821ac353ad920e2e6421..53898c5e957eb1a49cf063fa759= d5a9ca62e7954 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf @@ -57,5 +57,8 @@ [FixedPcd] gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase + gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 1d5fefc21726ba1b05d90e0e47677575d7fa2034..c8eefa0cf28b06d19929912d28d= 87bd78ed7d871 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -20,8 +20,10 @@ #include #include =20 +#define DP_BASE_DESCRIPTOR ((FixedPcdGet64 (PcdArmMaliDpBase) !=3D 0)= ? 1 : 0) + // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + DP_BASE_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -157,6 +159,14 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; } =20 + if (FixedPcdGet64 (PcdArmMaliDpBase) !=3D 0) { + // DP500/DP550/DP650 peripheral memory region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmMali= DpBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmMaliDpB= ase); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmMaliDpMemory= RegionLength); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + } + // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase =3D SparseMemoryBase; --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951730955173.35164345641317; Thu, 5 Apr 2018 11:08:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 52101226C7C33; Thu, 5 Apr 2018 11:08:16 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 91A0A226C7C33 for ; Thu, 5 Apr 2018 11:08:13 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qs027787; Thu, 5 Apr 2018 19:08:11 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:08:02 +0100 Message-Id: <20180405180803.33684-17-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 16/17] ARM/JunoPkg: Adding SCMI MTL library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This change adds a new Mailbox Transport Layer library for the Juno platform. This library is required for ArmScmiDxe driver communication with the SCP. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Reviewed-by: Leif Lindholm --- Notes: v3: - Please rename this library *instance* to something Juno-specific, e.g., ArmJunoMtlLib [Ard] =20 Renamed to ArmJunoMtlLib [Girish] Platform/ARM/JunoPkg/ArmJuno.dec | 9 +- Platform/ARM/JunoPkg/ArmJuno.dsc | 5 +- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c | 8 +- Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.c | 198 ++= ++++++++++++++++++ Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.inf | 39 ++= ++ Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlPrivateLib.h | 94 ++= ++++++++ 6 files changed, 349 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/JunoPkg/ArmJuno.dec b/Platform/ARM/JunoPkg/ArmJun= o.dec index 60cef6d23a2d904103b9806d871fd2b89fff51c3..fdb56fccb2b259301fd787016a9= c4de7ab3c356d 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dec +++ b/Platform/ARM/JunoPkg/ArmJuno.dec @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -46,3 +46,10 @@ [PcdsFixedAtBuild.common] # Juno Device Trees are loaded from NOR Flash gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath|L"VenHw(E7223039-5836-41E1-B= 542-D7EC736C5E59)/board.dtb"|VOID*|0x00000008 =20 + # MHU Register base used by SCMI Mailbox transport + gArmJunoTokenSpaceGuid.PcdArmMtlDoorBell|0x2B1F0000|UINT64|0x00000024 + + # ARM_JUNO_NON_SECURE_SRAM_BASE used by SCMI Mailbox transport + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxBase|0x2E000000|UINT64|0x00000025 + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxSize|0x80|UINT32|0x00000026 + diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJun= o.dsc index 9d7317683ef39ab47429234b98d94c04953b41cb..851dc0f04ad693e4a88cee070b2= 05f0234687d81 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dsc +++ b/Platform/ARM/JunoPkg/ArmJuno.dsc @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -47,6 +47,9 @@ [LibraryClasses.common] # USB Requirements UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf =20 + # SCMI Mailbox Transport Layer + ArmMtlLib|Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.inf + [LibraryClasses.common.SEC] PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c b/Platfor= m/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c index 2d9c2c95a80d9c34ba4a1a526950537a97ec5d10..2cac815e96104e74c9ceae2c414= 0bcab535432a8 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2013-2015, ARM Limited. All rights reserved. +* Copyright (c) 2013-2018, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -107,7 +107,11 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[++Index].PhysicalBase =3D ARM_JUNO_NON_SECURE_SRAM_B= ASE; VirtualMemoryTable[Index].VirtualBase =3D ARM_JUNO_NON_SECURE_SRAM_B= ASE; VirtualMemoryTable[Index].Length =3D ARM_JUNO_NON_SECURE_SRAM_S= Z; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + // This memory is shared between the application processor + // and the SCP. To avoid coherency problems, map it as uncached memory. + // NOTE: The attribute value is misleading, it indicates memory map type= as + // an un-cached, un-buffered but allows buffering and reordering. + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; =20 // PCI Root Complex VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieControlBa= seAddress); diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.c b/P= latform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.c new file mode 100644 index 0000000000000000000000000000000000000000..ee1efe1574c124c7f7cf1fb345b= 46806bc3a4466 --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.c @@ -0,0 +1,198 @@ +/** @file + + Copyright (c) 2017-2018, Arm Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ArmJunoMtlPrivateLib.h" + +// Each channel has a shared mailbox and a doorbell register. +STATIC CONST MTL_CHANNEL Channels[NUM_CHANNELS] =3D { + // Low priority channel. + { + MTL_CHANNEL_TYPE_LOW, + (MTL_MAILBOX*)(MTL_MAILBOX_BASE), + DOORBELL_LOW + }, + // High priority channel + { + MTL_CHANNEL_TYPE_HIGH, + (MTL_MAILBOX*)(MTL_MAILBOX_BASE + MTL_MAILBOX_HIGH_PRIORITY_OFFSET), + DOORBELL_HIGH + } + }; + +/** Wait until channel is free. + + @param[in] Channel Pointer to a channel. + @param[in] TimeOutInMicroSeconds Time out in micro seconds. + + @retval EFI_SUCCESS Channel is free. + @retval EFI_TIMEOUT Time out error. +**/ +EFI_STATUS +MtlWaitUntilChannelFree ( + IN MTL_CHANNEL *Channel, + IN UINTN TimeOutInMicroSeconds + ) +{ + while (TimeOutInMicroSeconds !=3D 0) { + // If channel is free then we have received the reply. + if (Channel->MailBox->ChannelStatus =3D=3D MTL_CHANNEL_FREE) { + return EFI_SUCCESS; + } + if (TimeOutInMicroSeconds < MTL_POLL_WAIT_TIME) { + gBS->Stall (TimeOutInMicroSeconds); + break; + } + // Wait for some arbitrary time. + gBS->Stall (MTL_POLL_WAIT_TIME); + TimeOutInMicroSeconds -=3D MTL_POLL_WAIT_TIME; + } + + // No response from SCP. + if (Channel->MailBox->ChannelStatus !=3D MTL_CHANNEL_FREE) { + ASSERT (FALSE); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/** Return the address of the message payload. + + @param[in] Channel Pointer to a channel. + + @retval UINT32* Pointer to the payload. +**/ +UINT32* +MtlGetChannelPayload ( + IN MTL_CHANNEL *Channel + ) +{ + return Channel->MailBox->Payload; +} + +/** Return pointer to a channel for the requested channel type. + + @param[in] ChannelType ChannelType, Low or High priority channel. + MTL_CHANNEL_TYPE_LOW or + MTL_CHANNEL_TYPE_HIGH + + @param[out] Channel Holds pointer to the channel. + + @retval EFI_SUCCESS Pointer to channel is returned. + @retval EFI_UNSUPPORTED Requested channel type not supported. +**/ +EFI_STATUS +MtlGetChannel ( + IN MTL_CHANNEL_TYPE ChannelType, + OUT MTL_CHANNEL **Channel + ) +{ + if (ChannelType !=3D MTL_CHANNEL_TYPE_LOW + && ChannelType !=3D MTL_CHANNEL_TYPE_HIGH) { + return EFI_UNSUPPORTED; + } + + *Channel =3D (MTL_CHANNEL*)&Channels[ChannelType]; + + return EFI_SUCCESS; +} + +/** Mark the channel busy and ring the doorbell. + + @param[in] Channel Pointer to a channel. + @param[in] MessageHeader Message header. + + @param[out] PayloadLength Message length. + + @retval EFI_SUCCESS Message sent successfully. + @retval EFI_DEVICE_ERROR Channel is busy. +**/ +EFI_STATUS +MtlSendMessage ( + IN MTL_CHANNEL *Channel, + IN UINT32 MessageHeader, + OUT UINT32 PayloadLength + ) +{ + MTL_MAILBOX *MailBox =3D Channel->MailBox; + + if (Channel->MailBox->ChannelStatus !=3D MTL_CHANNEL_FREE) { + return EFI_DEVICE_ERROR; + } + + // Mark the channel busy before ringing doorbell. + Channel->MailBox->ChannelStatus =3D MTL_CHANNEL_BUSY; + ArmDataSynchronizationBarrier (); + + MailBox->Flags =3D MTL_POLL; + MailBox->MessageHeader =3D MessageHeader; + + // Add length of message header. + MailBox->Length =3D PayloadLength + sizeof (MessageHeader); + + // Ring the doorbell. It sets SET bit of the MHU register. + MmioWrite32 ( + Channel->DoorBell.PhysicalAddress, + Channel->DoorBell.ModifyMask + ); + + return EFI_SUCCESS; +} + +/** Wait for a response on a channel. + + If channel is free after sending message, it implies SCP responded + with a response on the channel. + + @param[in] Channel Pointer to a channel. + + @retval EFI_SUCCESS Message received successfully. + @retval EFI_TIMEOUT Time out error. +**/ +EFI_STATUS +MtlReceiveMessage ( + IN MTL_CHANNEL *Channel, + OUT UINT32 *MessageHeader, + OUT UINT32 *PayloadLength + ) +{ + EFI_STATUS Status; + + MTL_MAILBOX *MailBox =3D Channel->MailBox; + + Status =3D MtlWaitUntilChannelFree (Channel, RESPONSE_TIMEOUT); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageHeader =3D MailBox->MessageHeader; + + // Deduct message header length. + *PayloadLength =3D MailBox->Length - sizeof (*MessageHeader); + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.inf b= /Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..4b46c8071db1dbb5c740576c754= 61f65216c7a95 --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.inf @@ -0,0 +1,39 @@ +#/** @file +# Copyright (c) 2017-2018, Arm Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmJunoMtlLib + FILE_GUID =3D 21FB2D8F-C6C8-4B2C-A616-A30CB2FBA277 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmMtlLib + +[Sources.common] + ArmJunoMtlLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/JunoPkg/ArmJuno.dec + +[LibraryClasses] + ArmLib + DebugLib + IoLib + UefiBootServicesTableLib + +[FixedPcd.common] + gArmJunoTokenSpaceGuid.PcdArmMtlDoorBell + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxBase + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxSize diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlPrivateLi= b.h b/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlPrivateLib.h new file mode 100644 index 0000000000000000000000000000000000000000..b2bac5e513e93b412307bff2429= 8bbecc083d30c --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlPrivateLib.h @@ -0,0 +1,94 @@ +/** @file + + Copyright (c) 2017-2018, Arm Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf + + Juno ARM Development Platform SoC + https://www.arm.com/files/pdf/ + DDI0515D1a_juno_arm_development_platform_soc_trm.pdf +**/ + +#ifndef ARM_JUNO_MTL_PRIVATE_LIB_H_ +#define ARM_JUNO_MTL_PRIVATE_LIB_H_ + +// Mailbox transport layer. +#define MTL_DOORBELL_MODIFY_MASK (0x00000001U) +#define MTL_DOORBELL_PRESERVE_MASK (~MTL_DOORBELL_MODIFY_MASK) + +#define MTL_DOORBELL_BASE (FixedPcdGet64 (PcdArmMtlDoorBell)) +#define MTL_MAILBOX_BASE (FixedPcdGet64 (PcdArmMtlMailBoxBase)) +#define MTL_MAILBOX_SIZE (FixedPcdGet32 (PcdArmMtlMailBoxSize)) + +#define MTL_POLL 0 +#define MTL_INTR 1 + +/* For Juno, the mailbox for high priority is non-trusted SRAM + 256. + + NOTE: Below is not documented anywhere (yet) + + The payload sizes are 128 bytes. + + There are two channels: + + Channel 0 + - Agent (OS) to Platform (SCP) memory base: non-trusted SRAM + 0 + - Platform (SCP) to Agent (OS) memory base: non-trusted SRAM + 128 + - Doorbell (both directions): MHU, bit 0 + + Channel 1 + - Agent (OS) to Platform (SCP) memory base: non-trusted SRAM + 256 + - Platform (SCP) to Agent (OS) memory base: non-trusted SRAM + 384 + - Doorbell (both directions): MHU, bit 0 +*/ +#define MTL_MAILBOX_HIGH_PRIORITY_OFFSET (MTL_MAILBOX_SIZE * 2) + +// ARM MHU interrupt registers. +#define CPU_INTR_L_SET 0x108 +#define CPU_INTR_H_SET 0x128 + +// MTL uses MHU interrupt registers for communication with the SCP. +#define MTL_DOORBELL_REGISTER_LOW (MTL_DOORBELL_BASE + CPU_INTR_L_SET) +#define MTL_DOORBELL_REGISTER_HIGH (MTL_DOORBELL_BASE + CPU_INTR_H_SET) + +#define MTL_CHANNEL_BUSY 0 +#define MTL_CHANNEL_FREE 1 + +// Response time out value on a MHU channel 20ms. +#define RESPONSE_TIMEOUT 20000 + +/* As per SCMI spec. as a agent UEFI(or OS) can access only two channels + (low or high priority) secure channel is only accessible + to ARM Trusted firmware. */ +#define NUM_CHANNELS 2 + +/* Each channel must use a doorbell register to interrupt the SCP firmware. + on Juno these are MHU interrupt registers for low and high priority + channels. */ +#define DOORBELL_LOW { \ + MTL_DOORBELL_REGISTER_LOW, \ + MTL_DOORBELL_MODIFY_MASK, \ + MTL_DOORBELL_PRESERVE_MASK \ + } + +#define DOORBELL_HIGH { \ + MTL_DOORBELL_REGISTER_HIGH, \ + MTL_DOORBELL_MODIFY_MASK, \ + MTL_DOORBELL_PRESERVE_MASK \ + } + +// Arbitarary poll time. +#define MTL_POLL_WAIT_TIME 100 + +#endif /* ARM_JUNO_MTL_PRIVATE_LIB_H_ */ + --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:20:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522951737205660.0526248447147; Thu, 5 Apr 2018 11:08:57 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A3D8D226FAA62; Thu, 5 Apr 2018 11:08:16 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 974B6226C7C3E for ; Thu, 5 Apr 2018 11:08:13 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w35I88qt027787; Thu, 5 Apr 2018 19:08:11 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org From: Girish Pathak To: edk2-devel@lists.01.org Date: Thu, 5 Apr 2018 19:08:03 +0100 Message-Id: <20180405180803.33684-18-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180405180803.33684-1-girish.pathak@arm.com> References: <20180405180803.33684-1-girish.pathak@arm.com> Subject: [edk2] [PATCH edk2-platforms v4 17/17] ARM/JunoPkg: Add HDLCD platform library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Stephanie.Hughes-Fitt@arm.com, Arvind.Chauhan@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This change adds the HDLCD platform lib for the Juno plaform. This library will be instantiated as a LcdPlatformLib to link with LcdGraphicsOutputDxe for the Juno platform. HDLCD platform library depends on the Arm SCMI DXE driver for communication with the SCP for clock setting. Therefore this change also enables building of Arm SCMI DXE driver for the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- Notes: v3: - Wouldn't it make more sense to add a macro ENABLE_HDLCD, rather than inverting the logic? [Ard] =20 We used this to correspond with the ACPI (FADT) terminology, where HEADLESS implies more than just no display. Refer below email [Evan] https://lists.01.org/pipermail/edk2-devel/ 2018-January/019925.html =20 - SRAM mapping: Couldn't you map it as non-cacheable memory instead [Ard] =20 Done [Girish] =20 - Please fix weird indentation [Ard] =20 Done [Girish] =20 - Please don't use CPP conditionals for control flow [Ard] =20 Done [Girish] Platform/ARM/JunoPkg/ArmJuno.dec | 8 + Platform/ARM/JunoPkg/ArmJuno.dsc | 26 + Platform/ARM/JunoPkg/ArmJuno.fdf | 12 +- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf | 5 +- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c | 21 +- Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c | 555 +++= +++++++++++++++++ Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf | 41 ++ 7 files changed, 665 insertions(+), 3 deletions(-) diff --git a/Platform/ARM/JunoPkg/ArmJuno.dec b/Platform/ARM/JunoPkg/ArmJun= o.dec index fdb56fccb2b259301fd787016a9c4de7ab3c356d..edbbb827ad45cf9e33adede0066= 28432aa41c77b 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dec +++ b/Platform/ARM/JunoPkg/ArmJuno.dec @@ -53,3 +53,11 @@ [PcdsFixedAtBuild.common] gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxBase|0x2E000000|UINT64|0x00000025 gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxSize|0x80|UINT32|0x00000026 =20 + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # + # Default value zero allows platform to enumerate maximum supported mode. + # + # For a list of mode numbers look in HdLcdArmJuno.c + gArmJunoTokenSpaceGuid.PcdArmHdLcdMaxMode|0|UINT32|0x00000017 + diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJun= o.dsc index 851dc0f04ad693e4a88cee070b205f0234687d81..d5e87f1edfd5d60a543e51cb42d= fbcc4489d3f7d 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dsc +++ b/Platform/ARM/JunoPkg/ArmJuno.dsc @@ -50,6 +50,11 @@ [LibraryClasses.common] # SCMI Mailbox Transport Layer ArmMtlLib|Platform/ARM/JunoPkg/Library/ArmJunoMtlLib/ArmJunoMtlLib.inf =20 +!ifndef HEADLESS_PLATFORM + LcdPlatformLib|Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno= Lib.inf + LcdHwLib|ArmPlatformPkg/Library/HdLcd/HdLcd.inf +!endif + [LibraryClasses.common.SEC] PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf @@ -100,7 +105,15 @@ [PcdsFixedAtBuild.common] =20 # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit addr= ess space) gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + +!ifdef HEADLESS_PLATFORM gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 +!else + # Default framebuffer size is 0x7E9000, reduce system memory size for fr= amebuffer. + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7E817000 + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0xFE817000 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|TRUE +!endif =20 # Juno Dual-Cluster profile gArmPlatformTokenSpaceGuid.PcdCoreCount|6 @@ -142,6 +155,11 @@ [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000 =20 +!ifndef HEADLESS_PLATFORM + # ARM Juno HDLCD Base + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x7FF60000 +!endif + # # PLDA PCI Root Complex # @@ -315,6 +333,11 @@ [Components.common] MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf =20 +!ifndef HEADLESS_PLATFORM + # Graphic Output Protocol + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif + # # Juno platform driver # @@ -348,6 +371,9 @@ [Components.common] BdsLib|Platform/ARM/Library/BdsLib/BdsLib.inf } =20 + # SCMI Driver + ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf + [Components.AARCH64] # # EBC diff --git a/Platform/ARM/JunoPkg/ArmJuno.fdf b/Platform/ARM/JunoPkg/ArmJun= o.fdf index ee9d0e7f4f6e6ac99ded6a14e88eb2c7854dd473..c538a9b754995bbc1c4657ecef2= eefdcdd907da5 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.fdf +++ b/Platform/ARM/JunoPkg/ArmJuno.fdf @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -163,6 +163,13 @@ [FV.FvMain] INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceDxe.inf =20 +!ifndef HEADLESS_PLATFORM + # + # Graphics Output Protocol + # + INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif + # # PCI Support # @@ -223,6 +230,9 @@ [FV.FvMain] # after the device drivers (eg: Ethernet) to ensure we have support for = them. INF Platform/ARM/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf =20 + # SCMI Driver + INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf + !if $(ARCH) =3D=3D AARCH64 # # EBC diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf b/Platf= orm/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf index d3fc9b6cc7fbed8bd9591a4a57f52e966b99534a..90628e04b27ad4546d9150309d7= 82b91ff40b068 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2016, ARM Limited. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -54,6 +54,9 @@ [FixedPcd] gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize =20 + # Framebuffer Memory + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 # # PL011 Serial Debug UART diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c b/Platfor= m/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c index 2cac815e96104e74c9ceae2c4140bcab535432a8..2403f51fa94b16bacb921a9695a= 40e1b5068c7cf 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c @@ -21,8 +21,10 @@ =20 #include =20 +#define FRAME_BUFFER_DESCRIPTOR ((FixedPcdGet32 (PcdArmLcdDdrFrameBufferBa= se) !=3D 0) ? 1 : 0) + // The total number of descriptors, including the final "end-of-table" des= criptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (16 + FRAME_BUFFER_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK @@ -149,6 +151,23 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D ARM_JUNO_SOC_PERIPHERALS_S= Z; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + // Framebuffer Memory + if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferBase) !=3D 0) { + ASSERT ((PcdGet64 (PcdSystemMemoryBase) + + PcdGet64 (PcdSystemMemorySize) - 1) < + FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase)); + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmLcd= DdrFrameBufferBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmLcd= DdrFrameBufferBase); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmLcd= DdrFrameBufferSize); + // Map as Normal Non-Cacheable memory, so that we can use the accelera= ted + // SetMem/CopyMem routines that may use unaligned accesses or + // DC ZVA instructions. If mapped as device memory, these routine may = cause + // alignment faults. + // NOTE: The attribute value is misleading, it indicates memory map ty= pe as + // an un-cached, un-buffered but allows buffering and reordering. + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_UNCACHED_UNBUFFERED; + } + // DDR - 2GB VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); diff --git a/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c b/= Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c new file mode 100644 index 0000000000000000000000000000000000000000..3e43ad6b7613853855168ea74ad= 1abcad3dbc60e --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c @@ -0,0 +1,555 @@ +/** @file + + Copyright (c) 2013-2018, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Display timings on Juno for 1920x1080. + On Juno due to instability of the PLLs, we set OSC + frequency to 138.5MHz which is stable for most monitors. + Frequency 148.5MHz does not work with some monitors. + 148.5MHz is set by SCP firmware by default. + +#define JUNO_HD_OSC_FREQUENCY 148500000 +*/ +#define JUNO_HD_OSC_FREQUENCY 138500000 +#define JUNO_HD_H_SYNC ( 32 - 1) +#define JUNO_HD_H_FRONT_PORCH ( 48 - 1) +#define JUNO_HD_H_BACK_PORCH ( 80 - 1) +#define JUNO_HD_V_SYNC ( 5 - 1) +#define JUNO_HD_V_FRONT_PORCH ( 3 - 1) +#define JUNO_HD_V_BACK_PORCH ( 23 - 1) + +/* SCMI defined clock device name and ID. This is not documented but + obtained using clock management protocol's CLOCK_ATTRIBUTES command. + + Generally we must discover clock device ID using clock name and then + set/get rate using CLOCK_RATE_SET/CLOCK_RATE_GET commands. However + because LcdGraphicsOutputDxe is a DXE driver, which gets initialized + at boot time, for faster boot, in release build we will directly use + this already known value as an argument to rate get/set functions. + + We expect these values not to change in future SCP firmware releases. + + DEBUG build however will probe SCP firmware and discover clock device + ID for HDLCD. +*/ +#define ARM_JUNO_CSS_CLK_NAME_HDLCD_0 "HDLCD_0" +#define ARM_JUNO_CSS_CLKID_HDLCD_0 3 + +typedef struct { + UINT32 OscFreq; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; + +STATIC DISPLAY_MODE mDisplayModes[] =3D { + { + // VGA : 640 x 480 x 24 bpp. + VGA_OSC_FREQUENCY, + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} + }, + { + // WVGA : 800 x 480 x 24 bpp. + WVGA_OSC_FREQUENCY, + {WVGA_H_RES_PIXELS, WVGA_H_SYNC, WVGA_H_BACK_PORCH, WVGA_H_FRONT_PORCH= }, + {WVGA_V_RES_PIXELS, WVGA_V_SYNC, WVGA_V_BACK_PORCH, WVGA_V_FRONT_PORCH} + }, + { + // SVGA : 800 x 600 x 24 bpp. + SVGA_OSC_FREQUENCY, + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} + }, + { + // QHD : 960 x 540 x 24 bpp. + QHD_OSC_FREQUENCY, + {QHD_H_RES_PIXELS, QHD_H_SYNC, QHD_H_BACK_PORCH, QHD_H_FRONT_PORCH}, + {QHD_V_RES_PIXELS, QHD_V_SYNC, QHD_V_BACK_PORCH, QHD_V_FRONT_PORCH} + }, + { + // WSVGA : 1024 x 600 x 24 bpp. + WSVGA_OSC_FREQUENCY, + {WSVGA_H_RES_PIXELS, WSVGA_H_SYNC, WSVGA_H_BACK_PORCH, WSVGA_H_FRONT_P= ORCH}, + {WSVGA_V_RES_PIXELS, WSVGA_V_SYNC, WSVGA_V_BACK_PORCH, WSVGA_V_FRONT_P= ORCH} + }, + { + // XGA : 1024 x 768 x 24 bpp. + XGA_OSC_FREQUENCY, + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} + }, + { + // HD : 1280 x 720 x 24 bpp. + HD720_OSC_FREQUENCY, + {HD720_H_RES_PIXELS, HD720_H_SYNC, HD720_H_BACK_PORCH, HD720_H_FRONT_P= ORCH}, + {HD720_V_RES_PIXELS, HD720_V_SYNC, HD720_V_BACK_PORCH, HD720_V_FRONT_P= ORCH} + }, + { + // WXGA : 1280 x 800 x 24 bpp. + WXGA_OSC_FREQUENCY, + {WXGA_H_RES_PIXELS, WXGA_H_SYNC, WXGA_H_BACK_PORCH, WXGA_H_FRONT_PORCH= }, + {WXGA_V_RES_PIXELS, WXGA_V_SYNC, WXGA_V_BACK_PORCH, WXGA_V_FRONT_PORCH} + }, + { + // SXGA : 1280 x 1024 x 24 bpp. + SXGA_OSC_FREQUENCY, + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} + }, + { + // WSXGA+ : 1680 x 1050 x 24 bpp. + WSXGA_OSC_FREQUENCY, + {WSXGA_H_RES_PIXELS, WSXGA_H_SYNC, WSXGA_H_BACK_PORCH, WSXGA_H_FRONT_P= ORCH}, + {WSXGA_V_RES_PIXELS, WSXGA_V_SYNC, WSXGA_V_BACK_PORCH, WSXGA_V_FRONT_P= ORCH} + }, + { + // HD : 1920 x 1080 x 24 bpp. + JUNO_HD_OSC_FREQUENCY, + {HD_H_RES_PIXELS, JUNO_HD_H_SYNC, JUNO_HD_H_BACK_PORCH, JUNO_HD_H_FRON= T_PORCH}, + {HD_V_RES_PIXELS, JUNO_HD_V_SYNC, JUNO_HD_V_BACK_PORCH, JUNO_HD_V_FRON= T_PORCH} + } +}; + +/* If PcdArmMaliDpMaxMode is 0, platform supports full range of modes + else platform supports modes from 0 to PcdArmHdLcdMaxMode - 1 +*/ +STATIC CONST UINT32 mMaxMode =3D ((FixedPcdGet32 (PcdArmHdLcdMaxMode) !=3D= 0) + ? FixedPcdGet32 (PcdArmHdLcdMaxMode) + : sizeof (mDisplayModes) / sizeof (DISP= LAY_MODE)); + +/** HDLCD platform specific initialization function. + + @param[in] Handle Handle to the LCD device instance. + + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ) +{ + (VOID)Handle; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + // PixelBitMask and PixelBltOnly pixel formats are not supported. + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor && + PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor || + PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** Allocate VRAM memory in DRAM for the framebuffer + (unless it is reserved already). + + The allocated address can be used to set the framebuffer. + + @param[out] VramBaseAddress A pointer to the framebuffer address. + @param[out] VramSize A pointer to the size of the framebuffer + in bytes + + @retval EFI_SUCCESS Framebuffer memory allocated successfull= y. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS * VramBaseAddress, + OUT UINTN * VramSize + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + EFI_CPU_ARCH_PROTOCOL *Cpu; + + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + + // Set the VRAM size. + *VramSize =3D (UINTN)FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize); + + // Check if memory is already reserved for the framebuffer. + *VramBaseAddress =3D + (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase); + + if (*VramBaseAddress =3D=3D 0) { + // If not already reserved, attempt to allocate the VRAM from the DRAM. + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (*VramSize), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "HdLcdArmJuno: Failed to allocate frame buffer.= \n")); + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Ensure the Cpu architectural protocol is already installed + Status =3D gBS->LocateProtocol ( + &gEfiCpuArchProtocolGuid, + NULL, + (VOID **)&Cpu + ); + if (!EFI_ERROR (Status)) { + // The VRAM is inside the DRAM, which is cacheable. + // Mark the VRAM as write-combining (uncached) and non-executable. + Status =3D Cpu->SetMemoryAttributes ( + Cpu, + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC | EFI_MEMORY_XP + ); + } + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + } + } + + return Status; +} + +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ +UINT32 +LcdPlatformGetMaxMode (VOID) +{ + return mMaxMode; +} + +#if !defined(MDEPKG_NDEBUG) +/** Probe Clock device ID of the HDLCD clock and current pixel clock frequ= ency. + NOTE: We will probe information only in DEBUG build. + + @param[in] ClockProtocol A pointer to SCMI clock protocol + interface instance. + @param[out] ClockId ID of the clock device + + @retval EFI_SUCCESS Clock ID of the HDLCD device returned + successfully. + @retval EFI_UNSUPPORTED SCMI clock management protocol unsupported. + @retval EFI_DEVICE_ERROR SCMI error. + @retval EFI_NOT_FOUND Not found valid clock device ID of the HDLCD. +**/ +STATIC +EFI_STATUS +ProbeHdLcdClock ( + IN SCMI_CLOCK_PROTOCOL * ClockProtocol, + OUT UINT32 * ClockId + ) +{ + EFI_STATUS Status; + UINT64 CurrentHdLcdFreq; + + UINT32 TotalClocks; + UINT32 ClockProtocolVersion; + BOOLEAN Enabled; + CHAR8 ClockName[SCMI_MAX_STR_LEN]; + BOOLEAN ClockFound =3D FALSE; + + UINT32 TotalRates =3D 0; + UINT32 ClockRateSize; + SCMI_CLOCK_RATE ClockRate; + SCMI_CLOCK_RATE_FORMAT ClockRateFormat; + + Status =3D ClockProtocol->GetVersion (ClockProtocol, &ClockProtocolVersi= on); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DEBUG ((DEBUG_ERROR, "SCMI clock management protocol version =3D %x\n", + ClockProtocolVersion)); + + if (ClockProtocolVersion !=3D SCMI_CLOCK_PROTOCOL_VERSION) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status =3D ClockProtocol->GetTotalClocks (ClockProtocol, &TotalClocks); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_ERROR, "Total number of clocks supported by SCMI clock man= agement protocol =3D %d\n", + TotalClocks)); + + for (*ClockId =3D 0; *ClockId < TotalClocks; (*ClockId)++) { + Status =3D ClockProtocol->GetClockAttributes ( + ClockProtocol, + *ClockId, + &Enabled, + ClockName + ); + if (EFI_ERROR (Status)) { + // In current implementation of SCMI, some clocks are not accessible= to + // calling agents (in our case UEFI is an agent) which results in an + // EFI_DEVICE_ERROR error. A bug fix for this is in discussions and = will + // be fixed in future versions of the SCP firmware. Irrespective of = a fix + // we must iterate over each clock to see if it matches with HDLCD. + continue; + } + + if (AsciiStrnCmp ((CONST CHAR8*)ClockName, + (CONST CHAR8*)ARM_JUNO_CSS_CLK_NAME_HDLCD_0, + sizeof (ARM_JUNO_CSS_CLK_NAME_HDLCD_0)) =3D=3D 0) { + ClockFound =3D TRUE; + break; + } + } + + if (!ClockFound) { + return EFI_NOT_FOUND; + } + + ClockRateSize =3D sizeof (ClockRate); + Status =3D ClockProtocol->DescribeRates ( + ClockProtocol, + *ClockId, + &ClockRateFormat, + &TotalRates, + &ClockRateSize, + &ClockRate + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status =3D ClockProtocol->RateGet (ClockProtocol, *ClockId, &CurrentHdLc= dFreq); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DEBUG ((DEBUG_ERROR, "Clock ID =3D %d Clock name =3D %a\n", *ClockId, Cl= ockName)); + DEBUG ((DEBUG_ERROR, "Minimum frequency =3D %uHz\n", ClockRate.Min)); + DEBUG ((DEBUG_ERROR, "Maximum frequency =3D %uHz\n", ClockRate.Max)); + DEBUG ((DEBUG_ERROR, "Clock rate step =3D %uHz\n", ClockRate.Step)); + + DEBUG ((DEBUG_ERROR, "HDLCD Current frequency =3D %uHz\n", CurrentHdLcdF= req)); + + return EFI_SUCCESS; +} +#endif + +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_NOT_FOUND Clock protocol instance not found. + @retval EFI_DEVICE_ERROR SCMI error. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval !(EFI_SUCCESS) Other errors. +*/ +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + SCMI_CLOCK_PROTOCOL *ClockProtocol; + UINT32 ClockId; + + EFI_GUID ClockProtocolGuid =3D ARM_SCMI_CLOCK_PROTOCOL_GUID; + + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + // Display debug information in boot log. + DEBUG ((DEBUG_ERROR, "HDLCD Display controller:\n")); + + DEBUG ((DEBUG_ERROR, "Required frequency for resolution %dx%d =3D %uHz\n= ", + mDisplayModes[ModeNumber].Horizontal.Resolution, + mDisplayModes[ModeNumber].Vertical.Resolution, + mDisplayModes[ModeNumber].OscFreq)); + + Status =3D gBS->LocateProtocol ( + &ClockProtocolGuid, + NULL, + (VOID**)&ClockProtocol + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + +#if !defined(MDEPKG_NDEBUG) + /* Avoid probing clock device ID in RELEASE build */ + Status =3D ProbeHdLcdClock (ClockProtocol, &ClockId); + if (EFI_ERROR (Status)) { + return Status; + } + + ASSERT (ClockId =3D=3D ARM_JUNO_CSS_CLKID_HDLCD_0); +#else + ClockId =3D ARM_JUNO_CSS_CLKID_HDLCD_0; +#endif + + // Set HDLCD clock required for the requested mode + Status =3D ClockProtocol->RateSet ( + ClockProtocol, + ClockId, + mDisplayModes[ModeNumber].OscFreq + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SCMI error: %r\n", Status)); + return Status; + } + +#if !defined(MDEPKG_NDEBUG) + UINT64 CurrentHdLcdFreq; + // Actual value set can differ from requested frequency so verify. + Status =3D ClockProtocol->RateGet ( + ClockProtocol, + ARM_JUNO_CSS_CLKID_HDLCD_0, + &CurrentHdLcdFreq + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SCMI Error: %r\n", Status)); + } else { + DEBUG ((DEBUG_ERROR, "Requested frequency change =3D %uHz, Actual chan= ged frequency =3D %uHz\n", + mDisplayModes[ModeNumber].OscFreq, + CurrentHdLcdFreq + )); + } +#endif + + return Status; +} + +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * Info + ) +{ + if (ModeNumber >=3D mMaxMode ){ + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Info !=3D NULL); + + Info->Version =3D 0; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; + + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + + return EFI_SUCCESS; +} + +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT SCAN_TIMINGS ** Horizontal, + OUT SCAN_TIMINGS ** Vertical + ) +{ + if (ModeNumber >=3D mMaxMode ){ + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; + + return EFI_SUCCESS; +} + +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to bits per pixel information. + + @retval EFI_SUCCESS Bits per pixel information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP * Bpp + ) +{ + if (ModeNumber >=3D mMaxMode) { + // Check valid ModeNumber and Bpp. + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Bpp !=3D NULL); + + *Bpp =3D LCD_BITS_PER_PIXEL_24; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.i= nf b/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..5590d95e2db15b2dea883d25572= ae73efcf8f10b --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Component description file for HdLcdArmJunoLib module +# +# Copyright (c) 2013-2018, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D HdLcdArmJunoLib + FILE_GUID =3D 7B1D26F7-7B88-47ED-B193-DD3BDF319006 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + HdLcdArmJuno.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/JunoPkg/ArmJuno.dec + +[LibraryClasses] + BaseLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize + gArmJunoTokenSpaceGuid.PcdArmHdLcdMaxMode + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel