From nobody Mon Apr 29 03:49:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1522252539313539.7491946159205; Wed, 28 Mar 2018 08:55:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ED2B421F85E8A; Wed, 28 Mar 2018 08:48:57 -0700 (PDT) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EDA4A22106DEC for ; Wed, 28 Mar 2018 08:48:55 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id p9so5839220wmc.3 for ; Wed, 28 Mar 2018 08:55:34 -0700 (PDT) Received: from localhost.localdomain ([84.203.68.191]) by smtp.gmail.com with ESMTPSA id h33sm2995268edh.1.2018.03.28.08.55.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Mar 2018 08:55:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uBl+p5CaY2ITfuvw8PdLUTIxLqDH/ydE+sT4OwKsYbQ=; b=D54omEixdvMQqtNKAogLZCIe7hLTBuiNQUFfSBJIz1h4B/Sq/Oh0DYPQANMkAK1rMq eCzY6sLmtHROjwiXcPrsIOFpwRnZR4KuOrqDqjabp/2nlPNmOrRSZR5wx6juMv528DR0 vVRqRxNBdallPBK7aLSHOH+nM44xYEPBqCC3CgX9jMt414HwUJ7HKIt21jjcM8UxxHmE etLbCrAFk+qe/JleJGT59pEDYGzVi/yEUt5cRz7WUA1VR8WlyaMmMQVhV5lNr42UpEFd 5iMfhdI1Os2c2ZL3XhkcZw+KAw4BALACvcG0zq7jV1qSvsxGo9jcUpRQYk6rKo1OchRq BIGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uBl+p5CaY2ITfuvw8PdLUTIxLqDH/ydE+sT4OwKsYbQ=; b=QD/4f+LaOyt0/J6s5//+750Piw/LwlD0QWN5HwMZX7tm6MGZ7089LTffNPPQSggX3c 04FAno9YXmy8Ir0yOy0wwl+3ZTEtW0PO2nsqSRzS/XVU9nvlRY7+ioCAq+9vIhpGyYYh 0r7QKimWGIwF1Mu1TEm9sh1RwkhVtODarczBEV5xC5gvlQv2M5xLkhY3+uDhcQ1M2jpe 9u2qFa3wecLZiE9dT1b5W2gU/Z9+WQjv031lloZDinSW51RpcM+4eMrxdxTQ4pT8Fc2S M5bSmgbxE9K5reADfaarE14Q1w0RTmQP/OLaM22b2DpuZnXMZTNWRa3nF7PpXj0az8h4 /X3Q== X-Gm-Message-State: AElRT7E89+32t44BJnFPuM2SPyCr4TMc7QDWpFG3DfmTEbqxxfuoNPFa DmgffA+rX4TiAoetBQNMJLD9Rvo5KMliEw== X-Google-Smtp-Source: AIpwx49WYvwKLIQtebekKzIYSC2sOorZZcheLYvyWiDwU3l8CkRnVnUxUNyDIAzHYw0k8ootqTDxcg== X-Received: by 10.80.177.81 with SMTP id l17mr3949260edd.65.1522252533002; Wed, 28 Mar 2018 08:55:33 -0700 (PDT) From: Pete Batard To: edk2-devel@lists.01.org Date: Wed, 28 Mar 2018 16:55:20 +0100 Message-Id: <20180328155521.7312-2-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180328155521.7312-1-pete@akeo.ie> References: <20180328155521.7312-1-pete@akeo.ie> Subject: [edk2] [PATCH 1/2] MdePkg/Library/BaseSynchronizationLib: Enable VS2017/ARM64 builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.asm | 205 ++= ++++++++++++++++++ MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 3 +- 2 files changed, 207 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.= asm b/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.asm new file mode 100644 index 000000000000..0b13b2662120 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.asm @@ -0,0 +1,205 @@ +; Implementation of synchronization functions for ARM architecture (AArch= 64) +; +; Copyright (c) 2012-2015, ARM Limited. All rights reserved. +; Copyright (c) 2015, Linaro Limited. All rights reserved. +; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the B= SD License +; which accompanies this distribution. The full text of the license may = be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +; +; + + EXPORT InternalSyncCompareExchange16 + EXPORT InternalSyncCompareExchange32 + EXPORT InternalSyncCompareExchange64 + EXPORT InternalSyncIncrement + EXPORT InternalSyncDecrement + AREA BaseSynchronizationLib_LowLevel, CODE, READONLY + +;/** +; Performs an atomic compare exchange operation on a 16-bit unsigned inte= ger. +; +; Performs an atomic compare exchange operation on the 16-bit unsigned in= teger +; specified by Value. If Value is equal to CompareValue, then Value is s= et to +; ExchangeValue and CompareValue is returned. If Value is not equal to C= ompareValue, +; then Value is returned. The compare exchange operation must be perform= ed using +; MP safe mechanisms. +; +; @param Value A pointer to the 16-bit value for the compare exc= hange +; operation. +; @param CompareValue 16-bit value used in compare operation. +; @param ExchangeValue 16-bit value used in exchange operation. +; +; @return The original *Value before exchange. +; +;**/ +;UINT16 +;EFIAPI +;InternalSyncCompareExchange16 ( +; IN volatile UINT16 *Value, +; IN UINT16 CompareValue, +; IN UINT16 ExchangeValue +; ) +InternalSyncCompareExchange16 + uxth w1, w1 + uxth w2, w2 + dmb sy + +InternalSyncCompareExchange16Again + ldxrh w3, [x0] + cmp w3, w1 + bne InternalSyncCompareExchange16Fail + +InternalSyncCompareExchange16Exchange + stxrh w4, w2, [x0] + cbnz w4, InternalSyncCompareExchange16Again + +InternalSyncCompareExchange16Fail + dmb sy + mov w0, w3 + ret + +;/** +; Performs an atomic compare exchange operation on a 32-bit unsigned inte= ger. +; +; Performs an atomic compare exchange operation on the 32-bit unsigned in= teger +; specified by Value. If Value is equal to CompareValue, then Value is s= et to +; ExchangeValue and CompareValue is returned. If Value is not equal to C= ompareValue, +; then Value is returned. The compare exchange operation must be perform= ed using +; MP safe mechanisms. +; +; @param Value A pointer to the 32-bit value for the compare exc= hange +; operation. +; @param CompareValue 32-bit value used in compare operation. +; @param ExchangeValue 32-bit value used in exchange operation. +; +; @return The original *Value before exchange. +; +;**/ +;UINT32 +;EFIAPI +;InternalSyncCompareExchange32 ( +; IN volatile UINT32 *Value, +; IN UINT32 CompareValue, +; IN UINT32 ExchangeValue +; ) +InternalSyncCompareExchange32 + dmb sy + +InternalSyncCompareExchange32Again + ldxr w3, [x0] + cmp w3, w1 + bne InternalSyncCompareExchange32Fail + +InternalSyncCompareExchange32Exchange + stxr w4, w2, [x0] + cbnz w4, InternalSyncCompareExchange32Again + +InternalSyncCompareExchange32Fail + dmb sy + mov w0, w3 + ret + +;/** +; Performs an atomic compare exchange operation on a 64-bit unsigned inte= ger. +; +; Performs an atomic compare exchange operation on the 64-bit unsigned in= teger specified +; by Value. If Value is equal to CompareValue, then Value is set to Exch= angeValue and +; CompareValue is returned. If Value is not equal to CompareValue, then = Value is returned. +; The compare exchange operation must be performed using MP safe mechanis= ms. +; +; @param Value A pointer to the 64-bit value for the compare exc= hange +; operation. +; @param CompareValue 64-bit value used in compare operation. +; @param ExchangeValue 64-bit value used in exchange operation. +; +; @return The original *Value before exchange. +; +;**/ +;UINT64 +;EFIAPI +;InternalSyncCompareExchange64 ( +; IN volatile UINT64 *Value, +; IN UINT64 CompareValue, +; IN UINT64 ExchangeValue +; ) +InternalSyncCompareExchange64 + dmb sy + +InternalSyncCompareExchange64Again + ldxr x3, [x0] + cmp x3, x1 + bne InternalSyncCompareExchange64Fail + +InternalSyncCompareExchange64Exchange + stxr w4, x2, [x0] + cbnz w4, InternalSyncCompareExchange64Again + +InternalSyncCompareExchange64Fail + dmb sy + mov x0, x3 + ret + +;/** +; Performs an atomic increment of an 32-bit unsigned integer. +; +; Performs an atomic increment of the 32-bit unsigned integer specified by +; Value and returns the incremented value. The increment operation must be +; performed using MP safe mechanisms. The state of the return value is not +; guaranteed to be MP safe. +; +; @param Value A pointer to the 32-bit value to increment. +; +; @return The incremented value. +; +;**/ +;UINT32 +;EFIAPI +;InternalSyncIncrement ( +; IN volatile UINT32 *Value +; ) +InternalSyncIncrement + dmb sy +TryInternalSyncIncrement + ldxr w1, [x0] + add w1, w1, #1 + stxr w2, w1, [x0] + cbnz w2, TryInternalSyncIncrement + mov w0, w1 + dmb sy + ret + +;/** +; Performs an atomic decrement of an 32-bit unsigned integer. +; +; Performs an atomic decrement of the 32-bit unsigned integer specified by +; Value and returns the decrement value. The decrement operation must be +; performed using MP safe mechanisms. The state of the return value is not +; guaranteed to be MP safe. +; +; @param Value A pointer to the 32-bit value to decrement. +; +; @return The decrement value. +; +;**/ +;UINT32 +;EFIAPI +;InternalSyncDecrement ( +; IN volatile UINT32 *Value +; ) +InternalSyncDecrement + dmb sy +TryInternalSyncDecrement + ldxr w1, [x0] + sub w1, w1, #1 + stxr w2, w1, [x0] + cbnz w2, TryInternalSyncDecrement + mov w0, w1 + dmb sy + ret + + END diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 265de1341a0f..6fca7dd29360 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -105,7 +105,8 @@ [Sources.ARM] =20 [Sources.AARCH64] Synchronization.c - AArch64/Synchronization.S + AArch64/Synchronization.S | GCC + AArch64/Synchronization.asm | MSFT =20 [Packages] MdePkg/MdePkg.dec --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 03:49:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm | 39 +++++++++++++++++++ MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm | 40 ++++++++++++++++++++ MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 8 ++-- 3 files changed, 84 insertions(+), 3 deletions(-) diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm b/MdePkg/Lib= rary/BaseCpuLib/AArch64/CpuFlushTlb.asm new file mode 100644 index 000000000000..aee9049fba12 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm @@ -0,0 +1,39 @@ +;-------------------------------------------------------------------------= ----- +; +; CpuFlushTlb() for ARM +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT CpuFlushTlb + AREA BaseCpuLib_LowLevel, CODE, READONLY + +;/** +; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. +; +; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. +; +;**/ +;VOID +;EFIAPI +;CpuFlushTlb ( +; VOID +; ); +; +CpuFlushTlb + tlbi vmalle1 // Invalidate Inst TLB and Data TLB + dsb sy + isb + ret + + END diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm b/MdePkg/Librar= y/BaseCpuLib/AArch64/CpuSleep.asm new file mode 100644 index 000000000000..7481c225d745 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm @@ -0,0 +1,40 @@ +;-------------------------------------------------------------------------= ----- +; +; CpuSleep() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT CpuSleep + AREA BaseCpuLib_LowLevel, CODE, READONLY + +;/** +; Places the CPU in a sleep state until an interrupt is received. +; +; Places the CPU in a sleep state until an interrupt is received. If inte= rrupts +; are disabled prior to calling this function, then the CPU will be place= d in a +; sleep state indefinitely. +; +;**/ +;VOID +;EFIAPI +;CpuSleep ( +; VOID +; ); +; + +CpuSleep + wfi + ret + + END diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index 996446ec1a38..dad08dfe7f54 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -1,7 +1,7 @@ ## @file # Instance of CPU Library for various architecture. # -# CPU Library implemented using ASM functions for IA-32 and X64, +# CPU Library implemented using ASM functions for IA32, X64, ARM, AARCH64, # PAL CALLs for IPF, and empty functions for EBC. # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
@@ -71,8 +71,10 @@ [Sources.ARM] Arm/CpuSleep.S | GCC =20 =20 [Sources.AARCH64] - AArch64/CpuFlushTlb.S | GCC - AArch64/CpuSleep.S | GCC + AArch64/CpuFlushTlb.S | GCC + AArch64/CpuSleep.S | GCC + AArch64/CpuFlushTlb.asm | MSFT + AArch64/CpuSleep.asm | MSFT =20 [Packages] MdePkg/MdePkg.dec --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel