From nobody Sun Apr 28 20:03:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1520386627246744.0599054964108; Tue, 6 Mar 2018 17:37:07 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7FD33224C0F32; Tue, 6 Mar 2018 17:30:49 -0800 (PST) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id CF5E82235229E for ; Tue, 6 Mar 2018 17:30:48 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 499961435; Tue, 6 Mar 2018 17:37:03 -0800 (PST) Received: from usa.arm.com (dbox2.austin.arm.com [10.118.34.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0969D3F24A; Tue, 6 Mar 2018 17:37:03 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=daniil.egranov@arm.com; receiver=edk2-devel@lists.01.org From: Daniil Egranov To: edk2-devel@lists.01.org Date: Tue, 6 Mar 2018 19:36:34 -0600 Message-Id: <20180307013637.16462-2-daniil.egranov@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180307013637.16462-1-daniil.egranov@arm.com> References: <20180307013637.16462-1-daniil.egranov@arm.com> Subject: [edk2] [PATCH 1/4] MdeModulePkg: Added new Virtio non-discoverable type and GUID X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Added Virtio type and GUID to the list of supported non-discoverable devices. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov --- MdeModulePkg/Include/Guid/NonDiscoverableDevice.h | 3 +++ MdeModulePkg/Include/Library/NonDiscoverableDeviceRegistrationLib.h | 1 + MdeModulePkg/MdeModulePkg.dec | 1 + 3 files changed, 5 insertions(+) diff --git a/MdeModulePkg/Include/Guid/NonDiscoverableDevice.h b/MdeModuleP= kg/Include/Guid/NonDiscoverableDevice.h index d182e4b9d2..9d598d0487 100644 --- a/MdeModulePkg/Include/Guid/NonDiscoverableDevice.h +++ b/MdeModulePkg/Include/Guid/NonDiscoverableDevice.h @@ -44,6 +44,8 @@ #define EDKII_NON_DISCOVERABLE_XHCI_DEVICE_GUID \ { 0xB1BE0BC5, 0x6C28, 0x442D, {0xAA, 0x37, 0x15, 0x1B, 0x42, 0x57, 0xBD,= 0x78 } } =20 +#define EDKII_NON_DISCOVERABLE_VIRTIO_DEVICE_GUID \ + { 0xA72A1646, 0x1A4D, 0x4A84, {0xB6, 0xAC, 0xEF, 0x18, 0x13, 0x62, 0xC5,= 0x85 } } =20 extern EFI_GUID gEdkiiNonDiscoverableAhciDeviceGuid; extern EFI_GUID gEdkiiNonDiscoverableAmbaDeviceGuid; @@ -54,5 +56,6 @@ extern EFI_GUID gEdkiiNonDiscoverableSdhciDeviceGuid; extern EFI_GUID gEdkiiNonDiscoverableUfsDeviceGuid; extern EFI_GUID gEdkiiNonDiscoverableUhciDeviceGuid; extern EFI_GUID gEdkiiNonDiscoverableXhciDeviceGuid; +extern EFI_GUID gEdkiiNonDiscoverableVirtioDeviceGuid; =20 #endif diff --git a/MdeModulePkg/Include/Library/NonDiscoverableDeviceRegistration= Lib.h b/MdeModulePkg/Include/Library/NonDiscoverableDeviceRegistrationLib.h index c2d9e48353..a3d35af275 100644 --- a/MdeModulePkg/Include/Library/NonDiscoverableDeviceRegistrationLib.h +++ b/MdeModulePkg/Include/Library/NonDiscoverableDeviceRegistrationLib.h @@ -26,6 +26,7 @@ typedef enum { NonDiscoverableDeviceTypeUfs, NonDiscoverableDeviceTypeUhci, NonDiscoverableDeviceTypeXhci, + NonDiscoverableDeviceTypeVirtio, NonDiscoverableDeviceTypeMax, } NON_DISCOVERABLE_DEVICE_TYPE; =20 diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 5d561ff484..cd18bbfbd2 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -396,6 +396,7 @@ gEdkiiNonDiscoverableUfsDeviceGuid =3D { 0x2EA77912, 0x80A8, 0x4947, {0x= BE, 0x69, 0xCD, 0xD0, 0x0A, 0xFB, 0xE5, 0x56 } } gEdkiiNonDiscoverableUhciDeviceGuid =3D { 0xA8CDA0A2, 0x4F37, 0x4A1B, {0= x8E, 0x10, 0x8E, 0xF3, 0xCC, 0x3B, 0xF3, 0xA8 } } gEdkiiNonDiscoverableXhciDeviceGuid =3D { 0xB1BE0BC5, 0x6C28, 0x442D, {0= xAA, 0x37, 0x15, 0x1B, 0x42, 0x57, 0xBD, 0x78 } } + gEdkiiNonDiscoverableVirtioDeviceGuid =3D { 0xA72A1646, 0x1A4D, 0x4A84, = {0xB6, 0xAC, 0xEF, 0x18, 0x13, 0x62, 0xC5, 0x85 } } =20 ## Include/Guid/PlatformHasAcpi.h gEdkiiPlatformHasAcpiGuid =3D { 0xf0966b41, 0xc23f, 0x41b9, { 0x96, 0x04= , 0x0f, 0xf7, 0xe1, 0x11, 0x96, 0x5a } } --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:03:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1520386629293358.08216350356406; Tue, 6 Mar 2018 17:37:09 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E08C1224C0F5B; Tue, 6 Mar 2018 17:30:51 -0800 (PST) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 12BFF2235229E for ; Tue, 6 Mar 2018 17:30:49 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F7DC1596; Tue, 6 Mar 2018 17:37:04 -0800 (PST) Received: from usa.arm.com (dbox2.austin.arm.com [10.118.34.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1EF253F24A; Tue, 6 Mar 2018 17:37:04 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=daniil.egranov@arm.com; receiver=edk2-devel@lists.01.org From: Daniil Egranov To: edk2-devel@lists.01.org Date: Tue, 6 Mar 2018 19:36:35 -0600 Message-Id: <20180307013637.16462-3-daniil.egranov@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180307013637.16462-1-daniil.egranov@arm.com> References: <20180307013637.16462-1-daniil.egranov@arm.com> Subject: [edk2] [PATCH 2/4] NonDiscoverableDeviceRegistrationLib: Added Virtio support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Added Virtio non-discoverable device case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov --- .../NonDiscoverableDeviceRegistrationLib.c | 3= +++ .../NonDiscoverableDeviceRegistrationLib.inf | 1= + 2 files changed, 4 insertions(+) diff --git a/MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonD= iscoverableDeviceRegistrationLib.c b/MdeModulePkg/Library/NonDiscoverableDe= viceRegistrationLib/NonDiscoverableDeviceRegistrationLib.c index 536dfc7297..2cc3da7772 100644 --- a/MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscover= ableDeviceRegistrationLib.c +++ b/MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscover= ableDeviceRegistrationLib.c @@ -67,6 +67,9 @@ GetGuidFromType ( case NonDiscoverableDeviceTypeXhci: return &gEdkiiNonDiscoverableXhciDeviceGuid; =20 + case NonDiscoverableDeviceTypeVirtio: + return &gEdkiiNonDiscoverableVirtioDeviceGuid; + default: return NULL; } diff --git a/MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonD= iscoverableDeviceRegistrationLib.inf b/MdeModulePkg/Library/NonDiscoverable= DeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf index 763f9a0a6f..8ebf869d1d 100644 --- a/MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscover= ableDeviceRegistrationLib.inf +++ b/MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscover= ableDeviceRegistrationLib.inf @@ -46,3 +46,4 @@ gEdkiiNonDiscoverableUfsDeviceGuid ## CONSUMES ## GUID gEdkiiNonDiscoverableUhciDeviceGuid ## CONSUMES ## GUID gEdkiiNonDiscoverableXhciDeviceGuid ## CONSUMES ## GUID + gEdkiiNonDiscoverableVirtioDeviceGuid ## CONSUMES ## GUID --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:03:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1520386632000259.35126103943264; Tue, 6 Mar 2018 17:37:12 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 56E75224E6911; Tue, 6 Mar 2018 17:30:52 -0800 (PST) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id BC75A2235229E for ; Tue, 6 Mar 2018 17:30:50 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5383F1435; Tue, 6 Mar 2018 17:37:05 -0800 (PST) Received: from usa.arm.com (dbox2.austin.arm.com [10.118.34.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 132733F24A; Tue, 6 Mar 2018 17:37:05 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=daniil.egranov@arm.com; receiver=edk2-devel@lists.01.org From: Daniil Egranov To: edk2-devel@lists.01.org Date: Tue, 6 Mar 2018 19:36:36 -0600 Message-Id: <20180307013637.16462-4-daniil.egranov@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180307013637.16462-1-daniil.egranov@arm.com> References: <20180307013637.16462-1-daniil.egranov@arm.com> Subject: [edk2] [PATCH 3/4] NonDiscoverablePciDeviceDxe: Added MMIO Virtio support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Added PCI IO to MMIO translation for Virtio case into the PCI IO=20 protocol functions. Added Virtio device type into the PCI IO protocol initialization procedure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov --- .../NonDiscoverablePciDeviceDxe.c | 3 +- .../NonDiscoverablePciDeviceDxe.inf | 5 +- .../NonDiscoverablePciDeviceIo.c | 240 +++++++++++++++++= +++- 3 files changed, 241 insertions(+), 7 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverab= lePciDeviceDxe.c b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDisc= overablePciDeviceDxe.c index 3e9ff6620d..2c3eeca914 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDe= viceDxe.c +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDe= viceDxe.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (C) 2016, Linaro Ltd. All rights reserved.
+ Copyright (C) 2016-2018, Linaro Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this @@ -32,6 +32,7 @@ SupportedNonDiscoverableDevices[] =3D { &gEdkiiNonDiscoverableUfsDeviceGuid, &gEdkiiNonDiscoverableUhciDeviceGuid, &gEdkiiNonDiscoverableXhciDeviceGuid, + &gEdkiiNonDiscoverableVirtioDeviceGuid }; =20 // diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverab= lePciDeviceDxe.inf b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDi= scoverablePciDeviceDxe.inf index ac551a82ab..a7bf5a5fc1 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDe= viceDxe.inf +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDe= viceDxe.inf @@ -1,7 +1,7 @@ ## @file # PCI I/O driver for non-discoverable devices. # -# Copyright (C) 2016, Linaro Ltd. +# Copyright (C) 2016-2018, Linaro Ltd. # # This program and the accompanying materials are licensed and made availa= ble # under the terms and conditions of the BSD License which accompanies this @@ -30,6 +30,7 @@ [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] BaseMemoryLib @@ -54,3 +55,5 @@ gEdkiiNonDiscoverableUfsDeviceGuid ## CONSUMES ## GUID gEdkiiNonDiscoverableUhciDeviceGuid ## CONSUMES ## GUID gEdkiiNonDiscoverableXhciDeviceGuid ## CONSUMES ## GUID + gEdkiiNonDiscoverableVirtioDeviceGuid ## CONSUMES ## GUID + diff --git a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverab= lePciDeviceIo.c b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDisco= verablePciDeviceIo.c index 0e42ae4bf6..cb99bf0ba6 100644 --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDe= viceIo.c +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDe= viceIo.c @@ -1,7 +1,7 @@ /** @file =20 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+ Copyright (c) 2016-2018, Linaro, Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -17,8 +17,12 @@ =20 #include =20 +#include + #include =20 +#include + #include =20 typedef struct { @@ -374,6 +378,82 @@ PciIoMemWrite ( } =20 /** + Translate PCI IO to MMIO for VirtIo Non-Discoverable devices. + + @param BaseAddress A base MMIO memory address of a VirtIo dev= ice. + @param PciIoOffset PCI IO offset. + @param DevConfigAddress The address is a device specific config sp= ace. + + @retval EFI_SUCCESS The address translated successfully. + @retval EFI_UNSUPPORTED The PCI IO address can not be translated. + +**/ +STATIC +EFI_STATUS +EFIAPI +VirtioPciIoToMemIoTranslation ( + IN UINTN BaseAddress, + IN UINTN PciIoOffset, + IN OUT UINTN *Address, + IN OUT BOOLEAN *DevConfigAddress + ) +{ + EFI_STATUS Status; + UINTN Offset; + INTN DevConfigSpaceOffset; + + Status =3D EFI_SUCCESS; + Offset =3D PciIoOffset; + *DevConfigAddress =3D FALSE; + DevConfigSpaceOffset =3D 0; + + // + //Check if it's device specific config space + // + if (PciIoOffset >=3D VIRTIO_DEVICE_SPECIFIC_CONFIGURATION_OFFSET_PCI ) { + Offset =3D VIRTIO_DEVICE_SPECIFIC_CONFIGURATION_OFFSET_PCI; + DevConfigSpaceOffset =3D PciIoOffset - VIRTIO_DEVICE_SPECIFIC_CONFIGUR= ATION_OFFSET_PCI; + *DevConfigAddress =3D TRUE; + } + + switch (Offset) { + case VIRTIO_PCI_OFFSET_DEVICE_FEATURES: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_HOST_FEATURES; + break; + case VIRTIO_PCI_OFFSET_GUEST_FEATURES: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_GUEST_FEATURES; + break; + case VIRTIO_PCI_OFFSET_QUEUE_ADDRESS: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_QUEUE_PFN; + break; + case VIRTIO_PCI_OFFSET_QUEUE_SIZE: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_QUEUE_NUM_MAX; + break; + case VIRTIO_PCI_OFFSET_QUEUE_SELECT: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_QUEUE_SEL; + break; + case VIRTIO_PCI_OFFSET_QUEUE_NOTIFY: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_QUEUE_NOTIFY; + break; + case VIRTIO_PCI_OFFSET_QUEUE_DEVICE_STATUS: + *Address =3D BaseAddress + VIRTIO_MMIO_OFFSET_STATUS; + break; + case VIRTIO_PCI_OFFSET_QUEUE_DEVICE_ISR: + Status =3D EFI_UNSUPPORTED; + break; + case VIRTIO_DEVICE_SPECIFIC_CONFIGURATION_OFFSET_PCI: + case VIRTIO_DEVICE_SPECIFIC_CONFIGURATION_OFFSET_PCI_WITH_MSI_X: + *Address =3D BaseAddress + VIRTIO_DEVICE_SPECIFIC_CONFIGURATION_OFFSET= _MMIO + DevConfigSpaceOffset; + break; + default: + Status =3D EFI_UNSUPPORTED; + break; + } + + return Status; +} + +/** Enable a PCI driver to access PCI controller registers in the PCI memory= or I/O space. =20 @param This A pointer to the EFI_PCI_IO_PROTOCOL insta= nce. @@ -398,8 +478,72 @@ PciIoIoRead ( IN OUT VOID *Buffer ) { - ASSERT (FALSE); - return EFI_UNSUPPORTED; + NON_DISCOVERABLE_PCI_DEVICE *Dev; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; + UINTN Length; + UINTN Address; + UINT32 ReadData; + BOOLEAN IsDevConfigSpace; + EFI_STATUS Status; + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Dev =3D NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This); + + // + // Only allow accesses to the BARs we emulate + // + Status =3D GetBarResource (Dev, BarIndex, &Desc); + if (EFI_ERROR (Status)) { + return Status; + } + + Length =3D Count << ((UINTN)Width & 0x3); + if (Offset + Length > Desc->AddrLen) { + return EFI_UNSUPPORTED; + } + + // + // Non-Discoverable devices are MMIO devices. Translate PCI IO requests = to MMIO. + // + + // + // VirtIo + // + if (CompareGuid (Dev->Device->Type, &gEdkiiNonDiscoverableVirtioDeviceGu= id)) { + // + // Check for a valid data size + // + if ((Length !=3D 1) && (Length !=3D 2) && + (Length !=3D 4) && (Length !=3D 8)) { + return EFI_INVALID_PARAMETER; + } + + Status =3D VirtioPciIoToMemIoTranslation (Desc->AddrRangeMin, Offset, = &Address, &IsDevConfigSpace); + if (!EFI_ERROR (Status)) { + if (IsDevConfigSpace =3D=3D TRUE) { // Device-specific configuration= registers + // + // The device-specific memory area of Virtio-MMIO can only be writ= ten in + // byte accesses. This is not currently in the Virtio spec. + // + MmioReadBuffer8 (Address, Length, Buffer); + } else if (Length < 8) { // 32-bit MMIO registers + ReadData =3D MmioRead32 (Address); + // The PCI IO register width may not be the same as MMIO register. + // Virtio MMIO registers are always 32-bit + CopyMem (Buffer, &ReadData, Length); + } else { + Status =3D EFI_INVALID_PARAMETER; + } + } + } else { + Status =3D EFI_UNSUPPORTED; + } + + ASSERT_EFI_ERROR (Status); + return Status; } =20 /** @@ -427,8 +571,72 @@ PciIoIoWrite ( IN OUT VOID *Buffer ) { - ASSERT (FALSE); - return EFI_UNSUPPORTED; + NON_DISCOVERABLE_PCI_DEVICE *Dev; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; + UINTN Length; + UINTN Address; + UINT32 WriteData; + BOOLEAN IsDevConfigSpace; + EFI_STATUS Status; + + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Dev =3D NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO (This); + + // + // Only allow accesses to the BARs we emulate + // + Status =3D GetBarResource (Dev, BarIndex, &Desc); + if (EFI_ERROR (Status)) { + return Status; + } + + Length =3D Count << ((UINTN)Width & 0x3); + if (Offset + Length > Desc->AddrLen) { + return EFI_UNSUPPORTED; + } + + // + // Non-Discoverable devices are MMIO devices. Translate PCI IO requests = to MMIO. + // + + // + // VirtIo + // + if (CompareGuid (Dev->Device->Type, &gEdkiiNonDiscoverableVirtioDeviceGu= id)) { + // + // Check for a valid data size + // + if ((Length !=3D 1) && (Length !=3D 2) && + (Length !=3D 4) && (Length !=3D 8)) { + return EFI_INVALID_PARAMETER; + } + + Status =3D VirtioPciIoToMemIoTranslation (Desc->AddrRangeMin, Offset, = &Address, &IsDevConfigSpace); + if (!EFI_ERROR (Status)) { + if (IsDevConfigSpace =3D=3D TRUE) { // Device-specific configuration= registers + // + // The device-specific memory area of Virtio-MMIO can only be writ= ten in + // byte accesses. This is not currently in the Virtio spec. + // + MmioWriteBuffer8 (Address, Length, Buffer); + } else if (Length < 8) { // 32-bit MMIO registers + // The PCI IO register width may not be the same as MMIO register. + // Virtio MMIO registers are always 32-bit + CopyMem (&WriteData, Buffer, Length); + MmioWrite32 (Address, WriteData); + } else { + return EFI_INVALID_PARAMETER; + } + } + } else { + Status =3D EFI_UNSUPPORTED; + } + + ASSERT_EFI_ERROR (Status); + return Status; } =20 /** @@ -1408,6 +1616,7 @@ InitializePciIoProtocol ( { EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; INTN Idx; + UINT32 VirtioMagicValue; =20 InitializeListHead (&Dev->UncachedAllocationList); =20 @@ -1471,6 +1680,15 @@ InitializePciIoProtocol ( Dev->ConfigSpace.Hdr.ClassCode[1] =3D 0x9; // UFS controller subclass; Dev->ConfigSpace.Hdr.ClassCode[2] =3D PCI_CLASS_MASS_STORAGE; Dev->BarOffset =3D 0; + } else if (CompareGuid (Dev->Device->Type, + &gEdkiiNonDiscoverableVirtioDeviceGuid)) { + Dev->ConfigSpace.Hdr.VendorId =3D VIRTIO_VENDOR_ID; // Required Virtio= vendor + Dev->ConfigSpace.Hdr.DeviceId =3D 0x1000; // Required Virtio device id + Dev->ConfigSpace.Hdr.RevisionID =3D 0x0; + Dev->ConfigSpace.Hdr.ClassCode[0] =3D 0x0; // don't care + Dev->ConfigSpace.Hdr.ClassCode[1] =3D 0x0; // don't care + Dev->ConfigSpace.Hdr.ClassCode[2] =3D 0x0; // don't care + Dev->BarOffset =3D 0; } else { ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); } @@ -1496,6 +1714,18 @@ InitializePciIoProtocol ( } =20 Dev->ConfigSpace.Device.Bar[Idx] =3D (UINT32)Desc->AddrRangeMin; + + // + // Initialize Virtio device Id + // + if (CompareGuid (Dev->Device->Type, &gEdkiiNonDiscoverableVirtioDevice= Guid)) { + VirtioMagicValue =3D MmioRead32 (Dev->ConfigSpace.Device.Bar[Idx] + = VIRTIO_MMIO_OFFSET_MAGIC); + if (VirtioMagicValue =3D=3D VIRTIO_MMIO_MAGIC) { + Dev->ConfigSpace.Device.SubsystemID =3D MmioRead32 (Dev->ConfigSpa= ce.Device.Bar[Idx] + + VIRTIO_MMIO_OFFS= ET_DEVICE_ID); + } + } + Dev->BarCount++; =20 if (Desc->AddrSpaceGranularity =3D=3D 64) { --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 20:03:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15203866346310.41360433121474216; Tue, 6 Mar 2018 17:37:14 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B122F224E691B; Tue, 6 Mar 2018 17:30:53 -0800 (PST) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id C714E224C0F58 for ; Tue, 6 Mar 2018 17:30:51 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57F2E1684; Tue, 6 Mar 2018 17:37:06 -0800 (PST) Received: from usa.arm.com (dbox2.austin.arm.com [10.118.34.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1706D3F24A; Tue, 6 Mar 2018 17:37:06 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=daniil.egranov@arm.com; receiver=edk2-devel@lists.01.org From: Daniil Egranov To: edk2-devel@lists.01.org Date: Tue, 6 Mar 2018 19:36:37 -0600 Message-Id: <20180307013637.16462-5-daniil.egranov@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180307013637.16462-1-daniil.egranov@arm.com> References: <20180307013637.16462-1-daniil.egranov@arm.com> Subject: [edk2] [PATCH 4/4] VirtioPciDeviceDxe: Added non-discoverable Virtio support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The VirtioPciDeviceDxe was extended to support a non-discoverable MMIO Virtio case. The Virtio spec defines both PCI and MMIO device types with the=20 set of registers that are not the same between these two types of devices. All PCI registers have corresponding MMIO registers but the number of registers is less then MMIO. The width of MMIO registers and PCI registers is not always the same. Compared to PCI, MMIO Virtio devices required more registers to be programmed in some cases. Added detection that a PCI device is=20 based on a non-discoverable device and allows MMIO transactions. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Daniil Egranov --- OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c | 143 ++++++++++++++++++= +++- OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.h | 21 +++- OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf | 4 +- OvmfPkg/VirtioPciDeviceDxe/VirtioPciFunctions.c | 117 +++++++++++++++++- 4 files changed, 278 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c b/OvmfPkg/VirtioP= ciDeviceDxe/VirtioPciDevice.c index d4b4ec21c3..df2a4ea116 100644 --- a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c +++ b/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.c @@ -4,7 +4,7 @@ =20 Copyright (C) 2012, Red Hat, Inc. Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
- Copyright (C) 2013, ARM Ltd. + Copyright (C) 2013 - 2018, ARM Ltd. Copyright (C) 2017, AMD Inc, All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble @@ -215,6 +215,147 @@ VirtioPciIoWrite ( =20 /** =20 + Read a word from Region 0 of the device specified by PciMemIo. + + Region 0 must be an iomem region. This is an internal function for the P= CI + implementation of the protocol. + + @param[in] Dev Virtio PCI device. + + @param[in] FieldOffset Source offset. + + @param[in] FieldSize Source field size, must be in { 1, 2, 4, 8 }. + + @param[in] BufferSize Number of bytes available in the target buffer. = Must + equal FieldSize. + + @param[out] Buffer Target buffer. + + + @return Status code returned by PciIo->Io.Read(). + +**/ +EFI_STATUS +EFIAPI +VirtioPciMemIoRead ( + IN VIRTIO_PCI_DEVICE *Dev, + IN UINTN FieldOffset, + IN UINTN FieldSize, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + UINTN Count; + EFI_PCI_IO_PROTOCOL_WIDTH Width; + EFI_PCI_IO_PROTOCOL *PciIo; + + ASSERT (FieldSize =3D=3D BufferSize); + + PciIo =3D Dev->PciIo; + Count =3D 1; + + switch (FieldSize) { + case 1: + Width =3D EfiPciIoWidthUint8; + break; + + case 2: + Width =3D EfiPciIoWidthUint16; + break; + + case 4: + Width =3D EfiPciIoWidthUint32; + break; + + case 8: + Width =3D EfiPciIoWidthUint64; + break; + + default: + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + return PciIo->Mem.Read ( + PciIo, + Width, + PCI_BAR_IDX0, + FieldOffset, + Count, + Buffer + ); +} + +/** + + Write a word into Region 0 of the device specified by PciMemIo. + + Region 0 must be an iomem region. This is an internal function for the P= CI + implementation of the protocol. + + @param[in] Dev Virtio PCI device. + + @param[in] FieldOffset Destination offset. + + @param[in] FieldSize Destination field size, must be in { 1, 2, 4, 8 = }. + + @param[in] Value Little endian value to write, converted to UINT6= 4. + The least significant FieldSize bytes will be us= ed. + + + @return Status code returned by PciIo->Io.Write(). + +**/ +EFI_STATUS +EFIAPI +VirtioPciMemIoWrite ( + IN VIRTIO_PCI_DEVICE *Dev, + IN UINTN FieldOffset, + IN UINTN FieldSize, + IN UINT64 Value + ) +{ + UINTN Count; + EFI_PCI_IO_PROTOCOL_WIDTH Width; + EFI_PCI_IO_PROTOCOL *PciIo; + + PciIo =3D Dev->PciIo; + Count =3D 1; + + switch (FieldSize) { + case 1: + Width =3D EfiPciIoWidthUint8; + break; + + case 2: + Width =3D EfiPciIoWidthUint16; + break; + + case 4: + Width =3D EfiPciIoWidthUint32; + break; + + case 8: + Width =3D EfiPciIoWidthUint64; + break; + + default: + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + return PciIo->Mem.Write ( + PciIo, + Width, + PCI_BAR_IDX0, + FieldOffset, + Count, + &Value + ); +} + +/** + Device probe function for this driver. =20 The DXE core calls this function for any given device in order to see if= the diff --git a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.h b/OvmfPkg/VirtioP= ciDeviceDxe/VirtioPciDevice.h index 1f0dc45d50..e91191689c 100644 --- a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.h +++ b/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDevice.h @@ -2,7 +2,7 @@ =20 Internal definitions for the VirtIo PCI Device driver =20 - Copyright (C) 2013, ARM Ltd + Copyright (C) 2013-2018, ARM Ltd Copyright (c) 2017, AMD Inc, All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble @@ -58,6 +58,25 @@ VirtioPciIoWrite ( IN UINT64 Value ); =20 +EFI_STATUS +EFIAPI +VirtioPciMemIoRead ( + IN VIRTIO_PCI_DEVICE *Dev, + IN UINTN FieldOffset, + IN UINTN FieldSize, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +VirtioPciMemIoWrite ( + IN VIRTIO_PCI_DEVICE *Dev, + IN UINTN FieldOffset, + IN UINTN FieldSize, + IN UINT64 Value + ); + /******************************************** * PCI Functions for VIRTIO_DEVICE_PROTOCOL *******************************************/ diff --git a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf b/OvmfPkg/Vi= rtioPciDeviceDxe/VirtioPciDeviceDxe.inf index 4b5d1a493e..675b156c82 100644 --- a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf +++ b/OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf @@ -2,7 +2,7 @@ # This driver produces the VirtIo Device Protocol instances for VirtIo PCI # Device # -# Copyright (C) 2013, ARM Ltd +# Copyright (C) 2013-2018, ARM Ltd # # This program and the accompanying materials are licensed and made availa= ble # under the terms and conditions of the BSD License which accompanies this @@ -28,6 +28,7 @@ =20 [Packages] MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] @@ -41,3 +42,4 @@ [Protocols] gEfiPciIoProtocolGuid ## TO_START gVirtioDeviceProtocolGuid ## BY_START + gEdkiiNonDiscoverableDeviceProtocolGuid diff --git a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciFunctions.c b/OvmfPkg/Virt= ioPciDeviceDxe/VirtioPciFunctions.c index b52060d13d..45b49f0915 100644 --- a/OvmfPkg/VirtioPciDeviceDxe/VirtioPciFunctions.c +++ b/OvmfPkg/VirtioPciDeviceDxe/VirtioPciFunctions.c @@ -4,7 +4,7 @@ =20 Copyright (C) 2012, Red Hat, Inc. Copyright (c) 2012, Intel Corporation. All rights reserved.
- Copyright (C) 2013, ARM Ltd. + Copyright (C) 2013-2018, ARM Ltd. Copyright (C) 2017, AMD Inc, All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble @@ -21,10 +21,76 @@ #include #include #include + +#include + #include "VirtioPciDevice.h" =20 /** =20 + Check if virtvo PCI device is a non discoverable virtio MMIO device. + + @param[in] Dev Pointer to the virtio PCI device structure. + + @return TRUE if PCI device is a non discoverable device. + +**/ +STATIC +BOOLEAN +VirtioIsNonDiscoverableMmioDevice ( + IN VIRTIO_PCI_DEVICE *Dev + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_PCI_IO_PROTOCOL *PciIo; + NON_DISCOVERABLE_DEVICE *Device; + EFI_STATUS Status; + UINTN HIndex; + UINTN HandleCount; + BOOLEAN RetStatus; + + RetStatus =3D FALSE; + Status =3D gBS->LocateHandleBuffer (ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + + if (!EFI_ERROR (Status)) { + for (HIndex =3D 0; HIndex < HandleCount; ++HIndex) { + Status =3D gBS->OpenProtocol (HandleBuffer[HIndex], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo, + NULL, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + + if (EFI_ERROR (Status)) { + continue; + } + + if (PciIo =3D=3D Dev->PciIo) { + Status =3D gBS->OpenProtocol (HandleBuffer[HIndex], + &gEdkiiNonDiscoverableDeviceProtocolGu= id, + (VOID **) &Device, + NULL, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + + if (!EFI_ERROR (Status)) { + RetStatus =3D TRUE; + } + break; + } + } + } + + gBS->FreePool (HandleBuffer); + return RetStatus; +} + +/** + Read a word from Region 0 of the device specified by VirtIo Device proto= col. =20 The function implements the ReadDevice protocol member of @@ -219,7 +285,21 @@ VirtioPciSetQueueAlignment ( IN UINT32 Alignment ) { - return EFI_SUCCESS; + VIRTIO_PCI_DEVICE *Dev; + EFI_STATUS Status; + + Dev =3D VIRTIO_PCI_DEVICE_FROM_VIRTIO_DEVICE (This); + Status =3D EFI_SUCCESS; + + // This register is required to be programmed for MMIO type of devices. + // Virtio MMIO device can be registered as a non-discoverable device on + // PCI bus, check if it's the case. + if (VirtioIsNonDiscoverableMmioDevice (Dev)) { + Status =3D VirtioPciMemIoWrite (Dev, VIRTIO_MMIO_OFFSET_QUEUE_ALIGN, + sizeof (UINT32), Alignment); + } + + return Status; } =20 EFI_STATUS @@ -229,7 +309,22 @@ VirtioPciSetPageSize ( IN UINT32 PageSize ) { - return (PageSize =3D=3D EFI_PAGE_SIZE) ? EFI_SUCCESS : EFI_UNSUPPORTED; + VIRTIO_PCI_DEVICE *Dev; + EFI_STATUS Status; + + Dev =3D VIRTIO_PCI_DEVICE_FROM_VIRTIO_DEVICE (This); + + // This register is required to be programmed for MMIO type of devices. + // Virtio MMIO device can be registered as a non-discoverable device on + // PCI bus, check if it's the case. + if (VirtioIsNonDiscoverableMmioDevice (Dev)) { + Status =3D VirtioPciMemIoWrite (Dev, VIRTIO_MMIO_OFFSET_GUEST_PAGE_SIZ= E, + sizeof (UINT32), PageSize); + } else { + Status =3D (PageSize =3D=3D EFI_PAGE_SIZE) ? EFI_SUCCESS : EFI_UNSUPPO= RTED; + } + + return Status; } =20 EFI_STATUS @@ -254,11 +349,25 @@ VirtioPciSetQueueSize ( IN UINT16 Size ) { + VIRTIO_PCI_DEVICE *Dev; + EFI_STATUS Status; + // // This function is only applicable in Virtio-MMIO. // (The QueueSize field is read-only in Virtio proper (PCI)) // - return EFI_SUCCESS; + Dev =3D VIRTIO_PCI_DEVICE_FROM_VIRTIO_DEVICE (This); + Status =3D EFI_SUCCESS; + + // This register is required to be programmed for MMIO type of devices. + // Virtio MMIO device can be registered as a non-discoverable device on + // PCI bus, check if it's the case. + if (VirtioIsNonDiscoverableMmioDevice (Dev)) { + Status =3D VirtioPciMemIoWrite (Dev, VIRTIO_MMIO_OFFSET_QUEUE_NUM, + sizeof (UINT32), (UINT32) Size); + } + + return Status; } =20 EFI_STATUS --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel