From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949059580600.8812842503625; Thu, 1 Mar 2018 16:04:19 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7A398224C0F38; Thu, 1 Mar 2018 15:58:06 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 935EC22485A98 for ; Thu, 1 Mar 2018 15:58:05 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E115E4084FEC; Fri, 2 Mar 2018 00:04:13 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id B11B310EE987; Fri, 2 Mar 2018 00:04:12 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:49 +0100 Message-Id: <20180302000408.14201-2-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:13 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:13 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 01/20] OvmfPkg/MemEncryptSevLib: rewrap to 79 characters width X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are many overlong lines; it's hard to work with the library like this. Rewrap all files to 79 columns. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf | 7 +- OvmfPkg/Include/Library/MemEncryptSevLib.h | 20 ++- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h | 111 ++++= ++++------ OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 34 +++-- OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c | 8 +- OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c | 58 ++++= --- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c | 158 ++++= +++++++++------- 7 files changed, 253 insertions(+), 143 deletions(-) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf = b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf index 3cfd80a28c1d..81b075194ace 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf @@ -1,45 +1,48 @@ ## @file # Library provides the helper functions for SEV guest # # Copyright (c) 2017 Advanced Micro Devices. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD # License which accompanies this distribution. The full text of the licen= se # may be found at http://opensource.org/licenses/bsd-license.php +# # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. # # ## =20 [Defines] INF_VERSION =3D 1.25 BASE_NAME =3D MemEncryptSevLib FILE_GUID =3D c1594631-3888-4be4-949f-9c630dbc842b MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D MemEncryptSevLib|PEIM DXE_DRIVER DXE_= RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER =20 # -# The following information is for reference only and not required by the = build tools. +# The following information is for reference only and not required by the = build +# tools. # # VALID_ARCHITECTURES =3D IA32 X64 # =20 [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [Sources.X64] MemEncryptSevLibInternal.c X64/MemEncryptSevLib.c X64/VirtualMemory.c =20 [Sources.IA32] MemEncryptSevLibInternal.c Ia32/MemEncryptSevLib.c =20 [LibraryClasses] diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index b6753762423e..4f3ba9f22cb4 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -18,64 +18,68 @@ #define _MEM_ENCRYPT_SEV_LIB_H_ =20 #include =20 /** Returns a boolean to indicate whether SEV is enabled =20 @retval TRUE SEV is active @retval FALSE SEV is not enabled **/ BOOLEAN EFIAPI MemEncryptSevIsEnabled ( VOID ); =20 /** This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and Number of pages from the current page table context. =20 - @param[in] BaseAddress The physical address that is the start= address - of a memory region. - @param[in] NumberOfPages The number of pages from start memory = region. + @param[in] BaseAddress The physical address that is the start + address of a memory region. + @param[in] NumberOfPages The number of pages from start memory + region. @param[in] Flush Flush the caches before clearing the b= it (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the me= mory region. + @retval RETURN_SUCCESS The attributes were cleared for the me= mory + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not supported **/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumberOfPages, IN BOOLEAN CacheFlush ); =20 /** This function sets memory encryption bit for the memory region specified= by BaseAddress and Number of pages from the current page table context. =20 - @param[in] BaseAddress The physical address that is the start= address - of a memory region. - @param[in] NumberOfPages The number of pages from start memory = region. + @param[in] BaseAddress The physical address that is the start + address of a memory region. + @param[in] NumberOfPages The number of pages from start memory + region. @param[in] Flush Flush the caches before clearing the b= it (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were set for the memory= region. + @retval RETURN_SUCCESS The attributes were set for the memory + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not supported **/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumberOfPages, IN BOOLEAN CacheFlush ); #endif // _MEM_ENCRYPT_SEV_LIB_H_ diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h index e7b5634b45c1..7dd1bbe0eb26 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h @@ -1,212 +1,239 @@ /** @file =20 Virtual Memory Management Services to set or clear the memory encryption= bit =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
-Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 -Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h + Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h =20 **/ =20 #ifndef __VIRTUAL_MEMORY__ #define __VIRTUAL_MEMORY__ =20 #include #include #include #include #include =20 #include #define SYS_CODE64_SEL 0x38 =20 #pragma pack(1) =20 // // Page-Map Level-4 Offset (PML4) and // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB // =20 typedef union { struct { - UINT64 Present:1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT64 Present:1; // 0 =3D Not present in memory, + // 1 =3D Present in memory UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough:1; // 0 =3D Write-Back caching, 1=3DWri= te-Through caching + UINT64 WriteThrough:1; // 0 =3D Write-Back caching, + // 1 =3D Write-Through caching UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed:1; // 0 =3D Not accessed, 1 =3D Accesse= d (set by CPU) + UINT64 Accessed:1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) UINT64 Reserved:1; // Reserved UINT64 MustBeZero:2; // Must Be Zero UINT64 Available:3; // Available for use by system softw= are UINT64 PageTableBaseAddress:40; // Page Table Base Address UINT64 AvabilableHigh:11; // Available for use by system softw= are UINT64 Nx:1; // No Execute bit } Bits; UINT64 Uint64; } PAGE_MAP_AND_DIRECTORY_POINTER; =20 // // Page Table Entry 4KB // typedef union { struct { - UINT64 Present:1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT64 Present:1; // 0 =3D Not present in memory, + // 1 =3D Present in memory UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough:1; // 0 =3D Write-Back caching, 1=3DWri= te-Through caching + UINT64 WriteThrough:1; // 0 =3D Write-Back caching, + // 1 =3D Write-Through caching UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed:1; // 0 =3D Not accessed, 1 =3D Accesse= d (set by CPU) - UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written by= processor on access to page + UINT64 Accessed:1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written by + // processor on access to page UINT64 PAT:1; // - UINT64 Global:1; // 0 =3D Not global page, 1 =3D glob= al page TLB not cleared on CR3 write + UINT64 Global:1; // 0 =3D Not global page, 1 =3D glob= al page + // TLB not cleared on CR3 write UINT64 Available:3; // Available for use by system softw= are UINT64 PageTableBaseAddress:40; // Page Table Base Address UINT64 AvabilableHigh:11; // Available for use by system softw= are - UINT64 Nx:1; // 0 =3D Execute Code, 1 =3D No Code= Execution + UINT64 Nx:1; // 0 =3D Execute Code, + // 1 =3D No Code Execution } Bits; UINT64 Uint64; } PAGE_TABLE_4K_ENTRY; =20 // // Page Table Entry 2MB // typedef union { struct { - UINT64 Present:1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT64 Present:1; // 0 =3D Not present in memory, + // 1 =3D Present in memory UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough:1; // 0 =3D Write-Back caching, 1=3DWri= te-Through caching + UINT64 WriteThrough:1; // 0 =3D Write-Back caching, + // 1=3DWrite-Through caching UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed:1; // 0 =3D Not accessed, 1 =3D Accesse= d (set by CPU) - UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written by= processor on access to page + UINT64 Accessed:1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written by + // processor on access to page UINT64 MustBe1:1; // Must be 1 - UINT64 Global:1; // 0 =3D Not global page, 1 =3D glob= al page TLB not cleared on CR3 write + UINT64 Global:1; // 0 =3D Not global page, 1 =3D glob= al page + // TLB not cleared on CR3 write UINT64 Available:3; // Available for use by system softw= are UINT64 PAT:1; // UINT64 MustBeZero:8; // Must be zero; UINT64 PageTableBaseAddress:31; // Page Table Base Address UINT64 AvabilableHigh:11; // Available for use by system softw= are - UINT64 Nx:1; // 0 =3D Execute Code, 1 =3D No Code= Execution + UINT64 Nx:1; // 0 =3D Execute Code, + // 1 =3D No Code Execution } Bits; UINT64 Uint64; } PAGE_TABLE_ENTRY; =20 // // Page Table Entry 1GB // typedef union { struct { - UINT64 Present:1; // 0 =3D Not present in memory, 1 = =3D Present in memory + UINT64 Present:1; // 0 =3D Not present in memory, + // 1 =3D Present in memory UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough:1; // 0 =3D Write-Back caching, 1=3DWri= te-Through caching + UINT64 WriteThrough:1; // 0 =3D Write-Back caching, + // 1 =3D Write-Through caching UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed:1; // 0 =3D Not accessed, 1 =3D Accesse= d (set by CPU) - UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written by= processor on access to page + UINT64 Accessed:1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written by + // processor on access to page UINT64 MustBe1:1; // Must be 1 - UINT64 Global:1; // 0 =3D Not global page, 1 =3D glob= al page TLB not cleared on CR3 write + UINT64 Global:1; // 0 =3D Not global page, 1 =3D glob= al page + // TLB not cleared on CR3 write UINT64 Available:3; // Available for use by system softw= are UINT64 PAT:1; // UINT64 MustBeZero:17; // Must be zero; UINT64 PageTableBaseAddress:22; // Page Table Base Address UINT64 AvabilableHigh:11; // Available for use by system softw= are - UINT64 Nx:1; // 0 =3D Execute Code, 1 =3D No Code= Execution + UINT64 Nx:1; // 0 =3D Execute Code, + // 1 =3D No Code Execution } Bits; UINT64 Uint64; } PAGE_TABLE_1G_ENTRY; =20 #pragma pack() =20 #define IA32_PG_P BIT0 #define IA32_PG_RW BIT1 #define IA32_PG_PS BIT7 =20 #define PAGING_PAE_INDEX_MASK 0x1FF =20 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull =20 #define PAGING_L1_ADDRESS_SHIFT 12 #define PAGING_L2_ADDRESS_SHIFT 21 #define PAGING_L3_ADDRESS_SHIFT 30 #define PAGING_L4_ADDRESS_SHIFT 39 =20 #define PAGING_PML4E_NUMBER 4 =20 #define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1) #define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK) #define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK) #define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK) #define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK) #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull =20 #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB #define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB -#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNI= T_SIZE) +#define PAGE_TABLE_POOL_UNIT_PAGES \ + EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE) #define PAGE_TABLE_POOL_ALIGN_MASK \ (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1)) =20 typedef struct { VOID *NextPool; UINTN Offset; UINTN FreePages; } PAGE_TABLE_POOL; =20 =20 =20 /** - This function clears memory encryption bit for the memory region specifi= ed by PhysicalAddress - and length from the current page table context. + This function clears memory encryption bit for the memory region specifi= ed by + PhysicalAddress and length from the current page table context. =20 - @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. + @param[in] PhysicalAddress The physical address that is the sta= rt + address of a memory region. @param[in] Length The length of memory region - @param[in] Flush Flush the caches before applying the= encryption mask + @param[in] Flush Flush the caches before applying the + encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is not supported + @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryDecrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINT64 Length, IN BOOLEAN CacheFlush ); =20 /** This function sets memory encryption bit for the memory region specified= by PhysicalAddress and length from the current page table context. =20 - @param[in] PhysicalAddress The physical address that is the sta= rt address - of a memory region. + @param[in] PhysicalAddress The physical address that is the sta= rt + address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is - not supported + @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryEncrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINT64 Length, IN BOOLEAN CacheFlush ); =20 #endif diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c b= /OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c index a2ea99019917..d1130df2d0e7 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c @@ -1,84 +1,90 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD - License which accompanies this distribution. The full text of the licen= se may - be found at http://opensource.org/licenses/bsd-license.php + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include #include #include #include #include =20 /** This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and Number of pages from the current page table context. =20 - @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent CR3) - @param[in] BaseAddress The physical address that is the start= address - of a memory region. - @param[in] NumberOfPages The number of pages from start memory = region. + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent + CR3) + @param[in] BaseAddress The physical address that is the start + address of a memory region. + @param[in] NumberOfPages The number of pages from start memory + region. @param[in] Flush Flush the caches before clearing the b= it (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the me= mory region. + @retval RETURN_SUCCESS The attributes were cleared for the me= mory + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not supported **/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumberOfPages, IN BOOLEAN Flush ) { // // Memory encryption bit is not accessible in 32-bit mode // return RETURN_UNSUPPORTED; } =20 /** This function sets memory encryption bit for the memory region specified= by BaseAddress and Number of pages from the current page table context. =20 - @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent CR3) - @param[in] BaseAddress The physical address that is the start= address - of a memory region. - @param[in] NumberOfPages The number of pages from start memory = region. + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent + CR3) + @param[in] BaseAddress The physical address that is the start + address of a memory region. + @param[in] NumberOfPages The number of pages from start memory + region. @param[in] Flush Flush the caches before clearing the b= it (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were set for the memory= region. + @retval RETURN_SUCCESS The attributes were set for the memory + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not supported **/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumberOfPages, IN BOOLEAN Flush ) { // // Memory encryption bit is not accessible in 32-bit mode // return RETURN_UNSUPPORTED; } diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.= c b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c index 002f079c7eb3..ff561236d819 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c @@ -1,30 +1,30 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD - License which accompanies this distribution. The full text of the licen= se may - be found at http://opensource.org/licenses/bsd-license.php + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include #include #include #include #include =20 STATIC BOOLEAN mSevStatus =3D FALSE; STATIC BOOLEAN mSevStatusChecked =3D FALSE; =20 /** =20 Returns a boolean to indicate whether SEV is enabled =20 diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c b/= OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c index 9ec76708bd7b..4b7fdf7d044d 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c @@ -1,84 +1,98 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD - License which accompanies this distribution. The full text of the licen= se may - be found at http://opensource.org/licenses/bsd-license.php + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include #include #include #include #include =20 #include "VirtualMemory.h" =20 /** =20 This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and Number of pages from the current page table context. =20 - @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use c= urrent CR3) - @param[in] BaseAddress The physical address that is the sta= rt address - of a memory region. - @param[in] NumberOfPages The number of pages from start memor= y region. + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumberOfPages The number of pages from start memory + region. @param[in] Flush Flush the caches before clearing the= bit (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory - region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute is - not supported + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported **/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ) { - return InternalMemEncryptSevSetMemoryDecrypted (Cr3BaseAddress, BaseAddr= ess, EFI_PAGES_TO_SIZE(NumPages), Flush); + return InternalMemEncryptSevSetMemoryDecrypted ( + Cr3BaseAddress, + BaseAddress, + EFI_PAGES_TO_SIZE (NumPages), + Flush + ); } =20 /** =20 This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and Number of pages from the current page table context. =20 - @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use c= urrent CR3) - @param[in] BaseAddress The physical address that is the sta= rt address - of a memory region. - @param[in] NumberOfPages The number of pages from start memor= y region. + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumberOfPages The number of pages from start memory + region. @param[in] Flush Flush the caches before clearing the= bit (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory - region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute is - not supported + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported **/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ) { - return InternalMemEncryptSevSetMemoryEncrypted (Cr3BaseAddress, BaseAddr= ess, EFI_PAGES_TO_SIZE(NumPages), Flush); + return InternalMemEncryptSevSetMemoryEncrypted ( + Cr3BaseAddress, + BaseAddress, + EFI_PAGES_TO_SIZE (NumPages), + Flush + ); } diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c index 4185874c99b8..65b8babaac44 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c @@ -1,36 +1,36 @@ /** @file =20 Virtual Memory Management Services to set or clear the memory encryption= bit =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
-Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 -Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c + Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c =20 **/ =20 #include #include #include =20 #include "VirtualMemory.h" =20 STATIC BOOLEAN mAddressEncMaskChecked =3D FALSE; STATIC UINT64 mAddressEncMask; STATIC PAGE_TABLE_POOL *mPageTablePool =3D NULL; =20 typedef enum { SetCBit, ClearCBit } MAP_RANGE_MODE; =20 /** Get the memory encryption mask @@ -52,45 +52,46 @@ GetMemEncryptionAddressMask ( } =20 // // CPUID Fn8000_001F[EBX] Bit 0:5 (memory encryption bit position) // AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, NULL, &Ebx.Uint32, NULL, NULL); EncryptionMask =3D LShiftU64 (1, Ebx.Bits.PtePosBits); =20 mAddressEncMask =3D EncryptionMask & PAGING_1G_ADDRESS_MASK_64; mAddressEncMaskChecked =3D TRUE; =20 return mAddressEncMask; } =20 /** Initialize a buffer pool for page table use only. =20 To reduce the potential split operation on page table, the pages reserve= d for page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGE= S and at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always - initialized with number of pages greater than or equal to the given Pool= Pages. + initialized with number of pages greater than or equal to the given + PoolPages. =20 Once the pages in the pool are used up, this method should be called aga= in to - reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't = happen - often in practice. + reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't + happen often in practice. =20 @param[in] PoolPages The least page number of the pool to be create= d. =20 @retval TRUE The pool is initialized successfully. @retval FALSE The memory is out of resource. **/ STATIC BOOLEAN InitializePageTablePool ( IN UINTN PoolPages ) { VOID *Buffer; =20 // // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one pag= e for // header. // PoolPages +=3D 1; // Add one page for header. PoolPages =3D ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) * @@ -166,89 +167,96 @@ AllocatePageTableMemory ( =20 mPageTablePool->Offset +=3D EFI_PAGES_TO_SIZE (Pages); mPageTablePool->FreePages -=3D Pages; =20 DEBUG (( DEBUG_VERBOSE, "%a:%a: Buffer=3D0x%Lx Pages=3D%ld\n", gEfiCallerBaseName, __FUNCTION__, Buffer, Pages )); =20 return Buffer; } =20 =20 /** Split 2M page to 4K. =20 - @param[in] PhysicalAddress Start physical address the 2M page= covered. + @param[in] PhysicalAddress Start physical address the 2M page + covered. @param[in, out] PageEntry2M Pointer to 2M page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. =20 **/ STATIC VOID Split2MPageTo4K ( IN PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry2M, IN PHYSICAL_ADDRESS StackBase, IN UINTN StackSize ) { PHYSICAL_ADDRESS PhysicalAddress4K; UINTN IndexOfPageTableEntries; PAGE_TABLE_4K_ENTRY *PageTableEntry, *PageTableEntry1; UINT64 AddressEncMask; =20 PageTableEntry =3D AllocatePageTableMemory(1); =20 PageTableEntry1 =3D PageTableEntry; =20 AddressEncMask =3D GetMemEncryptionAddressMask (); =20 ASSERT (PageTableEntry !=3D NULL); ASSERT (*PageEntry2M & AddressEncMask); =20 PhysicalAddress4K =3D PhysicalAddress; - for (IndexOfPageTableEntries =3D 0; IndexOfPageTableEntries < 512; Index= OfPageTableEntries++, PageTableEntry++, PhysicalAddress4K +=3D SIZE_4KB) { + for (IndexOfPageTableEntries =3D 0; + IndexOfPageTableEntries < 512; + (IndexOfPageTableEntries++, + PageTableEntry++, + PhysicalAddress4K +=3D SIZE_4KB)) { // // Fill in the Page Table entries // PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | AddressEncMask; PageTableEntry->Bits.ReadWrite =3D 1; PageTableEntry->Bits.Present =3D 1; - if ((PhysicalAddress4K >=3D StackBase) && (PhysicalAddress4K < StackBa= se + StackSize)) { + if ((PhysicalAddress4K >=3D StackBase) && + (PhysicalAddress4K < StackBase + StackSize)) { // // Set Nx bit for stack. // PageTableEntry->Bits.Nx =3D 1; } } =20 // // Fill in 2M page entry. // - *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry1 | IA32_PG_P | IA32_PG_= RW | AddressEncMask; + *PageEntry2M =3D ((UINT64)(UINTN)PageTableEntry1 | + IA32_PG_P | IA32_PG_RW | AddressEncMask); } =20 /** Set one page of page table pool memory to be read-only. =20 @param[in] PageTableBase Base address of page table (CR3). @param[in] Address Start address of a page to be set as read-on= ly. @param[in] Level4Paging Level 4 paging flag. =20 **/ STATIC VOID SetPageTablePoolReadOnly ( IN UINTN PageTableBase, IN EFI_PHYSICAL_ADDRESS Address, IN BOOLEAN Level4Paging ) { UINTN Index; UINTN EntryIndex; @@ -374,96 +382,108 @@ EnablePageTableProtection ( PAGE_TABLE_POOL *HeadPool; PAGE_TABLE_POOL *Pool; UINT64 PoolSize; EFI_PHYSICAL_ADDRESS Address; =20 if (mPageTablePool =3D=3D NULL) { return; } =20 // // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to // remember original one in advance. // HeadPool =3D mPageTablePool; Pool =3D HeadPool; do { Address =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Pool; PoolSize =3D Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages); =20 // - // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE,= which - // is one of page size of the processor (2MB by default). Let's apply = the - // protection to them one by one. + // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, + // which is one of page size of the processor (2MB by default). Let's = apply + // the protection to them one by one. // while (PoolSize > 0) { SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging); Address +=3D PAGE_TABLE_POOL_UNIT_SIZE; PoolSize -=3D PAGE_TABLE_POOL_UNIT_SIZE; } =20 Pool =3D Pool->NextPool; } while (Pool !=3D HeadPool); =20 } =20 =20 /** Split 1G page to 2M. =20 - @param[in] PhysicalAddress Start physical address the 1G page= covered. + @param[in] PhysicalAddress Start physical address the 1G page + covered. @param[in, out] PageEntry1G Pointer to 1G page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. =20 **/ STATIC VOID Split1GPageTo2M ( IN PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry1G, IN PHYSICAL_ADDRESS StackBase, IN UINTN StackSize ) { PHYSICAL_ADDRESS PhysicalAddress2M; UINTN IndexOfPageDirectoryEntries; PAGE_TABLE_ENTRY *PageDirectoryEntry; UINT64 AddressEncMask; =20 PageDirectoryEntry =3D AllocatePageTableMemory(1); =20 AddressEncMask =3D GetMemEncryptionAddressMask (); ASSERT (PageDirectoryEntry !=3D NULL); ASSERT (*PageEntry1G & GetMemEncryptionAddressMask ()); // // Fill in 1G page entry. // - *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_= PG_RW | AddressEncMask; + *PageEntry1G =3D ((UINT64)(UINTN)PageDirectoryEntry | + IA32_PG_P | IA32_PG_RW | AddressEncMask); =20 PhysicalAddress2M =3D PhysicalAddress; - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { - if ((PhysicalAddress2M < StackBase + StackSize) && ((PhysicalAddress2M= + SIZE_2MB) > StackBase)) { + for (IndexOfPageDirectoryEntries =3D 0; + IndexOfPageDirectoryEntries < 512; + (IndexOfPageDirectoryEntries++, + PageDirectoryEntry++, + PhysicalAddress2M +=3D SIZE_2MB)) { + if ((PhysicalAddress2M < StackBase + StackSize) && + ((PhysicalAddress2M + SIZE_2MB) > StackBase)) { // // Need to split this 2M page that covers stack range. // - Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize); + Split2MPageTo4K ( + PhysicalAddress2M, + (UINT64 *)PageDirectoryEntry, + StackBase, + StackSize + ); } else { // // Fill in the Page Directory entries // PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M | AddressE= ncMask; PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; } } } =20 =20 /** Set or Clear the memory encryption bit =20 @param[in] PagetablePoint Page table entry pointer (PTE). @param[in] Mode Set or Clear encryption bit =20 **/ @@ -510,62 +530,63 @@ VOID DisableReadOnlyPageWriteProtect ( VOID ) { AsmWriteCr0 (AsmReadCr0() & ~BIT16); } =20 /** Enable Write Protect on pages marked as read-only. **/ VOID EnableReadOnlyPageWriteProtect ( VOID ) { AsmWriteCr0 (AsmReadCr0() | BIT16); } =20 =20 /** - This function either sets or clears memory encryption bit for the memory= region - specified by PhysicalAddress and length from the current page table cont= ext. + This function either sets or clears memory encryption bit for the memory + region specified by PhysicalAddress and length from the current page tab= le + context. =20 The function iterates through the physicalAddress one page at a time, an= d set or clears the memory encryption mask in the page table. If it encounters that a given physical address range is part of large page then it attemp= ts to change the attribute at one go (based on size), otherwise it splits the large pages into smaller (e.g 2M page into 4K pages) and then try to set= or clear the encryption bit on the smallest page size. =20 @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Mode Set or Clear mode @param[in] Flush Flush the caches before applying the encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory - region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is - not supported + @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + is not supported **/ =20 STATIC RETURN_STATUS EFIAPI SetMemoryEncDec ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN MAP_RANGE_MODE Mode, IN BOOLEAN CacheFlush ) { PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; PAGE_MAP_AND_DIRECTORY_POINTER *PageUpperDirectoryPointerEntry; PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; PAGE_TABLE_ENTRY *PageDirectory2MEntry; PAGE_TABLE_4K_ENTRY *PageTableEntry; UINT64 PgTableMask; @@ -584,81 +605,84 @@ SetMemoryEncDec ( (Mode =3D=3D SetCBit) ? "Encrypt" : "Decrypt", (UINT32)CacheFlush )); =20 // // Check if we have a valid memory encryption mask // AddressEncMask =3D GetMemEncryptionAddressMask (); if (!AddressEncMask) { return RETURN_ACCESS_DENIED; } =20 PgTableMask =3D AddressEncMask | EFI_PAGE_MASK; =20 if (Length =3D=3D 0) { return RETURN_INVALID_PARAMETER; } =20 // // We are going to change the memory encryption attribute from C=3D0 -> = C=3D1 or - // vice versa Flush the caches to ensure that data is written into memor= y with - // correct C-bit + // vice versa Flush the caches to ensure that data is written into memory + // with correct C-bit // if (CacheFlush) { WriteBackInvalidateDataCacheRange((VOID*) (UINTN)PhysicalAddress, Leng= th); } =20 // // Make sure that the page table is changeable. // IsWpEnabled =3D IsReadOnlyPageWriteProtected (); if (IsWpEnabled) { DisableReadOnlyPageWriteProtect (); } =20 Status =3D EFI_SUCCESS; =20 while (Length) { // // If Cr3BaseAddress is not specified then read the current CR3 // if (Cr3BaseAddress =3D=3D 0) { Cr3BaseAddress =3D AsmReadCr3(); } =20 PageMapLevel4Entry =3D (VOID*) (Cr3BaseAddress & ~PgTableMask); PageMapLevel4Entry +=3D PML4_OFFSET(PhysicalAddress); if (!PageMapLevel4Entry->Bits.Present) { DEBUG (( DEBUG_ERROR, "%a:%a: bad PML4 for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); Status =3D RETURN_NO_MAPPING; goto Done; } =20 - PageDirectory1GEntry =3D (VOID*) ((PageMapLevel4Entry->Bits.PageTableB= aseAddress<<12) & ~PgTableMask); + PageDirectory1GEntry =3D (VOID *)( + (PageMapLevel4Entry->Bits.PageTableBaseAddres= s << + 12) & ~PgTableMask + ); PageDirectory1GEntry +=3D PDP_OFFSET(PhysicalAddress); if (!PageDirectory1GEntry->Bits.Present) { DEBUG (( DEBUG_ERROR, "%a:%a: bad PDPE for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); Status =3D RETURN_NO_MAPPING; goto Done; } =20 // // If the MustBe1 bit is not 1, it's not actually a 1GB entry // if (PageDirectory1GEntry->Bits.MustBe1) { // // Valid 1GB page // If we have at least 1GB to go, we can just update this entry @@ -668,90 +692,110 @@ SetMemoryEncDec ( DEBUG (( DEBUG_VERBOSE, "%a:%a: updated 1GB entry for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); PhysicalAddress +=3D BIT30; Length -=3D BIT30; } else { // // We must split the page // DEBUG (( DEBUG_VERBOSE, "%a:%a: splitting 1GB page for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); - Split1GPageTo2M(((UINT64)PageDirectory1GEntry->Bits.PageTableBaseA= ddress)<<30, (UINT64*) PageDirectory1GEntry, 0, 0); + Split1GPageTo2M ( + (UINT64)PageDirectory1GEntry->Bits.PageTableBaseAddress << 30, + (UINT64 *)PageDirectory1GEntry, + 0, + 0 + ); continue; } } else { // // Actually a PDP // - PageUpperDirectoryPointerEntry =3D (PAGE_MAP_AND_DIRECTORY_POINTER*)= PageDirectory1GEntry; - PageDirectory2MEntry =3D (VOID*) ((PageUpperDirectoryPointerEntry->B= its.PageTableBaseAddress<<12) & ~PgTableMask); + PageUpperDirectoryPointerEntry =3D + (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory1GEntry; + PageDirectory2MEntry =3D + (VOID *)( + (PageUpperDirectoryPointerEntry->Bits.PageTableBaseAddress << + 12) & ~PgTableMask + ); PageDirectory2MEntry +=3D PDE_OFFSET(PhysicalAddress); if (!PageDirectory2MEntry->Bits.Present) { DEBUG (( DEBUG_ERROR, "%a:%a: bad PDE for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); Status =3D RETURN_NO_MAPPING; goto Done; } // // If the MustBe1 bit is not a 1, it's not a 2MB entry // if (PageDirectory2MEntry->Bits.MustBe1) { // // Valid 2MB page // If we have at least 2MB left to go, we can just update this ent= ry // if (!(PhysicalAddress & (BIT21-1)) && Length >=3D BIT21) { SetOrClearCBit (&PageDirectory2MEntry->Uint64, Mode); PhysicalAddress +=3D BIT21; Length -=3D BIT21; } else { // // We must split up this page into 4K pages // DEBUG (( DEBUG_VERBOSE, "%a:%a: splitting 2MB page for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); - Split2MPageTo4K (((UINT64)PageDirectory2MEntry->Bits.PageTableBa= seAddress) << 21, (UINT64*) PageDirectory2MEntry, 0, 0); + Split2MPageTo4K ( + (UINT64)PageDirectory2MEntry->Bits.PageTableBaseAddress << 21, + (UINT64 *)PageDirectory2MEntry, + 0, + 0 + ); continue; } } else { - PageDirectoryPointerEntry =3D (PAGE_MAP_AND_DIRECTORY_POINTER*) Pa= geDirectory2MEntry; - PageTableEntry =3D (VOID*) (PageDirectoryPointerEntry->Bits.PageTa= bleBaseAddress<<12 & ~PgTableMask); + PageDirectoryPointerEntry =3D + (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory2MEntry; + PageTableEntry =3D + (VOID *)( + (PageDirectoryPointerEntry->Bits.PageTableBaseAddress << + 12) & ~PgTableMask + ); PageTableEntry +=3D PTE_OFFSET(PhysicalAddress); if (!PageTableEntry->Bits.Present) { DEBUG (( DEBUG_ERROR, "%a:%a: bad PTE for Physical=3D0x%Lx\n", gEfiCallerBaseName, __FUNCTION__, PhysicalAddress )); Status =3D RETURN_NO_MAPPING; goto Done; } SetOrClearCBit (&PageTableEntry->Uint64, Mode); PhysicalAddress +=3D EFI_PAGE_SIZE; Length -=3D EFI_PAGE_SIZE; } } } =20 // @@ -771,66 +815,78 @@ Done: // // Restore page table write protection, if any. // if (IsWpEnabled) { EnableReadOnlyPageWriteProtect (); } =20 return Status; } =20 /** This function clears memory encryption bit for the memory region specifi= ed by PhysicalAddress and length from the current page table context. =20 @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory - region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is - not supported + @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryDecrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN BOOLEAN Flush ) { =20 - return SetMemoryEncDec (Cr3BaseAddress, PhysicalAddress, Length, ClearCB= it, Flush); + return SetMemoryEncDec ( + Cr3BaseAddress, + PhysicalAddress, + Length, + ClearCBit, + Flush + ); } =20 /** This function sets memory encryption bit for the memory region specified= by PhysicalAddress and length from the current page table context. =20 - @param[in] PhysicalAddress The physical address that is the sta= rt address - of a memory region. + @param[in] PhysicalAddress The physical address that is the sta= rt + address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the = memory - region. + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is - not supported + @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryEncrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN BOOLEAN Flush ) { - return SetMemoryEncDec (Cr3BaseAddress, PhysicalAddress, Length, SetCBit= , Flush); + return SetMemoryEncDec ( + Cr3BaseAddress, + PhysicalAddress, + Length, + SetCBit, + Flush + ); } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949062445370.05112821396995; Thu, 1 Mar 2018 16:04:22 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E615722485A9D; Thu, 1 Mar 2018 15:58:09 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7508D22485A98 for ; Thu, 1 Mar 2018 15:58:08 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A46EF410FBA1; Fri, 2 Mar 2018 00:04:16 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id BFD9C10AF9D2; Fri, 2 Mar 2018 00:04:15 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:50 +0100 Message-Id: <20180302000408.14201-3-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:16 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:16 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 02/20] OvmfPkg/MemEncryptSevLib: clean up MemEncryptSevIsEnabled() decl X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The declaration and the definition(s) of the function should have identical leading comments and/or identical parameter lists. Also remove any excess space in the comment block, and unindent the trailing "**/" if necessary. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Include/Library/MemEncryptSevLib.h | 4 ++-- OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index 4f3ba9f22cb4..88b272ebedef 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -5,43 +5,43 @@ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #ifndef _MEM_ENCRYPT_SEV_LIB_H_ #define _MEM_ENCRYPT_SEV_LIB_H_ =20 #include =20 /** Returns a boolean to indicate whether SEV is enabled =20 - @retval TRUE SEV is active + @retval TRUE SEV is enabled @retval FALSE SEV is not enabled - **/ +**/ BOOLEAN EFIAPI MemEncryptSevIsEnabled ( VOID ); =20 /** This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and Number of pages from the current page table context. =20 @param[in] BaseAddress The physical address that is the start address of a memory region. @param[in] NumberOfPages The number of pages from start memory region. @param[in] Flush Flush the caches before clearing the b= it (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were cleared for the me= mory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.= c b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c index ff561236d819..44c2c98a6afc 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c @@ -50,41 +50,40 @@ InternalMemEncryptSevIsEnabled ( // // CPUID Fn8000_001F[EAX] Bit 1 (Sev supported) // AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax.Uint32, NULL, NULL, NULL); =20 if (Eax.Bits.SevBit) { // // Check MSR_0xC0010131 Bit 0 (Sev Enabled) // Msr.Uint32 =3D AsmReadMsr32 (MSR_SEV_STATUS); if (Msr.Bits.SevBit) { return TRUE; } } } =20 return FALSE; } =20 /** - Returns a boolean to indicate whether SEV is enabled =20 @retval TRUE SEV is enabled @retval FALSE SEV is not enabled - **/ +**/ BOOLEAN EFIAPI MemEncryptSevIsEnabled ( VOID ) { if (mSevStatusChecked) { return mSevStatus; } =20 mSevStatus =3D InternalMemEncryptSevIsEnabled(); mSevStatusChecked =3D TRUE; =20 return mSevStatus; } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949065672332.88579719002473; Thu, 1 Mar 2018 16:04:25 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6A8F0224E6916; Thu, 1 Mar 2018 15:58:11 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 80ADB22485A98 for ; Thu, 1 Mar 2018 15:58:09 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CDF198182D2E; Fri, 2 Mar 2018 00:04:17 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id E749610AF9D2; Fri, 2 Mar 2018 00:04:16 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:51 +0100 Message-Id: <20180302000408.14201-4-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Fri, 02 Mar 2018 00:04:17 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Fri, 02 Mar 2018 00:04:17 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 03/20] OvmfPkg/MemEncryptSevLib: clean up MemEncryptSevClearPageEncMask() decl X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The declaration and the definition(s) of the function should have identical leading comments and/or identical parameter lists. Also remove any excess space in the comment block, and unindent the trailing "**/" if necessary. Correct several parameter references. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Include/Library/MemEncryptSevLib.h | 34 ++++++++= +++--------- OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 34 ++++++++= ++---------- OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c | 7 ++-- 3 files changed, 38 insertions(+), 37 deletions(-) diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index 88b272ebedef..2d574dd30676 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -15,63 +15,65 @@ **/ =20 #ifndef _MEM_ENCRYPT_SEV_LIB_H_ #define _MEM_ENCRYPT_SEV_LIB_H_ =20 #include =20 /** Returns a boolean to indicate whether SEV is enabled =20 @retval TRUE SEV is enabled @retval FALSE SEV is not enabled **/ BOOLEAN EFIAPI MemEncryptSevIsEnabled ( VOID ); =20 /** - This function clears memory encryption bit for the memory region specifi= ed - by BaseAddress and Number of pages from the current page table context. + This function clears memory encryption bit for the memory region specifi= ed by + BaseAddress and NumPages from the current page table context. =20 - @param[in] BaseAddress The physical address that is the start - address of a memory region. - @param[in] NumberOfPages The number of pages from start memory - region. - @param[in] Flush Flush the caches before clearing the b= it - (mostly TRUE except MMIO addresses) + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + @param[in] Flush Flush the caches before clearing the= bit + (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the me= mory - region. - @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not - supported - **/ + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported +**/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, - IN UINTN NumberOfPages, - IN BOOLEAN CacheFlush + IN UINTN NumPages, + IN BOOLEAN Flush ); =20 /** This function sets memory encryption bit for the memory region specified= by BaseAddress and Number of pages from the current page table context. =20 @param[in] BaseAddress The physical address that is the start address of a memory region. @param[in] NumberOfPages The number of pages from start memory region. @param[in] Flush Flush the caches before clearing the b= it (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were set for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not supported **/ RETURN_STATUS diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c b= /OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c index d1130df2d0e7..d6067c52aacd 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c @@ -5,64 +5,64 @@ Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include #include #include #include #include =20 /** - This function clears memory encryption bit for the memory region specifi= ed - by BaseAddress and Number of pages from the current page table context. + This function clears memory encryption bit for the memory region specifi= ed by + BaseAddress and NumPages from the current page table context. =20 - @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent - CR3) - @param[in] BaseAddress The physical address that is the start - address of a memory region. - @param[in] NumberOfPages The number of pages from start memory - region. - @param[in] Flush Flush the caches before clearing the b= it - (mostly TRUE except MMIO addresses) + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + @param[in] Flush Flush the caches before clearing the= bit + (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the me= mory - region. - @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not - supported - **/ + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported +**/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, - IN UINTN NumberOfPages, + IN UINTN NumPages, IN BOOLEAN Flush ) { // // Memory encryption bit is not accessible in 32-bit mode // return RETURN_UNSUPPORTED; } =20 /** This function sets memory encryption bit for the memory region specified= by BaseAddress and Number of pages from the current page table context. =20 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent CR3) @param[in] BaseAddress The physical address that is the start address of a memory region. @param[in] NumberOfPages The number of pages from start memory region. @param[in] Flush Flush the caches before clearing the b= it diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c b/= OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c index 4b7fdf7d044d..5b8bc737645c 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c @@ -7,59 +7,58 @@ This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include #include #include #include #include =20 #include "VirtualMemory.h" =20 /** - This function clears memory encryption bit for the memory region specifi= ed by - BaseAddress and Number of pages from the current page table context. + BaseAddress and NumPages from the current page table context. =20 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3) @param[in] BaseAddress The physical address that is the sta= rt address of a memory region. - @param[in] NumberOfPages The number of pages from start memory + @param[in] NumPages The number of pages from start memory region. @param[in] Flush Flush the caches before clearing the= bit (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute is not supported - **/ +**/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ) { return InternalMemEncryptSevSetMemoryDecrypted ( Cr3BaseAddress, BaseAddress, EFI_PAGES_TO_SIZE (NumPages), Flush ); } =20 /** =20 This function clears memory encryption bit for the memory region specifi= ed by --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949068633725.5628570705551; Thu, 1 Mar 2018 16:04:28 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E0C35224E692F; Thu, 1 Mar 2018 15:58:11 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A20B0224E6906 for ; Thu, 1 Mar 2018 15:58:10 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 036044084FEC; Fri, 2 Mar 2018 00:04:19 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1D0A010AF9F5; Fri, 2 Mar 2018 00:04:17 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:52 +0100 Message-Id: <20180302000408.14201-5-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:19 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:19 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 04/20] OvmfPkg/MemEncryptSevLib: clean up MemEncryptSevSetPageEncMask() decl X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The declaration and the definition(s) of the function should have identical leading comments and/or identical parameter lists. Replace any leftover "clear" references to the C-bit with "set" references. Also remove any excess space in the comment block, and unindent the trailing "**/" if necessary. Correct several parameter references. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Include/Library/MemEncryptSevLib.h | 32 ++++++++= +++--------- OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 32 ++++++++= ++---------- OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c | 17 +++++---= --- 3 files changed, 41 insertions(+), 40 deletions(-) diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index 2d574dd30676..e5ebb4401818 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -44,44 +44,46 @@ MemEncryptSevIsEnabled ( @param[in] Flush Flush the caches before clearing the= bit (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute is not supported **/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ); =20 /** This function sets memory encryption bit for the memory region specified= by - BaseAddress and Number of pages from the current page table context. + BaseAddress and NumPages from the current page table context. =20 - @param[in] BaseAddress The physical address that is the start - address of a memory region. - @param[in] NumberOfPages The number of pages from start memory - region. - @param[in] Flush Flush the caches before clearing the b= it - (mostly TRUE except MMIO addresses) + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + @param[in] Flush Flush the caches before setting the = bit + (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were set for the memory - region. - @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not - supported - **/ + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute + is not supported +**/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, - IN UINTN NumberOfPages, - IN BOOLEAN CacheFlush + IN UINTN NumPages, + IN BOOLEAN Flush ); #endif // _MEM_ENCRYPT_SEV_LIB_H_ diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c b= /OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c index d6067c52aacd..614c97b23bb6 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c @@ -40,51 +40,51 @@ @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute is not supported **/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ) { // // Memory encryption bit is not accessible in 32-bit mode // return RETURN_UNSUPPORTED; } =20 /** This function sets memory encryption bit for the memory region specified= by - BaseAddress and Number of pages from the current page table context. + BaseAddress and NumPages from the current page table context. =20 - @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use cur= rent - CR3) - @param[in] BaseAddress The physical address that is the start - address of a memory region. - @param[in] NumberOfPages The number of pages from start memory - region. - @param[in] Flush Flush the caches before clearing the b= it - (mostly TRUE except MMIO addresses) + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + @param[in] Flush Flush the caches before setting the = bit + (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were set for the memory - region. - @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing memory encryption attribute i= s not - supported - **/ + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute + is not supported +**/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, - IN UINTN NumberOfPages, + IN UINTN NumPages, IN BOOLEAN Flush ) { // // Memory encryption bit is not accessible in 32-bit mode // return RETURN_UNSUPPORTED; } diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c b/= OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c index 5b8bc737645c..f165722ae550 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c @@ -43,55 +43,54 @@ is not supported **/ RETURN_STATUS EFIAPI MemEncryptSevClearPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ) { return InternalMemEncryptSevSetMemoryDecrypted ( Cr3BaseAddress, BaseAddress, EFI_PAGES_TO_SIZE (NumPages), Flush ); } =20 /** - - This function clears memory encryption bit for the memory region specifi= ed by - BaseAddress and Number of pages from the current page table context. + This function sets memory encryption bit for the memory region specified= by + BaseAddress and NumPages from the current page table context. =20 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3) @param[in] BaseAddress The physical address that is the sta= rt address of a memory region. - @param[in] NumberOfPages The number of pages from start memory + @param[in] NumPages The number of pages from start memory region. - @param[in] Flush Flush the caches before clearing the= bit + @param[in] Flush Flush the caches before setting the = bit (mostly TRUE except MMIO addresses) =20 - @retval RETURN_SUCCESS The attributes were cleared for the - memory region. + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute is not supported - **/ +**/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ) { return InternalMemEncryptSevSetMemoryEncrypted ( Cr3BaseAddress, BaseAddress, EFI_PAGES_TO_SIZE (NumPages), Flush ); } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949071232191.46048037612115; Thu, 1 Mar 2018 16:04:31 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 52CA322546B90; Thu, 1 Mar 2018 15:58:13 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1A98224E692B for ; Thu, 1 Mar 2018 15:58:11 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2BA76410FBA1; Fri, 2 Mar 2018 00:04:20 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 45FFE10B0F24; Fri, 2 Mar 2018 00:04:19 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:53 +0100 Message-Id: <20180302000408.14201-6-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:20 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:20 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 05/20] OvmfPkg/MemEncryptSevLib: clean up SetMemoryEncDec() comment block X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Document the "Cr3BaseAddress" parameter, and correct several parameter references. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c index 65b8babaac44..aed92127629f 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c @@ -531,55 +531,57 @@ DisableReadOnlyPageWriteProtect ( VOID ) { AsmWriteCr0 (AsmReadCr0() & ~BIT16); } =20 /** Enable Write Protect on pages marked as read-only. **/ VOID EnableReadOnlyPageWriteProtect ( VOID ) { AsmWriteCr0 (AsmReadCr0() | BIT16); } =20 =20 /** This function either sets or clears memory encryption bit for the memory - region specified by PhysicalAddress and length from the current page tab= le + region specified by PhysicalAddress and Length from the current page tab= le context. =20 - The function iterates through the physicalAddress one page at a time, an= d set + The function iterates through the PhysicalAddress one page at a time, an= d set or clears the memory encryption mask in the page table. If it encounters that a given physical address range is part of large page then it attemp= ts to change the attribute at one go (based on size), otherwise it splits the large pages into smaller (e.g 2M page into 4K pages) and then try to set= or clear the encryption bit on the smallest page size. =20 + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Mode Set or Clear mode - @param[in] Flush Flush the caches before applying the + @param[in] CacheFlush Flush the caches before applying the encryption mask =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is not supported **/ =20 STATIC RETURN_STATUS EFIAPI SetMemoryEncDec ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN MAP_RANGE_MODE Mode, IN BOOLEAN CacheFlush ) { --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949073967809.9233981692008; Thu, 1 Mar 2018 16:04:33 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B79C722546B99; Thu, 1 Mar 2018 15:58:14 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01AFD224E692B for ; Thu, 1 Mar 2018 15:58:12 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 52F6A410FBA2; Fri, 2 Mar 2018 00:04:21 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6E13F10B0F24; Fri, 2 Mar 2018 00:04:20 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:54 +0100 Message-Id: <20180302000408.14201-7-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:21 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:21 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 06/20] OvmfPkg/MemEncryptSevLib: clean up InternalMemEncryptSevSetMemoryDecrypted() decl X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The declaration and the definition(s) of the function should have identical leading comments and/or identical parameter lists. Document the "Cr3BaseAddress" parameter, and correct several parameter references. Replace a "set" reference to the C-bit with a "clear" reference. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h | 14 ++++++++----= -- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c | 6 ++++-- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h index 7dd1bbe0eb26..646a9781d04a 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h @@ -171,61 +171,63 @@ typedef union { #define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK) #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull =20 #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB #define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB #define PAGE_TABLE_POOL_UNIT_PAGES \ EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE) #define PAGE_TABLE_POOL_ALIGN_MASK \ (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1)) =20 typedef struct { VOID *NextPool; UINTN Offset; UINTN FreePages; } PAGE_TABLE_POOL; =20 =20 =20 /** This function clears memory encryption bit for the memory region specifi= ed by - PhysicalAddress and length from the current page table context. + PhysicalAddress and Length from the current page table context. =20 + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + @retval RETURN_UNSUPPORTED Clearing the memory encyrption attri= bute is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryDecrypted ( - IN PHYSICAL_ADDRESS Cr3BaseAddress, - IN PHYSICAL_ADDRESS PhysicalAddress, - IN UINT64 Length, - IN BOOLEAN CacheFlush + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS PhysicalAddress, + IN UINTN Length, + IN BOOLEAN Flush ); =20 /** This function sets memory encryption bit for the memory region specified= by PhysicalAddress and length from the current page table context. =20 @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is not supported **/ RETURN_STATUS EFIAPI diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c index aed92127629f..3f7704801c9c 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c @@ -809,52 +809,54 @@ SetMemoryEncDec ( } =20 // // Flush TLB // CpuFlushTlb(); =20 Done: // // Restore page table write protection, if any. // if (IsWpEnabled) { EnableReadOnlyPageWriteProtect (); } =20 return Status; } =20 /** This function clears memory encryption bit for the memory region specifi= ed by - PhysicalAddress and length from the current page table context. + PhysicalAddress and Length from the current page table context. =20 + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. - @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + @retval RETURN_UNSUPPORTED Clearing the memory encyrption attri= bute is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryDecrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN BOOLEAN Flush ) { =20 return SetMemoryEncDec ( Cr3BaseAddress, PhysicalAddress, Length, ClearCBit, Flush ); } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949076834939.4642704583971; Thu, 1 Mar 2018 16:04:36 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1EBE722546B9F; Thu, 1 Mar 2018 15:58:17 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5DD54224E6923 for ; Thu, 1 Mar 2018 15:58:14 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7B5F2410FBA3; Fri, 2 Mar 2018 00:04:22 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 95F5C10B0F24; Fri, 2 Mar 2018 00:04:21 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:55 +0100 Message-Id: <20180302000408.14201-8-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:22 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:22 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 07/20] OvmfPkg/MemEncryptSevLib: clean up InternalMemEncryptSevSetMemoryEncrypted() decl X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The declaration and the definition(s) of the function should have identical leading comments and/or identical parameter lists. Document the "Cr3BaseAddress" parameter, and correct several parameter references. Replace a "clear" reference to the C-bit with a "set" reference. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h | 16 +++++++++---= ---- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c | 8 +++++--- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h index 646a9781d04a..67ff69122d73 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h @@ -198,44 +198,46 @@ typedef struct { @param[in] Flush Flush the caches before applying the encryption mask =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing the memory encyrption attri= bute is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryDecrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN BOOLEAN Flush ); =20 /** This function sets memory encryption bit for the memory region specified= by - PhysicalAddress and length from the current page table context. + PhysicalAddress and Length from the current page table context. =20 + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the - memory region. + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryEncrypted ( - IN PHYSICAL_ADDRESS Cr3BaseAddress, - IN PHYSICAL_ADDRESS PhysicalAddress, - IN UINT64 Length, - IN BOOLEAN CacheFlush + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS PhysicalAddress, + IN UINTN Length, + IN BOOLEAN Flush ); =20 #endif diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c index 3f7704801c9c..39b246048f1f 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c @@ -846,50 +846,52 @@ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryDecrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN BOOLEAN Flush ) { =20 return SetMemoryEncDec ( Cr3BaseAddress, PhysicalAddress, Length, ClearCBit, Flush ); } =20 /** This function sets memory encryption bit for the memory region specified= by - PhysicalAddress and length from the current page table context. + PhysicalAddress and Length from the current page table context. =20 + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) @param[in] PhysicalAddress The physical address that is the sta= rt address of a memory region. @param[in] Length The length of memory region @param[in] Flush Flush the caches before applying the encryption mask =20 - @retval RETURN_SUCCESS The attributes were cleared for the - memory region. + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute is not supported **/ RETURN_STATUS EFIAPI InternalMemEncryptSevSetMemoryEncrypted ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS PhysicalAddress, IN UINTN Length, IN BOOLEAN Flush ) { return SetMemoryEncDec ( Cr3BaseAddress, PhysicalAddress, Length, SetCBit, Flush ); --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949079516961.9718241070301; Thu, 1 Mar 2018 16:04:39 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7614122485A9C; Thu, 1 Mar 2018 15:58:17 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 646DE224E6923 for ; Thu, 1 Mar 2018 15:58:15 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A6D4D87ABA; Fri, 2 Mar 2018 00:04:23 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id BE87810B0F24; Fri, 2 Mar 2018 00:04:22 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:56 +0100 Message-Id: <20180302000408.14201-9-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Fri, 02 Mar 2018 00:04:23 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Fri, 02 Mar 2018 00:04:23 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 08/20] OvmfPkg/MemEncryptSevLib: sort #includes, and entries in INF file sections X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf | 6 +++--- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h | 4 ++-- OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 4 ++-- OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c | 4 ++-- OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c | 4 ++-- OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf = b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf index 81b075194ace..2f0a2392a7ad 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf @@ -14,40 +14,40 @@ # # ## =20 [Defines] INF_VERSION =3D 1.25 BASE_NAME =3D MemEncryptSevLib FILE_GUID =3D c1594631-3888-4be4-949f-9c630dbc842b MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D MemEncryptSevLib|PEIM DXE_DRIVER DXE_= RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER =20 # # The following information is for reference only and not required by the = build # tools. # # VALID_ARCHITECTURES =3D IA32 X64 # =20 [Packages] - MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [Sources.X64] MemEncryptSevLibInternal.c X64/MemEncryptSevLib.c X64/VirtualMemory.c =20 [Sources.IA32] - MemEncryptSevLibInternal.c Ia32/MemEncryptSevLib.c + MemEncryptSevLibInternal.c =20 [LibraryClasses] BaseLib - CpuLib CacheMaintenanceLib + CpuLib DebugLib MemoryAllocationLib diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h index 67ff69122d73..95a08f3558e9 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h @@ -3,47 +3,47 @@ Virtual Memory Management Services to set or clear the memory encryption= bit =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h =20 **/ =20 #ifndef __VIRTUAL_MEMORY__ #define __VIRTUAL_MEMORY__ =20 -#include #include #include +#include #include #include +#include =20 -#include #define SYS_CODE64_SEL 0x38 =20 #pragma pack(1) =20 // // Page-Map Level-4 Offset (PML4) and // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB // =20 typedef union { struct { UINT64 Present:1; // 0 =3D Not present in memory, // 1 =3D Present in memory UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser UINT64 WriteThrough:1; // 0 =3D Write-Back caching, // 1 =3D Write-Through caching UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached UINT64 Accessed:1; // 0 =3D Not accessed, // 1 =3D Accessed (set by CPU) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c b= /OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c index 614c97b23bb6..5d909c17b0bc 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c @@ -1,42 +1,42 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include -#include +#include #include #include -#include +#include =20 /** This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and NumPages from the current page table context. =20 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3) @param[in] BaseAddress The physical address that is the sta= rt address of a memory region. @param[in] NumPages The number of pages from start memory region. @param[in] Flush Flush the caches before clearing the= bit (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute is not supported **/ diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.= c b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c index 44c2c98a6afc..7078ab0d3f46 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c @@ -1,42 +1,42 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include -#include +#include #include #include -#include +#include =20 STATIC BOOLEAN mSevStatus =3D FALSE; STATIC BOOLEAN mSevStatusChecked =3D FALSE; =20 /** =20 Returns a boolean to indicate whether SEV is enabled =20 @retval TRUE SEV is enabled @retval FALSE SEV is not enabled **/ STATIC BOOLEAN EFIAPI InternalMemEncryptSevIsEnabled ( VOID ) { UINT32 RegEax; MSR_SEV_STATUS_REGISTER Msr; diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c b/= OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c index f165722ae550..62059242fc79 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c @@ -1,42 +1,42 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include -#include +#include #include #include -#include +#include =20 #include "VirtualMemory.h" =20 /** This function clears memory encryption bit for the memory region specifi= ed by BaseAddress and NumPages from the current page table context. =20 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use current CR3) @param[in] BaseAddress The physical address that is the sta= rt address of a memory region. @param[in] NumPages The number of pages from start memory region. @param[in] Flush Flush the caches before clearing the= bit (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were cleared for the memory region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c b/Ovm= fPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c index 39b246048f1f..c1bfa35d7a30 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c @@ -1,42 +1,42 @@ /** @file =20 Virtual Memory Management Services to set or clear the memory encryption= bit =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c =20 **/ =20 #include -#include #include +#include =20 #include "VirtualMemory.h" =20 STATIC BOOLEAN mAddressEncMaskChecked =3D FALSE; STATIC UINT64 mAddressEncMask; STATIC PAGE_TABLE_POOL *mPageTablePool =3D NULL; =20 typedef enum { SetCBit, ClearCBit } MAP_RANGE_MODE; =20 /** Get the memory encryption mask =20 @param[out] EncryptionMask contains the pte mask. =20 **/ STATIC UINT64 --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949082258358.5921336103196; Thu, 1 Mar 2018 16:04:42 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D61B02255D6C2; Thu, 1 Mar 2018 15:58:19 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8F55A224E6923 for ; Thu, 1 Mar 2018 15:58:16 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id DD682404084B; Fri, 2 Mar 2018 00:04:24 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id EA26510B0F24; Fri, 2 Mar 2018 00:04:23 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:57 +0100 Message-Id: <20180302000408.14201-10-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:24 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:24 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 09/20] OvmfPkg/PlatformPei: sort #includes in "AmdSev.c" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" No functional changes. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/PlatformPei/AmdSev.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index ad31b69fb032..1509f260fb0b 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -1,44 +1,43 @@ /**@file Initialize Secure Encrypted Virtualization (SEV) support =20 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the licen= se may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ // // The package level header files this module uses // -#include - #include +#include #include -#include +#include #include -#include +#include =20 #include "Platform.h" =20 /** =20 Function checks if SEV support is available, if present then it sets the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption m= ask. =20 **/ VOID AmdSevInitialize ( VOID ) { CPUID_MEMORY_ENCRYPTION_INFO_EBX Ebx; UINT64 EncryptionMask; RETURN_STATUS PcdStatus; =20 // // Check if SEV is enabled --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949084874643.923854246169; Thu, 1 Mar 2018 16:04:44 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 49DBC2255D6CA; Thu, 1 Mar 2018 15:58:20 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D921722546BBE for ; Thu, 1 Mar 2018 15:58:17 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3AE4D410FBA1; Fri, 2 Mar 2018 00:04:26 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2C5C610B0F24; Fri, 2 Mar 2018 00:04:25 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:58 +0100 Message-Id: <20180302000408.14201-11-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:26 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Fri, 02 Mar 2018 00:04:26 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 10/20] OvmfPkg/SmmCpuFeaturesLib: rewrap to 79 columns X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are many overlong lines; it's hard to work with the library like this. Rewrap all files to 79 columns. ( The rewrapping of the "mSmmCpuRegisterRanges" and "mSmmCpuWidthOffset" arrays was verified by hexdumping the arrays in SmmCpuFeaturesLibConstructor(), both before and after the patch, and comparing the dumps. Contents of "mSmmCpuRegisterRanges", IA32 build: > mSmmCpuRegisterRanges: { > mSmmCpuRegisterRanges: 000000 04 00 00 00 0A 00 00 00 07 00 00 00 14 00 0= 0 00 > mSmmCpuRegisterRanges: 000010 2E 00 00 00 1B 00 00 00 33 00 00 00 36 00 0= 0 00 > mSmmCpuRegisterRanges: 000020 04 00 00 00 00 00 00 00 00 00 00 00 00 00 0= 0 00 > mSmmCpuRegisterRanges: } Contents of "mSmmCpuRegisterRanges", X64 build: > mSmmCpuRegisterRanges: { > mSmmCpuRegisterRanges: 000000 04 00 00 00 0A 00 00 00 07 00 00 00 00 00 0= 0 00 > mSmmCpuRegisterRanges: 000010 14 00 00 00 2E 00 00 00 1B 00 00 00 00 00 0= 0 00 > mSmmCpuRegisterRanges: 000020 33 00 00 00 36 00 00 00 04 00 00 00 00 00 0= 0 00 > mSmmCpuRegisterRanges: 000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0= 0 00 > mSmmCpuRegisterRanges: } Contents of "mSmmCpuWidthOffset", both IA32 and X64 builds: > mSmmCpuWidthOffset: { > mSmmCpuWidthOffset: 000000 00 00 00 00 00 00 00 00 00 00 00 08 00 00 68 02 > mSmmCpuWidthOffset: 000010 6C 02 00 00 00 08 00 00 88 02 8C 02 00 00 00 08 > mSmmCpuWidthOffset: 000020 00 00 78 02 7C 02 00 00 00 00 00 00 64 02 68 02 > mSmmCpuWidthOffset: 000030 00 00 00 00 00 00 84 02 88 02 00 00 00 00 00 00 > mSmmCpuWidthOffset: 000040 74 02 78 02 00 00 00 00 00 00 00 00 04 00 00 00 > mSmmCpuWidthOffset: 000050 04 04 A8 03 00 02 00 00 00 00 04 04 AC 03 10 02 > mSmmCpuWidthOffset: 000060 00 00 00 00 04 04 B0 03 20 02 00 00 00 00 04 04 > mSmmCpuWidthOffset: 000070 B4 03 30 02 00 00 00 00 04 04 B8 03 40 02 00 00 > mSmmCpuWidthOffset: 000080 00 00 04 04 BC 03 50 02 00 00 00 00 00 04 00 00 > mSmmCpuWidthOffset: 000090 70 02 00 00 00 00 04 04 C4 03 90 02 00 00 00 00 > mSmmCpuWidthOffset: 0000A0 04 08 C8 03 60 03 64 03 00 00 04 08 CC 03 68 03 > mSmmCpuWidthOffset: 0000B0 6C 03 00 00 00 08 00 00 B8 03 BC 03 01 00 00 08 > mSmmCpuWidthOffset: 0000C0 00 00 B0 03 B4 03 01 00 00 08 00 00 A8 03 AC 03 > mSmmCpuWidthOffset: 0000D0 01 00 00 08 00 00 A0 03 A4 03 01 00 00 08 00 00 > mSmmCpuWidthOffset: 0000E0 98 03 9C 03 01 00 00 08 00 00 90 03 94 03 01 00 > mSmmCpuWidthOffset: 0000F0 00 08 00 00 88 03 8C 03 01 00 00 08 00 00 80 03 > mSmmCpuWidthOffset: 000100 84 03 01 00 04 08 D0 03 F8 03 FC 03 01 00 04 08 > mSmmCpuWidthOffset: 000110 DC 03 E0 03 E4 03 01 00 04 08 D4 03 F0 03 F4 03 > mSmmCpuWidthOffset: 000120 01 00 04 08 D8 03 E8 03 EC 03 01 00 04 08 E0 03 > mSmmCpuWidthOffset: 000130 D8 03 DC 03 01 00 04 08 E4 03 D0 03 D4 03 01 00 > mSmmCpuWidthOffset: 000140 04 08 E8 03 C8 03 CC 03 01 00 04 08 EC 03 C0 03 > mSmmCpuWidthOffset: 000150 C4 03 01 00 04 08 F0 03 78 03 7C 03 01 00 04 08 > mSmmCpuWidthOffset: 000160 F4 03 70 03 74 03 01 00 04 08 FC 03 58 03 5C 03 > mSmmCpuWidthOffset: 000170 00 00 04 08 F8 03 50 03 54 03 00 00 00 04 00 00 > mSmmCpuWidthOffset: 000180 48 03 4C 03 00 00 > mSmmCpuWidthOffset: } ) Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 10 +- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 594 ++++++++++++= ++++---- 2 files changed, 489 insertions(+), 115 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 31edf3a9c1fd..75b24606b9df 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -1,31 +1,33 @@ ## @file # The CPU specific programming for PiSmmCpuDxeSmm module. # # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at # http://opensource.org/licenses/bsd-license.php # # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. # ## =20 [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D SmmCpuFeaturesLib MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni FILE_GUID =3D AC9991BE-D77A-464C-A8DE-A873DB8A4836 MODULE_TYPE =3D DXE_SMM_DRIVER VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SmmCpuFeaturesLib CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor =20 [Sources] SmmCpuFeaturesLib.c =20 [Packages] MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index a307f64c9c61..a876a6e34751 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -1,32 +1,32 @@ /** @file -The CPU specific programming for PiSmmCpuDxeSmm module. + The CPU specific programming for PiSmmCpuDxeSmm module. =20 -Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
-This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD = License -which accompanies this distribution. The full text of the license may be = found at -http://opensource.org/licenses/bsd-license.php + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
=20 -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ =20 #include #include #include #include #include #include #include #include #include =20 // // EFER register LMA bit // #define LMA BIT10 =20 /** The constructor function =20 @@ -70,95 +70,99 @@ SmmCpuFeaturesLibConstructor ( @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMAT= ION structures. ProcessorInfo[CpuIndex] contains= the information for the currently executing CPU. @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure th= at contains the ApidId and SmBase arrays. **/ VOID EFIAPI SmmCpuFeaturesInitializeProcessor ( IN UINTN CpuIndex, IN BOOLEAN IsMonarch, IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, IN CPU_HOT_PLUG_DATA *CpuHotPlugData ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuState; =20 // // Configure SMBASE. // - CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + S= MRAM_SAVE_STATE_MAP_OFFSET); + CpuState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)(UINTN)( + SMM_DEFAULT_SMBASE + + SMRAM_SAVE_STATE_MAP_OFFSET + ); if ((CpuState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; } else { CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; } =20 // // No need to program SMRRs on our virtual platform. // } =20 /** This function updates the SMRAM save state on the currently executing CPU to resume execution at a specific address after an RSM instruction. This function must evaluate the SMRAM save state to determine the execution m= ode the RSM instruction resumes and update the resume execution address with either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start flag in the SMRAM save state must always be cleared. This function retu= rns the value of the instruction pointer from the SMRAM save state that was replaced. If this function returns 0, then the SMRAM save state was not modified. =20 This function is called during the very first SMI on each CPU after SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de to signal that the SMBASE of each CPU has been updated before the default SMBASE address is used for the first SMI to the next CPU. =20 @param[in] CpuIndex The index of the CPU to hook. The v= alue must be between 0 and the NumberOfCp= us - field in the System Management Syste= m Table - (SMST). + field in the System Management System + Table (SMST). @param[in] CpuState Pointer to SMRAM Save State Map for = the currently executing CPU. @param[in] NewInstructionPointer32 Instruction pointer to use if resumi= ng to 32-bit execution mode from 64-bit SM= M. @param[in] NewInstructionPointer Instruction pointer to use if resumi= ng to same execution mode as SMM. =20 @retval 0 This function did modify the SMRAM save state. @retval > 0 The original instruction pointer value from the SMRAM save = state before it was replaced. **/ UINT64 EFIAPI SmmCpuFeaturesHookReturnFromSmm ( IN UINTN CpuIndex, IN SMRAM_SAVE_STATE_MAP *CpuState, IN UINT64 NewInstructionPointer32, IN UINT64 NewInstructionPointer ) { UINT64 OriginalInstructionPointer; - QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP = *)CpuState; + QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; =20 + CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)CpuState; if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { OriginalInstructionPointer =3D (UINT64)CpuSaveState->x86._EIP; CpuSaveState->x86._EIP =3D (UINT32)NewInstructionPointer; // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. // if ((CpuSaveState->x86.AutoHALTRestart & BIT0) !=3D 0) { CpuSaveState->x86.AutoHALTRestart &=3D ~BIT0; } } else { OriginalInstructionPointer =3D CpuSaveState->x64._RIP; if ((CpuSaveState->x64.IA32_EFER & LMA) =3D=3D 0) { CpuSaveState->x64._RIP =3D (UINT32)NewInstructionPointer32; } else { CpuSaveState->x64._RIP =3D (UINT32)NewInstructionPointer; } // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. @@ -174,58 +178,59 @@ SmmCpuFeaturesHookReturnFromSmm ( Hook point in normal execution mode that allows the one CPU that was ele= cted as monarch during System Management Mode initialization to perform addit= ional initialization actions immediately after all of the CPUs have processed = their first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBA= SE into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm(). **/ VOID EFIAPI SmmCpuFeaturesSmmRelocationComplete ( VOID ) { } =20 /** Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is returned, then a custom SMI handler is not provided by this library, and the default SMI handler must be used. =20 @retval 0 Use the default SMI handler. - @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHa= ndler() - The caller is required to allocate enough SMRAM for each CP= U to - support the size of the custom SMI handler. + @retval > 0 Use the SMI handler installed by + SmmCpuFeaturesInstallSmiHandler(). The caller is required to + allocate enough SMRAM for each CPU to support the size of t= he + custom SMI handler. **/ UINTN EFIAPI SmmCpuFeaturesGetSmiHandlerSize ( VOID ) { return 0; } =20 /** - Install a custom SMI handler for the CPU specified by CpuIndex. This fu= nction - is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is gr= eater - than zero and is called by the CPU that was elected as monarch during Sy= stem - Management Mode initialization. + Install a custom SMI handler for the CPU specified by CpuIndex. This + function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a s= ize + is greater than zero and is called by the CPU that was elected as monarch + during System Management Mode initialization. =20 @param[in] CpuIndex The index of the CPU to install the custom SMI han= dler. The value must be between 0 and the NumberOfCpus f= ield in the System Management System Table (SMST). @param[in] SmBase The SMBASE address for the CPU specified by CpuInd= ex. @param[in] SmiStack The stack to use when an SMI is processed by the the CPU specified by CpuIndex. @param[in] StackSize The size, in bytes, if the stack used when an SMI = is processed by the CPU specified by CpuIndex. @param[in] GdtBase The base address of the GDT to use when an SMI is processed by the CPU specified by CpuIndex. @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is processed by the CPU specified by CpuIndex. @param[in] IdtBase The base address of the IDT to use when an SMI is processed by the CPU specified by CpuIndex. @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is processed by the CPU specified by CpuIndex. @param[in] Cr3 The base address of the page tables to use when an= SMI is processed by the CPU specified by CpuIndex. **/ @@ -246,93 +251,93 @@ SmmCpuFeaturesInstallSmiHandler ( } =20 /** Determines if MTRR registers must be configured to set SMRAM cache-abili= ty when executing in System Management Mode. =20 @retval TRUE MTRR registers must be configured to set SMRAM cache-abil= ity. @retval FALSE MTRR registers do not need to be configured to set SMRAM cache-ability. **/ BOOLEAN EFIAPI SmmCpuFeaturesNeedConfigureMtrrs ( VOID ) { return FALSE; } =20 /** - Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigu= reMtrrs() - returns TRUE. + Disable SMRR register if SMRR is supported and + SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE. **/ VOID EFIAPI SmmCpuFeaturesDisableSmrr ( VOID ) { // // No SMRR support, nothing to do // } =20 /** - Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigur= eMtrrs() - returns TRUE. + Enable SMRR register if SMRR is supported and + SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE. **/ VOID EFIAPI SmmCpuFeaturesReenableSmrr ( VOID ) { // // No SMRR support, nothing to do // } =20 /** Processor specific hook point each time a CPU enters System Management M= ode. =20 @param[in] CpuIndex The index of the CPU that has entered SMM. The val= ue must be between 0 and the NumberOfCpus field in the System Management System Table (SMST). **/ VOID EFIAPI SmmCpuFeaturesRendezvousEntry ( IN UINTN CpuIndex ) { // // No SMRR support, nothing to do // } =20 /** Processor specific hook point each time a CPU exits System Management Mo= de. =20 - @param[in] CpuIndex The index of the CPU that is exiting SMM. The valu= e must - be between 0 and the NumberOfCpus field in the Syst= em - Management System Table (SMST). + @param[in] CpuIndex The index of the CPU that is exiting SMM. The value + must be between 0 and the NumberOfCpus field in the + System Management System Table (SMST). **/ VOID EFIAPI SmmCpuFeaturesRendezvousExit ( IN UINTN CpuIndex ) { } =20 /** Check to see if an SMM register is supported by a specified CPU. =20 @param[in] CpuIndex The index of the CPU to check for SMM register supp= ort. The value must be between 0 and the NumberOfCpus fi= eld in the System Management System Table (SMST). @param[in] RegName Identifies the SMM register to check for support. =20 @retval TRUE The SMM register specified by RegName is supported by the= CPU specified by CpuIndex. @retval FALSE The SMM register specified by RegName is not supported by= the @@ -382,263 +387,606 @@ SmmCpuFeaturesGetSmmRegister ( =20 @param[in] CpuIndex The index of the CPU to write the SMM register. The value must be between 0 and the NumberOfCpus field = in the System Management System Table (SMST). @param[in] RegName Identifies the SMM register to write. registers are read-only. @param[in] Value The value to write to the SMM register. **/ VOID EFIAPI SmmCpuFeaturesSetSmmRegister ( IN UINTN CpuIndex, IN SMM_REG_NAME RegName, IN UINT64 Value ) { ASSERT (FALSE); } =20 /// -/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_LOOKUP_ENTRY +/// Macro used to simplify the lookup table entries of type +/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY /// #define SMM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field) =20 /// -/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_REGISTER_RANGE +/// Macro used to simplify the lookup table entries of type +/// CPU_SMM_SAVE_STATE_REGISTER_RANGE /// #define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } =20 /// /// Structure used to describe a range of registers /// typedef struct { EFI_SMM_SAVE_STATE_REGISTER Start; EFI_SMM_SAVE_STATE_REGISTER End; UINTN Length; } CPU_SMM_SAVE_STATE_REGISTER_RANGE; =20 /// /// Structure used to build a lookup table to retrieve the widths and offs= ets /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value /// =20 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1 =20 typedef struct { UINT8 Width32; UINT8 Width64; UINT16 Offset32; UINT16 Offset64Lo; UINT16 Offset64Hi; BOOLEAN Writeable; } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; =20 /// -/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGI= STER=20 +/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGI= STER /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY /// static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D= { - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_ST= ATE_REGISTER_LDTINFO), - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_ST= ATE_REGISTER_RIP), - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_ST= ATE_REGISTER_CR4), + SMM_REGISTER_RANGE ( + EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, + EFI_SMM_SAVE_STATE_REGISTER_LDTINFO + ), + SMM_REGISTER_RANGE ( + EFI_SMM_SAVE_STATE_REGISTER_ES, + EFI_SMM_SAVE_STATE_REGISTER_RIP + ), + SMM_REGISTER_RANGE ( + EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, + EFI_SMM_SAVE_STATE_REGISTER_CR4 + ), { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 } }; =20 /// -/// Lookup table used to retrieve the widths and offsets associated with e= ach=20 -/// supported EFI_SMM_SAVE_STATE_REGISTER value=20 +/// Lookup table used to retrieve the widths and offsets associated with e= ach +/// supported EFI_SMM_SAVE_STATE_REGISTER value /// static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { - {0, 0, 0, 0, 0, FALSE}, = // Reserved + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + 0, // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // Reserved =20 // // CPU Save State registers defined in PI SMM CPU Protocol. // - {0, 8, 0 , SMM_CPU_OFFSET (x64._GDTRBase) , S= MM_CPU_OFFSET (x64._GDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_GDTBASE =3D 4 - {0, 8, 0 , SMM_CPU_OFFSET (x64._IDTRBase) , S= MM_CPU_OFFSET (x64._IDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_IDTBASE =3D 5 - {0, 8, 0 , SMM_CPU_OFFSET (x64._LDTRBase) , S= MM_CPU_OFFSET (x64._LDTRBase) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_LDTBASE =3D 6 - {0, 0, 0 , SMM_CPU_OFFSET (x64._GDTRLimit), S= MM_CPU_OFFSET (x64._GDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_GDTLIMIT =3D 7 - {0, 0, 0 , SMM_CPU_OFFSET (x64._IDTRLimit), S= MM_CPU_OFFSET (x64._IDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_IDTLIMIT =3D 8 - {0, 0, 0 , SMM_CPU_OFFSET (x64._LDTRLimit), S= MM_CPU_OFFSET (x64._LDTRLimit) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_LDTLIMIT =3D 9 - {0, 0, 0 , 0 , 0= + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTE= R_LDTINFO =3D 10 - - {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = =3D 20 - {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = =3D 21 - {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = =3D 22 - {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = =3D 23 - {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = =3D 24 - {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = =3D 25 - {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDT= R_SEL =3D 26 - {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 = , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_= SEL =3D 27 - {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM= _CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7= =3D 28 - {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM= _CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6= =3D 29 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM= _CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = =3D 30 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM= _CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = =3D 31 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM= _CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10= =3D 32 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM= _CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11= =3D 33 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM= _CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12= =3D 34 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM= _CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13= =3D 35 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM= _CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14= =3D 36 - {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM= _CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15= =3D 37 - {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM= _CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX= =3D 38 - {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM= _CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX= =3D 39 - {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM= _CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX= =3D 40 - {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM= _CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX= =3D 41 - {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM= _CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP= =3D 42 - {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM= _CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP= =3D 43 - {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM= _CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI= =3D 44 - {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM= _CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI= =3D 45 - {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM= _CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP= =3D 46 - - {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM= _CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFL= AGS =3D 51 - {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM= _CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0= =3D 52 - {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM= _CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3= =3D 53 - {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , SMM= _CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4= =3D 54 + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo + SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE =3D 4 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo + SMM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE =3D 5 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo + SMM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE =3D 6 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo + SMM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT =3D 7 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo + SMM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT =3D 8 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo + SMM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT =3D 9 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + 0, // Offset64Lo + 0 + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO =3D 10 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._ES), // Offset32 + SMM_CPU_OFFSET (x64._ES), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_ES =3D 20 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._CS), // Offset32 + SMM_CPU_OFFSET (x64._CS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_CS =3D 21 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._SS), // Offset32 + SMM_CPU_OFFSET (x64._SS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_SS =3D 22 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._DS), // Offset32 + SMM_CPU_OFFSET (x64._DS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_DS =3D 23 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._FS), // Offset32 + SMM_CPU_OFFSET (x64._FS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_FS =3D 24 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._GS), // Offset32 + SMM_CPU_OFFSET (x64._GS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_GS =3D 25 + + { + 0, // Width32 + 4, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._LDTR), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL =3D 26 + + { + 4, // Width32 + 4, // Width64 + SMM_CPU_OFFSET (x86._TR), // Offset32 + SMM_CPU_OFFSET (x64._TR), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL =3D 27 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._DR7), // Offset32 + SMM_CPU_OFFSET (x64._DR7), // Offset64Lo + SMM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 =3D 28 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._DR6), // Offset32 + SMM_CPU_OFFSET (x64._DR6), // Offset64Lo + SMM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 =3D 29 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R8), // Offset64Lo + SMM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R8 =3D 30 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R9), // Offset64Lo + SMM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R9 =3D 31 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R10), // Offset64Lo + SMM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R10 =3D 32 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R11), // Offset64Lo + SMM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R11 =3D 33 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R12), // Offset64Lo + SMM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R12 =3D 34 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R13), // Offset64Lo + SMM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R13 =3D 35 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R14), // Offset64Lo + SMM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R14 =3D 36 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._R15), // Offset64Lo + SMM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_R15 =3D 37 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EAX), // Offset32 + SMM_CPU_OFFSET (x64._RAX), // Offset64Lo + SMM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RAX =3D 38 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EBX), // Offset32 + SMM_CPU_OFFSET (x64._RBX), // Offset64Lo + SMM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RBX =3D 39 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._ECX), // Offset32 + SMM_CPU_OFFSET (x64._RCX), // Offset64Lo + SMM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RCX =3D 40 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EDX), // Offset32 + SMM_CPU_OFFSET (x64._RDX), // Offset64Lo + SMM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RDX =3D 41 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._ESP), // Offset32 + SMM_CPU_OFFSET (x64._RSP), // Offset64Lo + SMM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RSP =3D 42 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EBP), // Offset32 + SMM_CPU_OFFSET (x64._RBP), // Offset64Lo + SMM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RBP =3D 43 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._ESI), // Offset32 + SMM_CPU_OFFSET (x64._RSI), // Offset64Lo + SMM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RSI =3D 44 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EDI), // Offset32 + SMM_CPU_OFFSET (x64._RDI), // Offset64Lo + SMM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RDI =3D 45 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EIP), // Offset32 + SMM_CPU_OFFSET (x64._RIP), // Offset64Lo + SMM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RIP =3D 46 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._EFLAGS), // Offset32 + SMM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo + SMM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS =3D 51 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._CR0), // Offset32 + SMM_CPU_OFFSET (x64._CR0), // Offset64Lo + SMM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 =3D 52 + + { + 4, // Width32 + 8, // Width64 + SMM_CPU_OFFSET (x86._CR3), // Offset32 + SMM_CPU_OFFSET (x64._CR3), // Offset64Lo + SMM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 =3D 53 + + { + 0, // Width32 + 4, // Width64 + 0, // Offset32 + SMM_CPU_OFFSET (x64._CR4), // Offset64Lo + SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 =3D 54 }; =20 // // No support for I/O restart // =20 /** Read information from the CPU save state. =20 @param Register Specifies the CPU register to read form the save state. =20 @retval 0 Register is not valid @retval >0 Index into mSmmCpuWidthOffset[] associated with Register =20 **/ static UINTN GetRegisterIndex ( IN EFI_SMM_SAVE_STATE_REGISTER Register ) { UINTN Index; UINTN Offset; =20 - for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCp= uRegisterRanges[Index].Length !=3D 0; Index++) { - if (Register >=3D mSmmCpuRegisterRanges[Index].Start && Register <=3D = mSmmCpuRegisterRanges[Index].End) { + for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_FIRST_INDEX; + mSmmCpuRegisterRanges[Index].Length !=3D 0; + Index++) { + if (Register >=3D mSmmCpuRegisterRanges[Index].Start && + Register <=3D mSmmCpuRegisterRanges[Index].End) { return Register - mSmmCpuRegisterRanges[Index].Start + Offset; } Offset +=3D mSmmCpuRegisterRanges[Index].Length; } return 0; } =20 /** Read a CPU Save State register on the target processor. =20 - This function abstracts the differences that whether the CPU Save State = register is in the=20 - IA32 CPU Save State Map or X64 CPU Save State Map. + This function abstracts the differences that whether the CPU Save State + register is in the IA32 CPU Save State Map or X64 CPU Save State Map. =20 - This function supports reading a CPU Save State register in SMBase reloc= ation handler. + This function supports reading a CPU Save State register in SMBase reloc= ation + handler. =20 - @param[in] CpuIndex Specifies the zero-based index of the CPU sav= e state. + @param[in] CpuIndex Specifies the zero-based index of the CPU save + state. @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. - @param[in] Width The number of bytes to read from the CPU save= state. - @param[out] Buffer Upon return, this holds the CPU register valu= e read from the save state. + @param[in] Width The number of bytes to read from the CPU save + state. + @param[out] Buffer Upon return, this holds the CPU register value + read from the save state. =20 @retval EFI_SUCCESS The register was read from Save State. - @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. + @retval EFI_NOT_FOUND The register is not defined for the Save S= tate + of Processor. @retval EFI_INVALID_PARAMTER This or Buffer is NULL. =20 **/ static EFI_STATUS ReadSaveStateRegisterByIndex ( IN UINTN CpuIndex, IN UINTN RegisterIndex, IN UINTN Width, OUT VOID *Buffer ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; =20 CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuInd= ex]; =20 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { // - // If 32-bit mode width is zero, then the specified register can not b= e accessed + // If 32-bit mode width is zero, then the specified register can not be + // accessed // if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { return EFI_NOT_FOUND; } =20 // - // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed + // If Width is bigger than the 32-bit mode width, then the specified + // register can not be accessed // if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { return EFI_INVALID_PARAMETER; } =20 // // Write return buffer // ASSERT(CpuSaveState !=3D NULL); - CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterInd= ex].Offset32, Width); + CopyMem ( + Buffer, + (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, + Width + ); } else { // - // If 64-bit mode width is zero, then the specified register can not b= e accessed + // If 64-bit mode width is zero, then the specified register can not be + // accessed // if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { return EFI_NOT_FOUND; } =20 // - // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed + // If Width is bigger than the 64-bit mode width, then the specified + // register can not be accessed // if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { return EFI_INVALID_PARAMETER; } =20 // // Write lower 32-bits of return buffer // - CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterInd= ex].Offset64Lo, MIN(4, Width)); + CopyMem ( + Buffer, + (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, + MIN (4, Width) + ); if (Width >=3D 4) { // // Write upper 32-bits of return buffer // - CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOff= set[RegisterIndex].Offset64Hi, Width - 4); + CopyMem ( + (UINT8 *)Buffer + 4, + (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64= Hi, + Width - 4 + ); } } return EFI_SUCCESS; } =20 /** Read an SMM Save State register on the target processor. If this functi= on returns EFI_UNSUPPORTED, then the caller is responsible for reading the SMM Save Sate register. =20 @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The value must be between 0 and the NumberOfCpus field= in the System Management System Table (SMST). @param[in] Register The SMM Save State register to read. @param[in] Width The number of bytes to read from the CPU save stat= e. @param[out] Buffer Upon return, this holds the CPU register value read from the save state. =20 @retval EFI_SUCCESS The register was read from Save State. @retval EFI_INVALID_PARAMTER Buffer is NULL. - @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. - + @retval EFI_UNSUPPORTED This function does not support reading + Register. **/ EFI_STATUS EFIAPI SmmCpuFeaturesReadSaveStateRegister ( IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, OUT VOID *Buffer ) { UINTN RegisterIndex; QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; =20 // // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA // if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { // // Only byte access is supported for this register // @@ -657,178 +1005,202 @@ SmmCpuFeaturesReadSaveStateRegister ( *(UINT8 *)Buffer =3D 64; } =20 return EFI_SUCCESS; } =20 // // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO // if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { return EFI_NOT_FOUND; } =20 // // Convert Register to a register lookup table index. Let // PiSmmCpuDxeSmm implement other special registers (currently // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID). // RegisterIndex =3D GetRegisterIndex (Register); if (RegisterIndex =3D=3D 0) { - return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI= _UNSUPPORTED; + return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? + EFI_NOT_FOUND : + EFI_UNSUPPORTED); } =20 return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buf= fer); } =20 /** Writes an SMM Save State register on the target processor. If this func= tion returns EFI_UNSUPPORTED, then the caller is responsible for writing the SMM Save Sate register. =20 @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The value must be between 0 and the NumberOfCpus field = in the System Management System Table (SMST). @param[in] Register The SMM Save State register to write. @param[in] Width The number of bytes to write to the CPU save state. @param[in] Buffer Upon entry, this holds the new CPU register value. =20 @retval EFI_SUCCESS The register was written to Save State. @retval EFI_INVALID_PARAMTER Buffer is NULL. - @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. + @retval EFI_UNSUPPORTED This function does not support writing + Register. **/ EFI_STATUS EFIAPI SmmCpuFeaturesWriteSaveStateRegister ( IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer ) { UINTN RegisterIndex; QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; =20 // // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored // if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { return EFI_SUCCESS; } =20 // // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported // if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { return EFI_NOT_FOUND; } =20 // // Convert Register to a register lookup table index. Let // PiSmmCpuDxeSmm implement other special registers (currently // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID). // RegisterIndex =3D GetRegisterIndex (Register); if (RegisterIndex =3D=3D 0) { - return Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? EFI_NOT_FOUND : EFI= _UNSUPPORTED; + return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ? + EFI_NOT_FOUND : + EFI_UNSUPPORTED); } =20 CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuInd= ex]; =20 // // Do not write non-writable SaveState, because it will cause exception. - //=20 + // if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) { return EFI_UNSUPPORTED; } =20 // // Check CPU mode // if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { // - // If 32-bit mode width is zero, then the specified register can not b= e accessed + // If 32-bit mode width is zero, then the specified register can not be + // accessed // if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { return EFI_NOT_FOUND; } =20 // - // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed + // If Width is bigger than the 32-bit mode width, then the specified + // register can not be accessed // if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { return EFI_INVALID_PARAMETER; } // // Write SMM State register // ASSERT (CpuSaveState !=3D NULL); - CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offs= et32, Buffer, Width); + CopyMem ( + (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, + Buffer, + Width + ); } else { // - // If 64-bit mode width is zero, then the specified register can not b= e accessed + // If 64-bit mode width is zero, then the specified register can not be + // accessed // if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { return EFI_NOT_FOUND; } =20 // - // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed + // If Width is bigger than the 64-bit mode width, then the specified + // register can not be accessed // if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { return EFI_INVALID_PARAMETER; } =20 // // Write lower 32-bits of SMM State register // - CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offs= et64Lo, Buffer, MIN (4, Width)); + CopyMem ( + (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, + Buffer, + MIN (4, Width) + ); if (Width >=3D 4) { // // Write upper 32-bits of SMM State register // - CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Of= fset64Hi, (UINT8 *)Buffer + 4, Width - 4); + CopyMem ( + (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64= Hi, + (UINT8 *)Buffer + 4, + Width - 4 + ); } } return EFI_SUCCESS; } =20 /** This function is hook point called after the gEfiSmmReadyToLockProtocolG= uid notification is completely processed. **/ VOID EFIAPI SmmCpuFeaturesCompleteSmmReadyToLock ( VOID ) { } =20 /** - This API provides a method for a CPU to allocate a specific region for s= toring page tables. + This API provides a method for a CPU to allocate a specific region for + storing page tables. =20 This API can be called more once to allocate memory for page tables. =20 - Allocates the number of 4KB pages of type EfiRuntimeServicesData and ret= urns a pointer to the - allocated buffer. The buffer returned is aligned on a 4KB boundary. If= Pages is 0, then NULL - is returned. If there is not enough memory remaining to satisfy the req= uest, then NULL is - returned. + Allocates the number of 4KB pages of type EfiRuntimeServicesData and ret= urns + a pointer to the allocated buffer. The buffer returned is aligned on a = 4KB + boundary. If Pages is 0, then NULL is returned. If there is not enough + memory remaining to satisfy the request, then NULL is returned. =20 - This function can also return NULL if there is no preference on where th= e page tables are allocated in SMRAM. + This function can also return NULL if there is no preference on where the + page tables are allocated in SMRAM. =20 @param Pages The number of 4 KB pages to allocate. =20 @return A pointer to the allocated buffer for page tables. @retval NULL Fail to allocate a specific region for storing page ta= bles, - Or there is no preference on where the page tables are= allocated in SMRAM. + Or there is no preference on where the page tables are + allocated in SMRAM. =20 **/ VOID * EFIAPI SmmCpuFeaturesAllocatePageTableMemory ( IN UINTN Pages ) { return NULL; } =20 --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949087650752.194340478978; Thu, 1 Mar 2018 16:04:47 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BE5542255D6CE; Thu, 1 Mar 2018 15:58:20 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2AABF2255D6C0 for ; Thu, 1 Mar 2018 15:58:19 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6EC4F8D746; Fri, 2 Mar 2018 00:04:27 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 842EE10B0F24; Fri, 2 Mar 2018 00:04:26 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:59 +0100 Message-Id: <20180302000408.14201-12-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:27 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:27 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 11/20] OvmfPkg/SmmCpuFeaturesLib: upper-case the "static" keyword X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In edk2, the "static" keyword is spelled "STATIC". Also let "STATIC" stand alone on a line in function definitions. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index a876a6e34751..6b9924e49426 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -427,61 +427,61 @@ typedef struct { /// /// Structure used to build a lookup table to retrieve the widths and offs= ets /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value /// =20 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1 =20 typedef struct { UINT8 Width32; UINT8 Width64; UINT16 Offset32; UINT16 Offset64Lo; UINT16 Offset64Hi; BOOLEAN Writeable; } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; =20 /// /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGI= STER /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY /// -static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D= { +STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D= { SMM_REGISTER_RANGE ( EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO ), SMM_REGISTER_RANGE ( EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP ), SMM_REGISTER_RANGE ( EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4 ), { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 } }; =20 /// /// Lookup table used to retrieve the widths and offsets associated with e= ach /// supported EFI_SMM_SAVE_STATE_REGISTER value /// -static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { +STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { { 0, // Width32 0, // Width64 0, // Offset32 0, // Offset64Lo 0, // Offset64Hi FALSE // Writeable }, // Reserved =20 // // CPU Save State registers defined in PI SMM CPU Protocol. // { 0, // Width32 8, // Width64 0, // Offset32 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi FALSE // Writeable }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE =3D 4 @@ -816,41 +816,42 @@ static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuW= idthOffset[] =3D { 0, // Offset32 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi FALSE // Writeable }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 =3D 54 }; =20 // // No support for I/O restart // =20 /** Read information from the CPU save state. =20 @param Register Specifies the CPU register to read form the save state. =20 @retval 0 Register is not valid @retval >0 Index into mSmmCpuWidthOffset[] associated with Register =20 **/ -static UINTN +STATIC +UINTN GetRegisterIndex ( IN EFI_SMM_SAVE_STATE_REGISTER Register ) { UINTN Index; UINTN Offset; =20 for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length !=3D 0; Index++) { if (Register >=3D mSmmCpuRegisterRanges[Index].Start && Register <=3D mSmmCpuRegisterRanges[Index].End) { return Register - mSmmCpuRegisterRanges[Index].Start + Offset; } Offset +=3D mSmmCpuRegisterRanges[Index].Length; } return 0; } =20 /** @@ -859,41 +860,42 @@ GetRegisterIndex ( This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map. =20 This function supports reading a CPU Save State register in SMBase reloc= ation handler. =20 @param[in] CpuIndex Specifies the zero-based index of the CPU save state. @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. @param[in] Width The number of bytes to read from the CPU save state. @param[out] Buffer Upon return, this holds the CPU register value read from the save state. =20 @retval EFI_SUCCESS The register was read from Save State. @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. @retval EFI_INVALID_PARAMTER This or Buffer is NULL. =20 **/ -static EFI_STATUS +STATIC +EFI_STATUS ReadSaveStateRegisterByIndex ( IN UINTN CpuIndex, IN UINTN RegisterIndex, IN UINTN Width, OUT VOID *Buffer ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; =20 CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuInd= ex]; =20 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { // // If 32-bit mode width is zero, then the specified register can not be // accessed // if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { return EFI_NOT_FOUND; } =20 --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949090352841.35882337151; Thu, 1 Mar 2018 16:04:50 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 203812255D6D1; Thu, 1 Mar 2018 15:58:22 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 49A602255D6C9 for ; Thu, 1 Mar 2018 15:58:20 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 971FD87ABA; Fri, 2 Mar 2018 00:04:28 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id B196C10B0F24; Fri, 2 Mar 2018 00:04:27 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:00 +0100 Message-Id: <20180302000408.14201-13-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Fri, 02 Mar 2018 00:04:28 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Fri, 02 Mar 2018 00:04:28 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 12/20] OvmfPkg/SmmCpuFeaturesLib: sort #includes, and entries in INF file sections X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 2 +- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 75b24606b9df..9448bb166671 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -18,23 +18,23 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D SmmCpuFeaturesLib MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni FILE_GUID =3D AC9991BE-D77A-464C-A8DE-A873DB8A4836 MODULE_TYPE =3D DXE_SMM_DRIVER VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SmmCpuFeaturesLib CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor =20 [Sources] SmmCpuFeaturesLib.c =20 [Packages] MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [LibraryClasses] BaseLib BaseMemoryLib - PcdLib DebugLib + PcdLib SmmServicesTableLib diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 6b9924e49426..75b9ce0e2b12 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -1,42 +1,42 @@ /** @file The CPU specific programming for PiSmmCpuDxeSmm module. =20 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ =20 -#include -#include #include #include -#include +#include #include +#include +#include #include -#include +#include #include =20 // // EFER register LMA bit // #define LMA BIT10 =20 /** The constructor function =20 @param[in] ImageHandle The firmware allocated handle for the EFI image. @param[in] SystemTable A pointer to the EFI System Table. =20 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. =20 **/ EFI_STATUS EFIAPI SmmCpuFeaturesLibConstructor ( IN EFI_HANDLE ImageHandle, --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949092768420.6683917337442; Thu, 1 Mar 2018 16:04:52 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 955512255D6D9; Thu, 1 Mar 2018 15:58:22 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7C6AB2255D6D1 for ; Thu, 1 Mar 2018 15:58:21 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BF7E5402291E; Fri, 2 Mar 2018 00:04:29 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id D9C8710B0F24; Fri, 2 Mar 2018 00:04:28 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:01 +0100 Message-Id: <20180302000408.14201-14-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Fri, 02 Mar 2018 00:04:29 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Fri, 02 Mar 2018 00:04:29 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 13/20] OvmfPkg/SmmCpuFeaturesLib: remove unneeded #includes and LibraryClasses X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 1 - OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 2 -- 2 files changed, 3 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 9448bb166671..5184abbf21bd 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -19,22 +19,21 @@ [Defines] BASE_NAME =3D SmmCpuFeaturesLib MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni FILE_GUID =3D AC9991BE-D77A-464C-A8DE-A873DB8A4836 MODULE_TYPE =3D DXE_SMM_DRIVER VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SmmCpuFeaturesLib CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor =20 [Sources] SmmCpuFeaturesLib.c =20 [Packages] MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [LibraryClasses] BaseLib BaseMemoryLib DebugLib - PcdLib SmmServicesTableLib diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 75b9ce0e2b12..13d929a983be 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -1,39 +1,37 @@ /** @file The CPU specific programming for PiSmmCpuDxeSmm module. =20 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ =20 #include #include #include -#include -#include #include #include #include #include =20 // // EFER register LMA bit // #define LMA BIT10 =20 /** The constructor function =20 @param[in] ImageHandle The firmware allocated handle for the EFI image. @param[in] SystemTable A pointer to the EFI System Table. =20 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. =20 **/ EFI_STATUS --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151994909528491.15792937937567; Thu, 1 Mar 2018 16:04:55 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E17BD2255D6DC; Thu, 1 Mar 2018 15:58:23 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8C2C82255D6D7 for ; Thu, 1 Mar 2018 15:58:22 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E8D608D746; Fri, 2 Mar 2018 00:04:30 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0E20210B0F24; Fri, 2 Mar 2018 00:04:29 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:02 +0100 Message-Id: <20180302000408.14201-15-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:30 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:30 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 14/20] OvmfPkg/AmdSevDxe: rewrap to 79 characters width X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" There are many overlong lines; it's hard to work with the module like this. Rewrap all files to 79 columns. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/AmdSevDxe/AmdSevDxe.inf | 11 +++---- OvmfPkg/AmdSevDxe/AmdSevDxe.c | 30 +++++++++++--------- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf b/OvmfPkg/AmdSevDxe/AmdSevDxe.= inf index 41635a57a454..2ed778979373 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.inf @@ -1,33 +1,34 @@ #/** @file # # Driver clears the encryption attribute from MMIO regions when SEV is en= abled # # Copyright (c) 2017, AMD Inc. All rights reserved.
# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD -# License which accompanies this distribution. The full text of the lice= nse may -# be found at http://opensource.org/licenses/bsd-license.php +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php # # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. # #**/ =20 [Defines] INF_VERSION =3D 1.25 BASE_NAME =3D AmdSevDxe FILE_GUID =3D 2ec9da37-ee35-4de9-86c5-6d9a81dc38a7 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D AmdSevDxeEntryPoint =20 [Sources] AmdSevDxe.c =20 [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c index e472096320ea..065d7381b35b 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c @@ -1,75 +1,77 @@ /** @file =20 AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being= list - in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when = SEV is - enabled. + in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when = SEV + is enabled. =20 Copyright (c) 2017, AMD Inc. All rights reserved.
=20 - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD - License which accompanies this distribution. The full text of the licen= se may - be found at http://opensource.org/licenses/bsd-license.php + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php =20 - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 **/ =20 #include =20 #include #include #include #include #include #include #include =20 EFI_STATUS EFIAPI AmdSevDxeEntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { EFI_STATUS Status; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap; UINTN NumEntries; UINTN Index; =20 // // Do nothing when SEV is not enabled // if (!MemEncryptSevIsEnabled ()) { return EFI_UNSUPPORTED; } =20 // // Iterate through the GCD map and clear the C-bit from MMIO and NonExis= tent - // memory space. The NonExistent memory space will be used for mapping t= he MMIO - // space added later (eg PciRootBridge). By clearing both known MMIO and + // memory space. The NonExistent memory space will be used for mapping t= he + // MMIO space added later (eg PciRootBridge). By clearing both known MMI= O and // NonExistent memory space can gurantee that current and furture MMIO a= dds // will have C-bit cleared. // Status =3D gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap); if (!EFI_ERROR (Status)) { for (Index =3D 0; Index < NumEntries; Index++) { CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc; =20 Desc =3D &AllDescMap[Index]; if (Desc->GcdMemoryType =3D=3D EfiGcdMemoryTypeMemoryMappedIo || Desc->GcdMemoryType =3D=3D EfiGcdMemoryTypeNonExistent) { - Status =3D MemEncryptSevClearPageEncMask (0, - Desc->BaseAddress, - EFI_SIZE_TO_PAGES(Desc->Le= ngth), - FALSE); + Status =3D MemEncryptSevClearPageEncMask ( + 0, + Desc->BaseAddress, + EFI_SIZE_TO_PAGES (Desc->Length), + FALSE + ); ASSERT_EFI_ERROR (Status); } } =20 FreePool (AllDescMap); } =20 return EFI_SUCCESS; } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949097907911.4927454203064; Thu, 1 Mar 2018 16:04:57 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5AA762255D6D8; Thu, 1 Mar 2018 15:58:25 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BA6E02255D6C5 for ; Thu, 1 Mar 2018 15:58:23 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1D31B7D852; Fri, 2 Mar 2018 00:04:32 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 372F110B0F24; Fri, 2 Mar 2018 00:04:31 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:03 +0100 Message-Id: <20180302000408.14201-16-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:32 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:32 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 15/20] OvmfPkg/AmdSevDxe: sort #includes, and entries in INF file sections X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/AmdSevDxe/AmdSevDxe.inf | 10 +++++----- OvmfPkg/AmdSevDxe/AmdSevDxe.c | 9 ++++----- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf b/OvmfPkg/AmdSevDxe/AmdSevDxe.= inf index 2ed778979373..d4a0a2635d2e 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.inf @@ -10,35 +10,35 @@ # http://opensource.org/licenses/bsd-license.php # # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR # IMPLIED. # #**/ =20 [Defines] INF_VERSION =3D 1.25 BASE_NAME =3D AmdSevDxe FILE_GUID =3D 2ec9da37-ee35-4de9-86c5-6d9a81dc38a7 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D AmdSevDxeEntryPoint =20 [Sources] AmdSevDxe.c =20 [Packages] - MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] BaseLib - UefiLib - UefiDriverEntryPoint - UefiBootServicesTableLib - DxeServicesTableLib DebugLib + DxeServicesTableLib MemEncryptSevLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib =20 [Depex] TRUE diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c index 065d7381b35b..9ac13acb8b22 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c @@ -1,47 +1,46 @@ /** @file =20 AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being= list in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when = SEV is enabled. =20 Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 **/ =20 -#include - #include -#include #include -#include -#include +#include #include #include +#include +#include +#include =20 EFI_STATUS EFIAPI AmdSevDxeEntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { EFI_STATUS Status; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap; UINTN NumEntries; UINTN Index; =20 // // Do nothing when SEV is not enabled // if (!MemEncryptSevIsEnabled ()) { return EFI_UNSUPPORTED; } =20 --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949100413544.0059978803674; Thu, 1 Mar 2018 16:05:00 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B6FD22255D6E0; Thu, 1 Mar 2018 15:58:26 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EDC132255D6C5 for ; Thu, 1 Mar 2018 15:58:24 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 484B6404084B; Fri, 2 Mar 2018 00:04:33 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 60C8E10B0F24; Fri, 2 Mar 2018 00:04:32 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:04 +0100 Message-Id: <20180302000408.14201-17-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:33 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Fri, 02 Mar 2018 00:04:33 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 16/20] OvmfPkg/AmdSevDxe: refresh #includes and LibraryClasses X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" List those and only those libraries that are used. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/AmdSevDxe/AmdSevDxe.inf | 4 +--- OvmfPkg/AmdSevDxe/AmdSevDxe.c | 4 ---- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf b/OvmfPkg/AmdSevDxe/AmdSevDxe.= inf index d4a0a2635d2e..3aff7e292053 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.inf @@ -15,30 +15,28 @@ # #**/ =20 [Defines] INF_VERSION =3D 1.25 BASE_NAME =3D AmdSevDxe FILE_GUID =3D 2ec9da37-ee35-4de9-86c5-6d9a81dc38a7 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D AmdSevDxeEntryPoint =20 [Sources] AmdSevDxe.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] - BaseLib DebugLib DxeServicesTableLib MemEncryptSevLib - UefiBootServicesTableLib + MemoryAllocationLib UefiDriverEntryPoint - UefiLib =20 [Depex] TRUE diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c index 9ac13acb8b22..8f02d0627e02 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c @@ -1,46 +1,42 @@ /** @file =20 AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being= list in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when = SEV is enabled. =20 Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 **/ =20 -#include -#include #include #include #include #include -#include -#include =20 EFI_STATUS EFIAPI AmdSevDxeEntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { EFI_STATUS Status; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap; UINTN NumEntries; UINTN Index; =20 // // Do nothing when SEV is not enabled // if (!MemEncryptSevIsEnabled ()) { return EFI_UNSUPPORTED; } =20 --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949103169201.83141349020514; Thu, 1 Mar 2018 16:05:03 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1C7222255D6E5; Thu, 1 Mar 2018 15:58:28 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 247C32255D6E0 for ; Thu, 1 Mar 2018 15:58:26 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 744AA8182D2E; Fri, 2 Mar 2018 00:04:34 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8BBFB10B0F24; Fri, 2 Mar 2018 00:04:33 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:05 +0100 Message-Id: <20180302000408.14201-18-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Fri, 02 Mar 2018 00:04:34 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Fri, 02 Mar 2018 00:04:34 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 17/20] OvmfPkg/MemEncryptSevLib: find pages of initial SMRAM save state map X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In the next three patches, we're going to modify three modules under OvmfPkg. When OVMF is built with -D SMM_REQUIRE and runs in an SEV guest, each affected module will have to know the page range that covers the initial (pre-SMBASE relocation) SMRAM save state map. Add a helper function to MemEncryptSevLib that calculates the "base address" and "number of pages" constants for this page range. (In a RELEASE build -- i.e., with assertions disabled and optimization enabled --, the helper function can be compiled to store two constants determined at compile time.) Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf | 4 ++ OvmfPkg/Include/Library/MemEncryptSevLib.h | 23 +++++= ++++ OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c | 51 +++++= +++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf = b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf index 2f0a2392a7ad..464fe1f33e66 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf @@ -34,20 +34,24 @@ [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [Sources.X64] MemEncryptSevLibInternal.c X64/MemEncryptSevLib.c X64/VirtualMemory.c =20 [Sources.IA32] Ia32/MemEncryptSevLib.c MemEncryptSevLibInternal.c =20 [LibraryClasses] BaseLib CacheMaintenanceLib CpuLib DebugLib MemoryAllocationLib + PcdLib + +[FeaturePcd] + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index e5ebb4401818..1e2ec8641d46 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -69,21 +69,44 @@ MemEncryptSevClearPageEncMask ( address of a memory region. @param[in] NumPages The number of pages from start memory region. @param[in] Flush Flush the caches before setting the = bit (mostly TRUE except MMIO addresses) =20 @retval RETURN_SUCCESS The attributes were set for the memo= ry region. @retval RETURN_INVALID_PARAMETER Number of pages is zero. @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute is not supported **/ RETURN_STATUS EFIAPI MemEncryptSevSetPageEncMask ( IN PHYSICAL_ADDRESS Cr3BaseAddress, IN PHYSICAL_ADDRESS BaseAddress, IN UINTN NumPages, IN BOOLEAN Flush ); + + +/** + Locate the page range that covers the initial (pre-SMBASE-relocation) SM= RAM + Save State Map. + + @param[out] BaseAddress The base address of the lowest-address page = that + covers the initial SMRAM Save State Map. + + @param[out] NumberOfPages The number of pages in the page range that c= overs + the initial SMRAM Save State Map. + + @retval RETURN_SUCCESS BaseAddress and NumberOfPages have been set = on + output. + + @retval RETURN_UNSUPPORTED SMM is unavailable. +**/ +RETURN_STATUS +EFIAPI +MemEncryptSevLocateInitialSmramSaveStateMapPages ( + OUT UINTN *BaseAddress, + OUT UINTN *NumberOfPages + ); #endif // _MEM_ENCRYPT_SEV_LIB_H_ diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.= c b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c index 7078ab0d3f46..b92ba50c616c 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c @@ -1,42 +1,46 @@ /** @file =20 Secure Encrypted Virtualization (SEV) library helper function =20 Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 #include #include #include +#include #include #include #include +#include +#include +#include =20 STATIC BOOLEAN mSevStatus =3D FALSE; STATIC BOOLEAN mSevStatusChecked =3D FALSE; =20 /** =20 Returns a boolean to indicate whether SEV is enabled =20 @retval TRUE SEV is enabled @retval FALSE SEV is not enabled **/ STATIC BOOLEAN EFIAPI InternalMemEncryptSevIsEnabled ( VOID ) { UINT32 RegEax; MSR_SEV_STATUS_REGISTER Msr; @@ -70,20 +74,67 @@ InternalMemEncryptSevIsEnabled ( Returns a boolean to indicate whether SEV is enabled =20 @retval TRUE SEV is enabled @retval FALSE SEV is not enabled **/ BOOLEAN EFIAPI MemEncryptSevIsEnabled ( VOID ) { if (mSevStatusChecked) { return mSevStatus; } =20 mSevStatus =3D InternalMemEncryptSevIsEnabled(); mSevStatusChecked =3D TRUE; =20 return mSevStatus; } + + +/** + Locate the page range that covers the initial (pre-SMBASE-relocation) SM= RAM + Save State Map. + + @param[out] BaseAddress The base address of the lowest-address page = that + covers the initial SMRAM Save State Map. + + @param[out] NumberOfPages The number of pages in the page range that c= overs + the initial SMRAM Save State Map. + + @retval RETURN_SUCCESS BaseAddress and NumberOfPages have been set = on + output. + + @retval RETURN_UNSUPPORTED SMM is unavailable. +**/ +RETURN_STATUS +EFIAPI +MemEncryptSevLocateInitialSmramSaveStateMapPages ( + OUT UINTN *BaseAddress, + OUT UINTN *NumberOfPages + ) +{ + UINTN MapStart; + UINTN MapEnd; + UINTN MapPagesStart; // MapStart rounded down to page boundary + UINTN MapPagesEnd; // MapEnd rounded up to page boundary + UINTN MapPagesSize; // difference between MapPagesStart and MapPagesEnd + + if (!FeaturePcdGet (PcdSmmSmramRequire)) { + return RETURN_UNSUPPORTED; + } + + MapStart =3D SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET; + MapEnd =3D MapStart + sizeof (QEMU_SMRAM_SAVE_STATE_MAP); + MapPagesStart =3D MapStart & ~(UINTN)EFI_PAGE_MASK; + MapPagesEnd =3D ALIGN_VALUE (MapEnd, EFI_PAGE_SIZE); + MapPagesSize =3D MapPagesEnd - MapPagesStart; + + ASSERT ((MapPagesSize & EFI_PAGE_MASK) =3D=3D 0); + + *BaseAddress =3D MapPagesStart; + *NumberOfPages =3D MapPagesSize >> EFI_PAGE_SHIFT; + + return RETURN_SUCCESS; +} --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949105733928.9633599930041; Thu, 1 Mar 2018 16:05:05 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8FE292255D6E9; Thu, 1 Mar 2018 15:58:29 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48A102255D6E5 for ; Thu, 1 Mar 2018 15:58:27 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9F9247D852; Fri, 2 Mar 2018 00:04:35 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id B9FFC10B0F24; Fri, 2 Mar 2018 00:04:34 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:06 +0100 Message-Id: <20180302000408.14201-19-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:35 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:35 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 18/20] OvmfPkg/PlatformPei: SEV: allocate pages of initial SMRAM save state map X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In the next two patches, we'll temporarily decrypt the pages containing the initial SMRAM save state map, for SMBASE relocation. (Unlike the separate, relocated SMRAM save state map of each VCPU, the original, shared map behaves similarly to a "common buffer" between guest and host.) The decryption will occur near the beginning of the DXE phase, in AmdSevDxe, and the re-encryption will occur in PiSmmCpuDxeSmm, via OVMF's SmmCpuFeaturesLib instance. There is a non-trivial time gap between these two points, and the DXE phase might use the pages overlapping the initial SMRAM save state map for arbitrary purposes meanwhile. In order to prevent any information leak towards the hypervisor, make sure the DXE phase puts nothing in those pages until re-encryption is done. Creating a memalloc HOB for the area in question is safe: - the temporary SEC/PEI RAM (stack and heap) is based at PcdOvmfSecPeiTempRamBase, which is above 8MB, - the permanent PEI RAM (installed in PlatformPei's PublishPeiMemory() function) never starts below PcdOvmfDxeMemFvBase, which is also above 8MB. The allocated pages can be released to the DXE phase after SMBASE relocation and re-encryption are complete. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/PlatformPei/AmdSev.c | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 1509f260fb0b..2e14eaf8c3cc 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -1,38 +1,39 @@ /**@file Initialize Secure Encrypted Virtualization (SEV) support =20 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the licen= se may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ // // The package level header files this module uses // #include +#include #include #include #include #include #include =20 #include "Platform.h" =20 /** =20 Function checks if SEV support is available, if present then it sets the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption m= ask. =20 **/ VOID AmdSevInitialize ( VOID ) { CPUID_MEMORY_ENCRYPTION_INFO_EBX Ebx; @@ -49,21 +50,49 @@ AmdSevInitialize ( // // CPUID Fn8000_001F[EBX] Bit 0:5 (memory encryption bit position) // AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, NULL, &Ebx.Uint32, NULL, NULL); EncryptionMask =3D LShiftU64 (1, Ebx.Bits.PtePosBits); =20 // // Set Memory Encryption Mask PCD // PcdStatus =3D PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, Encryption= Mask); ASSERT_RETURN_ERROR (PcdStatus); =20 DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask)); =20 // // Set Pcd to Deny the execution of option ROM when security // violation. // PcdStatus =3D PcdSet32S (PcdOptionRomImageVerificationPolicy, 0x4); ASSERT_RETURN_ERROR (PcdStatus); + + // + // When SMM is required, cover the pages containing the initial SMRAM Sa= ve + // State Map with a memory allocation HOB: + // + // There's going to be a time interval between our decrypting those page= s for + // SMBASE relocation and re-encrypting the same pages after SMBASE + // relocation. We shall ensure that the DXE phase stay away from those p= ages + // until after re-encryption, in order to prevent an information leak to= the + // hypervisor. + // + if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode !=3D BOOT_ON_S3_RES= UME)) { + RETURN_STATUS LocateMapStatus; + UINTN MapPagesBase; + UINTN MapPagesCount; + + LocateMapStatus =3D MemEncryptSevLocateInitialSmramSaveStateMapPages ( + &MapPagesBase, + &MapPagesCount + ); + ASSERT_RETURN_ERROR (LocateMapStatus); + + BuildMemoryAllocationHob ( + MapPagesBase, // BaseAddress + EFI_PAGES_TO_SIZE (MapPagesCount), // Length + EfiBootServicesData // MemoryType + ); + } } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151994910882722.404431831134048; Thu, 1 Mar 2018 16:05:08 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EBE912255D6EE; Thu, 1 Mar 2018 15:58:29 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90D7E2255D6D6 for ; Thu, 1 Mar 2018 15:58:28 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C978E8D746; Fri, 2 Mar 2018 00:04:36 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id E31F610B0F24; Fri, 2 Mar 2018 00:04:35 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:07 +0100 Message-Id: <20180302000408.14201-20-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:36 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:36 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 19/20] OvmfPkg/SmmCpuFeaturesLib: SEV: encrypt+free pages of init. save state map X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Based on the following patch from Brijesh Singh : [PATCH v2 1/2] OvmfPkg/AmdSevDxe: Clear the C-bit from SMM Saved State http://mid.mail-archive.com/20180228161415.28723-2-brijesh.singh@amd.com https://lists.01.org/pipermail/edk2-devel/2018-February/022016.html Once PiSmmCpuDxeSmm relocates SMBASE for all VCPUs, the pages of the initial SMRAM save state map can be re-encrypted (including zeroing them out after setting the C-bit on them), and they can be released to DXE for general use (undoing the allocation that we did in PlatformPei's AmdSevInitialize() function). The decryption of the same pages (which will occur chronologically earlier) is implemented in the next patch; hence the "re-encryption" part of this patch is currently a no-op. The series is structured like this in order to be bisection-friendly. If the decryption patch preceded this patch, then an info leak would be created while standing between the patches. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 2 ++ OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 38 +++++++++++++= +++++++ 2 files changed, 40 insertions(+) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/Ovmf= Pkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index 5184abbf21bd..7c2aaa890b5e 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -19,21 +19,23 @@ [Defines] BASE_NAME =3D SmmCpuFeaturesLib MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni FILE_GUID =3D AC9991BE-D77A-464C-A8DE-A873DB8A4836 MODULE_TYPE =3D DXE_SMM_DRIVER VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SmmCpuFeaturesLib CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor =20 [Sources] SmmCpuFeaturesLib.c =20 [Packages] MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [LibraryClasses] BaseLib BaseMemoryLib DebugLib + MemEncryptSevLib SmmServicesTableLib + UefiBootServicesTableLib diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 13d929a983be..59c319e01bfb 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -1,39 +1,41 @@ /** @file The CPU specific programming for PiSmmCpuDxeSmm module. =20 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ =20 #include #include #include +#include #include #include +#include #include #include =20 // // EFER register LMA bit // #define LMA BIT10 =20 /** The constructor function =20 @param[in] ImageHandle The firmware allocated handle for the EFI image. @param[in] SystemTable A pointer to the EFI System Table. =20 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. =20 **/ EFI_STATUS EFIAPI SmmCpuFeaturesLibConstructor ( @@ -168,40 +170,76 @@ SmmCpuFeaturesHookReturnFromSmm ( if ((CpuSaveState->x64.AutoHALTRestart & BIT0) !=3D 0) { CpuSaveState->x64.AutoHALTRestart &=3D ~BIT0; } } return OriginalInstructionPointer; } =20 /** Hook point in normal execution mode that allows the one CPU that was ele= cted as monarch during System Management Mode initialization to perform addit= ional initialization actions immediately after all of the CPUs have processed = their first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBA= SE into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm(). **/ VOID EFIAPI SmmCpuFeaturesSmmRelocationComplete ( VOID ) { + EFI_STATUS Status; + UINTN MapPagesBase; + UINTN MapPagesCount; + + if (!MemEncryptSevIsEnabled ()) { + return; + } + + // + // Now that SMBASE relocation is complete, re-encrypt the original SMRAM= save + // state map's container pages, and release the pages to DXE. (The pages= were + // allocated in PlatformPei.) + // + Status =3D MemEncryptSevLocateInitialSmramSaveStateMapPages ( + &MapPagesBase, + &MapPagesCount + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MemEncryptSevSetPageEncMask ( + 0, // Cr3BaseAddress -- use current CR3 + MapPagesBase, // BaseAddress + MapPagesCount, // NumPages + TRUE // Flush + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevSetPageEncMask(): %r\n", + __FUNCTION__, Status)); + ASSERT (FALSE); + CpuDeadLoop (); + } + + ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount)); + + Status =3D gBS->FreePages (MapPagesBase, MapPagesCount); + ASSERT_EFI_ERROR (Status); } =20 /** Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is returned, then a custom SMI handler is not provided by this library, and the default SMI handler must be used. =20 @retval 0 Use the default SMI handler. @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler(). The caller is required to allocate enough SMRAM for each CPU to support the size of t= he custom SMI handler. **/ UINTN EFIAPI SmmCpuFeaturesGetSmiHandlerSize ( VOID ) { return 0; --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 18:11:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15199491115424.938866103875625; Thu, 1 Mar 2018 16:05:11 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5F4232255D6F2; Thu, 1 Mar 2018 15:58:31 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9C9DB2255D6EB for ; Thu, 1 Mar 2018 15:58:29 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F29368182D2E; Fri, 2 Mar 2018 00:04:37 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1860B10B0F24; Fri, 2 Mar 2018 00:04:36 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:04:08 +0100 Message-Id: <20180302000408.14201-21-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Fri, 02 Mar 2018 00:04:38 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.8]); Fri, 02 Mar 2018 00:04:38 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 20/20] OvmfPkg/AmdSevDxe: decrypt the pages of the initial SMRAM save state map X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Based on the following patch from Brijesh Singh : [PATCH v2 1/2] OvmfPkg/AmdSevDxe: Clear the C-bit from SMM Saved State http://mid.mail-archive.com/20180228161415.28723-2-brijesh.singh@amd.com https://lists.01.org/pipermail/edk2-devel/2018-February/022016.html Original commit message from Brijesh: > When OVMF is built with SMM, SMMSaved State area (SMM_DEFAULT_SMBASE + > SMRAM_SAVE_STATE_MAP_OFFSET) contains data which need to be accessed by > both guest and hypervisor. Since the data need to be accessed by both > hence we must map the SMMSaved State area as unencrypted (i.e C-bit > cleared). > > This patch clears the SavedStateArea address before SMBASE relocation. > Currently, we do not clear the SavedStateArea address after SMBASE is > relocated due to the following reasons: > > 1) Guest BIOS never access the relocated SavedStateArea. > > 2) The C-bit works on page-aligned address, but the SavedStateArea > address is not a page-aligned. Theoretically, we could roundup the > address and clear the C-bit of aligned address but looking carefully we > found that some portion of the page contains code -- which will causes a > bigger issue for the SEV guest. When SEV is enabled, all the code must > be encrypted otherwise hardware will cause trap. Changes by Laszlo: - separate AmdSevDxe bits from SmmCpuFeaturesLib bits; - spell out PcdLib dependency with #include and in LibraryClasses; - replace (SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET) calculation with call to new MemEncryptSevLocateInitialSmramSaveStateMapPages() function; - consequently, pass page-aligned BaseAddress to MemEncryptSevClearPageEncMask(); - zero the pages before clearing the C-bit; - pass Flush=3DTRUE to MemEncryptSevClearPageEncMask(); - harden the treatment of MemEncryptSevClearPageEncMask() failure. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Brijesh Singh Tested-by: Brijesh Singh --- OvmfPkg/AmdSevDxe/AmdSevDxe.inf | 6 +++ OvmfPkg/AmdSevDxe/AmdSevDxe.c | 53 ++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf b/OvmfPkg/AmdSevDxe/AmdSevDxe.= inf index 3aff7e292053..b7e7da002d5e 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.inf @@ -15,28 +15,34 @@ # #**/ =20 [Defines] INF_VERSION =3D 1.25 BASE_NAME =3D AmdSevDxe FILE_GUID =3D 2ec9da37-ee35-4de9-86c5-6d9a81dc38a7 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D AmdSevDxeEntryPoint =20 [Sources] AmdSevDxe.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] + BaseLib + BaseMemoryLib DebugLib DxeServicesTableLib MemEncryptSevLib MemoryAllocationLib + PcdLib UefiDriverEntryPoint =20 [Depex] TRUE + +[FeaturePcd] + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c index 8f02d0627e02..c697580ad5b8 100644 --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c @@ -1,42 +1,45 @@ /** @file =20 AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being= list in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when = SEV is enabled. =20 Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 **/ =20 +#include +#include #include #include #include #include +#include =20 EFI_STATUS EFIAPI AmdSevDxeEntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { EFI_STATUS Status; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap; UINTN NumEntries; UINTN Index; =20 // // Do nothing when SEV is not enabled // if (!MemEncryptSevIsEnabled ()) { return EFI_UNSUPPORTED; } =20 @@ -51,22 +54,72 @@ AmdSevDxeEntryPoint ( if (!EFI_ERROR (Status)) { for (Index =3D 0; Index < NumEntries; Index++) { CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc; =20 Desc =3D &AllDescMap[Index]; if (Desc->GcdMemoryType =3D=3D EfiGcdMemoryTypeMemoryMappedIo || Desc->GcdMemoryType =3D=3D EfiGcdMemoryTypeNonExistent) { Status =3D MemEncryptSevClearPageEncMask ( 0, Desc->BaseAddress, EFI_SIZE_TO_PAGES (Desc->Length), FALSE ); ASSERT_EFI_ERROR (Status); } } =20 FreePool (AllDescMap); } =20 + // + // When SMM is enabled, clear the C-bit from SMM Saved State Area + // + // NOTES: The SavedStateArea address cleared here is before SMBASE + // relocation. Currently, we do not clear the SavedStateArea address aft= er + // SMBASE is relocated due to the following reasons: + // + // 1) Guest BIOS never access the relocated SavedStateArea. + // + // 2) The C-bit works on page-aligned address, but the SavedStateArea + // address is not a page-aligned. Theoretically, we could roundup the ad= dress + // and clear the C-bit of aligned address but looking carefully we found + // that some portion of the page contains code -- which will causes a bi= gger + // issues for SEV guest. When SEV is enabled, all the code must be encry= pted + // otherwise hardware will cause trap. + // + // We restore the C-bit for this SMM Saved State Area after SMBASE reloc= ation + // is completed (See OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib= .c). + // + if (FeaturePcdGet (PcdSmmSmramRequire)) { + UINTN MapPagesBase; + UINTN MapPagesCount; + + Status =3D MemEncryptSevLocateInitialSmramSaveStateMapPages ( + &MapPagesBase, + &MapPagesCount + ); + ASSERT_EFI_ERROR (Status); + + // + // Although these pages were set aside (i.e., allocated) by PlatformPe= i, we + // could be after a warm reboot from the OS. Don't leak any stale OS d= ata + // to the hypervisor. + // + ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount)); + + Status =3D MemEncryptSevClearPageEncMask ( + 0, // Cr3BaseAddress -- use current CR3 + MapPagesBase, // BaseAddress + MapPagesCount, // NumPages + TRUE // Flush + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevClearPageEncMask(): %r\n", + __FUNCTION__, Status)); + ASSERT (FALSE); + CpuDeadLoop (); + } + } + return EFI_SUCCESS; } --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel