From nobody Sun Apr 28 10:21:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518613755782320.0324862908226; Wed, 14 Feb 2018 05:09:15 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2DEE222161160; Wed, 14 Feb 2018 05:03:21 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2C1B02216114C for ; Wed, 14 Feb 2018 05:03:18 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id t74so22588458wme.3 for ; Wed, 14 Feb 2018 05:09:10 -0800 (PST) Received: from localhost.localdomain ([84.203.84.137]) by smtp.gmail.com with ESMTPSA id b13sm1262955edk.59.2018.02.14.05.09.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Feb 2018 05:09:08 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J3Eq3/ZtacucHtWtxiDbOyDxJylN369Zu0pno0Hd/dY=; b=ezqd4QNFE5aloN8HU7c8QLB8eSfSvMBl+uUTzKB9K4udInn+k5pebHZNgdsCGob87Y fbaSOJ986ejARVEGSlu5ZR72uVTLyTkCQD8KUREt5AlN3xckhwRvSVjNx3IA7NjKZJAT T1P53auX4kfJ6iqarKhjjA04IsnrXgLsiMsdwd/qp9nn/ubBpo+8dvRmW3IbBTfzHrsW DZkksWNaGVO6B0Uozrm5IhqE8iONWQIkOn+hjxYcu5jq3VWc1Yl31SDPn7sizFbqV8Zb wxRAn5bS5gKtgukr/tIMhgjlNjgVGRRlsoDNx6T5nHA44FHwesI1jz42RFnfITbqZops PZUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J3Eq3/ZtacucHtWtxiDbOyDxJylN369Zu0pno0Hd/dY=; b=MbnTziiZph99BsjGcxIBwkxxniAWsGI+fyFbcdJ7embqZ75S/SWlCsRKq1QY/GjfL6 LEQ7hKbTX7joYXu2KSTXFdZl5E8V+cWzamZwzXcAkiidT4Oy7x6jiUm4w//ymq4iljoV S0j8NkydBaEQ6leC5nXugDQLbLSqhFj6t1n1RCo+Og2iXIj6JyDb9X6dsH9kFc+Q176v vJMJMxiR9OtowjHrPqnN5UJgfxZGyYvXZmtPPJhsl+YNLJi5+RtIKpS2U+v/lA+wett+ hJ0tJz7hgaE5hF3zNwn/D0xeC2o+qwd4Acf7lCHvSIIruSQwOJNZaq8NRfmNQK3GrRKF Y4ow== X-Gm-Message-State: APf1xPDmAlz0t19Bx8FtyAaDcZDYNaEmt8DFHVclsWPiQR7l+SNG3XKb wLIbGBvBxvWXaOOy5BYWSloMnbNlatY= X-Google-Smtp-Source: AH8x226dO48S/abNnYyfnUtSfTDqd3XGbGk39f2z1WG2Qr2voucPXHMBY8iqq9GCopJfizFjxgvf6Q== X-Received: by 10.80.164.161 with SMTP id w30mr6972710edb.283.1518613749163; Wed, 14 Feb 2018 05:09:09 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Wed, 14 Feb 2018 13:08:54 +0000 Message-Id: <20180214130857.5020-2-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180214130857.5020-1-pete@akeo.ie> References: <20180214130857.5020-1-pete@akeo.ie> Subject: [edk2] [PATCH 1/4] MdePkg: Disable some Level 4 warnings for VS2017/ARM64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" We disable the exact same warnings as IA32 and X64. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Include/AArch64/ProcessorBind.h | 53 +++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch6= 4/ProcessorBind.h index bc473562f9e5..4f341ebeb03f 100644 --- a/MdePkg/Include/AArch64/ProcessorBind.h +++ b/MdePkg/Include/AArch64/ProcessorBind.h @@ -1,7 +1,7 @@ /** @file Processor or Compiler specific defines and types for AArch64. =20 - Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=20 @@ -30,7 +30,56 @@ #pragma pack() #endif =20 -#if _MSC_EXTENSIONS +#if defined(_MSC_EXTENSIONS) + +// +// Disable some level 4 compilation warnings (same as IA32 and X64) +// + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this war= ning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompil= ed header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For = precompiled header only. +// +#pragma warning ( disable : 4206 ) + +// +// Disable 'potentially uninitialized local variable X used' warnings +// +#pragma warning ( disable : 4701 ) + +// +// Disable 'potentially uninitialized local pointer variable X used' warni= ngs +// +#pragma warning ( disable : 4703 ) + +#endif + +#if defined(_MSC_EXTENSIONS) // // use Microsoft* C compiler dependent integer width types // --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 10:21:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518613759895997.08512340704; Wed, 14 Feb 2018 05:09:19 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9BCAB22161171; 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Wed, 14 Feb 2018 05:09:11 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Wed, 14 Feb 2018 13:08:55 +0000 Message-Id: <20180214130857.5020-3-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180214130857.5020-1-pete@akeo.ie> References: <20180214130857.5020-1-pete@akeo.ie> Subject: [edk2] [PATCH 2/4] MdePkg/Library/BaseLib: Enable VS2017/ARM64 builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Required GCC assembly files are converted for the MSFT assembler Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm | 39 ++++++++ MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm | 37 +++++++ MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm | 37 +++++++ MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm | 49 ++++++++++ MdePkg/Library/BaseLib/AArch64/MemoryFence.asm | 38 ++++++++ MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm | 101 ++++++++++++++= ++++++ MdePkg/Library/BaseLib/AArch64/SwitchStack.asm | 69 +++++++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 8 ++ 8 files changed, 378 insertions(+) diff --git a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/MdePkg/Libr= ary/BaseLib/AArch64/CpuBreakpoint.asm new file mode 100644 index 000000000000..17e993f5b77e --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm @@ -0,0 +1,39 @@ +;-------------------------------------------------------------------------= ----- +; +; CpuBreakpoint() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + + EXPORT CpuBreakpoint + AREA BaseLib_LowLevel, CODE, READONLY + +;/** +; Generates a breakpoint on the CPU. +; +; Generates a breakpoint on the CPU. The breakpoint must be implemented s= uch +; that code can resume normal execution after the breakpoint. +; +;**/ +;VOID +;EFIAPI +;CpuBreakpoint ( +; VOID +; ); +; +CpuBreakpoint + svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had = 'swi' here. + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/MdePkg/= Library/BaseLib/AArch64/DisableInterrupts.asm new file mode 100644 index 000000000000..498493454c7d --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm @@ -0,0 +1,37 @@ +;-------------------------------------------------------------------------= ----- +; +; DisableInterrupts() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT DisableInterrupts + AREA BaseLib_LowLevel, CODE, READONLY + +DAIF_WR_IRQ_BIT EQU (1 << 1) + +;/** +; Disables CPU interrupts. +; +;**/ +;VOID +;EFIAPI +;DisableInterrupts ( +; VOID +; ); +; +DisableInterrupts + msr daifset, #DAIF_WR_IRQ_BIT + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/MdePkg/L= ibrary/BaseLib/AArch64/EnableInterrupts.asm new file mode 100644 index 000000000000..ec3d6e45ff8a --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm @@ -0,0 +1,37 @@ +;-------------------------------------------------------------------------= ----- +; +; EnableInterrupts() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT EnableInterrupts + AREA BaseLib_LowLevel, CODE, READONLY + +DAIF_WR_IRQ_BIT EQU (1 << 1) + +;/** +; Enables CPU interrupts. +; +;**/ +;VOID +;EFIAPI +;EnableInterrupts ( +; VOID +; ); +; +EnableInterrupts + msr daifclr, #DAIF_WR_IRQ_BIT + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/MdePkg= /Library/BaseLib/AArch64/GetInterruptsState.asm new file mode 100644 index 000000000000..d64b0d513ce3 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm @@ -0,0 +1,49 @@ +;-------------------------------------------------------------------------= ----- +; +; GetInterruptState() function for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT GetInterruptState + AREA BaseLib_LowLevel, CODE, READONLY + +DAIF_RD_IRQ_BIT EQU (1 << 7) + +;/** +; Retrieves the current CPU interrupt state. +; +; Returns TRUE is interrupts are currently enabled. Otherwise +; returns FALSE. +; +; @retval TRUE CPU interrupts are enabled. +; @retval FALSE CPU interrupts are disabled. +; +;**/ +; +;BOOLEAN +;EFIAPI +;GetInterruptState ( +; VOID +; ); +; +GetInterruptState + mrs x0, daif + mov w0, wzr + tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=3D1 if clear/un= masked + bne exit // if Z=3D1 (eq) return 1, else 0 + mov w0, #1 +exit + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/MdePkg/Librar= y/BaseLib/AArch64/MemoryFence.asm new file mode 100644 index 000000000000..84dede698ee0 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm @@ -0,0 +1,38 @@ +;-------------------------------------------------------------------------= ----- +; +; MemoryFence() for AArch64 +; +; Copyright (c) 2013, ARM Ltd. All rights reserved. +; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT MemoryFence + AREA BaseLib_LowLevel, CODE, READONLY + +;/** +; Used to serialize load and store operations. +; +; All loads and stores that proceed calls to this function are guaranteed= to be +; globally visible when this function returns. +; +;**/ +;VOID +;EFIAPI +;MemoryFence ( +; VOID +; ); +; +MemoryFence + // System wide Data Memory Barrier. + dmb sy + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/MdePkg/Li= brary/BaseLib/AArch64/SetJumpLongJump.asm new file mode 100644 index 000000000000..e0a9715ff2d1 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm @@ -0,0 +1,101 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2009-2013, ARM Ltd. All rights reserved. +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +;-------------------------------------------------------------------------= ----- + + EXPORT SetJump + EXPORT InternalLongJump + AREA BaseLib_LowLevel, CODE, READONLY + +#define GPR_LAYOUT \ + REG_PAIR (x19, x20, #0); \ + REG_PAIR (x21, x22, #16); \ + REG_PAIR (x23, x24, #32); \ + REG_PAIR (x25, x26, #48); \ + REG_PAIR (x27, x28, #64); \ + REG_PAIR (x29, x30, #80);/*FP, LR*/ \ + REG_ONE (x16, #96) /*IP0*/ + +#define FPR_LAYOUT \ + REG_PAIR ( d8, d9, #112); \ + REG_PAIR (d10, d11, #128); \ + REG_PAIR (d12, d13, #144); \ + REG_PAIR (d14, d15, #160); + +;/** +; Saves the current CPU context that can be restored with a call to LongJ= ump() and returns 0.# +; +; Saves the current CPU context in the buffer specified by JumpBuffer and= returns 0. The initial +; call to SetJump() must always return 0. Subsequent calls to LongJump()= cause a non-zero +; value to be returned by SetJump(). +; +; If JumpBuffer is NULL, then ASSERT(). +; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then = ASSERT(). +; +; @param JumpBuffer A pointer to CPU context buffer. +; +;**/ +; +;UINTN +;EFIAPI +;SetJump ( +; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0 +; ); +; +SetJump + mov x16, sp // use IP0 so save SP +#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS] +#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS] + GPR_LAYOUT + FPR_LAYOUT +#undef REG_PAIR +#undef REG_ONE + mov w0, #0 + ret + +;/** +; Restores the CPU context that was saved with SetJump().# +; +; Restores the CPU context from the buffer specified by JumpBuffer. +; This function never returns to the caller. +; Instead is resumes execution based on the state of JumpBuffer. +; +; @param JumpBuffer A pointer to CPU context buffer. +; @param Value The value to return when the SetJump() context is= restored. +; +;**/ +;VOID +;EFIAPI +;InternalLongJump ( +; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0 +; IN UINTN Value // X1 +; ); +; +InternalLongJump +#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS] +#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS] + GPR_LAYOUT + FPR_LAYOUT +#undef REG_PAIR +#undef REG_ONE + mov sp, x16 + cmp w1, #0 + mov w0, #1 + beq exit + mov w0, w1 +exit + // use br not ret, as ret is guaranteed to mispredict + br x30 + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED + + END + diff --git a/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/MdePkg/Librar= y/BaseLib/AArch64/SwitchStack.asm new file mode 100644 index 000000000000..c1b2de07e205 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm @@ -0,0 +1,69 @@ +//------------------------------------------------------------------------= ------ +// +// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved. +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the B= SD License +// which accompanies this distribution. The full text of the license may = be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +// +//------------------------------------------------------------------------= ------ + + EXPORT InternalSwitchStackAsm + EXPORT CpuPause + AREA BaseLib_LowLevel, CODE, READONLY + +/** +// +// This allows the caller to switch the stack and goes to the new entry p= oint +// +// @param EntryPoint The pointer to the location to enter +// @param Context Parameter to pass in +// @param Context2 Parameter2 to pass in +// @param NewStack New Location of the stack +// +// @return Nothing. Goes to the Entry Point passing in the new paramet= ers +// +VOID +EFIAPI +InternalSwitchStackAsm ( + SWITCH_STACK_ENTRY_POINT EntryPoint, + VOID *Context, + VOID *Context2, + VOID *NewStack + ); +**/ +InternalSwitchStackAsm + mov x29, #0 + mov x30, x0 + mov sp, x3 + mov x0, x1 + mov x1, x2 + ret + +/** +// +// Requests CPU to pause for a short period of time. +// +// Requests CPU to pause for a short period of time. Typically used in MP +// systems to prevent memory starvation while waiting for a spin lock. +// +VOID +EFIAPI +CpuPause ( + VOID + ) +**/ +CpuPause + nop + nop + nop + nop + nop + ret + + END diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3c07e6bad977..80d00ebed75b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -867,6 +867,14 @@ [Sources.AARCH64] AArch64/SetJumpLongJump.S | GCC AArch64/CpuBreakpoint.S | GCC =20 + AArch64/MemoryFence.asm | MSFT + AArch64/SwitchStack.asm | MSFT + AArch64/EnableInterrupts.asm | MSFT + AArch64/DisableInterrupts.asm | MSFT + AArch64/GetInterruptsState.asm | MSFT + AArch64/SetJumpLongJump.asm | MSFT + AArch64/CpuBreakpoint.asm | MSFT + [Packages] MdePkg/MdePkg.dec =20 --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 10:21:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" We need to explicitly call the built-in __va_start() for ARM64, otherwise the variable parameters are not properly enqueued for the next function calls. Also do the same for ARM, as as it doesn't harm us. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Include/Base.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index a94182f08886..4f7bd4449c36 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -668,16 +668,15 @@ struct _LIST_ENTRY { =20 #define VA_COPY(Dest, Start) __va_copy (Dest, Start) =20 -#elif defined(_M_ARM) +#elif defined(_M_ARM) || defined(_M_ARM64) // // MSFT ARM variable argument list support. -// Same as the generic macros below, except for VA_ARG that needs extra ad= justment. // =20 typedef char* VA_LIST; =20 -#define VA_START(Marker, Parameter) (Marker =3D (VA_LIST) ((UINTN) & (= Parameter) + _INT_SIZE_OF(Parameter))) -#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker +=3D _INT_SIZE= _OF(TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE))) +#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _= INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter) +#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker +=3D _INT_SIZE= _OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE))) #define VA_END(Marker) (Marker =3D (VA_LIST) 0) #define VA_COPY(Dest, Start) ((void)((Dest) =3D (Start))) =20 --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 10:21:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151861376456345.3035092518445; Wed, 14 Feb 2018 05:09:24 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP 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X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Build options for ARM64 are the same as for ARM, except for /BASE:0 which is removed from DLINK flags to avoid LNK1355 error: invalid base address 0x0; ARM64 image cannot have base address below 4GB Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- BaseTools/Conf/build_rule.template | 2 +- BaseTools/Conf/tools_def.template | 32 ++++++++++++++++++-- 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule= .template index 77ed282e0311..308505b3dca5 100755 --- a/BaseTools/Conf/build_rule.template +++ b/BaseTools/Conf/build_rule.template @@ -206,7 +206,7 @@ # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iii =20 -[Assembly-Code-File.COMMON.ARM] +[Assembly-Code-File.COMMON.ARM,Assembly-Code-File.COMMON.AARCH64] # Remove --convert-hex for ARM as it breaks MSFT assemblers ?.asm, ?.Asm, ?.ASM diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 427ad60b0e26..703019129f79 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -80,6 +80,7 @@ DEFINE VS2017_BIN_HOST =3D DEF(VS2017_BIN)\HostDEF(VS2= 017_HOST)\DEF(VS2017_HOST DEFINE VS2017_BIN_IA32 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x86 DEFINE VS2017_BIN_X64 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x64 DEFINE VS2017_BIN_ARM =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\arm +DEFINE VS2017_BIN_AARCH64 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\arm64 =20 DEFINE WINSDK_BIN =3D ENV(WINSDK_PREFIX) DEFINE WINSDKx86_BIN =3D ENV(WINSDKx86_PREFIX) @@ -329,7 +330,7 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Intel(r) ACPI Compiler (iasl.exe) from # https://acpica.org/downloads # VS2017 -win32- Requires: -# Microsoft Visual Studio 2017 version 15.2 or= later +# Microsoft Visual Studio 2017 version 15.2 (1= 5.4 for ARM64) or later # Optional: # Required to build EBC drivers: # Intel(r) Compiler for Efi Byte Code (Intel= (r) EBC Compiler) @@ -337,7 +338,7 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Intel(r) ACPI Compiler (iasl.exe) from # https://acpica.org/downloads # Note: -# Building of XIP firmware images for ARM is n= ot currently supported (only applications). +# Building of XIP firmware images for ARM/ARM6= 4 is not currently supported (only applications). # /FILEALIGN:4096 and other changes are needed= for ARM firmware builds. # DDK3790 -win32- Requires: # Microsoft Windows Server 2003 Driver Develop= ment Kit (Microsoft WINDDK) version 3790.1830 @@ -4200,6 +4201,33 @@ NOOPT_VS2017_ARM_ASM_FLAGS =3D /nologo RELEASE_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D= /MACHINE:ARM /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SE= RVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=3D.data NOOPT_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM= /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER = /SAFESEH:NO /BASE:0 /DRIVER /DEBUG =20 +##################### +# AARCH64 definitions +##################### +*_VS2017_AARCH64_CC_PATH =3D DEF(VS2017_BIN_AARCH64)\cl.exe +*_VS2017_AARCH64_VFRPP_PATH =3D DEF(VS2017_BIN_AARCH64)\cl.exe +*_VS2017_AARCH64_SLINK_PATH =3D DEF(VS2017_BIN_AARCH64)\lib.exe +*_VS2017_AARCH64_DLINK_PATH =3D DEF(VS2017_BIN_AARCH64)\link.exe +*_VS2017_AARCH64_APP_PATH =3D DEF(VS2017_BIN_AARCH64)\cl.exe +*_VS2017_AARCH64_PP_PATH =3D DEF(VS2017_BIN_AARCH64)\cl.exe +*_VS2017_AARCH64_ASM_PATH =3D DEF(VS2017_BIN_AARCH64)\armasm64.exe +*_VS2017_AARCH64_ASLCC_PATH =3D DEF(VS2017_BIN_AARCH64)\cl.exe +*_VS2017_AARCH64_ASLPP_PATH =3D DEF(VS2017_BIN_AARCH64)\cl.exe +*_VS2017_AARCH64_ASLDLINK_PATH =3D DEF(VS2017_BIN_AARCH64)\link.exe + + *_VS2017_AARCH64_MAKE_FLAGS =3D /nologo + DEBUG_VS2017_AARCH64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D= UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Gw /Oi- +RELEASE_VS2017_AARCH64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D= UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gw /Oi- +NOOPT_VS2017_AARCH64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D= UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Od /Oi- + + DEBUG_VS2017_AARCH64_ASM_FLAGS =3D /nologo /g +RELEASE_VS2017_AARCH64_ASM_FLAGS =3D /nologo +NOOPT_VS2017_AARCH64_ASM_FLAGS =3D /nologo + + DEBUG_VS2017_AARCH64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 = /OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:AR= M64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIV= ER /SAFESEH:NO /DRIVER /DEBUG +RELEASE_VS2017_AARCH64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 = /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,= D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT= _SERVICE_DRIVER /SAFESEH:NO /DRIVER /MERGE:.rdata=3D.data +NOOPT_VS2017_AARCH64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 = /OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:AR= M64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIV= ER /SAFESEH:NO /DRIVER /DEBUG + ################## # EBC definitions ################## --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org 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