From nobody Sat May 4 12:49:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518576340089903.1892967116933; Tue, 13 Feb 2018 18:45:40 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4AB8A222DE127; Tue, 13 Feb 2018 18:39:47 -0800 (PST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0209421CF1CEF for ; Tue, 13 Feb 2018 18:39:45 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2018 18:45:36 -0800 Received: from zwei4-mobl1.ccr.corp.intel.com ([10.239.193.69]) by fmsmga006.fm.intel.com with ESMTP; 13 Feb 2018 18:45:35 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,510,1511856000"; d="scan'208";a="204015871" From: zwei4 To: edk2-devel@lists.01.org Date: Wed, 14 Feb 2018 10:45:32 +0800 Message-Id: <20180214024532.13772-1-david.wei@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] IDTP9180 PMIC Power Sequence Configuration. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (off= set 0x2A) to 1. If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to = G3 when SUSPWRDNACK goes high in S4 state. If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 --- .../AuroraGlacier/BoardInitDxe/BoardInitDxe.c | 114 +++++++++++++++++= +++ .../AuroraGlacier/BoardInitDxe/BoardInitDxe.inf | 1 + .../BensonGlacier/BoardInitDxe/BoardInitDxe.c | 115 +++++++++++++++++= +++- .../BensonGlacier/BoardInitDxe/BoardInitDxe.inf | 1 + .../PlatformSettings/PlatformDxe/PlatformDxe.inf | 2 +- Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 5 + Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc | 15 ++- Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc | 6 +- .../BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h | 2 +- .../SouthCluster/Smbus/Dxe/PchSmbusEntry.c | 2 + 10 files changed, 258 insertions(+), 5 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/B= oardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDx= e/BoardInitDxe.c index e948594c8..f06a540eb 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardIni= tDxe.c +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardIni= tDxe.c @@ -15,6 +15,7 @@ **/ =20 #include "BoardInitDxe.h" +#include =20 GET_BOARD_NAME mAuroraGetBoardNamePtr =3D AuroraGetBoardName; =20 @@ -38,6 +39,111 @@ AuroraGetBoardName ( } =20 =20 +VOID +EFIAPI +AuroraProgramPmicPowerSequence ( + EFI_EVENT Event, + VOID *Context + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + EFI_SMBUS_DEVICE_COMMAND Command; + UINTN Length; + UINT8 BufferData[1]; + EFI_SMBUS_HC_PROTOCOL *SmbusControllerProtocol; + =20 + // + // Programe IDTP9810 PMIC. + // + =20 + DEBUG ((EFI_D_INFO, "Programe PMIC. \n")); + =20 + // + // Locate SMBus protocol + // + Status =3D gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID *= *)&SmbusControllerProtocol); + ASSERT_EFI_ERROR(Status); + =20 + SlaveAddress.SmbusDeviceAddress =3D (0xBC >> 1); // 0x5E + Command =3D 0x00; // Offset + Length =3D 1; + =20 + // + // Read one byte + // + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + BufferData + ); + =20 + =20 + DEBUG ((EFI_D_INFO, "PMIC Vendor ID =3D %0x. \n", (UINT32) BufferData[0]= )); + =20 + + SlaveAddress.SmbusDeviceAddress =3D (0xBC >> 1); // 0x5E + Command =3D 0x2A; // Offset + Length =3D 1; + =20 + // + // Read one byte + // + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + BufferData + ); + =20 + =20 + DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRS= EQCFG =3D %0x. \n", (UINT32) BufferData[0]));=20 + + // + // Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG. + // 0 =3D SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSP= WRDNACK goes high in S4 state. + // 1 =3D PMIC responses to SUSPWRDNACK signal. + // + // + BufferData[0] =3D BufferData[0] | 0x04; + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusWriteByte, + FALSE, + &Length, + BufferData + ); + DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Set Bit 2 (SUSPWR= DNACKCFG) of PWRSEQCFG. \n"));=20 + + + // + // Read one byte + // + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + BufferData + ); + =20 + =20 + DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRS= EQCFG =3D %0x. \n", (UINT32) BufferData[0]));=20 +} + + + /** Set PCDs for board specific functions. =20 @@ -55,6 +161,7 @@ AuroraBoardInitDxeConstructor ( ) { UINT8 BoardId; + EFI_EVENT ReadyToBootEvent; =20 BoardId =3D PcdGet8 (PcdBoardId); if (BoardId !=3D (UINT8) BOARD_ID_AURORA) { @@ -63,6 +170,13 @@ AuroraBoardInitDxeConstructor ( =20 PcdSet64 (PcdGetBoardNameFunc, (UINT64) mAuroraGetBoardNamePtr); =20 + EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + AuroraProgramPmicPowerSequence, + NULL, + &ReadyToBootEvent + ); + =20 return EFI_SUCCESS; } =20 diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/B= oardInitDxe.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInit= Dxe/BoardInitDxe.inf index 62899f61e..5fb96438a 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardIni= tDxe.inf +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitDxe/BoardIni= tDxe.inf @@ -43,6 +43,7 @@ PrintLib =20 [Protocols] + gEfiSmbusHcProtocolGuid =20 [Guids] =20 diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/B= oardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDx= e/BoardInitDxe.c index d49d2594e..702c53c49 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardIni= tDxe.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardIni= tDxe.c @@ -2,7 +2,7 @@ Board specific functions in DXE phase to be set as dynamic PCD and consu= med by commmon platform code. =20 - Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -15,6 +15,7 @@ **/ =20 #include "BoardInitDxe.h" +#include =20 GET_BOARD_NAME mBgGetBoardNamePtr =3D BgGetBoardName; =20 @@ -38,6 +39,110 @@ BgGetBoardName ( } =20 =20 +VOID +EFIAPI +BensonProgramPmicPowerSequence ( + EFI_EVENT Event, + VOID *Context + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + EFI_SMBUS_DEVICE_COMMAND Command; + UINTN Length; + UINT8 BufferData[1]; + EFI_SMBUS_HC_PROTOCOL *SmbusControllerProtocol; + =20 + // + // Programe PMIC. + // + =20 + DEBUG ((EFI_D_INFO, "Programe IDTP9810 PMIC. \n")); + =20 + // + // Locate SMBus protocol + // + Status =3D gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID *= *)&SmbusControllerProtocol); + ASSERT_EFI_ERROR(Status); + =20 + SlaveAddress.SmbusDeviceAddress =3D (0xBC >> 1); // 0x5E + Command =3D 0x00; // Offset + Length =3D 1; + =20 + // + // Read one byte + // + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + BufferData + ); + =20 + =20 + DEBUG ((EFI_D_INFO, "PMIC Vendor ID =3D %0x. \n", (UINT32) BufferData[0]= )); + =20 + + SlaveAddress.SmbusDeviceAddress =3D (0xBC >> 1); // 0x5E + Command =3D 0x2A; // Offset + Length =3D 1; + =20 + // + // Read one byte + // + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + BufferData + ); + =20 + =20 + DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRS= EQCFG =3D %0x. \n", (UINT32) BufferData[0]));=20 + + // + // Set Bit 2 (SUSPWRDNACKCFG) of PWRSEQCFG. + // 0 =3D SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSP= WRDNACK goes high in S4 state. + // 1 =3D PMIC responses to SUSPWRDNACK signal. + // + BufferData[0] =3D BufferData[0] | 0x04; + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusWriteByte, + FALSE, + &Length, + BufferData + ); + DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Set Bit 2 (SUSPWR= DNACKCFG) of PWRSEQCFG. \n"));=20 + + + // + // Read one byte + // + Status =3D SmbusControllerProtocol->Execute (=20 + SmbusControllerProtocol, + SlaveAddress, + Command, + EfiSmbusReadByte, + FALSE, + &Length, + BufferData + ); + =20 + =20 + DEBUG ((EFI_D_INFO, "PMIC Power Sequence Configuration Offset 0x2A PWRS= EQCFG =3D %0x. \n", (UINT32) BufferData[0]));=20 +} + + + /** Set PCDs for board specific functions. =20 @@ -55,6 +160,7 @@ BgBoardInitDxeConstructor ( ) { UINT8 BoardId; + EFI_EVENT ReadyToBootEvent; =20 BoardId =3D PcdGet8 (PcdBoardId); if (BoardId !=3D (UINT8) BOARD_ID_BENSON) { @@ -63,6 +169,13 @@ BgBoardInitDxeConstructor ( =20 PcdSet64 (PcdGetBoardNameFunc, (UINT64) mBgGetBoardNamePtr); =20 + EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + BensonProgramPmicPowerSequence, + NULL, + &ReadyToBootEvent + ); + return EFI_SUCCESS; } =20 diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/B= oardInitDxe.inf b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInit= Dxe/BoardInitDxe.inf index d7e7400cb..2f5a1a406 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardIni= tDxe.inf +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitDxe/BoardIni= tDxe.inf @@ -43,6 +43,7 @@ PrintLib =20 [Protocols] + gEfiSmbusHcProtocolGuid =20 [Guids] =20 diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDx= e/PlatformDxe.inf b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformDxe/PlatformDxe.inf index 8cb63e946..440071fd4 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platf= ormDxe.inf +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platf= ormDxe.inf @@ -120,7 +120,7 @@ gEfiSeCOperationProtocolGuid gEfiUgaDrawProtocolGuid gEfiUgaDrawProtocolGuid |PcdUgaConsumeSupport - gEfiShellProtocolGuid + gEfiShellProtocolGuid =20 [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/Broxton= PlatformPkg/PlatformPkg.fdf index a037708f7..6c377553f 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf @@ -692,6 +692,11 @@ APRIORI DXE { # INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf INF $(PLATFORM_PACKAGE_COMMON)/Features/Smbios/SmBiosMiscDxe/SmBiosMiscD= xe.inf + =20 + # + #SM Bus + # + INF $(PLATFORM_SI_PACKAGE)/SouthCluster/Smbus/Dxe/PchSmbusDxe.inf =20 # # LAN/Network diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc b/Silicon/Broxton= SoC/BroxtonSiPkg/SiPkgDxe.dsc index 4ae080302..1a9da7729 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxe.dsc @@ -1,7 +1,7 @@ ## @file # Component description file for the Broxton RC DXE drivers. # -# Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -41,3 +41,16 @@ $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf { } !endif =20 +$(PLATFORM_SI_PACKAGE)/SouthCluster/Smbus/Dxe/PchSmbusDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xFFFFFFFF + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + +!if $(TARGET) !=3D RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf +!endif + + ICC:*_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG + GCC:*_*_*_CC_FLAGS =3D -D MDEPKG_NDEBUG + } diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc b/Silicon/Brox= tonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc index ff36dccd4..935691a29 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SiPkgDxeLib.dsc @@ -1,7 +1,7 @@ ## @file # Component description file for the Broxton RC DXE libraries. # -# Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -33,3 +33,7 @@ HeciMsgLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLi= b.inf SeCLib|$(PLATFORM_SI_PACKAGE)/Txe/Library/SeCLib/SeCLib.inf =20 +# +# SMBus +# =20 + ScSmbusCommonLib|$(PLATFORM_SI_PACKAGE)/SouthCluster/Library/Private/Pei= DxeSmmScSmbusCommonLib/PeiDxeSmmScSmbusCommonLib.inf diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbu= s.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h index 5e226a80d..6218de8dd 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbus.h @@ -92,7 +92,7 @@ typedef struct _SMBUS_INSTANCE { // // Driver global data // -SMBUS_INSTANCE *mSmbusContext; +extern SMBUS_INSTANCE *mSmbusContext; =20 // // Prototypes diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbu= sEntry.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusE= ntry.c index 6ae16f343..021cf26c9 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Smbus/Dxe/PchSmbusEntry.c @@ -17,6 +17,8 @@ =20 extern EFI_GUID gEfiSmbusArpMapGuid; =20 +SMBUS_INSTANCE *mSmbusContext; + /** Execute an SMBus operation =20 --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel