From nobody Mon Apr 29 15:50:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517918668890147.0256402007135; Tue, 6 Feb 2018 04:04:28 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A5F7F223972BF; Tue, 6 Feb 2018 03:58:44 -0800 (PST) Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 10E0C223972AE for ; Tue, 6 Feb 2018 03:58:42 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id h9so1628098wre.12 for ; Tue, 06 Feb 2018 04:04:25 -0800 (PST) Received: from localhost.localdomain ([160.162.151.6]) by smtp.gmail.com with ESMTPSA id 2sm6669561wra.58.2018.02.06.04.04.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 04:04:22 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=vlDLMYuyHmYEPcVS7IUlxxLtvCwUiFPva/JXBN8gCN8=; b=DXi1Wi7qG54gR37ch2E1McZjGY+HSbhTCU5AyLWLYszZ+5dcKOpUhwDuKyLQIwe3CP UeZVbuUcRBGgBtDJ/OkwEt8V4w7OHa2QjE0IqNQ7liJ1ILhsRQOL3xbKdR3xdZOVRag+ KzPVdG6+DybYhYGS4yWTIjxLLZvZegBYUJLTQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vlDLMYuyHmYEPcVS7IUlxxLtvCwUiFPva/JXBN8gCN8=; b=A71ZkgoHI7ScBxyAQGoiy2mHEE3p7t9R3pfpcIyXoU748vUAY5HxDT0InNnEO93m1v 2haiz8ZTs2ey9VlCpUiq8c02ABHYSyHb+btXJuAgH619tb5fElKdW1MgjK9VxafnrIBe TgCEK16eoxBtRck+WzhRXiGbAwo80emh06Nzcp9QbmBv+c6bYxSTLY3tBf1aKyXNUP4N TjHaX1cichcwk9eLlrLuyzxkVXh8E4jKR73BGImjntPZlA+p0aGbzcszTpTQ1wKSAj4Y ad/QVdclxB+QY7KTE42IHk90UO6aEpbj++crywfs+2q53qQbk2q6J2IDjWK9oIb2ySvg nm7A== X-Gm-Message-State: APf1xPAAKOYiFwkMhCmeSCJ4xd258xZYWJSIG9sRO/IxtCrN5QIS9Qvb kKRChADU0uEUkp8/jy/bPbStx9r9RPQ= X-Google-Smtp-Source: AH8x227sZ0kXNmot1F85YmfrZ45loUKWie0oDkDa9o7e4os9x8zTWj8qvSgR6TeHZcHXcGtsNGD/AA== X-Received: by 10.223.191.10 with SMTP id p10mr1900921wrh.62.1517918663202; Tue, 06 Feb 2018 04:04:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Tue, 6 Feb 2018 12:04:16 +0000 Message-Id: <20180206120416.17462-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH] ArmPkg/Gic: force GIC driver to run before CPU arch protocol driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently, the GIC driver has a static dependency on the CPU arch protocol driver, so it can register its IRQ handler at init time. This means there is a window between dispatch of the CPU driver and dispatch of the GIC driver where any unexpected GIC state may trigger an interrupt which we are not set up to handle yet. Note that this is even the case if we enter UEFI with interrupts disabled at the CPU, given that any TPL manipulation involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side regardless of whether they were enabled to begin with (but only as soon as the CPU arch protocol is actually installed) So let's reorder the GIC driver with the CPU driver, and let it run its initialization that puts the GIC into a known state before enabling interrupts. Move its installation of its IRQ handler to a protocol notify callback on the CPU arch protocol so that it runs as soon as it becomes available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Tested-by: Marc Zyngier --- This fixes an issue observed with GICv3 guests running under KVM. ArmPkg/ArmPkg.dec | 2 + ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c | 69 +++++++++++++------- ArmPkg/Drivers/ArmGic/ArmGicDxe.h | 1 + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 5 +- ArmPkg/Drivers/CpuDxe/CpuDxe.inf | 2 +- 5 files changed, 54 insertions(+), 25 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 5dbd019e2966..a55b6268ff85 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -48,6 +48,8 @@ [Guids.common] # Include/Guid/ArmMpCoreInfo.h gArmMpCoreInfoGuid =3D { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65,= 0x8e, 0xd8, 0x57, 0xe8, 0x34} } =20 + gArmGicDxeFileGuid =3D { 0xde371f7c, 0xdec4, 0x4d21, { 0xad, 0xf1, 0x59,= 0x3a, 0xbc, 0xc1, 0x58, 0x82 } } + [Ppis] ## Include/Ppi/ArmMpCoreInfo.h gArmMpCoreInfoPpiGuid =3D { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xa= b, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } diff --git a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/ArmPkg/Drivers/ArmGi= c/ArmGicCommonDxe.c index bff8d983cf02..e1adcd3bc6d3 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -121,6 +121,44 @@ RegisterInterruptSource ( } } =20 +STATIC VOID *mCpuArchProtocolNotifyEventRegistration; + +STATIC +VOID +EFIAPI +CpuArchEventProtocolNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_CPU_ARCH_PROTOCOL *Cpu; + EFI_STATUS Status; + + // Get the CPU protocol that this driver requires. + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= )&Cpu); + if (EFI_ERROR (Status)) { + return; + } + + // Unregister the default exception handler. + Status =3D Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, N= ULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", + __FUNCTION__, Status)); + return; + } + + // Register to receive interrupts + Status =3D Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, + Context); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", + __FUNCTION__, Status)); + } + + gBS->CloseEvent (Event); +} + EFI_STATUS InstallAndRegisterInterruptService ( IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, @@ -130,7 +168,6 @@ InstallAndRegisterInterruptService ( ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; CONST UINTN RihArraySize =3D (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts); =20 @@ -152,27 +189,15 @@ InstallAndRegisterInterruptService ( return Status; } =20 - // Get the CPU protocol that this driver requires. - Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= )&Cpu); - if (EFI_ERROR (Status)) { - return Status; - } - - // Unregister the default exception handler. - Status =3D Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, N= ULL); - if (EFI_ERROR (Status)) { - return Status; - } - - // Register to receive interrupts - Status =3D Cpu->RegisterInterruptHandler ( - Cpu, - ARM_ARCH_EXCEPTION_IRQ, - InterruptHandler - ); - if (EFI_ERROR (Status)) { - return Status; - } + // + // Install the interrupt handler as soon as the CPU arch protocol appear= s. + // + EfiCreateProtocolNotifyEvent ( + &gEfiCpuArchProtocolGuid, + TPL_CALLBACK, + CpuArchEventProtocolNotify, + InterruptHandler, + &mCpuArchProtocolNotifyEventRegistration); =20 // Register for an ExitBootServicesEvent Status =3D gBS->CreateEvent ( diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/ArmPkg/Drivers/ArmGic/ArmG= icDxe.h index 610ffacc7eb0..f6b75d729601 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -21,6 +21,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include =20 #include #include diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/Ar= mGicDxe.inf index d5921533fb68..24b02ef30e83 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D ArmGicDxe - FILE_GUID =3D DE371F7C-DEC4-4D21-ADF1-593ABCC15882 + FILE_GUID =3D DE371F7C-DEC4-4D21-ADF1-593ABCC15882 = # gArmGicDxeFileGuid MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 =20 @@ -45,6 +45,7 @@ [LibraryClasses] UefiDriverEntryPoint IoLib PcdLib + UefiLib =20 [Protocols] gHardwareInterruptProtocolGuid @@ -58,4 +59,4 @@ [Pcd.common] gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy =20 [Depex] - gEfiCpuArchProtocolGuid + TRUE diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/ArmPkg/Drivers/CpuDxe/CpuDx= e.inf index d068e06803ed..cda549922e9c 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf @@ -76,4 +76,4 @@ [FeaturePcd.common] gArmTokenSpaceGuid.PcdDebuggerExceptionSupport =20 [Depex] - TRUE + AFTER gArmGicDxeFileGuid --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel