From nobody Thu Apr 25 00:11:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515601629983156.99156527261914; Wed, 10 Jan 2018 08:27:09 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F12CF222CF1DE; Wed, 10 Jan 2018 08:21:49 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 84F9E222CF1CD for ; Wed, 10 Jan 2018 08:21:47 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id b141so121718wme.1 for ; Wed, 10 Jan 2018 08:26:59 -0800 (PST) Received: from localhost.localdomain ([84.203.41.108]) by smtp.gmail.com with ESMTPSA id a52sm10543021eda.92.2018.01.10.08.26.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 08:26:54 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HdYN7DdtPr4H2YuDR7zzPSSL/AliulcNO2vbj0/dPho=; b=Tq7mR6OEPMbrnAibCn3B1gO6Z4reP69vLVVOTpuQV05F8VqEGjSmBzSOZ71ACx3rjJ eUJ+ezbrt1ZOI9AjleXFDv2GN3ekPKc+hwe6K2+mOvpwSTrrOVmz0IgKWfWYLSyJyLUX uVurCge0OVL6TBMNDxQDPL83tzjPrffo6spxdmLa2+i3P2XoqmP2pwtLIDlb8JrxRGvh 2Z9k/xc/+LnvXmKIR35e5t3ELiZNiLzfl0aHcdA5ED1Lv2SKE1t6htsZ1YMZxYxdVp7n 6mFzuTeRYYT8xgsLNKLiGQquI3X3zGv1dBDqV6mb6V1Y+xOJrq0Uc/iU4NkJpOM4V3c6 SAVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HdYN7DdtPr4H2YuDR7zzPSSL/AliulcNO2vbj0/dPho=; b=iQLw09IvUwy6l0W69OITi2wkknG1JNA299mV57dObZazauD1dkJjPKDqhF0iCEyx2/ xT+k2/KYV0YE/ryw4xOQABZjbxDUL8NSyl+BnG+jEQCknFxoPvTgHetS5OaPpHNYD86k FoNwCCxefItg395CfS3nqKGWDtUOCnnfxHtF3Nt8yVn+dhzXvANB+CkbDb+9nui+f3UH tJbcomGJfd3A0MdfaM5N4Hki3nVbmmaODa2cXXW8Lx+k66YkMT6dBoRvwe2FYcX4Mgxj Oxz6LkMnv3L21RMiY2nLAO2t2JCojLNWeTQvbswjd6ZPAqiVb+Z5KoIDiS/UT+jom6Xu a9GQ== X-Gm-Message-State: AKGB3mKRqVFZkcDWdinyaanLqNnORT1YS2T9kf7dI4JfW4vJT9FEBEnE BY5P633UDo/HOJ6HHkQiVPcBn9+m8l4= X-Google-Smtp-Source: ACJfBos2fHcDeeoEhS4JnhBZbk7kXvrg+AQT8Tm4mYQqEt3CVhz0TILj2kSuO9Vd2IFokhZFCUlJOQ== X-Received: by 10.80.207.67 with SMTP id d3mr26690253edk.119.1515601615266; Wed, 10 Jan 2018 08:26:55 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 16:26:39 +0000 Message-Id: <20180110162644.11208-2-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180110162644.11208-1-pete@akeo.ie> References: <20180110162644.11208-1-pete@akeo.ie> Subject: [edk2] [PATCH v4 1/6] MdePkg: Disable some Level 4 warnings for VS2017/ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" We disable the exact same warnings as IA32 and X64. Also create a dummy macro for PRESERVE8, as this is not supported by the Microsoft ARM assembler. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Include/Arm/ProcessorBind.h | 96 +++++++++++++++----- 1 file changed, 75 insertions(+), 21 deletions(-) diff --git a/MdePkg/Include/Arm/ProcessorBind.h b/MdePkg/Include/Arm/Proces= sorBind.h index 42ea2f3055f3..afb2f05446f0 100644 --- a/MdePkg/Include/Arm/ProcessorBind.h +++ b/MdePkg/Include/Arm/ProcessorBind.h @@ -1,15 +1,15 @@ /** @file Processor or Compiler specific defines and types for ARM. =20 - Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- This program and the accompanying materials =20 - are licensed and made available under the terms and conditions of the BS= D License =20 - which accompanies this distribution. The full text of the license may b= e found at =20 - http://opensource.org/licenses/bsd-license.php = =20 + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php =20 - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, = =20 - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -28,14 +28,63 @@ #pragma pack() #endif =20 +#if defined(_MSC_EXTENSIONS) + // -// RVCT does not support the __builtin_unreachable() macro +// Disable some level 4 compilation warnings (same as IA32 and X64) // -#ifdef __ARMCC_VERSION + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this war= ning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompil= ed header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For = precompiled header only. +// +#pragma warning ( disable : 4206 ) + +// +// Disable 'potentially uninitialized local variable X used' warnings +// +#pragma warning ( disable : 4701 ) + +// +// Disable 'potentially uninitialized local pointer variable X used' warni= ngs +// +#pragma warning ( disable : 4703 ) + +#endif + +// +// RVCT and MSFT don't support the __builtin_unreachable() macro +// +#if defined(__ARMCC_VERSION) || defined(_MSC_EXTENSIONS) #define UNREACHABLE() #endif =20 -#if _MSC_EXTENSIONS=20 +#if defined(_MSC_EXTENSIONS) // // use Microsoft* C compiler dependent integer width types // @@ -52,7 +101,7 @@ typedef signed char INT8; #else // - // Assume standard ARM alignment.=20 + // Assume standard ARM alignment. // Need to check portability of long long // typedef unsigned long long UINT64; @@ -121,7 +170,7 @@ typedef INT32 INTN; // use the correct C calling convention. All protocol member functions and // EFI intrinsics are required to modify their member functions with EFIAP= I. // -#define EFIAPI =20 +#define EFIAPI =20 // When compiling with Clang, we still use GNU as for the assembler, so we= still // need to define the GCC_ASM* macros. @@ -142,34 +191,39 @@ typedef INT32 INTN; =20 #define GCC_ASM_EXPORT(func__) \ .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function =20 + .type ASM_PFX(func__), %function =20 #define GCC_ASM_IMPORT(func__) \ .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - =20 + #else // - // .type not supported by Apple Xcode tools=20 + // .type not supported by Apple Xcode tools // - #define INTERWORK_FUNC(func__) =20 + #define INTERWORK_FUNC(func__) =20 #define GCC_ASM_EXPORT(func__) \ .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \ - =20 - #define GCC_ASM_IMPORT(name) =20 + + #define GCC_ASM_IMPORT(name) =20 #endif +#elif defined(_MSC_EXTENSIONS) + // + // PRESERVE8 is not supported by the MSFT assembler. + // + #define PRESERVE8 #endif =20 /** Return the pointer to the first instruction of a function given a functi= on pointer. - On ARM CPU architectures, these two pointer values are the same,=20 + On ARM CPU architectures, these two pointer values are the same, so the implementation of this macro is very simple. - =20 + @param FunctionPointer A pointer to a function. =20 @return The pointer to the first instruction of a function given a funct= ion pointer. - =20 + **/ #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoin= ter) =20 --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 25 00:11:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf | 5 +++-- MdePkg/Library/BaseStackCheckLib/BaseStackCheckNull.c | 18 ++++++++++++++= ++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf b/MdePk= g/Library/BaseStackCheckLib/BaseStackCheckLib.inf index d02d97107b08..e280651b1199 100644 --- a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf +++ b/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf @@ -30,8 +30,9 @@ [Defines] # =20 [Sources] - BaseStackCheckGcc.c | GCC - BaseStackCheckGcc.c | RVCT + BaseStackCheckGcc.c | GCC + BaseStackCheckGcc.c | RVCT + BaseStackCheckNull.c | MSFT =20 [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckNull.c b/MdePkg= /Library/BaseStackCheckLib/BaseStackCheckNull.c new file mode 100644 index 000000000000..ebb387fee5e1 --- /dev/null +++ b/MdePkg/Library/BaseStackCheckLib/BaseStackCheckNull.c @@ -0,0 +1,18 @@ +/*++ + + Copyright (c) 2018, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +Abstract: + + This file is purely empty as a work around for BaseStackCheck to pass MS= VC build. + +**/ + +extern int __BaseStackCheckNull; --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 25 00:11:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515601624445452.53548347298386; Wed, 10 Jan 2018 08:27:04 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4C643222CF1D8; Wed, 10 Jan 2018 08:21:49 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 80EB5222CF1B4 for ; Wed, 10 Jan 2018 08:21:47 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id i11so90331wmf.4 for ; Wed, 10 Jan 2018 08:26:59 -0800 (PST) Received: from localhost.localdomain ([84.203.41.108]) by smtp.gmail.com with ESMTPSA id a52sm10543021eda.92.2018.01.10.08.26.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 08:26:56 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u4CKXqpFMI2C1FqAFOKC7cbWc6gnlEg0Eh+ov0SoYW8=; b=umC1O7ZWQTI4WXiKrrX0dODHPZstxnbx/nE7V0LWXmD4T6D42ZhzHi3LMcW7jzHQqw kMy2CfpwyeXRiiZTWYbGOecKlWmk7XrzTVhGfLznVZroCrf5MN/7ocHMdztRBnWlYrTF 341xq+KMmvnl4BEI/QCe/6hnQa2ihVadXVfAZzG6F5qw7yCQzuPK6uXKcNOHjseG4Fmq veCTG52ULYqkkt1Op7sb0AaVj5LpbhNYf8dgr6heVu8ovAUDKYozmunNH/4vZi4sN2HA ZEOgofZkLnFGHyAtm9mhlq3qApOgiRq431zUWd5qe1B7Ihf5GeKl3k3SmDdT17p/GWk3 RiOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u4CKXqpFMI2C1FqAFOKC7cbWc6gnlEg0Eh+ov0SoYW8=; b=LQEDEa5E+3OLnvm6AiUF2SyNWNzsF2td63iAVxSzYj/6qye9AYUG4xH+0RlD16za6r 8qFVuxlmO3c1LIptL2kwUxyLEwv1ZOGoIBt8GpBiHdwYo1btBPcda7/IR+mQBkI/NGyB q3YrBjbcJ86pWtwF6/c2K0C87jAUNvprJzxCBS5InzgwNUP5utxlUPO6qNOr1M+Z1r0T yyElh5W6pb8NRDNiYGUkeqWeS1dr59sEhJNopNBzzBJ2xdup5KoN1k/0Kpr4iDraAd2Y NBorZllj8BsD2CUaK0bl+Wh5+U73VOGJnb6u3RsrdLrNX7TUKHcCNMzzmz76nBWt6kdv pJ4A== X-Gm-Message-State: AKwxytfdrFLEWryhGs+8Y+QAQ7Gj5oJ2nVsjRZsZdNHWGgU/brYLWMgi l1hjUNmjygqUniGyOkh5lgZJkrTaRc0= X-Google-Smtp-Source: ACJfBosKt1s06XHRNRfp8YZsbfy/QHru+LsqMOrWJTQzcNDssmBR8sAuJB/FaX0PeZfihEV0lntEPA== X-Received: by 10.80.245.10 with SMTP id t10mr3869629edm.168.1515601617284; Wed, 10 Jan 2018 08:26:57 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 16:26:41 +0000 Message-Id: <20180110162644.11208-4-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180110162644.11208-1-pete@akeo.ie> References: <20180110162644.11208-1-pete@akeo.ie> Subject: [edk2] [PATCH v4 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Most of the RVCT assembly can be reused as is for MSFT except for CpuBreakpoint.asm, which we need to force to Arm mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- MdePkg/Library/BaseLib/BaseLib.inf | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Library/= BaseLib/Arm/CpuBreakpoint.asm index 8a8065159bf2..e7490b09d3dc 100644 --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -16,7 +16,10 @@ =20 EXPORT CpuBreakpoint =20 - AREA Cpu_Breakpoint, CODE, READONLY +; Force ARM mode for this section, as MSFT assembler defaults to THUMB + AREA Cpu_Breakpoint, CODE, READONLY, ARM + + ARM =20 ;/** ; Generates a breakpoint on the CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index fbfb0063b75f..3c07e6bad977 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -824,8 +824,9 @@ [Sources.EBC] [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT=20 - =20 + Math64.c | RVCT + Math64.c | MSFT + Arm/SwitchStack.asm | RVCT Arm/SetJumpLongJump.asm | RVCT Arm/DisableInterrupts.asm | RVCT @@ -834,7 +835,16 @@ [Sources.ARM] Arm/CpuPause.asm | RVCT Arm/CpuBreakpoint.asm | RVCT Arm/MemoryFence.asm | RVCT -=20 + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/DisableInterrupts.asm | MSFT + Arm/EnableInterrupts.asm | MSFT + Arm/GetInterruptsState.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/Math64.S | GCC Arm/SwitchStack.S | GCC Arm/EnableInterrupts.S | GCC --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 25 00:11:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Introduce CRT assembly replacements for __rt_sdiv, __rt_udiv, __rt_udiv64, __rt_sdiv64, __rt_srsh (by reusing the RVCT code) as well as memcpy and memset. For MSFT compatibility, some of the code needs to be explicitly forced to ARM, and the /oldit assembly flag needs to be added. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard Reviewed-by: Ard Biesheuvel --- ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm | 43 ++++++= +++++++++++--- ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm | 40 ++++++= +++++++----- ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm | 22 +++++-= ---- ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm | 29 ++++++= +++++-- ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 16 ++++++= +- ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c | 34 ++++++= ++++++++++ ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c | 33 ++++++= +++++++++ 7 files changed, 185 insertions(+), 32 deletions(-) diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm b/ArmPkg/Libr= ary/CompilerIntrinsicsLib/Arm/div.asm index b539e516892d..f9e0107395f2 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm @@ -1,6 +1,7 @@ //------------------------------------------------------------------------= ------ // // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2018, Pete Batard. All rights reserved.
// // This program and the accompanying materials // are licensed and made available under the terms and conditions of the B= SD License @@ -17,18 +18,19 @@ EXPORT __aeabi_uidivmod EXPORT __aeabi_idiv EXPORT __aeabi_idivmod + EXPORT __rt_udiv + EXPORT __rt_sdiv =20 AREA Math, CODE, READONLY =20 ; ;UINT32 ;EFIAPI -;__aeabi_uidivmode ( -; IN UINT32 Dividen +;__aeabi_uidivmod ( +; IN UINT32 Dividend ; IN UINT32 Divisor ; ); ; - __aeabi_uidiv __aeabi_uidivmod RSBS r12, r1, r0, LSR #4 @@ -40,10 +42,40 @@ __aeabi_uidivmod B __arm_div_large =20 ; +;UINT64 +;EFIAPI +;__rt_udiv ( +; IN UINT32 Divisor, +; IN UINT32 Dividend +; ); +; +__rt_udiv + ; Swap R0 and R1 + MOV r12, r0 + MOV r0, r1 + MOV r1, r12 + B __aeabi_uidivmod + +; +;UINT64 +;EFIAPI +;__rt_sdiv ( +; IN INT32 Divisor, +; IN INT32 Dividend +; ); +; +__rt_sdiv + ; Swap R0 and R1 + MOV r12, r0 + MOV r0, r1 + MOV r1, r12 + B __aeabi_idivmod + +; ;INT32 ;EFIAPI -;__aeabi_idivmode ( -; IN INT32 Dividen +;__aeabi_idivmod ( +; IN INT32 Dividend ; IN INT32 Divisor ; ); ; @@ -152,4 +184,3 @@ __aeabi_idiv0 BX r14 =20 END - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm b/ArmPkg/= Library/CompilerIntrinsicsLib/Arm/ldivmod.asm index c71bd59e4520..3794cac35eed 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm @@ -1,6 +1,7 @@ //------------------------------------------------------------------------= ------ // // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2018, Pete Batard. All rights reserved.
// // This program and the accompanying materials // are licensed and made available under the terms and conditions of the B= SD License @@ -13,20 +14,41 @@ //------------------------------------------------------------------------= ------ =20 =20 - EXTERN __aeabi_uldivmod + IMPORT __aeabi_uldivmod + EXPORT __aeabi_ldivmod + EXPORT __rt_sdiv64 =20 - INCLUDE AsmMacroExport.inc + AREA Math, CODE, READONLY, ARM + + ARM =20 ; -;UINT32 +;INT64 ;EFIAPI -;__aeabi_uidivmode ( -; IN UINT32 Dividen -; IN UINT32 Divisor +;__rt_sdiv64 ( +; IN INT64 Divisor +; IN INT64 Dividend ; ); ; +__rt_sdiv64 + ; Swap r0-r1 and r2-r3 + MOV r12, r0 + MOV r0, r2 + MOV r2, r12 + MOV r12, r1 + MOV r1, r3 + MOV r3, r12 + B __aeabi_ldivmod =20 - RVCT_ASM_EXPORT __aeabi_ldivmod +; +;INT64 +;EFIAPI +;__aeabi_ldivmod ( +; IN INT64 Dividend +; IN INT64 Divisor +; ); +; +__aeabi_ldivmod PUSH {r4,lr} ASRS r4,r1,#1 EOR r4,r4,r3,LSR #1 @@ -39,7 +61,7 @@ L_Test1 RSBS r2,r2,#0 RSC r3,r3,#0 L_Test2 - BL __aeabi_uldivmod ; + BL __aeabi_uldivmod TST r4,#0x40000000 BEQ L_Test3 RSBS r0,r0,#0 @@ -53,5 +75,3 @@ L_Exit POP {r4,pc} =20 END - - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm b/ArmPkg/Lib= rary/CompilerIntrinsicsLib/Arm/llsr.asm index 881db106d9d7..db2fd5057832 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm @@ -1,6 +1,7 @@ //------------------------------------------------------------------------= ------ // // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2018, Pete Batard. All rights reserved.
// // This program and the accompanying materials // are licensed and made available under the terms and conditions of the B= SD License @@ -12,32 +13,33 @@ // //------------------------------------------------------------------------= ------ =20 + EXPORT __aeabi_llsr + EXPORT __rt_srsh =20 + AREA Math, CODE, READONLY, ARM =20 - INCLUDE AsmMacroExport.inc + ARM =20 ; ;VOID ;EFIAPI ;__aeabi_llsr ( -; IN VOID *Destination, -; IN VOID *Source, -; IN UINT32 Size -; ); +; IN UINT64 Value, +; IN UINT32 Shift +;) ; - RVCT_ASM_EXPORT __aeabi_llsr +__aeabi_llsr +__rt_srsh SUBS r3,r2,#0x20 - BPL {pc} + 0x18 ; 0x1c + BPL __aeabi_llsr_label1 RSB r3,r2,#0x20 LSR r0,r0,r2 ORR r0,r0,r1,LSL r3 LSR r1,r1,r2 BX lr +__aeabi_llsr_label1 LSR r0,r1,r3 MOV r1,#0 BX lr =20 END - - - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm b/ArmPkg/Li= brary/CompilerIntrinsicsLib/Arm/uldiv.asm index 6b6184ebd3fc..c5632b4e95e7 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm @@ -1,6 +1,7 @@ //------------------------------------------------------------------------= ------ // // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2018, Pete Batard. All rights reserved.
// // This program and the accompanying materials // are licensed and made available under the terms and conditions of the B= SD License @@ -13,9 +14,30 @@ //------------------------------------------------------------------------= ------ =20 =20 + EXPORT __aeabi_uldivmod + EXPORT __rt_udiv64 =20 + AREA Math, CODE, READONLY, ARM =20 - INCLUDE AsmMacroExport.inc + ARM + +; +;UINT64 +;EFIAPI +;__rt_udiv64 ( +; IN UINT64 Divisor +; IN UINT64 Dividend +; ) +; +__rt_udiv64 + ; Swap r0-r1 and r2-r3 + mov r12, r0 + mov r0, r2 + mov r2, r12 + mov r12, r1 + mov r1, r3 + mov r3, r12 + b __aeabi_uldivmod =20 ; ;UINT64 @@ -25,7 +47,7 @@ ; IN UINT64 Divisor ; ) ; - RVCT_ASM_EXPORT __aeabi_uldivmod +__aeabi_uldivmod stmdb sp!, {r4, r5, r6, lr} mov r4, r1 mov r5, r0 @@ -261,7 +283,6 @@ _ll_div0 b __aeabi_ldiv0 =20 __aeabi_ldiv0 - BX r14 + bx r14 =20 END - diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf= b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf index 44333141a70a..14e88da7ce06 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf +++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf @@ -23,8 +23,12 @@ [Defines] LIBRARY_CLASS =3D CompilerIntrinsicsLib =20 [Sources] - memcpy.c - memset.c + memcpy.c | RVCT + memcpy.c | GCC + memcpy_ms.c | MSFT + memset.c | RVCT + memset.c | GCC + memset_ms.c | MSFT =20 [Sources.ARM] Arm/mullu.asm | RVCT @@ -94,6 +98,10 @@ [Sources.ARM] Arm/llsr.S | GCC Arm/llsl.S | GCC =20 + Arm/div.asm | MSFT + Arm/uldiv.asm | MSFT + Arm/ldivmod.asm | MSFT + Arm/llsr.asm | MSFT =20 [Packages] MdePkg/MdePkg.dec @@ -101,3 +109,7 @@ [Packages] =20 [LibraryClasses] =20 +[BuildOptions] + MSFT:*_*_ARM_CC_FLAGS =3D /GL- + MSFT:*_*_ARM_ASM_FLAGS =3D /oldit + MSFT:*_*_AARCH64_CC_FLAGS =3D /GL- diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c b/ArmPkg/Libr= ary/CompilerIntrinsicsLib/memcpy_ms.c new file mode 100644 index 000000000000..90bbbb930d31 --- /dev/null +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c @@ -0,0 +1,34 @@ +//------------------------------------------------------------------------= ------ +// +// Copyright (c) 2017, Pete Batard. All rights reserved.
+// +// This program and the accompanying materials are licensed and made +// available under the terms and conditions of the BSD License which +// accompanies this distribution. The full text of the license may be +// found at http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +// IMPLIED. +// +//------------------------------------------------------------------------= ------ + +#if defined(_M_ARM64) +typedef unsigned __int64 size_t; +#else +typedef unsigned __int32 size_t; +#endif + +void* memcpy(void *, const void *, size_t); +#pragma intrinsic(memcpy) +#pragma function(memcpy) +void* memcpy(void *dest, const void *src, size_t n) +{ + unsigned char *d =3D dest; + unsigned char const *s =3D src; + + while (n--) + *d++ =3D *s++; + + return dest; +} diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c b/ArmPkg/Libr= ary/CompilerIntrinsicsLib/memset_ms.c new file mode 100644 index 000000000000..64205e5d1012 --- /dev/null +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------ +// +// Copyright (c) 2017, Pete Batard. All rights reserved.
+// +// This program and the accompanying materials are licensed and made +// available under the terms and conditions of the BSD License which +// accompanies this distribution. The full text of the license may be +// found at http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +// IMPLIED. +// +//------------------------------------------------------------------------= ------ + +#if defined(_M_ARM64) +typedef unsigned __int64 size_t; +#else +typedef unsigned __int32 size_t; +#endif + +void* memset(void *, int, size_t); +#pragma intrinsic(memset) +#pragma function(memset) +void *memset(void *s, int c, size_t n) +{ + unsigned char *d =3D s; + + while (n--) + *d++ =3D (unsigned char)c; + + return s; +} --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 25 00:11:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151560163662088.34715083084586; Wed, 10 Jan 2018 08:27:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B57082035D312; Wed, 10 Jan 2018 08:21:51 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A417E222CF1DB for ; Wed, 10 Jan 2018 08:21:49 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id g75so134711wme.0 for ; Wed, 10 Jan 2018 08:27:01 -0800 (PST) Received: from localhost.localdomain ([84.203.41.108]) by smtp.gmail.com with ESMTPSA id a52sm10543021eda.92.2018.01.10.08.26.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 08:26:59 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sfHhI01b4vuiWOtzDgw0fXq4bbCIrusOw6A5PKblTFs=; b=TKe0//h69B+NvobTWEU3T1X6rGmXeiPjH3deDavSqS9q3dxpNQrLl37oNdqFxhIkOA Xr4LwwNGN7YbRwKQ9znucnVIg0Vcyze/uTA9CV4LacK0ubXOrC1DFgo+Bg91Rn32tgZN B50GfevQRqA924kYpbTtdxg0VSY1tI88acKMxnc9BZuuIJOJNUHdMhNXfbI+A5J/K/BL 6bXfLoTJW7CeR+FPmpiPLi1ECPmPNSlF3oPEhuroKryqOxJReXoF/z5h/LfYey4mFoHi 3FVUSu4PiS87MipROddU1vyRxb2f4zg0QKagKmdxjv0wBrK8Fvkc2/tI3Mw4BSlupINX I9NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sfHhI01b4vuiWOtzDgw0fXq4bbCIrusOw6A5PKblTFs=; b=q+XoyFwbHlAC4hSuaO9ZvSWsAMCLZIY8z81EfEwkVOBt3LTnF8owT9rccaEC+Nbl3I QV2OGqvq8ez52fes5kaT79zJcn1e806s2ypaN0QBIIF60XqIcEAuEVrIr2FsdNwNQpDr XShK/JlhAkrg1O+KBY6buIANNsiDumROlaeLse+QWpWhQUtHk1NPt2O0g72yNGwsS8Ll YIiIIkL9gosXgOz5KSY43TXcjEMmNuh04lEERqDsvMb/4NDHUsP7ZbE3fMn2Ie/g0DS4 OaTIKbYtr+VqWwE+wWQn3w/vzsh2o1eaiz5vBcxfkVm5dKR/antnGK4WZK5v7Uz5bJUy aFMg== X-Gm-Message-State: AKwxytcBFEY3E++p8iRJP/Jn9IJKNl7FJ9bRGnPqG2kvG+lJujHLVWx0 IrjkOL6TpCUja9VjQroXjZL73Qc81nk= X-Google-Smtp-Source: ACJfBouy2scqfU8pVehxE5QFREn5mYPFlFIfEg6MdNNtNdwN8sNhQvIFUVOm4rszHEMYnE/g1qCDBA== X-Received: by 10.80.142.216 with SMTP id x24mr1806592edx.307.1515601620409; Wed, 10 Jan 2018 08:27:00 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 16:26:43 +0000 Message-Id: <20180110162644.11208-6-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180110162644.11208-1-pete@akeo.ie> References: <20180110162644.11208-1-pete@akeo.ie> Subject: [edk2] [PATCH v4 5/6] MdePkg/Include: Add VA list support for VS2017/ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" VA_START, VA_END and VA_COPY are the same as the generic macros. VA_ARG was reverse engineered from MS ARM assembly output. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Include/Base.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index 29db8a253e2f..7152ccda9764 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -660,6 +660,19 @@ struct _LIST_ENTRY { =20 #define VA_COPY(Dest, Start) __va_copy (Dest, Start) =20 +#elif defined(_M_ARM) +// +// MSFT ARM variable argument list support. +// Same as the generic macros below, except for VA_ARG that needs extra ad= justment. +// + +typedef char* VA_LIST; + +#define VA_START(Marker, Parameter) (Marker =3D (VA_LIST) ((UINTN) & (= Parameter) + _INT_SIZE_OF(Parameter))) +#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker +=3D _INT_SIZE= _OF(TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE))) +#define VA_END(Marker) (Marker =3D (VA_LIST) 0) +#define VA_COPY(Dest, Start) ((void)((Dest) =3D (Start))) + #elif defined(__GNUC__) =20 #if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS) --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Apr 25 00:11:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" We duplicate the Assembly-Code-File section from build_rule.template because --convert-hex cannot be used with the MSFT ARM assembler. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- BaseTools/Conf/build_rule.template | 31 +++++++++++++++++++- BaseTools/Conf/tools_def.template | 31 ++++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule= .template index 3e6aa8ff0f34..6ea14fb7aa02 100755 --- a/BaseTools/Conf/build_rule.template +++ b/BaseTools/Conf/build_rule.template @@ -182,7 +182,6 @@ =20 =20 - [Assembly-Code-File.COMMON.COMMON] ?.asm, ?.Asm, ?.ASM @@ -207,6 +206,36 @@ # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iii =20 +[Assembly-Code-File.COMMON.ARM] + # Remove --convert-hex for ARM as it breaks MSFT assemblers + + ?.asm, ?.Asm, ?.ASM + + + ?.S, ?.s + + + $(MAKE_FILE) + + + $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj + + + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i + Trim --source-code --convert-hex --trim-long -o ${d_path}(+)${s_ba= se}.iii ${d_path}(+)${s_base}.i + "$(ASM)" /Fo${dst} $(ASM_FLAGS) /I${s_path} $(INC) ${d_path}(+)${s= _base}.iii + + + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i + Trim --source-code --trim-long -o ${d_path}(+)${s_base}.iii ${d_pa= th}(+)${s_base}.i + "$(ASM)" /Fo${dst} $(ASM_FLAGS) /I${s_path} $(INC) ${d_path}(+)${s= _base}.iii + + + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i + Trim --trim-long --source-code -o ${d_path}(+)${s_base}.iii ${d_pa= th}(+)${s_base}.i + # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues + "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iii + [Nasm-Assembly-Code-File.COMMON.COMMON] ?.nasm diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 98ab6dd45e81..f76c4da05938 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -79,6 +79,7 @@ DEFINE VS2017_HOST =3D x86 DEFINE VS2017_BIN_HOST =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\DEF(VS2= 017_HOST) DEFINE VS2017_BIN_IA32 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x86 DEFINE VS2017_BIN_X64 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x64 +DEFINE VS2017_BIN_ARM =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\arm =20 DEFINE WINSDK_BIN =3D ENV(WINSDK_PREFIX) DEFINE WINSDKx86_BIN =3D ENV(WINSDKx86_PREFIX) @@ -335,6 +336,9 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Required to build platforms or ACPI tables: # Intel(r) ACPI Compiler (iasl.exe) from # https://acpica.org/downloads +# Note: +# Building of XIP firmware images for ARM is n= ot currently supported (only applications). +# /FILEALIGN:4096 and other changes are needed= for ARM firmware builds. # DDK3790 -win32- Requires: # Microsoft Windows Server 2003 Driver Develop= ment Kit (Microsoft WINDDK) version 3790.1830 # Optional: @@ -4169,6 +4173,33 @@ NOOPT_VS2017_X64_NASM_FLAGS =3D -O0 -f win64 -g RELEASE_VS2017_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IG= NORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:= .pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI= _BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=3D.data NOOPT_VS2017_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OP= T:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Mac= hine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE= _DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG =20 +################# +# ARM definitions +################# +*_VS2017_ARM_CC_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_VFRPP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_SLINK_PATH =3D DEF(VS2017_BIN_ARM)\lib.exe +*_VS2017_ARM_DLINK_PATH =3D DEF(VS2017_BIN_ARM)\link.exe +*_VS2017_ARM_APP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_PP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_ASM_PATH =3D DEF(VS2017_BIN_ARM)\armasm.exe +*_VS2017_ARM_ASLCC_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_ASLPP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_ASLDLINK_PATH =3D DEF(VS2017_BIN_ARM)\link.exe + + *_VS2017_ARM_MAKE_FLAGS =3D /nologo + DEBUG_VS2017_ARM_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D = UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Gw /Oi- +RELEASE_VS2017_ARM_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D = UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gw /Oi- +NOOPT_VS2017_ARM_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D = UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Od /Oi- + + DEBUG_VS2017_ARM_ASM_FLAGS =3D /nologo /g +RELEASE_VS2017_ARM_ASM_FLAGS =3D /nologo +NOOPT_VS2017_ARM_ASM_FLAGS =3D /nologo + + DEBUG_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM= /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER = /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +RELEASE_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D= /MACHINE:ARM /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SE= RVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=3D.data +NOOPT_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM= /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER = /SAFESEH:NO /BASE:0 /DRIVER /DEBUG + ################## # EBC definitions ################## --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel