From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969712529201.50815460641854; Fri, 22 Dec 2017 11:08:32 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EA26322198F62; Fri, 22 Dec 2017 11:03:40 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 351E322225C1B for ; Fri, 22 Dec 2017 11:03:38 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qws005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:04 +0000 Message-Id: <20171222190821.12440-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 01/18] ARM/VExpressPkg: Fix MODULE_TYPE of HDLCD/PL111 platform libraries X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel This change fixes incorrect MODULE_TYPE of HDLCD and PL111 LcdPlatformLibs. Currently set MODUL_TYPE DXE_DRIVER is incorrect for these platform libraries. Hence set this to type BASE. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 4 ++-- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index fc51c781b45122eaf4f2269af61b44c8630cdfb8..18d210ce718db45e018681cd1cc= dad48f4adc7f3 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -2,7 +2,7 @@ # # Component description file for HdLcdArmLib module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -18,7 +18,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D HdLcdArmVExpress FILE_GUID =3D 535a720e-06c0-4bb9-b563-452216abbed4 - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D LcdPlatformLib =20 diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index fd83d2412d4fd2dfa59204f21626c62e377e3c55..335c84841a4ff4b57c0d495bc48= e93579b5ce576 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -2,7 +2,7 @@ # # Component description file for ArmVeGraphicsDxe module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -18,7 +18,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D PL111LcdArmVExpressLib FILE_GUID =3D b7f06f20-496f-11e0-a8e8-0002a5d5c51b - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D LcdPlatformLib =20 --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969720847750.9282153251295; Fri, 22 Dec 2017 11:08:40 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6337722198F6A; Fri, 22 Dec 2017 11:03:44 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3139C21A0292D for ; Fri, 22 Dec 2017 11:03:38 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qwt005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:05 +0000 Message-Id: <20171222190821.12440-3-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 02/18] ARM/VExpressPkg: Tidy HDLCD and PL11LCD platform Lib: Coding standard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 5 +- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 136 ++++++----- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 238 +++++++++++--------- 3 files changed, 218 insertions(+), 161 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index 18d210ce718db45e018681cd1ccdad48f4adc7f3..d44aa7776a4ac60d60f3b4386e6= 7c53423287383 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -1,6 +1,6 @@ #/** @file # -# Component description file for HdLcdArmLib module +# Component description file for HdLcdArmVExpress module # # Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# @@ -23,8 +23,7 @@ [Defines] LIBRARY_CLASS =3D LcdPlatformLib =20 [Sources.common] - -HdLcdArmVExpress.c + HdLcdArmVExpress.c =20 [Packages] ArmPlatformPkg/ArmPlatformPkg.dec diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index b1106ee19b98cebac01820924514eac79b97d0d5..851ba83b79f0fea7019269c30e7= add58f5ff9cb2 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -1,6 +1,6 @@ -/** +/** @file =20 - Copyright (c) 2012, ARM Ltd. All rights reserved. + Copyright (c) 2012-2017, ARM Ltd. All rights reserved. =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -44,35 +44,40 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 - LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OS= C_FREQUENCY, + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVG= A_OSC_FREQUENCY, + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OS= C_FREQUENCY, + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SX= GA_OSC_FREQUENCY/2), + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UX= GA_OSC_FREQUENCY/2), + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_F= REQUENCY/2), + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH } @@ -95,19 +100,25 @@ LcdPlatformInitializeDisplay ( { EFI_STATUS Status; =20 - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { + // Set the FPGA multiplexer to select the video output from the + // motherboard or the daughterboard + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_MUXFPGA, + ARM_VE_DAUGHTERBOARD_1_SITE + ); + if (EFI_ERROR (Status)) { return Status; } =20 // Install the EDID Protocols Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); + &Handle, + &gEfiEdidDiscoveredProtocolGuid, + &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, + &mEdidActive, + NULL + ); =20 return Status; } @@ -132,16 +143,25 @@ LcdPlatformGetVram ( } else { AllocationType =3D AllocateAddress; } - Status =3D gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_= SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { + Status =3D gBS->AllocatePages ( + AllocationType, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { return Status; } =20 - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { + // Mark the VRAM as write-combining. + // The VRAM is inside the DRAM, which is cacheable. + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -150,15 +170,11 @@ LcdPlatformGetVram ( } =20 UINT32 -LcdPlatformGetMaxMode ( - VOID - ) +LcdPlatformGetMaxMode (VOID) { - // // The following line will report correctly the total number of graphics= modes - // that could be supported by the graphics driver: - // - return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION)); + // that could be supported by the graphics driver + return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); } =20 EFI_STATUS @@ -174,25 +190,35 @@ LcdPlatformSetMode ( =20 // Set the video mode oscillator do { - Status =3D ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(= PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq); + Status =3D ArmPlatformSysConfigSetDevice ( + SYS_CFG_OSC_SITE1, + PcdGet32 (PcdHdLcdVideoModeOscId), + mResolutions[ModeNumber].OscFreq + ); } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the DVI into the new mode do { - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mode= Number].Mode); + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_MUXFPGA, + ARM_VE_DAUGHTERBOARD_1_SITE + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -216,25 +242,25 @@ LcdPlatformQueryMode ( Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; =20 switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; =20 - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT(FALSE); - break; + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT (FALSE); + break; } =20 return EFI_SUCCESS; diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 3f3ceb3d2fa82f614e0c6dac8455c117745cf3a6..2586a6d8c2076c9aff15f50d652= e462d783f13dc 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -41,87 +41,102 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 - LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_= OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, S= VGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_= OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (SXGA_OSC_FREQUENCY/2), + SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, + SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (UXGA_OSC_FREQUENCY/2), + UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, + UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC= _FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (HD_OSC_FREQUENCY/2), + HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, + HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH }, { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = 63500000, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + 63500000, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH } }; =20 @@ -135,7 +150,6 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 - EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -143,16 +157,19 @@ LcdPlatformInitializeDisplay ( { EFI_STATUS Status; =20 - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard + // Set the FPGA multiplexer to select the video output from the motherbo= ard + // or the daughterboard Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); - if (!EFI_ERROR(Status)) { + if (!EFI_ERROR (Status)) { // Install the EDID Protocols - Status =3D gBS->InstallMultipleProtocolInterfaces( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, + &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, + &mEdidActive, + NULL + ); } =20 return Status; @@ -169,29 +186,38 @@ LcdPlatformGetVram ( Status =3D EFI_SUCCESS; =20 // Is it on the motherboard or on the daughterboard? - switch(PL111_CLCD_SITE) { + switch (PL111_CLCD_SITE) { =20 case ARM_VE_MOTHERBOARD_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOAR= D_BASE; + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; break; =20 case ARM_VE_DAUGHTERBOARD_1_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE; + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; *VramSize =3D LCD_VRAM_SIZE; =20 // Allocate the VRAM from the DRAM so that nobody else uses it. - Status =3D gBS->AllocatePages( AllocateAddress, EfiBootServicesData, E= FI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { + Status =3D gBS->AllocatePages ( + AllocateAddress, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { return Status; } =20 - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, whic= h is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { - gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); + // Mark the VRAM as write-combining. + // The VRAM is inside the DRAM, which is cacheable. + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } break; @@ -206,19 +232,18 @@ LcdPlatformGetVram ( } =20 UINT32 -LcdPlatformGetMaxMode ( - VOID - ) +LcdPlatformGetMaxMode (VOID) { - // The following line will report correctly the total number of graphics= modes - // supported by the PL111CLCD. - //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; + // The following line would correctly report the total number + // of graphics modes supported by the PL111CLCD. + // return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; =20 // However, on some platforms it is desirable to ignore some graphics mo= des. - // This could be because the specific implementation of PL111 has certai= n limitations. + // This could be because the specific implementation of PL111 has + // certain limitations. =20 // Set the maximum mode allowed - return (PcdGet32(PcdPL111LcdMaxMode)); + return (PcdGet32 (PcdPL111LcdMaxMode)); } =20 EFI_STATUS @@ -238,22 +263,26 @@ LcdPlatformSetMode ( =20 LcdSite =3D PL111_CLCD_SITE; =20 - switch(LcdSite) { + switch (LcdSite) { case ARM_VE_MOTHERBOARD_SITE: Function =3D SYS_CFG_OSC; OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; break; case ARM_VE_DAUGHTERBOARD_1_SITE: Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId); + OscillatorId =3D (UINT32)PcdGet32 (PcdPL111LcdVideoModeOscId); break; default: return EFI_UNSUPPORTED; } =20 // Set the video mode oscillator - Status =3D ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResol= utions[ModeNumber].OscFreq); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSetDevice ( + Function, + OscillatorId, + mResolutions[ModeNumber].OscFreq + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -267,8 +296,11 @@ LcdPlatformSetMode ( SysId &=3D ~ARM_FVP_SYS_ID_VARIANT_MASK; if (SysId !=3D ARM_FVP_BASE_BOARD_SYS_ID) { // Set the DVI into the new mode - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mo= deNumber].Mode); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -277,7 +309,7 @@ LcdPlatformSetMode ( =20 // Set the multiplexer Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -301,25 +333,25 @@ LcdPlatformQueryMode ( Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; =20 switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; =20 - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT(FALSE); - break; + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT (FALSE); + break; } =20 return EFI_SUCCESS; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969718128452.26553073200364; Fri, 22 Dec 2017 11:08:38 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 06D1722198F5A; Fri, 22 Dec 2017 11:03:44 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 53CD322225C1E for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qwu005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:06 +0000 Message-Id: <20171222190821.12440-4-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 03/18] ARM/VExpressPkg: Tidy HdLcd/PL111Lcd code: Updated comments X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change. In this change some comments in HDLCD and PL111LCD platform library code are modified and a few new comments are added. This is to prevent mixing formatting changes with functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 2 +- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 74 ++++++++++++++++++++ Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 73 +++++++++++++++++++ 3 files changed, 148 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index 335c84841a4ff4b57c0d495bc48e93579b5ce576..e97febb91c89f82f8cad12823f5= ffe182e87f8cd 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -1,6 +1,6 @@ #/** @file # -# Component description file for ArmVeGraphicsDxe module +# Component description file for PL111LcdArmVExpressLib module # # Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 851ba83b79f0fea7019269c30e7add58f5ff9cb2..e4d0a4c8407835df6ab62c02d18= 531c4d3f08c97 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -44,6 +44,8 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 +/** The display modes supported by the platform. +**/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, @@ -93,6 +95,13 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 +/** HDLCD platform specific initialization function. + + @param[in] Handle Handle to the LCD device instance. + + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -123,6 +132,18 @@ LcdPlatformInitializeDisplay ( return Status; } =20 +/** Allocate VRAM memory in DRAM for the frame buffer + (unless it is reserved already). + + The allocated address can be used to set the frame buffer. + + @param[out] VramBaseAddress A pointer to the frame buffer address. + @param[out] VramSize A pointer to the size of the frame + buffer in bytes + + @retval EFI_SUCCESS Frame buffer memory allocated successful= ly. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, @@ -169,6 +190,13 @@ LcdPlatformGetVram ( return EFI_SUCCESS; } =20 +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode (VOID) { @@ -177,6 +205,14 @@ LcdPlatformGetMaxMode (VOID) return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); } =20 +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber @@ -226,6 +262,17 @@ LcdPlatformSetMode ( return Status; } =20 +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, @@ -266,6 +313,23 @@ LcdPlatformQueryMode ( return EFI_SUCCESS; } =20 +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] HRes Pointer to horizontal resolution. + @param[out] HSync Pointer to horizontal sync width. + @param[out] HBackPorch Pointer to horizontal back porch. + @param[out] HFrontPorch Pointer to horizontal front porch. + @param[out] VRes Pointer to vertical resolution. + @param[out] VSync Pointer to vertical sync width. + @param[out] VBackPorch Pointer to vertical back porch. + @param[out] VFrontPorch Pointer to vertical front porch. + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -295,6 +359,16 @@ LcdPlatformGetTimings ( return EFI_SUCCESS; } =20 +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to value bits per pixel. + + @retval EFI_SUCCESS Bit per pixel information for the reques= ted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 2586a6d8c2076c9aff15f50d652e462d783f13dc..0bbd40ceeb850209cd4842f34e7= 2a0b635309a15 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -41,6 +41,8 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 +/** The display modes supported by the platform. +**/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, @@ -150,6 +152,12 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 +/** PL111 Platform specific initialization function. + + @param[in] Handle Handle to the LCD device instance. + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -175,6 +183,18 @@ LcdPlatformInitializeDisplay ( return Status; } =20 +/** Allocate VRAM memory in DRAM for the frame buffer + (unless it is reserved already). + + The allocated address can be used to set the frame buffer. + + @param[out] VramBaseAddress A pointer to the frame buffer address. + @param[out] VramSize A pointer to the size of the frame + buffer in bytes + + @retval EFI_SUCCESS Frame buffer memory allocated successful= ly. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, @@ -231,6 +251,13 @@ LcdPlatformGetVram ( return Status; } =20 +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode (VOID) { @@ -246,6 +273,15 @@ LcdPlatformGetMaxMode (VOID) return (PcdGet32 (PcdPL111LcdMaxMode)); } =20 +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval EFI_UNSUPPORTED PLL111 configuration not supported. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber @@ -317,6 +353,16 @@ LcdPlatformSetMode ( return Status; } =20 +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, @@ -357,6 +403,23 @@ LcdPlatformQueryMode ( return EFI_SUCCESS; } =20 +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] HRes Pointer to horizontal resolution. + @param[out] HSync Pointer to horizontal sync width. + @param[out] HBackPorch Pointer to horizontal back porch. + @param[out] HFrontPorch Pointer to horizontal front porch. + @param[out] VRes Pointer to vertical resolution. + @param[out] VSync Pointer to vertical sync width. + @param[out] VBackPorch Pointer to vertical back porch. + @param[out] VFrontPorch Pointer to vertical front porch. + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -386,6 +449,16 @@ LcdPlatformGetTimings ( return EFI_SUCCESS; } =20 +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to value bits per pixel. + + @retval EFI_SUCCESS Bit per pixel information for the reques= ted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969716013133.79007922997903; Fri, 22 Dec 2017 11:08:36 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9DCE721A0292D; Fri, 22 Dec 2017 11:03:43 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 51CDF22225C1D for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qwv005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:07 +0000 Message-Id: <20171222190821.12440-5-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 04/18] ARM/VExpressPkg: Remove unused PcdPL111LcdMaxMode from HDLCD inf X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak PCD PcdPL111LcdMaxMode is not used in HDLCD platform library. Presence of this PCD in HDLCD is probably due to copy/paste code from PL111 Lcd platform library. This change removes it from the HdLcdArmVExpressLib.inf file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish Pathak Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index d44aa7776a4ac60d60f3b4386e67c53423287383..52158c4771b5b7651e234fdd732= 08dcae14c1025 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -40,5 +40,4 @@ [Protocols] gEfiEdidActiveProtocolGuid # Produced =20 [Pcd] - gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969723973557.9310021561744; Fri, 22 Dec 2017 11:08:43 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B5C1222198F6D; Fri, 22 Dec 2017 11:03:44 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 819BE22225C1F for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qww005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:08 +0000 Message-Id: <20171222190821.12440-6-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 05/18] ARM/VExpressPkg: PL111 and HDLCD: add const qualifier X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds some STATIC and CONST qualifiers (mainly to arguments of functions) in PL111 and HdLcd platform libraries. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 34 ++++++++++---------- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 32 +++++++++--------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index e4d0a4c8407835df6ab62c02d18531c4d3f08c97..6afd764897f49c64490ce891682= f99bb0f5d993b 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -46,7 +46,7 @@ typedef struct { =20 /** The display modes supported by the platform. **/ -LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, @@ -146,8 +146,8 @@ LcdPlatformInitializeDisplay ( **/ EFI_STATUS LcdPlatformGetVram ( - OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, - OUT UINTN* VramSize + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize ) { EFI_STATUS Status; @@ -215,7 +215,7 @@ LcdPlatformGetMaxMode (VOID) **/ EFI_STATUS LcdPlatformSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; @@ -275,8 +275,8 @@ LcdPlatformSetMode ( **/ EFI_STATUS LcdPlatformQueryMode ( - IN UINT32 ModeNumber, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -332,15 +332,15 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + IN CONST UINT32 ModeNumber, + OUT UINT32 * CONST HRes, + OUT UINT32 * CONST HSync, + OUT UINT32 * CONST HBackPorch, + OUT UINT32 * CONST HFrontPorch, + OUT UINT32 * CONST VRes, + OUT UINT32 * CONST VSync, + OUT UINT32 * CONST VBackPorch, + OUT UINT32 * CONST VFrontPorch ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -371,8 +371,8 @@ LcdPlatformGetTimings ( **/ EFI_STATUS LcdPlatformGetBpp ( - IN UINT32 ModeNumber, - OUT LCD_BPP * Bpp + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 0bbd40ceeb850209cd4842f34e72a0b635309a15..799fb3fc781ce04bb64cb1fa0b8= 7f262a670ed78 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -197,8 +197,8 @@ LcdPlatformInitializeDisplay ( **/ EFI_STATUS LcdPlatformGetVram ( - OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, - OUT UINTN* VramSize + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize ) { EFI_STATUS Status; @@ -284,7 +284,7 @@ LcdPlatformGetMaxMode (VOID) **/ EFI_STATUS LcdPlatformSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; @@ -365,8 +365,8 @@ LcdPlatformSetMode ( **/ EFI_STATUS LcdPlatformQueryMode ( - IN UINT32 ModeNumber, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -422,15 +422,15 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + IN CONST UINT32 ModeNumber, + OUT UINT32 * CONST HRes, + OUT UINT32 * CONST HSync, + OUT UINT32 * CONST HBackPorch, + OUT UINT32 * CONST HFrontPorch, + OUT UINT32 * CONST VRes, + OUT UINT32 * CONST VSync, + OUT UINT32 * CONST VBackPorch, + OUT UINT32 * CONST VFrontPorch ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -461,8 +461,8 @@ LcdPlatformGetTimings ( **/ EFI_STATUS LcdPlatformGetBpp ( - IN UINT32 ModeNumber, - OUT LCD_BPP * Bpp + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:09 +0000 Message-Id: <20171222190821.12440-7-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 06/18] ARM/VExpressPkg: Add and update debug ASSERTS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds some debug assertions e.g to catch NULL pointer errors missing in PL11Lcd and HdLcd platform libraries. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 22 +++++++++++++++++- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 24 +++++++++++++++++++- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 6afd764897f49c64490ce891682f99bb0f5d993b..a8fe8696da0653017ce9fa6e4a8= 6caf283bc04c9 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -153,6 +153,9 @@ LcdPlatformGetVram ( EFI_STATUS Status; EFI_ALLOCATE_TYPE AllocationType; =20 + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + // Set the vram size *VramSize =3D LCD_VRAM_SIZE; =20 @@ -171,6 +174,7 @@ LcdPlatformGetVram ( VramBaseAddress ); if (EFI_ERROR (Status)) { + ASSERT (FALSE); return Status; } =20 @@ -181,8 +185,8 @@ LcdPlatformGetVram ( *VramSize, EFI_MEMORY_WC ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { + ASSERT (FALSE); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -221,6 +225,7 @@ LcdPlatformSetMode ( EFI_STATUS Status; =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -279,7 +284,10 @@ LcdPlatformQueryMode ( OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { + ASSERT (Info !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -343,7 +351,18 @@ LcdPlatformGetTimings ( OUT UINT32 * CONST VFrontPorch ) { + // One of the pointers is NULL + ASSERT (HRes !=3D NULL); + ASSERT (HSync !=3D NULL); + ASSERT (HBackPorch !=3D NULL); + ASSERT (HFrontPorch !=3D NULL); + ASSERT (VRes !=3D NULL); + ASSERT (VSync !=3D NULL); + ASSERT (VBackPorch !=3D NULL); + ASSERT (VFrontPorch !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -376,6 +395,7 @@ LcdPlatformGetBpp ( ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 799fb3fc781ce04bb64cb1fa0b87f262a670ed78..fd4eea8f8e2397bc7d4ddf4cfe3= dcc97a5109edb 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -205,6 +205,9 @@ LcdPlatformGetVram ( =20 Status =3D EFI_SUCCESS; =20 + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + // Is it on the motherboard or on the daughterboard? switch (PL111_CLCD_SITE) { =20 @@ -225,6 +228,7 @@ LcdPlatformGetVram ( VramBaseAddress ); if (EFI_ERROR (Status)) { + ASSERT (FALSE); return Status; } =20 @@ -235,8 +239,8 @@ LcdPlatformGetVram ( *VramSize, EFI_MEMORY_WC ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { + ASSERT (FALSE); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -294,6 +298,7 @@ LcdPlatformSetMode ( UINT32 SysId; =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -369,7 +374,10 @@ LcdPlatformQueryMode ( OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { + ASSERT (Info !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -433,7 +441,18 @@ LcdPlatformGetTimings ( OUT UINT32 * CONST VFrontPorch ) { + // One of the pointers is NULL + ASSERT (HRes !=3D NULL); + ASSERT (HSync !=3D NULL); + ASSERT (HBackPorch !=3D NULL); + ASSERT (HFrontPorch !=3D NULL); + ASSERT (VRes !=3D NULL); + ASSERT (VSync !=3D NULL); + ASSERT (VBackPorch !=3D NULL); + ASSERT (VFrontPorch !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 @@ -465,7 +484,10 @@ LcdPlatformGetBpp ( OUT LCD_BPP * CONST Bpp ) { + ASSERT (Bpp !=3D NULL); + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969729137350.3477927630255; Fri, 22 Dec 2017 11:08:49 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7552A22198F7B; Fri, 22 Dec 2017 11:03:47 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0303A22225C1A for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx0005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:10 +0000 Message-Id: <20171222190821.12440-8-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 07/18] ARM/VExpressPkg: PL111LcdArmVExpressLib: Minor code cleanup X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This minor change removes some unecessary initializations and variables in PL111LcdArmVExpress.c Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index fd4eea8f8e2397bc7d4ddf4cfe3dcc97a5109edb..11335bb2cef9d7ca2606d4a8671= 382bf3dc2d254 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -203,8 +203,6 @@ LcdPlatformGetVram ( { EFI_STATUS Status; =20 - Status =3D EFI_SUCCESS; - ASSERT (VramBaseAddress !=3D NULL); ASSERT (VramSize !=3D NULL); =20 @@ -214,6 +212,7 @@ LcdPlatformGetVram ( case ARM_VE_MOTHERBOARD_SITE: *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; + Status =3D EFI_SUCCESS; break; =20 case ARM_VE_DAUGHTERBOARD_1_SITE: @@ -242,7 +241,6 @@ LcdPlatformGetVram ( if (EFI_ERROR (Status)) { ASSERT (FALSE); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); - return Status; } break; =20 @@ -292,7 +290,6 @@ LcdPlatformSetMode ( ) { EFI_STATUS Status; - UINT32 LcdSite; UINT32 OscillatorId; SYS_CONFIG_FUNCTION Function; UINT32 SysId; @@ -302,9 +299,7 @@ LcdPlatformSetMode ( return EFI_INVALID_PARAMETER; } =20 - LcdSite =3D PL111_CLCD_SITE; - - switch (LcdSite) { + switch (PL111_CLCD_SITE) { case ARM_VE_MOTHERBOARD_SITE: Function =3D SYS_CFG_OSC; OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; @@ -349,11 +344,8 @@ LcdPlatformSetMode ( } =20 // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); + ASSERT_EFI_ERROR (Status); =20 return Status; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969731788313.17698599059895; Fri, 22 Dec 2017 11:08:51 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C5494221ED752; Fri, 22 Dec 2017 11:03:47 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 034F722225C1B for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx1005645; Fri, 22 Dec 2017 19:08:27 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:11 +0000 Message-Id: <20171222190821.12440-9-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 08/18] ARM/VExpressPkg: PL111 and HDLCD: Use FixedPcdGet32 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change replaces PcdGet32 with FixedPcdGet32 for the PCDs which are defined as fixed PCDs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 2 +- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 2 +- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 2 +- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index 52158c4771b5b7651e234fdd73208dcae14c1025..2e83736609cf8c63cb498368cd3= 77f6a23964ef4 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -39,5 +39,5 @@ [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced gEfiEdidActiveProtocolGuid # Produced =20 -[Pcd] +[FixedPcd] gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index e97febb91c89f82f8cad12823f5ffe182e87f8cd..1ee878041559fa84a810f65175f= 2507bda663d76 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -39,6 +39,6 @@ [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced gEfiEdidActiveProtocolGuid # Produced =20 -[Pcd] +[FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index a8fe8696da0653017ce9fa6e4a86caf283bc04c9..f8d19df79260cdfbe1876d6ccc1= 0d49abd0637cf 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -233,7 +233,7 @@ LcdPlatformSetMode ( do { Status =3D ArmPlatformSysConfigSetDevice ( SYS_CFG_OSC_SITE1, - PcdGet32 (PcdHdLcdVideoModeOscId), + FixedPcdGet32 (PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq ); } while (Status =3D=3D EFI_TIMEOUT); diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 11335bb2cef9d7ca2606d4a8671382bf3dc2d254..92918bb4ee6811db47791a435bc= 06a6dc77ae9a3 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -272,7 +272,7 @@ LcdPlatformGetMaxMode (VOID) // certain limitations. =20 // Set the maximum mode allowed - return (PcdGet32 (PcdPL111LcdMaxMode)); + return (FixedPcdGet32 (PcdPL111LcdMaxMode)); } =20 /** Set the requested display mode. @@ -306,7 +306,7 @@ LcdPlatformSetMode ( break; case ARM_VE_DAUGHTERBOARD_1_SITE: Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32 (PcdPL111LcdVideoModeOscId); + OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); break; default: return EFI_UNSUPPORTED; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151396973432648.53241351362715; Fri, 22 Dec 2017 11:08:54 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2E941222447D1; Fri, 22 Dec 2017 11:03:48 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0BB6022198F44 for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx2005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:12 +0000 Message-Id: <20171222190821.12440-10-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 09/18] ARM/VExpressPkg: PL11LcdArmVExpressLib: Improvement conditional X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak PL111_CLCD_SITE and ARM_VE_MOTHERBOARD_SITE are both constants and available at build time. Use conditional compilation to process the code based on the value of PL111_CLCD_SITE, instead of selecting code in a switch statement at runtime. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 40 +++++++------------- 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 92918bb4ee6811db47791a435bc06a6dc77ae9a3..cf50b20fd9b1b44a81963655c2f= 88305ce6bdc67 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -206,16 +206,11 @@ LcdPlatformGetVram ( ASSERT (VramBaseAddress !=3D NULL); ASSERT (VramSize !=3D NULL); =20 - // Is it on the motherboard or on the daughterboard? - switch (PL111_CLCD_SITE) { - - case ARM_VE_MOTHERBOARD_SITE: +#if (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; Status =3D EFI_SUCCESS; - break; - - case ARM_VE_DAUGHTERBOARD_1_SITE: +#elif (PL111_CLCD_SITE =3D=3D ARM_VE_DAUGHTERBOARD_1_SITE) *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; *VramSize =3D LCD_VRAM_SIZE; =20 @@ -242,13 +237,9 @@ LcdPlatformGetVram ( ASSERT (FALSE); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); } - break; - - default: - // Unsupported site - Status =3D EFI_UNSUPPORTED; - break; - } +#else +#error PL111LcdVExpressLib: Unsupported PL111_CLCD_SITE +#endif // (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) =20 return Status; } @@ -299,18 +290,15 @@ LcdPlatformSetMode ( return EFI_INVALID_PARAMETER; } =20 - switch (PL111_CLCD_SITE) { - case ARM_VE_MOTHERBOARD_SITE: - Function =3D SYS_CFG_OSC; - OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; - break; - case ARM_VE_DAUGHTERBOARD_1_SITE: - Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); - break; - default: - return EFI_UNSUPPORTED; - } +#if (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) + Function =3D SYS_CFG_OSC; + OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; +#elif (PL111_CLCD_SITE =3D=3D ARM_VE_DAUGHTERBOARD_1_SITE) + Function =3D SYS_CFG_OSC_SITE1; + OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); +#else +#error PL111LcdVExpressLib: Unsupported PL111_CLCD_SITE +#endif // (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) =20 // Set the video mode oscillator Status =3D ArmPlatformSysConfigSetDevice ( --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969736946283.08600400904174; Fri, 22 Dec 2017 11:08:56 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8497D222447DE; Fri, 22 Dec 2017 11:03:48 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2B16122198F4A for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx3005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:13 +0000 Message-Id: <20171222190821.12440-11-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 10/18] ARM/VExpressPkg: HdLcdArmVExpressLib: Remove status check EFI_TIMEOUT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak None of the ArmPlatformSys* functions returns EFI_TIMEOUT. Hence checking this in the do {} while loop in LcdPlatformSetMode is wrong. Therefore remove this comparision and as a result remove the do {} while loop. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | = 22 ++++++++------------ 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index f8d19df79260cdfbe1876d6ccc10d49abd0637cf..533d7fa4777e8f22429e2ae63a8= 28dcb5401b5c0 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -230,25 +230,21 @@ LcdPlatformSetMode ( } =20 // Set the video mode oscillator - do { - Status =3D ArmPlatformSysConfigSetDevice ( - SYS_CFG_OSC_SITE1, - FixedPcdGet32 (PcdHdLcdVideoModeOscId), - mResolutions[ModeNumber].OscFreq - ); - } while (Status =3D=3D EFI_TIMEOUT); + Status =3D ArmPlatformSysConfigSetDevice ( + SYS_CFG_OSC_SITE1, + FixedPcdGet32 (PcdHdLcdVideoModeOscId), + mResolutions[ModeNumber].OscFreq + ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the DVI into the new mode - do { - Status =3D ArmPlatformSysConfigSet ( - SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode - ); - } while (Status =3D=3D EFI_TIMEOUT); + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969739385689.9244903824355; Fri, 22 Dec 2017 11:08:59 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E18ED222CB30A; Fri, 22 Dec 2017 11:03:48 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3749222198F4B for ; Fri, 22 Dec 2017 11:03:39 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx4005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:14 +0000 Message-Id: <20171222190821.12440-12-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 11/18] ARM/VExpressPkg: HdLcdArmVExpressLib: Remove redundant Bpp X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: EvanLloyd Because of copy/paste effects, HdLcdArmVExpress.c contained a table entry "LCD_BPP Bpp;" specifying the Bits per Pixel for each mode. However, all modes are LCD_BITS_PER_PIXEL_24. This change removes the table entry and related use of the field. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | = 42 ++++++-------------- 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 533d7fa4777e8f22429e2ae63a828dcb5401b5c0..8496a0215bc78585b546f63312c= 9d7f1ad07adb6 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -32,7 +32,6 @@ typedef struct { UINT32 Mode; UINT32 HorizontalResolution; UINT32 VerticalResolution; - LCD_BPP Bpp; UINT32 OscFreq; =20 // These are used by HDLCD @@ -48,37 +47,37 @@ typedef struct { **/ STATIC CONST LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH @@ -292,27 +291,12 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; =20 - switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; =20 return EFI_SUCCESS; } @@ -395,7 +379,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mResolutions[ModeNumber].Bpp; + *Bpp =3D LCD_BITS_PER_PIXEL_24; =20 return EFI_SUCCESS; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969746459456.39800189498374; Fri, 22 Dec 2017 11:09:06 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 03E4A222F4E00; Fri, 22 Dec 2017 11:03:50 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D61EA22225C1E for ; Fri, 22 Dec 2017 11:03:40 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx5005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:15 +0000 Message-Id: <20171222190821.12440-13-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 12/18] ARM/VExpressPkg: Redefine LcdPlatformGetTimings function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak The LcdPlatformGetTimings interface function takes similar sets of multiple parameters for horizontal and vertical timings which can be aggregated in a common data type. This change defines a structure SCAN_TIMINGS for this which can be used to describe both horizontal and vertical scan timings, and accordingly redefines the LcdPlatformGetTiming interface, greatly reducing the amount of data passed about. Similarly the mode definition tables are also changed to use this data type and thus enable pass through access. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 104 +++++------- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 168 ++++++++------------ 2 files changed, 108 insertions(+), 164 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index 8496a0215bc78585b546f63312c9d7f1ad07adb6..b448d70f86d6acbc6bdae9749c7= b6d0205935ba7 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -30,57 +30,51 @@ =20 typedef struct { UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; UINT32 OscFreq; =20 // These are used by HDLCD - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; =20 /** The display modes supported by the platform. **/ -STATIC CONST LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, + VGA, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, + SVGA, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, + XGA, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, + SXGA, (SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, + UXGA, (UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH= }, + {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, + HD, (HD_OSC_FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} } }; =20 @@ -205,7 +199,7 @@ LcdPlatformGetMaxMode (VOID) { // The following line will report correctly the total number of graphics= modes // that could be supported by the graphics driver - return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); + return (sizeof (mDisplayModes) / sizeof (DISPLAY_MODE)); } =20 /** Set the requested display mode. @@ -242,7 +236,7 @@ LcdPlatformSetMode ( // Set the DVI into the new mode Status =3D ArmPlatformSysConfigSet ( SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode + mDisplayModes[ModeNumber].Mode ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -287,9 +281,9 @@ LcdPlatformQueryMode ( } =20 Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; @@ -305,14 +299,10 @@ LcdPlatformQueryMode ( =20 @param[in] ModeNumber Mode Number. =20 - @param[out] HRes Pointer to horizontal resolution. - @param[out] HSync Pointer to horizontal sync width. - @param[out] HBackPorch Pointer to horizontal back porch. - @param[out] HFrontPorch Pointer to horizontal front porch. - @param[out] VRes Pointer to vertical resolution. - @param[out] VSync Pointer to vertical sync width. - @param[out] VBackPorch Pointer to vertical back porch. - @param[out] VFrontPorch Pointer to vertical front porch. + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) =20 @retval EFI_SUCCESS Display timing information for the reque= sted mode returned successfully. @@ -320,40 +310,22 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN CONST UINT32 ModeNumber, - OUT UINT32 * CONST HRes, - OUT UINT32 * CONST HSync, - OUT UINT32 * CONST HBackPorch, - OUT UINT32 * CONST HFrontPorch, - OUT UINT32 * CONST VRes, - OUT UINT32 * CONST VSync, - OUT UINT32 * CONST VBackPorch, - OUT UINT32 * CONST VFrontPorch + IN CONST UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS ** Horizontal, + OUT CONST SCAN_TIMINGS ** Vertical ) { // One of the pointers is NULL - ASSERT (HRes !=3D NULL); - ASSERT (HSync !=3D NULL); - ASSERT (HBackPorch !=3D NULL); - ASSERT (HFrontPorch !=3D NULL); - ASSERT (VRes !=3D NULL); - ASSERT (VSync !=3D NULL); - ASSERT (VBackPorch !=3D NULL); - ASSERT (VFrontPorch !=3D NULL); + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; =20 return EFI_SUCCESS; } diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index cf50b20fd9b1b44a81963655c2f88305ce6bdc67..439cbdb1a73145fc4dc9c3c9587= ce3fd9b9fff56 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -28,117 +28,111 @@ =20 typedef struct { UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; LCD_BPP Bpp; UINT32 OscFreq; =20 - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; =20 /** The display modes supported by the platform. **/ -LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH= }, + {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} }, { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + VGA, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + SVGA, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + XGA, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + VGA, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + SVGA, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA, LCD_BITS_PER_PIXEL_16_555, 63500000, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + VGA, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + SVGA, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + XGA, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} } }; =20 @@ -304,7 +298,7 @@ LcdPlatformSetMode ( Status =3D ArmPlatformSysConfigSetDevice ( Function, OscillatorId, - mResolutions[ModeNumber].OscFreq + mDisplayModes[ModeNumber].OscFreq ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -322,7 +316,7 @@ LcdPlatformSetMode ( // Set the DVI into the new mode Status =3D ArmPlatformSysConfigSet ( SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode + mDisplayModes[ModeNumber].Mode ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -362,11 +356,11 @@ LcdPlatformQueryMode ( } =20 Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mResolutions[ModeNumber].Bpp) { + switch (mDisplayModes[ModeNumber].Bpp) { case LCD_BITS_PER_PIXEL_24: Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; @@ -395,14 +389,10 @@ LcdPlatformQueryMode ( =20 @param[in] ModeNumber Mode Number. =20 - @param[out] HRes Pointer to horizontal resolution. - @param[out] HSync Pointer to horizontal sync width. - @param[out] HBackPorch Pointer to horizontal back porch. - @param[out] HFrontPorch Pointer to horizontal front porch. - @param[out] VRes Pointer to vertical resolution. - @param[out] VSync Pointer to vertical sync width. - @param[out] VBackPorch Pointer to vertical back porch. - @param[out] VFrontPorch Pointer to vertical front porch. + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) =20 @retval EFI_SUCCESS Display timing information for the reque= sted mode returned successfully. @@ -410,40 +400,22 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN CONST UINT32 ModeNumber, - OUT UINT32 * CONST HRes, - OUT UINT32 * CONST HSync, - OUT UINT32 * CONST HBackPorch, - OUT UINT32 * CONST HFrontPorch, - OUT UINT32 * CONST VRes, - OUT UINT32 * CONST VSync, - OUT UINT32 * CONST VBackPorch, - OUT UINT32 * CONST VFrontPorch + IN CONST UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS ** Horizontal, + OUT CONST SCAN_TIMINGS ** Vertical ) { // One of the pointers is NULL - ASSERT (HRes !=3D NULL); - ASSERT (HSync !=3D NULL); - ASSERT (HBackPorch !=3D NULL); - ASSERT (HFrontPorch !=3D NULL); - ASSERT (VRes !=3D NULL); - ASSERT (VSync !=3D NULL); - ASSERT (VBackPorch !=3D NULL); - ASSERT (VFrontPorch !=3D NULL); + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { ASSERT (FALSE); return EFI_INVALID_PARAMETER; } =20 - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; =20 return EFI_SUCCESS; } @@ -471,7 +443,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mResolutions[ModeNumber].Bpp; + *Bpp =3D mDisplayModes[ModeNumber].Bpp; =20 return EFI_SUCCESS; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969744238997.6222121929226; Fri, 22 Dec 2017 11:09:04 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A128B22198F73; Fri, 22 Dec 2017 11:03:49 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D59BB21A0292D for ; Fri, 22 Dec 2017 11:03:40 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx6005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:16 +0000 Message-Id: <20171222190821.12440-14-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 13/18] ARM/VExpressPkg: PL111 and HDLCD: Add PCD to select pixel format X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Current HDLCD and PL111 platform libraries do not support display modes with PixelBlueGreenRedReserved8BitPerColor format, i.e. because of historical confusion, they do not support the UEFI default PixelBlueGreenRedReserved8BitPerColor LcdPlatformLib for PL111, LcdPlatformQueryMode function returns the pixel format as PixelRedGreenBlueReserved8BitPerColor which is wrong, because that does not match the display controller's pixel format which is set to BGR in PL111Lcd GOP driver. Also it is not possible to configure pixel format as RGB/BGR for the display modes for a platform at build time. This change adds PcdGopPixelFormat to configure pixel format as PixelRedGreenBlueReserved8BitPerColor or PixelBlueGreenRedReserved8BitPerColor or PixelBitMask. With this change, pixel format can be selected in the platform specific .dsc file for all supported display modes. Support for PixelBitMask is not implemented in PL111 or HDLCD GOP driver, hence HDLCD and PL111 platform libraries will return error EFI_UNSUPPORTED if PcdGopPixelFormat is set to PixelBitMask. Indeed, it is not clear what selecting PixelBitMask might mean, but the option is allowed as it might suit a custom platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 1 + Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 1 + Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 23 ++++++++---- Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 38 +++++++++----------- 4 files changed, 35 insertions(+), 28 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf index 2e83736609cf8c63cb498368cd377f6a23964ef4..4cbd324338be76a0b0bfb811159= d893628e74155 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -41,3 +41,4 @@ [Protocols] =20 [FixedPcd] gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf index 1ee878041559fa84a810f65175f2507bda663d76..20045380149241ce14f41bcb70a= fcb8145fe821f 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -42,3 +42,4 @@ [Protocols] [FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c index b448d70f86d6acbc6bdae9749c7b6d0205935ba7..f1c18ac955f621e9eab3dede867= 58f5f1b1a791d 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -15,7 +15,6 @@ #include =20 #include -#include #include #include #include @@ -93,6 +92,10 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { @param[in] Handle Handle to the LCD device instance. =20 @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -101,6 +104,17 @@ LcdPlatformInitializeDisplay ( ) { EFI_STATUS Status; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } =20 // Set the FPGA multiplexer to select the video output from the // motherboard or the daughterboard @@ -285,12 +299,7 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); =20 return EFI_SUCCESS; } diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c index 439cbdb1a73145fc4dc9c3c9587ce3fd9b9fff56..16a74c76cf27526493165dc6d81= 384f752fd3f20 100644 --- a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -149,7 +149,12 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { /** PL111 Platform specific initialization function. =20 @param[in] Handle Handle to the LCD device instance. + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -158,6 +163,17 @@ LcdPlatformInitializeDisplay ( ) { EFI_STATUS Status; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } =20 // Set the FPGA multiplexer to select the video output from the motherbo= ard // or the daughterboard @@ -360,27 +376,7 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mDisplayModes[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitP= erColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); =20 return EFI_SUCCESS; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969741863650.7535765186055; Fri, 22 Dec 2017 11:09:01 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 444BB222CB327; Fri, 22 Dec 2017 11:03:49 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9317E22225C1D for ; Fri, 22 Dec 2017 11:03:40 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx7005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:17 +0000 Message-Id: <20171222190821.12440-15-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 14/18] ARM/VExpressPkg: Reserving framebuffer at build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change uses two PCDs, PcdArmLcdFrameBufferBase and PcdArmLcdFrameBufferSize introduced in correspondiong EDK2 patch to reserve framebuffer in DRAM if these values are defined in platform specific DSC file, avoiding the need to allocate dynamically. This allows the framebuffer to appear as "I/O memory" outside of the normal RAM map, which is similar to the "VRAM" case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | = 4 +++- Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 2= 0 ++++++++++++++++++-- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpres= sLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf index 4cbd2ff4b4faf11ccd4fe30117708d7cc4c1bf0e..c70c4ce64826174e6d15611de64= 0ad3b902835b9 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf @@ -1,5 +1,5 @@ #/* @file -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2011-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -57,6 +57,8 @@ [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore =20 gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 6379e81751fca5e7972c5c30f305be65fd1ae71d..1e8f3205312ebf30fa1666130bc= 944261384359a 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -20,8 +20,10 @@ #include #include =20 +#define FRAME_BUFFER_DESCRIPTOR ((FixedPcdGet64 (PcdArmLcdDdrFrameBufferBa= se) !=3D 0) ? 1 : 0) + // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + FRAME_BUFFER_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -142,6 +144,20 @@ ArmPlatformGetVirtualMemoryMap ( // VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; =20 + // Map region for the frame buffer in the system RAM +#if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize) !=3D 0) + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmLcdDdr= FrameBufferBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmLcdDdrFra= meBufferBase); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmLcdDdrFrameBuf= ferSize); + // Map as Normal Non-Cacheable memory, so that we can use the accelerated + // SetMem/CopyMem routines that may use unaligned accesses or + // DC ZVA instructions. If mapped as device memory, these routine may ca= use + // alignment faults. + // NOTE: The attribute value is misleading, it indicates memory map type= as + // an un-cached, un-buffered but allows buffering and reordering. + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; +#endif + // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase =3D SparseMemoryBase; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969749035939.8982692351121; Fri, 22 Dec 2017 11:09:09 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 567F2222F4E04; Fri, 22 Dec 2017 11:03:50 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D9EC622225C1F for ; Fri, 22 Dec 2017 11:03:40 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx8005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:18 +0000 Message-Id: <20171222190821.12440-16-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 15/18] ARM/VExpressPkg: New DP500/DP550/DP650 platform library. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds LcdPlatformLib implementation for ARM Mali DP500/DP500/DP650 display processors for models (with DP550 support). NOTE: Versions for actual hardware are liable to require extra handling for clock input changes, etc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- Platform/ARM/VExpressPkg/ArmVExpressPkg.dec | = 3 +- Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf | = 45 +++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | = 3 + Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c | 3= 74 ++++++++++++++++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | = 10 +- 5 files changed, 433 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec b/Platform/ARM/VEx= pressPkg/ArmVExpressPkg.dec index 695553a94f7f7e963b5db995c5e54f1ae1559daf..a82bc905b3a2180e85f78a6c16a= eba9fcb495bed 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec +++ b/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec @@ -1,7 +1,7 @@ #/** @file # Arm Versatile Express package. # -# Copyright (c) 2012-2015, ARM Limited. All rights reserved. +# Copyright (c) 2012-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials are licensed and made avail= able # under the terms and conditions of the BSD License which accompanies this @@ -51,6 +51,7 @@ [PcdsFixedAtBuild.common] gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000003 =20 gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000005 + gArmVExpressTokenSpaceGuid.PcdArmMaliDpMaxMode|0|UINT32|0x00000008 =20 # # Device path of block device on which Fastboot will flash partitions diff --git a/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf= b/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..4c8f3c3b3b6540505fce173ef16= e2f3eafeb048b --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf @@ -0,0 +1,45 @@ +#/** @file ArmMaliDpLib.inf +# +# Component description file for ArmMaliDpLib module +# +# Copyright (c) 2017, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmMaliDpLib + FILE_GUID =3D 36C47FED-2F3F-49C7-89CE-31B13F0431D8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + ArmMaliDpLib.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + BaseLib + DxeServicesTableLib + +[FixedPcd.common] + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat + + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # See Section 12.9 of the UEFI Specification 2.7 + gArmVExpressTokenSpaceGuid.PcdArmMaliDpMaxMode + diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpres= sLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf index c70c4ce64826174e6d15611de640ad3b902835b9..c2d8749d0c08d6afc71f7c41a27= 075d58ff27557 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf @@ -60,5 +60,8 @@ [FixedPcd] gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase + gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c b= /Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c new file mode 100644 index 0000000000000000000000000000000000000000..63f7c3b874b4fea80ab81c396a0= 8e3e2e9b0581c --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c @@ -0,0 +1,374 @@ +/** @file ArmMaliDpLib.c + + The file contains ARM Mali DP platform specific implementation. + + Copyright (c) 2017, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** Check an address is within 40 bits. + + The ARM Mali DP framebuffer address size can not be wider than 40 bits +**/ +#define DP_VALID_BASE_ADDR(Address) ((Address >> 40) =3D=3D 0) + +typedef struct { + UINT32 OscFreq; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; + +/** The display modes implemented by this driver. + + On Models, the OSC frequencies (listed for each mode below) are not used. + However these frequencies are useful on hardware plaforms where related + clock (or PLL) settings are based on these pixel clocks. + + Since the clock settings are defined externally, the driver must + communicate pixel clock frequencies to relevant modules + responsible for setting clocks. e.g. SCP. +**/ +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { + { + // Mode 0 : VGA : 640 x 480 x 24 bpp. + VGA_OSC_FREQUENCY, + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} + }, + { + // Mode 1 : WVGA : 800 x 480 x 24 bpp. + WVGA_OSC_FREQUENCY, + {WVGA_H_RES_PIXELS, WVGA_H_SYNC, WVGA_H_BACK_PORCH, WVGA_H_FRONT_PORCH= }, + {WVGA_V_RES_PIXELS, WVGA_V_SYNC, WVGA_V_BACK_PORCH, WVGA_V_FRONT_PORCH} + }, + { + // Mode 2 : SVGA : 800 x 600 x 24 bpp. + SVGA_OSC_FREQUENCY, + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} + }, + { + // Mode 3 : QHD : 960 x 540 x 24 bpp. + QHD_OSC_FREQUENCY, + {QHD_H_RES_PIXELS, QHD_H_SYNC, QHD_H_BACK_PORCH, QHD_H_FRONT_PORCH}, + {QHD_V_RES_PIXELS, QHD_V_SYNC, QHD_V_BACK_PORCH, QHD_V_FRONT_PORCH} + }, + { + // Mode 4 : WSVGA : 1024 x 600 x 24 bpp. + WSVGA_OSC_FREQUENCY, + {WSVGA_H_RES_PIXELS, WSVGA_H_SYNC, WSVGA_H_BACK_PORCH, WSVGA_H_FRONT_P= ORCH}, + {WSVGA_V_RES_PIXELS, WSVGA_V_SYNC, WSVGA_V_BACK_PORCH, WSVGA_V_FRONT_P= ORCH} + }, + { + // Mode 5 : XGA : 1024 x 768 x 24 bpp. + XGA_OSC_FREQUENCY, + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} + }, + { + // Mode 6 : HD : 1280 x 720 x 24 bpp. + HD720_OSC_FREQUENCY, + {HD720_H_RES_PIXELS, HD720_H_SYNC, HD720_H_BACK_PORCH, HD720_H_FRONT_P= ORCH}, + {HD720_V_RES_PIXELS, HD720_V_SYNC, HD720_V_BACK_PORCH, HD720_V_FRONT_P= ORCH} + }, + { + // Mode 7 : WXGA : 1280 x 800 x 24 bpp. + WXGA_OSC_FREQUENCY, + {WXGA_H_RES_PIXELS, WXGA_H_SYNC, WXGA_H_BACK_PORCH, WXGA_H_FRONT_PORCH= }, + {WXGA_V_RES_PIXELS, WXGA_V_SYNC, WXGA_V_BACK_PORCH, WXGA_V_FRONT_PORCH} + }, + { // Mode 8 : SXGA : 1280 x 1024 x 24 bpp. + SXGA_OSC_FREQUENCY, + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} + }, + { // Mode 9 : WSXGA+ : 1680 x 1050 x 24 bpp. + WSXGA_OSC_FREQUENCY, + {WSXGA_H_RES_PIXELS, WSXGA_H_SYNC, WSXGA_H_BACK_PORCH, WSXGA_H_FRONT_P= ORCH}, + {WSXGA_V_RES_PIXELS,WSXGA_V_SYNC, WSXGA_V_BACK_PORCH, WSXGA_V_FRONT_PO= RCH} + }, + { + // Mode 10 : HD : 1920 x 1080 x 24 bpp. + HD_OSC_FREQUENCY, + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} + } +}; + +/** If PcdArmMaliDpMaxMode is 0, platform supports full range of modes + else platform supports modes from 0 to PcdArmMaliDpMaxMode - 1 +**/ +STATIC CONST UINT32 mMaxMode =3D ((FixedPcdGet32 (PcdArmMaliDpMaxMode) != =3D 0) + ? FixedPcdGet32 (PcdArmMaliDpMaxMode) + : sizeof (mDisplayModes) / sizeof (DISP= LAY_MODE)); + +/** Platform related initialization function. + + @param[in] Handle Handle to the instance of the device. + + @retval EFI_SUCCESS Initialization of platform library success= ful. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. +**/ +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN CONST EFI_HANDLE Handle + ) +{ + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + (VOID)Handle; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/* Internal helper function to allocate memory if memory is not already + reserved for framebuffer + + @param[in] VramSize Requested framebuffer size in bytes. + @param[out] VramBaseAddress Pointer to memory allocated for framebuffe= r. + + @retval EFI_SUCCESS Framebuffer memory allocated successfully. + @retval EFI_UNSUPPORTED Allocated address wider than 40 bits. + @retval !EFI_SUCCESS Other errors. +**/ +STATIC +EFI_STATUS +GetVram ( + IN UINTN CONST VramSize, + OUT EFI_PHYSICAL_ADDRESS *CONST VramBaseAddress + ) +{ + EFI_STATUS Status; + + // Check if memory is already reserved for the framebuffer. +#if (FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase) !=3D 0) + +#if (!DP_VALID_BASE_ADDR (FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase))) +#error ARM Mali DP framebuffer base address cannot be wider than 40 bits. +#else + *VramBaseAddress =3D + (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase); + + Status =3D EFI_SUCCESS; +#endif + +#else + // If not already reserved, attempt to allocate the VRAM from the DRAM. + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (*VramSize), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ArmMaliDpLib: Failed to allocate framebuffer.\n"= )); + ASSERT (FALSE); + return Status; + } + + // ARM Mali DP framebuffer base address can not be wider than 40 bits. + if (!DP_VALID_BASE_ADDR (*VramBaseAddress)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + ASSERT (DP_VALID_BASE_ADDR (*VramBaseAddress)); + return EFI_UNSUPPORTED; + } + + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is + // cacheable, for ARM/AArch64 EFI_MEMORY_WC memory is actually uncached. + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + } +#endif + + return Status; +} + +/** Allocate VRAM memory in DRAM for the framebuffer + (unless it is reserved already). + + The allocated address can be used to set the framebuffer as a base buffer + address for any layer of the ARM Mali DP. + + @param[out] VramBaseAddress A pointer to the framebuffer address. + @param[out] VramSize A pointer to the size of the frame + buffer in bytes + + @retval EFI_SUCCESS Frame buffer memory allocation success. + @retval EFI_UNSUPPORTED Allocated address wider than 40 bits + @retval !EFI_SUCCESS Other errors. +**/ +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize + ) +{ + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + + // Set the VRAM size. + *VramSize =3D (UINTN)FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize); + + return GetVram (*VramSize, VramBaseAddress); +} + +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ +UINT32 +LcdPlatformGetMaxMode (VOID) +{ + return mMaxMode; +} + +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successful. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformSetMode ( + IN CONST UINT32 ModeNumber + ) +{ + + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + // On models, platform specific clock/mux settings are not required. + // Display controller specific settings for Mali DP are done in LcdSetMo= de. + return EFI_SUCCESS; +} + +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Display mode information of the requested + mode returned successfully. +**/ +EFI_STATUS +LcdPlatformQueryMode ( + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info + ) +{ + ASSERT (ModeNumber < mMaxMode); + ASSERT (Info !=3D NULL); + + Info->Version =3D 0; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; + + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + + return EFI_SUCCESS; +} + +/** Return the display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front porc= h) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front porc= h) + + @retval EFI_SUCCESS Display timing information of the reques= ted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS ** Horizontal, + OUT CONST SCAN_TIMINGS ** Vertical + ) +{ + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; + + return EFI_SUCCESS; +} + +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Bpp Pointer to value Bytes Per Pixel. + + @retval EFI_SUCCESS Bits per pixel information of the display + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetBpp ( + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp + ) +{ + ASSERT (Bpp !=3D NULL); + if (ModeNumber >=3D mMaxMode) { + // Check valid ModeNumber. + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D LCD_BITS_PER_PIXEL_24; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 1e8f3205312ebf30fa1666130bc944261384359a..f0b482f91a84d91ac9914c18b79= 41dd32ab8c8a7 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -21,9 +21,10 @@ #include =20 #define FRAME_BUFFER_DESCRIPTOR ((FixedPcdGet64 (PcdArmLcdDdrFrameBufferBa= se) !=3D 0) ? 1 : 0) +#define DP_BASE_DESCRIPTOR ((FixedPcdGet64 (PcdArmMaliDpBase) !=3D 0)= ? 1 : 0) =20 // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + FRAME_BUFFER_DESCRIPTOR) +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + FRAME_BUFFER_DESCRIPTOR + = DP_BASE_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -158,6 +159,13 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; #endif =20 +#if (FixedPcdGet64 (PcdArmMaliDpBase) !=3D 0) + // DP500/DP550/DP650 peripheral memory region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmMaliDp= Base); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmMaliDpBas= e); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmMaliDpMemoryRe= gionLength); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; +#endif // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase =3D SparseMemoryBase; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969751603508.5428273413197; Fri, 22 Dec 2017 11:09:11 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9EBAB222F4E08; Fri, 22 Dec 2017 11:03:50 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F7DA208F7A87 for ; Fri, 22 Dec 2017 11:03:41 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8Qx9005645; Fri, 22 Dec 2017 19:08:28 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:19 +0000 Message-Id: <20171222190821.12440-17-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 16/18] ARM/JunoPkg: Mapping Non-Trused SRAM as device memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This fix changes the cache attribute of Non-Trusted SRAM on the Juno platform to device memory. This change is required to avoid coherency problems as Non-Trusted SRAM is used as a shared memory between the application processor and the SCP for communication. This change is a prerequisite for upcoming SCMI driver for the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Reviewed-by: Ard Biesheuvel --- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c b/Platfor= m/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c index aa8d7d9c3b0d41e62d1849e6e88760e3066617f7..afb2db0050c65b0d1b2b69c9038= e168755c152c1 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2013-2015, ARM Limited. All rights reserved. +* Copyright (c) 2013-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -111,7 +111,9 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[++Index].PhysicalBase =3D ARM_JUNO_NON_SECURE_SRAM_B= ASE; VirtualMemoryTable[Index].VirtualBase =3D ARM_JUNO_NON_SECURE_SRAM_B= ASE; VirtualMemoryTable[Index].Length =3D ARM_JUNO_NON_SECURE_SRAM_S= Z; - VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + // This memory is shared between the application processor + // and the SCP. To avoid coherency problems, map it as device memory. + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 // PCI Root Complex VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieControlBa= seAddress); --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969754238152.33613000604407; Fri, 22 Dec 2017 11:09:14 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DCE68222F4E0C; Fri, 22 Dec 2017 11:03:50 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D74522198F6A for ; Fri, 22 Dec 2017 11:03:41 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8QxA005645; Fri, 22 Dec 2017 19:08:29 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:20 +0000 Message-Id: <20171222190821.12440-18-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 17/18] ARM/JunoPkg: Adding SCMI MTL library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds a new Mailbox Transport Layer library for the Juno platform. This library is required for ArmScmiDxe driver communication with the SCP. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak --- Platform/ARM/JunoPkg/ArmJuno.dec | 9 +- Platform/ARM/JunoPkg/ArmJuno.dsc | 3 + Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.inf | 39 ++++ Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtlPrivate.h | 94 ++++++++++ Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.c | 195 ++++++++++++++++= ++++ 5 files changed, 339 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/JunoPkg/ArmJuno.dec b/Platform/ARM/JunoPkg/ArmJun= o.dec index 60cef6d23a2d904103b9806d871fd2b89fff51c3..b733480c3198d135df16ca024b5= e85ff350e11c7 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dec +++ b/Platform/ARM/JunoPkg/ArmJuno.dec @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# Copyright (c) 2013-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -46,3 +46,10 @@ [PcdsFixedAtBuild.common] # Juno Device Trees are loaded from NOR Flash gArmJunoTokenSpaceGuid.PcdJunoFdtDevicePath|L"VenHw(E7223039-5836-41E1-B= 542-D7EC736C5E59)/board.dtb"|VOID*|0x00000008 =20 + # MHU Register base used by SCMI Mailbox transport + gArmJunoTokenSpaceGuid.PcdArmMtlDoorBell|0x2B1F0000|UINT64|0x00000024 + + # ARM_JUNO_NON_SECURE_SRAM_BASE used by SCMI Mailbox transport + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxBase|0x2E000000|UINT64|0x00000025 + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxSize|0x80|UINT32|0x00000026 + diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJun= o.dsc index 5c2a29fe8330bbf308e31e34b617517a5aebcf6d..fe860956a4dc497cac52be70bab= 3657246a08bd0 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dsc +++ b/Platform/ARM/JunoPkg/ArmJuno.dsc @@ -47,6 +47,9 @@ [LibraryClasses.common] # USB Requirements UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf =20 + # SCMI Mailbox Transport Layer + ArmMtl|Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.inf + [LibraryClasses.common.SEC] PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf diff --git a/Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.inf b/Platform/ARM/= JunoPkg/Library/ArmMtl/ArmMtl.inf new file mode 100644 index 0000000000000000000000000000000000000000..69e845f93f9332205fd5d36af27= 53681304058e3 --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.inf @@ -0,0 +1,39 @@ +#/** @file +# Copyright (c) 2017, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmMtl + FILE_GUID =3D 21FB2D8F-C6C8-4B2C-A616-A30CB2FBA277 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmMtl + +[Sources.common] + ArmMtl.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/JunoPkg/ArmJuno.dec + +[LibraryClasses] + ArmLib + DebugLib + IoLib + UefiBootServicesTableLib + +[FixedPcd.common] + gArmJunoTokenSpaceGuid.PcdArmMtlDoorBell + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxBase + gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxSize diff --git a/Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtlPrivate.h b/Platform= /ARM/JunoPkg/Library/ArmMtl/ArmMtlPrivate.h new file mode 100644 index 0000000000000000000000000000000000000000..825fc788722bbe01ede24d9f867= 565c4c1dc938b --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtlPrivate.h @@ -0,0 +1,94 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf + + Juno ARM Development Platform SoC + https://www.arm.com/files/pdf/ + DDI0515D1a_juno_arm_development_platform_soc_trm.pdf +**/ + +#ifndef ARM_MTL_PRIVATE_H_ +#define ARM_MTL_PRIVATE_H_ + +// Mailbox transport layer. +#define MTL_DOORBELL_MODIFY_MASK (0x00000001U) +#define MTL_DOORBELL_PRESERVE_MASK (~MTL_DOORBELL_MODIFY_MASK) + +#define MTL_DOORBELL_BASE (FixedPcdGet64 (PcdArmMtlDoorBell)) +#define MTL_MAILBOX_BASE (FixedPcdGet64 (PcdArmMtlMailBoxBase)) +#define MTL_MAILBOX_SIZE (FixedPcdGet32 (PcdArmMtlMailBoxSize)) + +#define MTL_POLL 0 +#define MTL_INTR 1 + +/* For Juno, the mailbox for high priority is non-trusted SRAM + 256. + + NOTE: Below is not documented anywhere (yet) + + The payload sizes are 128 bytes. + + There are two channels: + + Channel 0 + - Agent (OS) to Platform (SCP) memory base: non-trusted SRAM + 0 + - Platform (SCP) to Agent (OS) memory base: non-trusted SRAM + 128 + - Doorbell (both directions): MHU, bit 0 + + Channel 1 + - Agent (OS) to Platform (SCP) memory base: non-trusted SRAM + 256 + - Platform (SCP) to Agent (OS) memory base: non-trusted SRAM + 384 + - Doorbell (both directions): MHU, bit 0 +*/ +#define MTL_MAILBOX_HIGH_PRIORITY_OFFSET (MTL_MAILBOX_SIZE * 2) + +// ARM MHU interrupt registers. +#define CPU_INTR_L_SET 0x108 +#define CPU_INTR_H_SET 0x128 + +// MTL uses MHU interrupt registers for communication with the SCP. +#define MTL_DOORBELL_REGISTER_LOW (MTL_DOORBELL_BASE + CPU_INTR_L_SET) +#define MTL_DOORBELL_REGISTER_HIGH (MTL_DOORBELL_BASE + CPU_INTR_H_SET) + +#define MTL_CHANNEL_BUSY 0 +#define MTL_CHANNEL_FREE 1 + +// Response timeout value on a MHU channel 20ms. +#define RESPONSE_TIMEOUT 20000 + +/* As per SCMI spec. as a agent UEFI(or OS) can access only two channels + (low or high priority) secure channel is only accessible + to ARM Trusted firmware. */ +#define NUM_CHANNELS 2 + +/* Each channel must use a doorbell register to interrupt the SCP firmware. + on Juno these are MHU interrupt registers for low and high priority + channels. */ +#define DOORBELL_LOW { \ + MTL_DOORBELL_REGISTER_LOW, \ + MTL_DOORBELL_MODIFY_MASK, \ + MTL_DOORBELL_PRESERVE_MASK \ + } + +#define DOORBELL_HIGH { \ + MTL_DOORBELL_REGISTER_HIGH, \ + MTL_DOORBELL_MODIFY_MASK, \ + MTL_DOORBELL_PRESERVE_MASK \ + } + +// Arbitarary poll time. +#define MTL_POLL_WAIT_TIME 100 + +#endif /* ARM_MTL_PRIVATE_H_ */ + diff --git a/Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.c b/Platform/ARM/Ju= noPkg/Library/ArmMtl/ArmMtl.c new file mode 100644 index 0000000000000000000000000000000000000000..b5e469f9a51a8f739526c7eeb87= 3c32403d191f9 --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.c @@ -0,0 +1,195 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "ArmMtlPrivate.h" + +// Each channel has a shared mailbox and a doorbell register. +STATIC CONST MTL_CHANNEL Channels[NUM_CHANNELS] =3D { + // Low priority channel. + { + MTL_CHANNEL_TYPE_LOW, + (MTL_MAILBOX*)(MTL_MAILBOX_BASE), + DOORBELL_LOW + }, + // High priority channel + { + MTL_CHANNEL_TYPE_HIGH, + (MTL_MAILBOX*)(MTL_MAILBOX_BASE + MTL_MAILBOX_HIGH_PRIORITY_OFFSET), + DOORBELL_HIGH + } + }; + +/** Wait until channel is free. + + @param[in] Channel Pointer to a channel. + @param[in] TimeOutInMicroSeconds Time out in micro seconds. + + @retval EFI_SUCCESS Channel is free. + @retval EFI_TIMOUT Time out error. +**/ +EFI_STATUS +MtlWaitUntilChannelFree ( + IN MTL_CHANNEL *Channel, + IN UINTN TimeOutInMicroSeconds + ) +{ + while (TimeOutInMicroSeconds !=3D 0) { + // If channel is free then we have received the reply. + if (Channel->MailBox->ChannelStatus =3D=3D MTL_CHANNEL_FREE) { + return EFI_SUCCESS; + } + if (TimeOutInMicroSeconds < MTL_POLL_WAIT_TIME) { + gBS->Stall (TimeOutInMicroSeconds); + break; + } + // Wait for some arbitrary time. + gBS->Stall (MTL_POLL_WAIT_TIME); + TimeOutInMicroSeconds -=3D MTL_POLL_WAIT_TIME; + } + + // No response from SCP. + if (Channel->MailBox->ChannelStatus !=3D MTL_CHANNEL_FREE) { + ASSERT (FALSE); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/** Return the address of the message payload. + + @param[in] Channel Pointer to a channel. + + @retval UINT32* Pointer to the payload. +**/ +UINT32* +MtlGetChannelPayload ( + IN MTL_CHANNEL *Channel + ) +{ + return Channel->MailBox->Payload; +} + +/** Return pointer to a channel for the requested channel type. + + @param[in] ChannelType ChannelType, Low or High priority channel. + MTL_CHANNEL_TYPE_LOW or + MTL_CHANNEL_TYPE_HIGH + + @param[out] Channel Holds pointer to the channel. + + @retval EFI_SUCCESS Pointer to channel is returned. + @retval EFI_UNSUPPORTED Requested channel type not supported. +**/ +EFI_STATUS +MtlGetChannel ( + IN MTL_CHANNEL_TYPE ChannelType, + OUT MTL_CHANNEL **Channel + ) +{ + if (ChannelType !=3D MTL_CHANNEL_TYPE_LOW + && ChannelType !=3D MTL_CHANNEL_TYPE_HIGH) { + return EFI_UNSUPPORTED; + } + + *Channel =3D (MTL_CHANNEL*)&Channels[ChannelType]; + + return EFI_SUCCESS; +} + +/** Mark the channel busy and ring the doorbell. + + @param[in] Channel Pointer to a channel. + @param[in] MessageHeader Message header. + + @param[out] PayloadLength Message length. + + @retval EFI_SUCCESS Message sent successfully. + @retval EFI_DEVICE_ERROR Channel is busy. +**/ +EFI_STATUS +MtlSendMessage ( + IN MTL_CHANNEL *Channel, + IN UINT32 MessageHeader, + OUT UINT32 PayloadLength + ) +{ + MTL_MAILBOX *MailBox =3D Channel->MailBox; + + if (Channel->MailBox->ChannelStatus !=3D MTL_CHANNEL_FREE) { + return EFI_DEVICE_ERROR; + } + + // Mark the channel busy before ringing doorbell. + Channel->MailBox->ChannelStatus =3D MTL_CHANNEL_BUSY; + + MailBox->Flags =3D MTL_POLL; + MailBox->MessageHeader =3D MessageHeader; + + // Add length of message header. + MailBox->Length =3D PayloadLength + sizeof (MessageHeader); + + // Ring the doorbell. It sets SET bit of the MHU register. + MmioWrite32 ( + Channel->DoorBell.PhysicalAddress, + Channel->DoorBell.ModifyMask + ); + + return EFI_SUCCESS; +} + +/** Wait for a response on a channel. + + If channel is free after sending message, it implies SCP responded + with a response on the channel. + + @param[in] Channel Pointer to a channel. + + @retval EFI_SUCCESS Message received successfully. + @retval EFI_TIMOUT Timeout error. +**/ +EFI_STATUS +MtlReceiveMessage ( + IN MTL_CHANNEL *Channel, + OUT UINT32 *MessageHeader, + OUT UINT32 *PayloadLength + ) +{ + EFI_STATUS Status; + + MTL_MAILBOX *MailBox =3D Channel->MailBox; + + Status =3D MtlWaitUntilChannelFree (Channel, RESPONSE_TIMEOUT); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageHeader =3D MailBox->MessageHeader; + + // Deduct message header length. + *PayloadLength =3D MailBox->Length - sizeof (*MessageHeader); + + return EFI_SUCCESS; +} --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 00:34:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513969756812821.358949204734; Fri, 22 Dec 2017 11:09:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 38B9A222F4E11; Fri, 22 Dec 2017 11:03:51 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 89B2E22225C1B for ; Fri, 22 Dec 2017 11:03:41 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMJ8QxB005645; Fri, 22 Dec 2017 19:08:29 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 19:08:21 +0000 Message-Id: <20171222190821.12440-19-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222190821.12440-1-evan.lloyd@arm.com> References: <20171222190821.12440-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH edk2-platforms v2 18/18] ARM/JunoPkg: Add HDLCD platform library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Matteo.Carlini@arm.com"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, Arvind Chauhan , Thomas Panakamattam Abraham , "ard.biesheuvel@linaro.org"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds the HDLCD platform lib for the Juno plaform. This library will be instantiated as a LcdPlatformLib to link with LcdGraphicsOutputDxe for the Juno platform. HDLCD platform library depends on the Arm SCMI DXE driver for communication with the SCP for clock setting. Therefore this change also enables building of Arm SCMI DXE driver for the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak --- Platform/ARM/JunoPkg/ArmJuno.dec | 8 + Platform/ARM/JunoPkg/ArmJuno.dsc | 29 + Platform/ARM/JunoPkg/ArmJuno.fdf | 12 +- Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf | 5 +- Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf | 40 ++ Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c | 18 +- Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c | 559 +++= +++++++++++++++++ 7 files changed, 668 insertions(+), 3 deletions(-) diff --git a/Platform/ARM/JunoPkg/ArmJuno.dec b/Platform/ARM/JunoPkg/ArmJun= o.dec index b733480c3198d135df16ca024b5e85ff350e11c7..cd6710feb2faf0bd17b5ea39a21= dbe5406cd4ffd 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dec +++ b/Platform/ARM/JunoPkg/ArmJuno.dec @@ -53,3 +53,11 @@ [PcdsFixedAtBuild.common] gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxBase|0x2E000000|UINT64|0x00000025 gArmJunoTokenSpaceGuid.PcdArmMtlMailBoxSize|0x80|UINT32|0x00000026 =20 + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # + # Default value zero allows platform to enumerate maximum supported mode. + # + # For a list of mode numbers look in HdLcdArmJuno.c + gArmJunoTokenSpaceGuid.PcdArmHdLcdMaxMode|0|UINT32|0x00000017 + diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJun= o.dsc index fe860956a4dc497cac52be70bab3657246a08bd0..9027c5b0728a6941f850636b3bc= 315fd33b867fb 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.dsc +++ b/Platform/ARM/JunoPkg/ArmJuno.dsc @@ -50,6 +50,11 @@ [LibraryClasses.common] # SCMI Mailbox Transport Layer ArmMtl|Platform/ARM/JunoPkg/Library/ArmMtl/ArmMtl.inf =20 +!ifndef HEADLESS_PLATFORM + LcdPlatformLib|Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno= Lib.inf + LcdHwLib|ArmPlatformPkg/Library/HdLcd/HdLcd.inf +!endif + [LibraryClasses.common.SEC] PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf @@ -100,7 +105,15 @@ [PcdsFixedAtBuild.common] =20 # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit addr= ess space) gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + +!ifdef HEADLESS_PLATFORM gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 +!else + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000 + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0xFB000000 + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x04000000 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|TRUE +!endif =20 # Juno Dual-Cluster profile gArmPlatformTokenSpaceGuid.PcdCoreCount|6 @@ -142,6 +155,11 @@ [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000 =20 +!ifndef HEADLESS_PLATFORM + # ARM Juno HDLCD Base + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x7FF60000 +!endif + # # PLDA PCI Root Complex # @@ -314,6 +332,11 @@ [Components.common] MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf =20 +!ifndef HEADLESS_PLATFORM + # Graphic Output Protocol + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif + # # Juno platform driver # @@ -347,6 +370,12 @@ [Components.common] BdsLib|Platform/ARM/Library/BdsLib/BdsLib.inf } =20 + # SCMI Driver + ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + [Components.AARCH64] # # EBC diff --git a/Platform/ARM/JunoPkg/ArmJuno.fdf b/Platform/ARM/JunoPkg/ArmJun= o.fdf index ee9d0e7f4f6e6ac99ded6a14e88eb2c7854dd473..0b62760cbb3ff93490204ac636b= 41d5a867dfb80 100644 --- a/Platform/ARM/JunoPkg/ArmJuno.fdf +++ b/Platform/ARM/JunoPkg/ArmJuno.fdf @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# Copyright (c) 2013-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -163,6 +163,13 @@ [FV.FvMain] INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciD= eviceDxe.inf =20 +!ifndef HEADLESS_PLATFORM + # + # Graphics Output Protocol + # + INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif + # # PCI Support # @@ -223,6 +230,9 @@ [FV.FvMain] # after the device drivers (eg: Ethernet) to ensure we have support for = them. INF Platform/ARM/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf =20 + # SCMI Driver + INF ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf + !if $(ARCH) =3D=3D AARCH64 # # EBC diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf b/Platf= orm/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf index 2dd384daba3d6076ba4898a0251ebc91bc0beee2..f131035be684f22e9f4c0041775= 9b7845b29dcc6 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoLib.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2016, ARM Limited. All rights reserved. +# Copyright (c) 2013-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -57,6 +57,9 @@ [FixedPcd] gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize =20 + # Frame Buffer Memory + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 # # PL011 Serial Debug UART diff --git a/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.i= nf b/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..a10bff135abf154484d36c67083= b498846f24753 --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJunoLib.inf @@ -0,0 +1,40 @@ +#/** @file +# +# Component description file for HdLcdArmJunoLib module +# +# Copyright (c) 2013-2017, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D HdLcdArmJunoLib + FILE_GUID =3D 7B1D26F7-7B88-47ED-B193-DD3BDF319006 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + HdLcdArmJuno.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/JunoPkg/ArmJuno.dec + +[LibraryClasses] + BaseLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize + gArmJunoTokenSpaceGuid.PcdArmHdLcdMaxMode + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c b/Platfor= m/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c index afb2db0050c65b0d1b2b69c9038e168755c152c1..baa5221cb906ed5d077414475da= 006cf2e5cafc5 100644 --- a/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c +++ b/Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJunoMem.c @@ -21,8 +21,10 @@ =20 #include =20 +#define FRAME_BUFFER_DESCRIPTOR ((FixedPcdGet32 (PcdArmLcdDdrFrameBufferSi= ze) !=3D 0) ? 1 : 0) + // The total number of descriptors, including the final "end-of-table" des= criptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (16 + FRAME_BUFFER_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK @@ -151,6 +153,20 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D ARM_JUNO_SOC_PERIPHERALS_S= Z; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + // Frame Buffer Memory +#if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize) !=3D 0) + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmLcdDd= rFrameBufferBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmLcdDd= rFrameBufferBase); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmLcdDd= rFrameBufferSize); + // Map as Normal Non-Cacheable memory, so that we can use the accelerated + // SetMem/CopyMem routines that may use unaligned accesses or + // DC ZVA instructions. If mapped as device memory, these routine may ca= use + // alignment faults. + // NOTE: The attribute value is misleading, it indicates memory map type= as + // an un-cached, un-buffered but allows buffering and reordering. + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_UNCACHED_UNBUFFERED; +#endif + // DDR - 2GB VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); diff --git a/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c b/= Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c new file mode 100644 index 0000000000000000000000000000000000000000..72be0a39846fb0a78ebcf3248b6= c51377adf4f73 --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/HdLcdArmJunoLib/HdLcdArmJuno.c @@ -0,0 +1,559 @@ +/** @file + + Copyright (c) 2013-2017, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Display timings on Juno for 1920x1080. + On Juno due to instability of the PLLs, we set OSC + frequency to 138.5 MHz which is stable for most monitors. + Frequency 148.5MHz does not work with some monitors. + 148.5 MHz is set by SCP firmware by default. + +#define JUNO_HD_OSC_FREQUENCY 148500000 +*/ +#define JUNO_HD_OSC_FREQUENCY 138500000 +#define JUNO_HD_H_SYNC ( 32 - 1) +#define JUNO_HD_H_FRONT_PORCH ( 48 - 1) +#define JUNO_HD_H_BACK_PORCH ( 80 - 1) +#define JUNO_HD_V_SYNC ( 5 - 1) +#define JUNO_HD_V_FRONT_PORCH ( 3 - 1) +#define JUNO_HD_V_BACK_PORCH ( 23 - 1) + +/* SCMI defined clock device name and ID. This is not documented but + obtained using clock management protocol's CLOCK_ATTRIBUTES command. + + Generally we must discover clock device ID using clock name and then + set/get rate using CLOCK_RATE_SET/CLOCK_RATE_GET commands. However + because LcdGraphicsOutputDxe is a DXE driver, which gets initialized + at boot time, for faster boot, in release build we will directly use + this already known value as an argument to rate get/set functions. + + We expect these values not to change in future SCP firmware releases. + + DEBUG build however will probe SCP firmware and discover clock device + ID for HDLCD. +*/ +#define ARM_JUNO_CSS_CLK_NAME_HDLCD_0 "HDLCD_0" +#define ARM_JUNO_CSS_CLKID_HDLCD_0 3 + +typedef struct { + UINT32 Mode; + UINT32 OscFreq; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; + +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { + { + // Mode 0 : VGA : 640 x 480 x 24 bpp. + VGA, + VGA_OSC_FREQUENCY, + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} + }, + { + // Mode 1 : WVGA : 800 x 480 x 24 bpp. + WVGA, + WVGA_OSC_FREQUENCY, + {WVGA_H_RES_PIXELS, WVGA_H_SYNC, WVGA_H_BACK_PORCH, WVGA_H_FRONT_PORCH= }, + {WVGA_V_RES_PIXELS, WVGA_V_SYNC, WVGA_V_BACK_PORCH, WVGA_V_FRONT_PORCH} + }, + { + // Mode 2 : SVGA : 800 x 600 x 24 bpp. + SVGA, + SVGA_OSC_FREQUENCY, + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} + }, + { + // Mode 3 : QHD : 960 x 540 x 24 bpp. + QHD, + QHD_OSC_FREQUENCY, + {QHD_H_RES_PIXELS, QHD_H_SYNC, QHD_H_BACK_PORCH, QHD_H_FRONT_PORCH}, + {QHD_V_RES_PIXELS, QHD_V_SYNC, QHD_V_BACK_PORCH, QHD_V_FRONT_PORCH} + }, + { + // Mode 4 : WSVGA : 1024 x 600 x 24 bpp. + WSVGA, + WSVGA_OSC_FREQUENCY, + {WSVGA_H_RES_PIXELS, WSVGA_H_SYNC, WSVGA_H_BACK_PORCH, WSVGA_H_FRONT_P= ORCH}, + {WSVGA_V_RES_PIXELS, WSVGA_V_SYNC, WSVGA_V_BACK_PORCH, WSVGA_V_FRONT_P= ORCH} + }, + { + // Mode 5 : XGA : 1024 x 768 x 24 bpp. + XGA, + XGA_OSC_FREQUENCY, + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} + }, + { + // Mode 6 : HD : 1280 x 720 x 24 bpp. + HD720, + HD720_OSC_FREQUENCY, + {HD720_H_RES_PIXELS, HD720_H_SYNC, HD720_H_BACK_PORCH, HD720_H_FRONT_P= ORCH}, + {HD720_V_RES_PIXELS, HD720_V_SYNC, HD720_V_BACK_PORCH, HD720_V_FRONT_P= ORCH} + }, + { + // Mode 7 : WXGA : 1280 x 800 x 24 bpp. + WXGA, + WXGA_OSC_FREQUENCY, + {WXGA_H_RES_PIXELS, WXGA_H_SYNC, WXGA_H_BACK_PORCH, WXGA_H_FRONT_PORCH= }, + {WXGA_V_RES_PIXELS, WXGA_V_SYNC, WXGA_V_BACK_PORCH, WXGA_V_FRONT_PORCH} + }, + { + // Mode 8 : SXGA : 1280 x 1024 x 24 bpp. + SXGA, + SXGA_OSC_FREQUENCY, + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} + }, + { + // Mode 9 : WSXGA+ : 1680 x 1050 x 24 bpp. + WSXGA, + WSXGA_OSC_FREQUENCY, + {WSXGA_H_RES_PIXELS, WSXGA_H_SYNC, WSXGA_H_BACK_PORCH, WSXGA_H_FRONT_P= ORCH}, + {WSXGA_V_RES_PIXELS, WSXGA_V_SYNC, WSXGA_V_BACK_PORCH, WSXGA_V_FRONT_P= ORCH} + }, + { + // Mode 10 : HD : 1920 x 1080 x 24 bpp. + HD, + JUNO_HD_OSC_FREQUENCY, + {HD_H_RES_PIXELS, JUNO_HD_H_SYNC, JUNO_HD_H_BACK_PORCH, JUNO_HD_H_FRON= T_PORCH}, + {HD_V_RES_PIXELS, JUNO_HD_V_SYNC, JUNO_HD_V_BACK_PORCH, JUNO_HD_V_FRON= T_PORCH} + } +}; + +/* If PcdArmMaliDpMaxMode is 0, platform supports full range of modes + else platform supports modes from 0 to PcdArmHdLcdMaxMode - 1 +*/ +STATIC CONST UINT32 mMaxMode =3D ((FixedPcdGet32 (PcdArmHdLcdMaxMode) !=3D= 0) + ? FixedPcdGet32 (PcdArmHdLcdMaxMode) + : sizeof (mDisplayModes) / sizeof (DISP= LAY_MODE)); + +/** HDLCD platform specific initialization function. + + @param[in] Handle Handle to the LCD device instance. + + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN CONST EFI_HANDLE Handle + ) +{ + (VOID)Handle; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + // PixelBitMask and PixelBltOnly pixel formats are not supported. + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** Allocate VRAM memory in DRAM for the frame buffer + (unless it is reserved already). + + The allocated address can be used to set the frame buffer. + + @param[out] VramBaseAddress A pointer to the frame buffer address. + @param[out] VramSize A pointer to the size of the frame + buffer in bytes + + @retval EFI_SUCCESS Frame buffer memory allocated successful= ly. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + + // Set the VRAM size. + *VramSize =3D (UINTN)FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize); + + // Check if memory is already reserved for the frame buffer. +#if (FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase) !=3D 0) + *VramBaseAddress =3D + (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase); +#else + // If not already reserved, attempt to allocate the VRAM from the DRAM. + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (*VramSize), + VramBaseAddress + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "HdLcdArmJuno: Failed to allocate frame buffer.\n= ")); + ASSERT_EFI_ERROR (Status); + return Status; + } + + /* Mark the VRAM as write-combining. + The VRAM is inside the DRAM, which is cacheable. + */ + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + } +#endif + + return Status; +} + +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ +UINT32 +LcdPlatformGetMaxMode (VOID) +{ + return mMaxMode; +} + +#if !defined(MDEPKG_NDEBUG) +/** Probe Clock device ID of the HDLCD clock and current pixel clock frequ= ency. + NOTE: We will probe information only in DEBUG build. + + @param[in] ClockProtocol A pointer to SCMI clock protocol + interface instance. + @param[out] ClockId ID of the clock device + + @retval EFI_SUCCESS Clock ID of the HDLCD device returned + successfully. + @retval EFI_UNSUPPORTED SCMI clock management protocol unsupported. + @retval EFI_DEVICE_ERROR SCMI error. + @retval EFI_NOT_FOUND Not found valid clock device ID of the HDLCD. +**/ +STATIC +EFI_STATUS +ProbeHdLcdClock ( + IN SCMI_CLOCK_PROTOCOL *ClockProtocol, + OUT UINT32 *ClockId + ) +{ + EFI_STATUS Status; + UINT64 CurrentHdLcdFreq; + + UINT32 TotalClocks; + UINT32 ClockProtocolVersion; + BOOLEAN Enabled; + CHAR8 ClockName[SCMI_MAX_STR_LEN]; + BOOLEAN ClockFound =3D FALSE; + + UINT32 TotalRates =3D 0; + UINT32 ClockRateSize; + SCMI_CLOCK_RATE ClockRate; + SCMI_CLOCK_RATE_FORMAT ClockRateFormat; + + Status =3D ClockProtocol->GetVersion (ClockProtocol, &ClockProtocolVersi= on); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + DEBUG ((DEBUG_ERROR, "SCMI clock management protocol version =3D %x\n", + ClockProtocolVersion)); + + if (ClockProtocolVersion !=3D SCMI_CLOCK_PROTOCOL_VERSION) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status =3D ClockProtocol->GetTotalClocks (ClockProtocol, &TotalClocks); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_ERROR, "Total number of clocks supported by SCMI clock man= agement protocol =3D %d\n", + TotalClocks)); + + for (*ClockId =3D 0; *ClockId < TotalClocks; (*ClockId)++) { + Status =3D ClockProtocol->GetClockAttributes ( + ClockProtocol, + *ClockId, + &Enabled, + ClockName + ); + if (EFI_ERROR (Status)) { + // In current implementation of SCMI, some clocks are not accessible= to + // calling agents (in our case UEFI is an agent) which results in an + // EFI_DEVICE_ERROR error. A bug fix for this is in discussions and = will + // be fixed in future versions of the SCP firmware. Irrespective of = a fix + // we must iterate over each clock to see if it matches with HDLCD. + continue; + } + + if (AsciiStrnCmp ((CONST CHAR8*)ClockName, + (CONST CHAR8*)ARM_JUNO_CSS_CLK_NAME_HDLCD_0, + sizeof (ARM_JUNO_CSS_CLK_NAME_HDLCD_0)) =3D=3D 0) { + ClockFound =3D TRUE; + break; + } + } + + if (!ClockFound) { + return EFI_NOT_FOUND; + } + + ClockRateSize =3D sizeof (ClockRate); + Status =3D ClockProtocol->DescribeRates ( + ClockProtocol, + *ClockId, + &ClockRateFormat, + &TotalRates, + &ClockRateSize, + &ClockRate + ); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + Status =3D ClockProtocol->RateGet (ClockProtocol, *ClockId, &CurrentHdLc= dFreq); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + DEBUG ((DEBUG_ERROR, "Clock ID =3D %d Clock name =3D %a\n", *ClockId, Cl= ockName)); + DEBUG ((DEBUG_ERROR, "Minimum frequency =3D %uHz\n", ClockRate.Min)); + DEBUG ((DEBUG_ERROR, "Maximum frequency =3D %uHz\n", ClockRate.Max)); + DEBUG ((DEBUG_ERROR, "Clock rate step =3D %uHz\n", ClockRate.Step)); + + DEBUG ((DEBUG_ERROR, "HDLCD Current frequency =3D %uHz\n", CurrentHdLcdF= req)); + + return EFI_SUCCESS; +} +#endif + +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_NOT_FOUND Clock protocol instance not found. + @retval EFI_DEVICE_ERROR SCMI error. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval !(EFI_SUCCESS) Other errors. +*/ +EFI_STATUS +LcdPlatformSetMode ( + IN CONST UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + SCMI_CLOCK_PROTOCOL *ClockProtocol; + UINT32 ClockId; + + EFI_GUID ClockProtocolGuid =3D ARM_SCMI_CLOCK_PROTOCOL_GUID; + + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + // Display debug information in boot log. + DEBUG ((DEBUG_ERROR, "HDLCD Display controller:\n")); + + DEBUG ((DEBUG_ERROR, "Required frequency for resolution %dx%d =3D %uHz\n= ", + mDisplayModes[ModeNumber].Horizontal.Resolution, + mDisplayModes[ModeNumber].Vertical.Resolution, + mDisplayModes[ModeNumber].OscFreq)); + + Status =3D gBS->LocateProtocol ( + &ClockProtocolGuid, + NULL, + (VOID**)&ClockProtocol + ); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + +#if !defined(MDEPKG_NDEBUG) + /* Avoid probing clock device id in RELEASE build */ + Status =3D ProbeHdLcdClock (ClockProtocol, &ClockId); + if (EFI_ERROR (Status)) { + return Status; + } + + ASSERT (ClockId =3D=3D ARM_JUNO_CSS_CLKID_HDLCD_0); +#else + ClockId =3D ARM_JUNO_CSS_CLKID_HDLCD_0; +#endif + + // Set HDLCD clock required for the requested mode + Status =3D ClockProtocol->RateSet ( + ClockProtocol, + ClockId, + mDisplayModes[ModeNumber].OscFreq + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SCMI error: %r\n", Status)); + return Status; + } + +#if !defined(MDEPKG_NDEBUG) + UINT64 CurrentHdLcdFreq; + // Actual value set can differ from requested frequency so verify. + Status =3D ClockProtocol->RateGet ( + ClockProtocol, + ARM_JUNO_CSS_CLKID_HDLCD_0, + &CurrentHdLcdFreq + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SCMI Error: %r\n", Status)); + } else { + DEBUG ((DEBUG_ERROR, "Mode =3D %d, Requested frequency change =3D %uHz= , Actual changed frequency =3D %uHz\n", + ModeNumber, + mDisplayModes[ModeNumber].OscFreq, + CurrentHdLcdFreq + )); + } +#endif + + return Status; +} + +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformQueryMode ( + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info + ) +{ + if (ModeNumber >=3D mMaxMode ){ + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Info !=3D NULL); + + Info->Version =3D 0; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; + + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + + return EFI_SUCCESS; +} + +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS **Horizontal, + OUT CONST SCAN_TIMINGS **Vertical + ) +{ + if (ModeNumber >=3D mMaxMode ){ + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; + + return EFI_SUCCESS; +} + +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to value bits per pixel. + + @retval EFI_SUCCESS Bit per pixel information for the reques= ted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformGetBpp ( + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp + ) +{ + if (ModeNumber >=3D mMaxMode) { + // Check valid ModeNumber and Bpp. + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + + ASSERT (Bpp !=3D NULL); + + *Bpp =3D LCD_BITS_PER_PIXEL_24; + + return EFI_SUCCESS; +} --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel