From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967690090736.9999725050924; Fri, 22 Dec 2017 10:34:50 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 297B622198F78; Fri, 22 Dec 2017 10:29:45 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2A48D22225C15 for ; Fri, 22 Dec 2017 10:29:36 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYW007680; Fri, 22 Dec 2017 18:34:24 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:06 +0000 Message-Id: <20171222183418.8616-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 01/13] ArmPlatformPkg: Tidy Lcd code: Coding standard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Of specific note, some invalid include guards were fixed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h | 10 +- ArmPlatformPkg/Include/Library/LcdPlatformLib.h | 14 +- ArmPlatformPkg/Library/HdLcd/HdLcd.h | 21 += +- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c | 187 += ++++++++++--------- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 96 += ++++----- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 72 += +++---- 6 files changed, 212 insertions(+), 188 deletions(-) diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h index b66efd34561f655b74a5ecfad8a97281cdd5929d..2b001b107927fc75317ce39d370= 049d7740953a8 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2011, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -11,9 +11,8 @@ =20 **/ =20 -#ifndef __ARM_VE_GRAPHICS_DXE_H__ -#define __ARM_VE_GRAPHICS_DXE_H__ - +#ifndef LCD_GRAPHICS_OUTPUT_DXE_H_ +#define LCD_GRAPHICS_OUTPUT_DXE_H_ =20 #include =20 @@ -25,7 +24,6 @@ =20 #include =20 - // // Device structures // @@ -106,4 +104,4 @@ InitializeDisplay ( IN LCD_INSTANCE* Instance ); =20 -#endif /* __ARM_VE_GRAPHICS_DXE_H__ */ +#endif /* LCD_GRAPHICS_OUTPUT_DXE_H_ */ diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index b9bdf471e2d65dba7a0fcb0f7ecc352bd576b46b..b9316ec8de8425a83e2f627f5c2= 4821ff9a2f750 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2011, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD= License which accompanies this distribution. The full text of the license may be= found at @@ -11,8 +11,8 @@ =20 **/ =20 -#ifndef __LCDPLATFORMLIB_H -#define __LCDPLATFORMLIB_H +#ifndef LCD_PLATFORM_LIB_H_ +#define LCD_PLATFORM_LIB_H_ =20 #include =20 @@ -158,8 +158,9 @@ #define LCD_12BPP_444_BLUE_MASK 0x0000000F #define LCD_12BPP_444_RESERVED_MASK 0x0000F000 =20 - -// The enumeration indexes maps the PL111 LcdBpp values used in the LCD Co= ntrol Register +/** The enumeration indexes maps the PL111 LcdBpp values used in the LCD C= ontrol + Register +**/ typedef enum { LCD_BITS_PER_PIXEL_1 =3D 0, LCD_BITS_PER_PIXEL_2, @@ -171,7 +172,6 @@ typedef enum { LCD_BITS_PER_PIXEL_12_444 } LCD_BPP; =20 - EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -218,4 +218,4 @@ LcdPlatformGetBpp ( OUT LCD_BPP* Bpp ); =20 -#endif +#endif /* LCD_PLATFORM_LIB_H_ */ diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/ArmPlatformPkg/Library/= HdLcd/HdLcd.h index 6df97a9dfee60e9fda615cf3bea1b6a164a42333..861d3c398f7d6b9a171b4d8718c= 2816419d8e20a 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.h +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.h @@ -1,6 +1,6 @@ -/** @file HDLcd.h +/** @file =20 - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD= License @@ -12,13 +12,10 @@ =20 **/ =20 -#ifndef _HDLCD_H_ -#define _HDLCD_H_ +#ifndef HDLCD_H_ +#define HDLCD_H_ =20 -// // HDLCD Controller Register Offsets -// - #define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x000) #define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x010) #define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x014) @@ -44,10 +41,7 @@ #define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x248) #define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x24C) =20 - -// // HDLCD Values of registers -// =20 // HDLCD Interrupt mask, clear and status register #define HDLCD_DMA_END BIT0 /* DMA has finished read= ing a frame */ @@ -79,6 +73,11 @@ #define HDLCD_DATA_LOW 0 #define HDLCD_PXCLK_LOW 0 =20 +// Default polarities +#define HDLCD_DEFAULT_POLARITIES HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH = \ + | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW = \ + | HDLCD_VSYNC_HIGH + // Pixel Format #define HDLCD_LITTLE_ENDIAN (0 << 31) #define HDLCD_BIG_ENDIAN (1 << 31) @@ -86,4 +85,4 @@ // Number of bytes per pixel #define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) =20 -#endif /* _HDLCD_H_ */ +#endif /* HDLCD_H_ */ diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c index b721061fc1df5695092e8c71da97ae0b9af46b3f..948e5692c943cdf62a10f4e6290= 470d3ccd334f1 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD= License which accompanies this distribution. The full text of the license may be= found at @@ -9,7 +9,7 @@ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. =20 - **/ +**/ =20 #include #include @@ -22,12 +22,10 @@ =20 #include "LcdGraphicsOutputDxe.h" =20 -/********************************************************************** - * - * This file implements the Graphics Output protocol on ArmVersatileExpre= ss - * using the Lcd controller - * - **********************************************************************/ +/** This file implements the Graphics Output protocol on ArmVersatileExpre= ss + using the Lcd controller + +**/ =20 // // Global variables @@ -64,7 +62,10 @@ LCD_INSTANCE mLcdTemplate =3D { { { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, - { (UINT8) (sizeof(VENDOR_DEVICE_PATH)), (UINT8) ((sizeof(VENDOR_DE= VICE_PATH)) >> 8) }, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + }, }, // Hardware Device Path for Lcd EFI_CALLER_ID_GUID // Use the driver's GUID @@ -73,10 +74,13 @@ LCD_INSTANCE mLcdTemplate =3D { { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, - { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 } + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } } }, - (EFI_EVENT) NULL // ExitBootServicesEvent + (EFI_EVENT)NULL // ExitBootServicesEvent }; =20 EFI_STATUS @@ -86,7 +90,7 @@ LcdInstanceContructor ( { LCD_INSTANCE* Instance; =20 - Instance =3D AllocateCopyPool (sizeof(LCD_INSTANCE), &mLcdTemplate); + Instance =3D AllocateCopyPool (sizeof (LCD_INSTANCE), &mLcdTemplate); if (Instance =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } @@ -113,23 +117,23 @@ InitializeDisplay ( UINTN VramSize; =20 Status =3D LcdPlatformGetVram (&VramBaseAddress, &VramSize); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { return Status; } =20 // Setup the LCD Status =3D LcdInitialize (VramBaseAddress); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT_ERROR_LCD_SHUTDOWN; } =20 Status =3D LcdPlatformInitializeDisplay (Instance->Handle); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT_ERROR_LCD_SHUTDOWN; } =20 // Setup all the relevant mode information - Instance->Gop.Mode->SizeOfInfo =3D sizeof(EFI_GRAPHICS_OUTPUT_MODE_= INFORMATION); + Instance->Gop.Mode->SizeOfInfo =3D sizeof (EFI_GRAPHICS_OUTPUT_MODE= _INFORMATION); Instance->Gop.Mode->FrameBufferBase =3D VramBaseAddress; =20 // Set the flag before changing the mode, to avoid infinite loops @@ -139,7 +143,8 @@ InitializeDisplay ( goto EXIT; =20 EXIT_ERROR_LCD_SHUTDOWN: - DEBUG((DEBUG_ERROR, "InitializeDisplay: ERROR - Can not initialise the d= isplay. Exit Status=3D%r\n", Status)); + DEBUG ((DEBUG_ERROR, "InitializeDisplay: ERROR - Can not initialise the = display. Exit Status=3D%r\n", Status)); + LcdShutdown (); =20 EXIT: @@ -157,40 +162,44 @@ LcdGraphicsOutputDxeInitialize ( LCD_INSTANCE* Instance; =20 Status =3D LcdIdentify (); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT; } =20 Status =3D LcdInstanceContructor (&Instance); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT; } =20 // Install the Graphics Output Protocol and the Device Path - Status =3D gBS->InstallMultipleProtocolInterfaces( - &Instance->Handle, - &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, - &gEfiDevicePathProtocolGuid, &Instance->DevicePath, - NULL - ); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, + &Instance->Gop, + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, + NULL + ); =20 - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the = protocol. Exit Status=3D%r\n", Status)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsOutputDxeInitialize: Can not install = the protocol. Exit Status=3D%r\n", Status)); goto EXIT; } =20 // Register for an ExitBootServicesEvent - // When ExitBootServices starts, this function here will make sure that = the graphics driver will shut down properly, - // i.e. it will free up all allocated memory and perform any necessary h= ardware re-configuration. + // When ExitBootServices starts, this function will make sure that the + // graphics driver shuts down properly, i.e. it will free up all + // allocated memory and perform any necessary hardware re-configuration. Status =3D gBS->CreateEvent ( - EVT_SIGNAL_EXIT_BOOT_SERVICES, - TPL_NOTIFY, - LcdGraphicsExitBootServicesEvent, NULL, - &Instance->ExitBootServicesEvent - ); + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + LcdGraphicsExitBootServicesEvent, + NULL, + &Instance->ExitBootServicesEvent + ); =20 - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the = ExitBootServicesEvent handler. Exit Status=3D%r\n", Status)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsOutputDxeInitialize: Can not install = the ExitBootServicesEvent handler. Exit Status=3D%r\n", Status)); goto EXIT_ERROR_UNINSTALL_PROTOCOL; } =20 @@ -198,48 +207,46 @@ LcdGraphicsOutputDxeInitialize ( goto EXIT; =20 EXIT_ERROR_UNINSTALL_PROTOCOL: - /* The following function could return an error message, - * however, to get here something must have gone wrong already, - * so preserve the original error, i.e. don't change - * the Status variable, even it fails to uninstall the protocol. - */ + // The following function could return an error message, + // however, to get here something must have gone wrong already, + // so preserve the original error, i.e. don't change + // the Status variable, even it fails to uninstall the protocol. gBS->UninstallMultipleProtocolInterfaces ( - Instance->Handle, - &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, // Uninstall Graphics= Output protocol - &gEfiDevicePathProtocolGuid, &Instance->DevicePath, // Uninsta= ll device path - NULL - ); + Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, + &Instance->Gop, // Uninstall Graphics Output protocol + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, // Uninstall device path + NULL + ); =20 EXIT: return Status; - } =20 -/*************************************** - * This function should be called - * on Event: ExitBootServices - * to free up memory, stop the driver - * and uninstall the protocols - ***************************************/ +/** This function should be called + on Event: ExitBootServices + to free up memory, stop the driver + and uninstall the protocols +**/ VOID LcdGraphicsExitBootServicesEvent ( IN EFI_EVENT Event, IN VOID *Context ) { - // By default, this PCD is FALSE. But if a platform starts a predefined = OS that - // does not use a framebuffer then we might want to disable the display = controller - // to avoid to display corrupted information on the screen. + // By default, this PCD is FALSE. But if a platform starts a predefined = OS + // that does not use a framebuffer then we might want to disable the dis= play + // controller to avoid to display corrupted information on the screen. if (FeaturePcdGet (PcdGopDisableOnExitBootServices)) { // Turn-off the Display controller LcdShutdown (); } } =20 -/*************************************** - * GraphicsOutput Protocol function, mapping to - * EFI_GRAPHICS_OUTPUT_PROTOCOL.QueryMode - ***************************************/ +/** GraphicsOutput Protocol function, mapping to + EFI_GRAPHICS_OUTPUT_PROTOCOL.QueryMode +**/ EFI_STATUS EFIAPI LcdGraphicsQueryMode ( @@ -252,19 +259,22 @@ LcdGraphicsQueryMode ( EFI_STATUS Status =3D EFI_SUCCESS; LCD_INSTANCE *Instance; =20 - Instance =3D LCD_INSTANCE_FROM_GOP_THIS(This); + Instance =3D LCD_INSTANCE_FROM_GOP_THIS (This); =20 // Setup the hardware if not already done - if( !mDisplayInitialized ) { - Status =3D InitializeDisplay(Instance); - if (EFI_ERROR(Status)) { + if (!mDisplayInitialized) { + Status =3D InitializeDisplay (Instance); + if (EFI_ERROR (Status)) { goto EXIT; } } =20 // Error checking - if ( (This =3D=3D NULL) || (Info =3D=3D NULL) || (SizeOfInfo =3D=3D NULL= ) || (ModeNumber >=3D This->Mode->MaxMode) ) { - DEBUG((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d = : Invalid Parameter.\n", ModeNumber )); + if ((This =3D=3D NULL) + || (Info =3D=3D NULL) + || (SizeOfInfo =3D=3D NULL) + || (ModeNumber >=3D This->Mode->MaxMode)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d= : Invalid Parameter.\n", ModeNumber)); Status =3D EFI_INVALID_PARAMETER; goto EXIT; } @@ -275,21 +285,20 @@ LcdGraphicsQueryMode ( goto EXIT; } =20 - *SizeOfInfo =3D sizeof( EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + *SizeOfInfo =3D sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); =20 - Status =3D LcdPlatformQueryMode (ModeNumber,*Info); - if (EFI_ERROR(Status)) { - FreePool(*Info); + Status =3D LcdPlatformQueryMode (ModeNumber, *Info); + if (EFI_ERROR (Status)) { + FreePool (*Info); } =20 EXIT: return Status; } =20 -/*************************************** - * GraphicsOutput Protocol function, mapping to - * EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode - ***************************************/ +/** GraphicsOutput Protocol function, mapping to + EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode +**/ EFI_STATUS EFIAPI LcdGraphicsSetMode ( @@ -305,47 +314,48 @@ LcdGraphicsSetMode ( Instance =3D LCD_INSTANCE_FROM_GOP_THIS (This); =20 // Setup the hardware if not already done - if(!mDisplayInitialized) { + if (!mDisplayInitialized) { Status =3D InitializeDisplay (Instance); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT; } } =20 // Check if this mode is supported - if( ModeNumber >=3D This->Mode->MaxMode ) { - DEBUG((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Unsupported mode numb= er %d .\n", ModeNumber )); + if (ModeNumber >=3D This->Mode->MaxMode) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Unsupported mode num= ber %d .\n", ModeNumber)); Status =3D EFI_UNSUPPORTED; goto EXIT; } =20 // Set the oscillator frequency to support the new mode Status =3D LcdPlatformSetMode (ModeNumber); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { Status =3D EFI_DEVICE_ERROR; goto EXIT; } =20 // Update the UEFI mode information This->Mode->Mode =3D ModeNumber; - LcdPlatformQueryMode (ModeNumber,&Instance->ModeInfo); - Status =3D LcdPlatformGetBpp(ModeNumber, &Bpp); - if (EFI_ERROR(Status)) { + LcdPlatformQueryMode (ModeNumber, &Instance->ModeInfo); + Status =3D LcdPlatformGetBpp (ModeNumber, &Bpp); + if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Couldn't get bytes p= er pixel, status: %r\n", Status)); goto EXIT; } This->Mode->FrameBufferSize =3D Instance->ModeInfo.VerticalResolution - * Instance->ModeInfo.PixelsPerScanLine - * GetBytesPerPixel(Bpp); + * Instance->ModeInfo.PixelsPerScanLine + * GetBytesPerPixel (Bpp); =20 // Set the hardware to the new mode Status =3D LcdSetMode (ModeNumber); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { Status =3D EFI_DEVICE_ERROR; goto EXIT; } =20 - // The UEFI spec requires that we now clear the visible portions of the = output display to black. + // The UEFI spec requires that we now clear the visible portions of the + // output display to black. =20 // Set the fill colour to black SetMem (&FillColour, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0); @@ -361,7 +371,8 @@ LcdGraphicsSetMode ( 0, This->Mode->Info->HorizontalResolution, This->Mode->Info->VerticalResolution, - 0); + 0 + ); =20 EXIT: return Status; @@ -372,7 +383,7 @@ GetBytesPerPixel ( IN LCD_BPP Bpp ) { - switch(Bpp) { + switch (Bpp) { case LCD_BITS_PER_PIXEL_24: return 4; =20 diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index 24efb68f23e3393a96fc760732d978b6346a2807..f1fffb1e83173f03f044fc0f4a5= ad5c0b864695b 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -1,6 +1,6 @@ -/** @file Lcd.c +/** @file =20 - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -21,12 +21,9 @@ =20 #include "HdLcd.h" =20 -/********************************************************************** - * - * This file contains all the bits of the Lcd that are - * platform independent. - * - **********************************************************************/ +/** This file contains all the bits of the Lcd that are + platform independent. +**/ =20 STATIC UINTN @@ -34,7 +31,7 @@ GetBytesPerPixel ( IN LCD_BPP Bpp ) { - switch(Bpp) { + switch (Bpp) { case LCD_BITS_PER_PIXEL_24: return 4; =20 @@ -60,21 +57,27 @@ LcdInitialize ( ) { // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); =20 // Disable all interrupts - MmioWrite32(HDLCD_REG_INT_MASK, 0); + MmioWrite32 (HDLCD_REG_INT_MASK, 0); =20 // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); + MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress); =20 // Setup various registers that never change - MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); - MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | = HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH); - MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_P= ER_PIXEL); - MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); - MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); - MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); + MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); + + MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES); + + MmioWrite32 ( + HDLCD_REG_PIXEL_FORMAT, + HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL + ); + + MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); + MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); + MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); =20 return EFI_SUCCESS; } @@ -96,63 +99,66 @@ LcdSetMode ( UINT32 BytesPerPixel; LCD_BPP LcdBpp; =20 - // Set the video mode timings and other relevant information - Status =3D LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); + Status =3D LcdPlatformGetTimings ( + ModeNumber, + &HRes, + &HSync, + &HBackPorch, + &HFrontPorch, + &VRes, + &VSync, + &VBackPorch, + &VFrontPorch + ); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 - Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); + Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 - BytesPerPixel =3D GetBytesPerPixel(LcdBpp); + BytesPerPixel =3D GetBytesPerPixel (LcdBpp); =20 // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); =20 // Update the frame buffer information with the new settings - MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1); + MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); + MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); + MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1); =20 // Set the vertical timing information - MmioWrite32(HDLCD_REG_V_SYNC, VSync); - MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch); - MmioWrite32(HDLCD_REG_V_DATA, VRes - 1); - MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch); + MmioWrite32 (HDLCD_REG_V_SYNC, VSync); + MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch); + MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1); + MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch); =20 // Set the horizontal timing information - MmioWrite32(HDLCD_REG_H_SYNC, HSync); - MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch); - MmioWrite32(HDLCD_REG_H_DATA, HRes - 1); - MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch); + MmioWrite32 (HDLCD_REG_H_SYNC, HSync); + MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch); + MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1); + MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch); =20 // Enable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE); + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE); =20 return EFI_SUCCESS; } =20 VOID -LcdShutdown ( - VOID - ) +LcdShutdown (VOID) { // Disable the controller MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); } =20 EFI_STATUS -LcdIdentify ( - VOID - ) +LcdIdentify (VOID) { return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index 9b4a02045ab7ca170e0d4362ee0e2bcf1d275bdb..19a5f3c58c63173f6528d7c1eed= f51053dbeaf7e 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -1,6 +1,6 @@ -/** @file PL111Lcd.c +/** @file =20 - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -19,17 +19,12 @@ =20 #include "PL111Lcd.h" =20 -/********************************************************************** - * - * This file contains all the bits of the PL111 that are - * platform independent. - * - **********************************************************************/ +/** This file contains all the bits of the PL111 that are + platform independent. =20 +**/ EFI_STATUS -LcdIdentify ( - VOID - ) +LcdIdentify (VOID) { DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", PL111_REG_CLCD_PERIPH_ID_0)); @@ -54,11 +49,11 @@ LcdInitialize ( ) { // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); - MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buff= er + MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress); + MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buf= fer =20 // Disable all interrupts from the PL111 - MmioWrite32(PL111_REG_LCD_IMSC, 0); + MmioWrite32 (PL111_REG_LCD_IMSC, 0); =20 return EFI_SUCCESS; } @@ -81,45 +76,60 @@ LcdSetMode ( LCD_BPP LcdBpp; =20 // Set the video mode timings and other relevant information - Status =3D LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); + Status =3D LcdPlatformGetTimings ( + ModeNumber, + &HRes, + &HSync, + &HBackPorch, + &HFrontPorch, + &VRes, + &VSync, + &VBackPorch, + &VFrontPorch + ); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 - Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); + Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 // Disable the CLCD_LcdEn bit - LcdControl =3D MmioRead32( PL111_REG_LCD_CONTROL); - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); + LcdControl =3D MmioRead32 (PL111_REG_LCD_CONTROL); + MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1); =20 // Set Timings - MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPo= rch, HSync, HRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPo= rch, VSync, VRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); + MmioWrite32 ( + PL111_REG_LCD_TIMING_0, + HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes) + ); + + MmioWrite32 ( + PL111_REG_LCD_TIMING_1, + VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes) + ); + + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes)); MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); =20 // PL111_REG_LCD_CONTROL - LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CT= RL_LCD_TFT | PL111_CTRL_BGR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) + | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 // Turn on power to the LCD Panel LcdControl |=3D PL111_CTRL_LCD_PWR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 return EFI_SUCCESS; } =20 VOID -LcdShutdown ( - VOID - ) +LcdShutdown (VOID) { // Disable the controller MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967682000871.7962004788452; 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receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:07 +0000 Message-Id: <20171222183418.8616-3-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 02/13] ArmPlatformPkg: Tidy Lcd code: Updated comments X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change some comments are modified and a few new comments are added. This is to prevent mixing formatting changes with functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Include/Library/LcdPlatformLib.h | 92 ++= +++++++++++++----- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c | 20 ++= --- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 29 ++= +++- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 24 ++= ++- 4 files changed, 127 insertions(+), 38 deletions(-) diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index b9316ec8de8425a83e2f627f5c24821ff9a2f750..2a70307031fc21c8fb0d655d358= ca9a102a95920 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -18,9 +18,7 @@ =20 #define LCD_VRAM_SIZE SIZE_8MB =20 -// // Modes definitions -// #define VGA 0 #define SVGA 1 #define XGA 2 @@ -29,9 +27,7 @@ #define UXGA 5 #define HD 6 =20 -// // VGA Mode: 640 x 480 -// #define VGA_H_RES_PIXELS 640 #define VGA_V_RES_PIXELS 480 #define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */ @@ -44,9 +40,7 @@ #define VGA_V_FRONT_PORCH ( 3 - 1) #define VGA_V_BACK_PORCH ( 13 - 1) =20 -// // SVGA Mode: 800 x 600 -// #define SVGA_H_RES_PIXELS 800 #define SVGA_V_RES_PIXELS 600 #define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */ @@ -59,9 +53,7 @@ #define SVGA_V_FRONT_PORCH ( 3 - 1) #define SVGA_V_BACK_PORCH ( 17 - 1) =20 -// // XGA Mode: 1024 x 768 -// #define XGA_H_RES_PIXELS 1024 #define XGA_V_RES_PIXELS 768 #define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */ @@ -74,9 +66,7 @@ #define XGA_V_FRONT_PORCH ( 3 - 1) #define XGA_V_BACK_PORCH ( 23 - 1) =20 -// // SXGA Mode: 1280 x 1024 -// #define SXGA_H_RES_PIXELS 1280 #define SXGA_V_RES_PIXELS 1024 #define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */ @@ -89,9 +79,7 @@ #define SXGA_V_FRONT_PORCH ( 3 - 1) #define SXGA_V_BACK_PORCH ( 29 - 1) =20 -// // WSXGA+ Mode: 1680 x 1050 -// #define WSXGA_H_RES_PIXELS 1680 #define WSXGA_V_RES_PIXELS 1050 #define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */ @@ -104,9 +92,7 @@ #define WSXGA_V_FRONT_PORCH ( 4 - 1) #define WSXGA_V_BACK_PORCH ( 41 - 1) =20 -// // UXGA Mode: 1600 x 1200 -// #define UXGA_H_RES_PIXELS 1600 #define UXGA_V_RES_PIXELS 1200 #define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */ @@ -119,9 +105,7 @@ #define UXGA_V_FRONT_PORCH ( 3 - 1) #define UXGA_V_BACK_PORCH ( 38 - 1) =20 -// // HD Mode: 1920 x 1080 -// #define HD_H_RES_PIXELS 1920 #define HD_V_RES_PIXELS 1080 #define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */ @@ -134,10 +118,7 @@ #define HD_V_FRONT_PORCH ( 3 - 1) #define HD_V_BACK_PORCH ( 32 - 1) =20 -// // Colour Masks -// - #define LCD_24BPP_RED_MASK 0x00FF0000 #define LCD_24BPP_GREEN_MASK 0x0000FF00 #define LCD_24BPP_BLUE_MASK 0x000000FF @@ -158,7 +139,7 @@ #define LCD_12BPP_444_BLUE_MASK 0x0000000F #define LCD_12BPP_444_RESERVED_MASK 0x0000F000 =20 -/** The enumeration indexes maps the PL111 LcdBpp values used in the LCD C= ontrol +/** The enumeration maps the PL111 LcdBpp values used in the LCD Control Register **/ typedef enum { @@ -172,33 +153,94 @@ typedef enum { LCD_BITS_PER_PIXEL_12_444 } LCD_BPP; =20 +/** Platform related initialization function. + + @param[in] Handle Handle to the LCD device instance. + + @retval EFI_SUCCESS Plaform library initialized successfully. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle ); =20 +/** Allocate VRAM memory in DRAM for the frame buffer + (unless it is reserved already). + + The allocated address can be used to set the frame buffer. + + @param[out] VramBaseAddress A pointer to the frame buffer address. + @param[out] VramSize A pointer to the size of the frame + buffer in bytes + + @retval EFI_SUCCESS Frame buffer memory allocated successfu= lly. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, OUT UINTN* VramSize ); =20 +/** Return total number of modes supported. + + Note: Valid mode numbers are 0 to MaxMode - 1 + See Section 12.9 of the UEFI Specification 2.7 + + @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode ( VOID ); =20 +/** Set the requested display mode. + + @param[in] ModeNumber Mode Number. + + @retval EFI_SUCCESS Mode set successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. + @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber ); =20 +/** Return information for the requested mode number. + + @param[in] ModeNumber Mode Number. + @param[out] Info Pointer for returned mode information + (on success). + + @retval EFI_SUCCESS Mode information for the requested mode + returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info ); =20 +/** Return display timing information for the requested mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] HRes Pointer to horizontal resolution. + @param[out] HSync Pointer to horizontal sync width. + @param[out] HBackPorch Pointer to horizontal back porch. + @param[out] HFrontPorch Pointer to horizontal front porch. + @param[out] VRes Pointer to vertical resolution. + @param[out] VSync Pointer to vertical sync width. + @param[out] VBackPorch Pointer to vertical back porch. + @param[out] VFrontPorch Pointer to vertical front porch. + + @retval EFI_SUCCESS Display timing information for the reque= sted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -212,6 +254,16 @@ LcdPlatformGetTimings ( OUT UINT32* VFrontPorch ); =20 +/** Return bits per pixel information for a mode number. + + @param[in] ModeNumber Mode Number. + + @param[out] Bpp Pointer to value bits per pixel. + + @retval EFI_SUCCESS Bit per pixel information for the reques= ted + mode returned successfully. + @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c index 948e5692c943cdf62a10f4e6290470d3ccd334f1..72895a751784413d50e2cbf4550= 091b896a4f1d3 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -1,13 +1,14 @@ /** @file + This file implements the Graphics Output protocol for Arm platforms =20 - Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD= License - which accompanies this distribution. The full text of the license may be= found at - http://opensource.org/licenses/bsd-license.php + Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php =20 - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -22,11 +23,6 @@ =20 #include "LcdGraphicsOutputDxe.h" =20 -/** This file implements the Graphics Output protocol on ArmVersatileExpre= ss - using the Lcd controller - -**/ - // // Global variables // diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index f1fffb1e83173f03f044fc0f4a5ad5c0b864695b..079fe64ccf30dc21c357298511a= eb660faa67e4a 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -1,4 +1,5 @@ /** @file + This file contains the platform independent parts of HdLcd =20 Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 @@ -21,10 +22,6 @@ =20 #include "HdLcd.h" =20 -/** This file contains all the bits of the Lcd that are - platform independent. -**/ - STATIC UINTN GetBytesPerPixel ( @@ -51,6 +48,12 @@ GetBytesPerPixel ( } } =20 +/** Initialize display. + + @param[in] VramBaseAddress Address of the frame buffer. + + @retval EFI_SUCCESS Display initialization successful. +**/ EFI_STATUS LcdInitialize ( IN EFI_PHYSICAL_ADDRESS VramBaseAddress @@ -82,6 +85,14 @@ LcdInitialize ( return EFI_SUCCESS; } =20 +/** Set requested mode of the display. + + @param[in] ModeNumber Display mode number. + + @retval EFI_SUCCESS Display mode set successfully. + @retval EFI_DEVICE_ERROR Reurns an error if display timing + information is not available. +**/ EFI_STATUS LcdSetMode ( IN UINT32 ModeNumber @@ -150,6 +161,8 @@ LcdSetMode ( return EFI_SUCCESS; } =20 +/** De-initializes the display. +**/ VOID LcdShutdown (VOID) { @@ -157,6 +170,14 @@ LcdShutdown (VOID) MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); } =20 +/** Check for presence of HDLCD. + + @retval EFI_SUCCESS Returns success if platform implements a = HDLCD + controller. + + @retval EFI_NOT_FOUND HDLCD display controller not found on the + platform +**/ EFI_STATUS LcdIdentify (VOID) { diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index 19a5f3c58c63173f6528d7c1eedf51053dbeaf7e..b1b7d0dd19076e3afba0d144af8= d95b9f350006c 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -1,4 +1,5 @@ /** @file + This file contains the platform independent parts of PL111Lcd =20 Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 @@ -19,9 +20,12 @@ =20 #include "PL111Lcd.h" =20 -/** This file contains all the bits of the PL111 that are - platform independent. +/** Check for presence of PL111. =20 + @retval EFI_SUCCESS Returns success if platform implements a + PL111 controller. + + @retval EFI_NOT_FOUND PL111 display controller not found the plaf= orm. **/ EFI_STATUS LcdIdentify (VOID) @@ -43,6 +47,12 @@ LcdIdentify (VOID) return EFI_NOT_FOUND; } =20 +/** Initialize display. + + @param[in] VramBaseAddress Address of the frame buffer. + + @retval EFI_SUCCESS Initialization of display successful. +**/ EFI_STATUS LcdInitialize ( IN EFI_PHYSICAL_ADDRESS VramBaseAddress @@ -58,6 +68,14 @@ LcdInitialize ( return EFI_SUCCESS; } =20 +/** Set requested mode of the display. + + @param[in] ModeNumbe Display mode number. + + @retval EFI_SUCCESS Display set mode successfuly. + @retval EFI_DEVICE_ERROR It returns an error if display timing + information is not available. +**/ EFI_STATUS LcdSetMode ( IN UINT32 ModeNumber @@ -128,6 +146,8 @@ LcdSetMode ( return EFI_SUCCESS; } =20 +/** De-initializes the display. +*/ VOID LcdShutdown (VOID) { --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151396767716088.30743516219809; Fri, 22 Dec 2017 10:34:37 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 97DF322198F4D; Fri, 22 Dec 2017 10:29:40 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39F6422225C19 for ; Fri, 22 Dec 2017 10:29:36 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYY007680; Fri, 22 Dec 2017 18:34:24 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:08 +0000 Message-Id: <20171222183418.8616-4-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 03/13] ArmPlatformPkg: PL111 and HDLCD: add const qualifier X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds CONST qualifiers (mainly to arguments of functions) in PL111 and HdLcd libraries. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 4 ++-- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index 079fe64ccf30dc21c357298511aeb660faa67e4a..a1eeabfefe7d32e6182371e5b13= 1ac5df0dd4dd7 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -56,7 +56,7 @@ GetBytesPerPixel ( **/ EFI_STATUS LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress + IN CONST EFI_PHYSICAL_ADDRESS VramBaseAddress ) { // Disable the controller @@ -95,7 +95,7 @@ LcdInitialize ( **/ EFI_STATUS LcdSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index b1b7d0dd19076e3afba0d144af8d95b9f350006c..53b402f711ff10d70feba386711= 71c027a98b4ba 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -55,7 +55,7 @@ LcdIdentify (VOID) **/ EFI_STATUS LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress + IN CONST EFI_PHYSICAL_ADDRESS VramBaseAddress ) { // Define start of the VRAM. This never changes for any graphics mode @@ -78,7 +78,7 @@ LcdInitialize ( **/ EFI_STATUS LcdSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967672642790.88224207663; Fri, 22 Dec 2017 10:34:32 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0312C22225C1E; Fri, 22 Dec 2017 10:29:40 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2C01D21A0292D for ; Fri, 22 Dec 2017 10:29:36 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYZ007680; Fri, 22 Dec 2017 18:34:24 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:09 +0000 Message-Id: <20171222183418.8616-5-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 04/13] ArmPlatformPkg: HDLCD and PL111: Update debug ASSERTS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change moves some ASSERTs in error handling code to improve efficiency in DEBUG build. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 11 ++++------- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 8 ++++---- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index a1eeabfefe7d32e6182371e5b131ac5df0dd4dd7..d71b6020dc0c4b91e74d16e96b0= 6a60601b9628a 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -122,15 +122,15 @@ LcdSetMode ( &VBackPorch, &VFrontPorch ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT (FALSE); + return Status; } =20 Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT (FALSE); + return Status; } =20 BytesPerPixel =3D GetBytesPerPixel (LcdBpp); @@ -174,9 +174,6 @@ LcdShutdown (VOID) =20 @retval EFI_SUCCESS Returns success if platform implements a = HDLCD controller. - - @retval EFI_NOT_FOUND HDLCD display controller not found on the - platform **/ EFI_STATUS LcdIdentify (VOID) diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index 53b402f711ff10d70feba38671171c027a98b4ba..267c972bf795997f1df88b82acb= aea5f75a7a00e 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -105,15 +105,15 @@ LcdSetMode ( &VBackPorch, &VFrontPorch ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT (FALSE); + return Status; } =20 Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT (FALSE); + return Status; } =20 // Disable the CLCD_LcdEn bit --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967674799792.3410344794762; Fri, 22 Dec 2017 10:34:34 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4E8E122198F4A; Fri, 22 Dec 2017 10:29:40 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3701622225C18 for ; Fri, 22 Dec 2017 10:29:36 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYa007680; Fri, 22 Dec 2017 18:34:24 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:10 +0000 Message-Id: <20171222183418.8616-6-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 05/13] ArmPlatformPkg: PL111Lcd: Replace magic number with macro X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Minor code change, replaces magic number with macro in LCD disable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index 267c972bf795997f1df88b82acbaea5f75a7a00e..b236cbfcfffadd6fa7610dcae5c= 5bc748aac0f69 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -117,8 +117,7 @@ LcdSetMode ( } =20 // Disable the CLCD_LcdEn bit - LcdControl =3D MmioRead32 (PL111_REG_LCD_CONTROL); - MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1); + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); =20 // Set Timings MmioWrite32 ( --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967679483405.6039873959322; Fri, 22 Dec 2017 10:34:39 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DE23422198F62; Fri, 22 Dec 2017 10:29:40 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48EDB22225C1B for ; Fri, 22 Dec 2017 10:29:36 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYb007680; Fri, 22 Dec 2017 18:34:25 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:11 +0000 Message-Id: <20171222183418.8616-7-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 06/13] ArmPlatformPkg: Implement LcdIdentify function for HDLCD GOP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak LcdIdentify function does not currently check presence of HDLCD controller. Implement this functionality by reading HDLCD_REG_VERSION and checking against the PRODUCT_ID field to detect presence of HDLCD controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- ArmPlatformPkg/Library/HdLcd/HdLcd.h | 2 ++ ArmPlatformPkg/Library/HdLcd/HdLcd.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/ArmPlatformPkg/Library/= HdLcd/HdLcd.h index 861d3c398f7d6b9a171b4d8718c2816419d8e20a..b69fc3436a190b7b20df63fac42= e4bef2b522942 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.h +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.h @@ -85,4 +85,6 @@ // Number of bytes per pixel #define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) =20 +#define HDLCD_PRODUCT_ID 0x1CDC + #endif /* HDLCD_H_ */ diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index d71b6020dc0c4b91e74d16e96b06a60601b9628a..b2779af041fae58d712270002cc= 7d6d277360311 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -174,9 +174,15 @@ LcdShutdown (VOID) =20 @retval EFI_SUCCESS Returns success if platform implements a = HDLCD controller. + @retval EFI_NOT_FOUND HDLCD display controller not found on the + platform. **/ EFI_STATUS LcdIdentify (VOID) { - return EFI_SUCCESS; + if ((MmioRead32 (HDLCD_REG_VERSION) >> 16) =3D=3D HDLCD_PRODUCT_ID) { + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967687659143.45091796858298; Fri, 22 Dec 2017 10:34:47 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE5E022198F73; Fri, 22 Dec 2017 10:29:44 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3DD9922225C1A for ; Fri, 22 Dec 2017 10:29:36 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYc007680; Fri, 22 Dec 2017 18:34:25 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:12 +0000 Message-Id: <20171222183418.8616-8-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 07/13] ArmPlatformPkg: Redefine LcdPlatformGetTimings function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak The LcdPlatformGetTimings interface function takes similar sets of multiple parameters for horizontal and vertical timings which can be aggregated in a common data type. This change defines a structure SCAN_TIMINGS for this which can be used to describe both horizontal and vertical scan timings, and accordingly redefines the LcdPlatformGetTiming interface, greatly reducing the amount of data passed about. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- ArmPlatformPkg/Include/Library/LcdPlatformLib.h | 31 ++++++----- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 56 +++++++++----------- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 49 +++++++++-------- 3 files changed, 68 insertions(+), 68 deletions(-) diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index 2a70307031fc21c8fb0d655d358ca9a102a95920..0943f28a19133e7bc558f9d529b= b8ac8f66ba3fd 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -153,6 +153,14 @@ typedef enum { LCD_BITS_PER_PIXEL_12_444 } LCD_BPP; =20 +// Display timing settings. +typedef struct { + UINT32 Resolution; + UINT32 Sync; + UINT32 BackPorch; + UINT32 FrontPorch; +} SCAN_TIMINGS; + /** Platform related initialization function. =20 @param[in] Handle Handle to the LCD device instance. @@ -228,14 +236,11 @@ LcdPlatformQueryMode ( =20 @param[in] ModeNumber Mode Number. =20 - @param[out] HRes Pointer to horizontal resolution. - @param[out] HSync Pointer to horizontal sync width. - @param[out] HBackPorch Pointer to horizontal back porch. - @param[out] HFrontPorch Pointer to horizontal front porch. - @param[out] VRes Pointer to vertical resolution. - @param[out] VSync Pointer to vertical sync width. - @param[out] VBackPorch Pointer to vertical back porch. - @param[out] VFrontPorch Pointer to vertical front porch. + @param[out] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[out] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + =20 @retval EFI_SUCCESS Display timing information for the reque= sted mode returned successfully. @@ -244,14 +249,8 @@ LcdPlatformQueryMode ( EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + OUT CONST SCAN_TIMINGS **Horizontal, + OUT CONST SCAN_TIMINGS **Vertical ); =20 /** Return bits per pixel information for a mode number. diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index b2779af041fae58d712270002cc7d6d277360311..1fc04c2d14d8185370454be459a= 23bdec41f6602 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -98,35 +98,26 @@ LcdSetMode ( IN CONST UINT32 ModeNumber ) { - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 BytesPerPixel; - LCD_BPP LcdBpp; + EFI_STATUS Status; + CONST SCAN_TIMINGS *Horizontal; + CONST SCAN_TIMINGS *Vertical; + UINT32 BytesPerPixel; + LCD_BPP LcdBpp; =20 // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( ModeNumber, - &HRes, - &HSync, - &HBackPorch, - &HFrontPorch, - &VRes, - &VSync, - &VBackPorch, - &VFrontPorch + &Horizontal, + &Vertical ); if (EFI_ERROR (Status)) { ASSERT (FALSE); return Status; } =20 + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); if (EFI_ERROR (Status)) { ASSERT (FALSE); @@ -139,21 +130,26 @@ LcdSetMode ( MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); =20 // Update the frame buffer information with the new settings - MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); - MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); - MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1); + MmioWrite32 ( + HDLCD_REG_FB_LINE_LENGTH, + Horizontal->Resolution * BytesPerPixel + ); + + MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, Horizontal->Resolution * BytesPerP= ixel); + + MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1); =20 // Set the vertical timing information - MmioWrite32 (HDLCD_REG_V_SYNC, VSync); - MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch); - MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1); - MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch); + MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync); + MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch); + MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1); + MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch); =20 // Set the horizontal timing information - MmioWrite32 (HDLCD_REG_H_SYNC, HSync); - MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch); - MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1); - MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch); + MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync); + MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch); + MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1); + MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch); =20 // Enable the controller MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE); diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index b236cbfcfffadd6fa7610dcae5c5bc748aac0f69..d1aba083fdc2ee4a7c25294955c= 4413465dca1e8 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -81,35 +81,26 @@ LcdSetMode ( IN CONST UINT32 ModeNumber ) { - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 LcdControl; - LCD_BPP LcdBpp; + EFI_STATUS Status; + CONST SCAN_TIMINGS *Horizontal; + CONST SCAN_TIMINGS *Vertical; + UINT32 LcdControl; + LCD_BPP LcdBpp; =20 // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( ModeNumber, - &HRes, - &HSync, - &HBackPorch, - &HFrontPorch, - &VRes, - &VSync, - &VBackPorch, - &VFrontPorch + &Horizontal, + &Vertical ); if (EFI_ERROR (Status)) { ASSERT (FALSE); return Status; } =20 + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); if (EFI_ERROR (Status)) { ASSERT (FALSE); @@ -122,15 +113,29 @@ LcdSetMode ( // Set Timings MmioWrite32 ( PL111_REG_LCD_TIMING_0, - HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes) + HOR_AXIS_PANEL ( + Horizontal->BackPorch, + Horizontal->FrontPorch, + Horizontal->Sync, + Horizontal->Resolution + ) ); =20 MmioWrite32 ( PL111_REG_LCD_TIMING_1, - VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes) + VER_AXIS_PANEL ( + Vertical->BackPorch, + Vertical->FrontPorch, + Vertical->Sync, + Vertical->Resolution + ) + ); + + MmioWrite32 ( + PL111_REG_LCD_TIMING_2, + CLK_SIG_POLARITY (Horizontal->Resolution) ); =20 - MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes)); MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); =20 // PL111_REG_LCD_CONTROL --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151396769278063.36956672378699; Fri, 22 Dec 2017 10:34:52 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8C8FB22198F7B; Fri, 22 Dec 2017 10:29:45 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 60FEE22225C1C for ; Fri, 22 Dec 2017 10:29:37 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYd007680; Fri, 22 Dec 2017 18:34:25 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:13 +0000 Message-Id: <20171222183418.8616-9-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 08/13] ArmPlatformPkg: Add PCD to select pixel format X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Current HDLCD and PL111 platform libraries do not support display modes with PixelBlueGreenRedReserved8BitPerColor format, i.e. because of historical confusion, they do not support the UEFI default PixelBlueGreenRedReserved8BitPerColor format In LcdPlatformLib for PL111, LcdPlatformQueryMode returns the pixel format as PixelRedGreenBlueReserved8BitPerColor which is wrong, because that does not match the display controller's pixel format which is set to BGR in PL111Lcd LcdHwLib. Also it is not possible to configure pixel format as RGB/BGR for the display modes for a platform at build time. This change adds PcdGopPixelFormat to configure pixel format as PixelRedGreenBlueReserved8BitPerColor or PixelBlueGreenRedReserved8BitPerColor or PixelBitMask. With this change, pixel format can be selected in the platform specific .dsc file for all supported display modes. Support for PixelBitMask is not implemented in PL111 or HDLCD LcdHwLib libraries, hence HDLCD and PL111 platform libraries will return error EFI_UNSUPPORTED if PcdGopPixelFormat is set to PixelBitMask. Indeed, it is not clear what selecting PixelBitMask might mean, but the option is allowed as it might suit a custom platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dec | 7 +++ ArmPlatformPkg/Include/Library/LcdPlatformLib.h | 4 ++ ArmPlatformPkg/Library/HdLcd/HdLcd.c | 55 +++++++------------- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 15 +++++- 4 files changed, 45 insertions(+), 36 deletions(-) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 7cec775abeee219e6821488a2c5abe88d23bbed1..e412414e0ba6506c7158e69bac0= 4469e45601736 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -97,6 +97,13 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x= 00000028 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00= 000029 =20 + # Graphics Output Pixel format + # 0 : PixelRedGreenBlueReserved8BitPerColor + # 1 : PixelBlueGreenRedReserved8BitPerColor + # 2 : PixelBitMask + # Default is set to UEFI console font format PixelBlueGreenRedReserved8B= itPerColor + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040 + [PcdsFixedAtBuild.common,PcdsDynamic.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index 0943f28a19133e7bc558f9d529bb8ac8f66ba3fd..02be124f00ff5c34c3f8c07ff16= ebb4ffc1ba20f 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -166,6 +166,10 @@ typedef struct { @param[in] Handle Handle to the LCD device instance. =20 @retval EFI_SUCCESS Plaform library initialized successfully. + @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + PixelRedGreenBlueReserved8BitPerColor OR + PixelBlueGreenRedReserved8BitPerColor + any other format is not supported. @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index 1fc04c2d14d8185370454be459a23bdec41f6602..72cd5fa33b2553195638c595e72= 843a56b2e267c 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -22,31 +22,7 @@ =20 #include "HdLcd.h" =20 -STATIC -UINTN -GetBytesPerPixel ( - IN LCD_BPP Bpp - ) -{ - switch (Bpp) { - case LCD_BITS_PER_PIXEL_24: - return 4; - - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_12_444: - return 2; - - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - return 1; - - default: - return 0; - } -} +#define BYTES_PER_PIXEL 4 =20 /** Initialize display. =20 @@ -78,10 +54,6 @@ LcdInitialize ( HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL ); =20 - MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); - MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); - MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); - return EFI_SUCCESS; } =20 @@ -92,6 +64,7 @@ LcdInitialize ( @retval EFI_SUCCESS Display mode set successfully. @retval EFI_DEVICE_ERROR Reurns an error if display timing information is not available. + @retval !EFI_SUCCESS Other errors. **/ EFI_STATUS LcdSetMode ( @@ -101,8 +74,8 @@ LcdSetMode ( EFI_STATUS Status; CONST SCAN_TIMINGS *Horizontal; CONST SCAN_TIMINGS *Vertical; - UINT32 BytesPerPixel; - LCD_BPP LcdBpp; + + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; =20 // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( @@ -118,13 +91,22 @@ LcdSetMode ( ASSERT (Horizontal !=3D NULL); ASSERT (Vertical !=3D NULL); =20 - Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); + // Get the pixel format information. + Status =3D LcdPlatformQueryMode (ModeNumber, &ModeInfo); if (EFI_ERROR (Status)) { ASSERT (FALSE); return Status; } =20 - BytesPerPixel =3D GetBytesPerPixel (LcdBpp); + if (ModeInfo.PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { + MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16); + MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0); + } else { + MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16); + MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0); + } + + MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8); =20 // Disable the controller MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); @@ -132,10 +114,13 @@ LcdSetMode ( // Update the frame buffer information with the new settings MmioWrite32 ( HDLCD_REG_FB_LINE_LENGTH, - Horizontal->Resolution * BytesPerPixel + Horizontal->Resolution * BYTES_PER_PIXEL ); =20 - MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, Horizontal->Resolution * BytesPerP= ixel); + MmioWrite32 ( + HDLCD_REG_FB_LINE_PITCH, + Horizontal->Resolution * BYTES_PER_PIXEL + ); =20 MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1); =20 diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c index d1aba083fdc2ee4a7c25294955c4413465dca1e8..6f4fe9c051ff3524b3d26daddb0= ac5e0e3ebe19d 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -75,6 +75,7 @@ LcdInitialize ( @retval EFI_SUCCESS Display set mode successfuly. @retval EFI_DEVICE_ERROR It returns an error if display timing information is not available. + @retval !EFI_SUCCESS Other errors. **/ EFI_STATUS LcdSetMode ( @@ -87,6 +88,8 @@ LcdSetMode ( UINT32 LcdControl; LCD_BPP LcdBpp; =20 + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( ModeNumber, @@ -107,6 +110,13 @@ LcdSetMode ( return Status; } =20 + // Get the pixel format information + Status =3D LcdPlatformQueryMode (ModeNumber, &ModeInfo); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + // Disable the CLCD_LcdEn bit MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); =20 @@ -140,7 +150,10 @@ LcdSetMode ( =20 // PL111_REG_LCD_CONTROL LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) - | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + | PL111_CTRL_LCD_TFT; + if (ModeInfo.PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { + LcdControl |=3D PL111_CTRL_BGR; + } MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 // Turn on power to the LCD Panel --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967684851124.18360760598807; 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receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:14 +0000 Message-Id: <20171222183418.8616-10-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 09/13] ArmPlatformPkg: PCD to swap red/blue format for HDLCD X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds a new PCD PcdArmHdlcdSwapBlueRedSelect to swap values for HDLCD RED_SELECT and BLUE_SELECT registers on platforms where blue and red hardware lines are swapped. If set to TRUE in the platform dsc, HDLCD library will swap the values while setting RED_SELECT and BLUE_SELECT registers. The default value of the PCD is FALSE. NOTE: The motive for this is that a discrepancy in the Red/Blue lines exists between some VersatileExpress platforms. Rather than have divergent code, this build switch allows a simple, pragmatic solution. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmPlatformPkg.dec | 3 +++ ArmPlatformPkg/Library/HdLcd/HdLcd.inf | 2 ++ ArmPlatformPkg/Library/HdLcd/HdLcd.c | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index e412414e0ba6506c7158e69bac04469e45601736..9a61e4a511024c80e787500de50= 38779363f0d95 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -104,6 +104,9 @@ [PcdsFixedAtBuild.common] # Default is set to UEFI console font format PixelBlueGreenRedReserved8B= itPerColor gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040 =20 + ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT = registers + gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x= 00000045 + [PcdsFixedAtBuild.common,PcdsDynamic.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.inf b/ArmPlatformPkg/Librar= y/HdLcd/HdLcd.inf index 67aad05d210b95b2d23b8e52e4392685efcf3795..0f440d1ef730159a8be37806677= 00979b607a1e2 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.inf +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.inf @@ -40,3 +40,5 @@ [LibraryClasses] =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase + gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect + diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c index 72cd5fa33b2553195638c595e72843a56b2e267c..4f802977e8b55ed83364d3ec8fa= 46082e128c76b 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -98,7 +98,11 @@ LcdSetMode ( return Status; } =20 +#if (!FixedPcdGetBool (PcdArmHdLcdSwapBlueRedSelect)) if (ModeInfo.PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { +#else + if (ModeInfo.PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor) { +#endif MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16); MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0); } else { --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15139676981951014.4377084200238; Fri, 22 Dec 2017 10:34:58 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 39D002219BCAF; Fri, 22 Dec 2017 10:29:46 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ED1D822225C16 for ; Fri, 22 Dec 2017 10:29:37 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYf007680; Fri, 22 Dec 2017 18:34:25 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:15 +0000 Message-Id: <20171222183418.8616-11-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 10/13] ArmPlatformPkg: Additional display modes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Add definitions for new display modes such as HD 720. This has no effect on existing display drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- ArmPlatformPkg/Include/Library/LcdPlatformLib.h | 60 ++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index 02be124f00ff5c34c3f8c07ff16ebb4ffc1ba20f..82426f7c903cff09de962e9b7ce= 10bb2568d340c 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -26,6 +26,11 @@ #define WSXGA 4 #define UXGA 5 #define HD 6 +#define WVGA 7 +#define QHD 8 +#define WSVGA 9 +#define HD720 10 +#define WXGA 11 =20 // VGA Mode: 640 x 480 #define VGA_H_RES_PIXELS 640 @@ -118,6 +123,61 @@ #define HD_V_FRONT_PORCH ( 3 - 1) #define HD_V_BACK_PORCH ( 32 - 1) =20 +// WVGA Mode: 800 x 480 +#define WVGA_H_RES_PIXELS 800 +#define WVGA_V_RES_PIXELS 480 +#define WVGA_OSC_FREQUENCY 29500000 /* 0x01C22260 */ +#define WVGA_H_SYNC ( 72 - 1) +#define WVGA_H_FRONT_PORCH ( 24 - 1) +#define WVGA_H_BACK_PORCH ( 96 - 1) +#define WVGA_V_SYNC ( 7 - 1) +#define WVGA_V_FRONT_PORCH ( 3 - 1) +#define WVGA_V_BACK_PORCH ( 10 - 1) + +// QHD Mode: 960 x 540 +#define QHD_H_RES_PIXELS 960 +#define QHD_V_RES_PIXELS 540 +#define QHD_OSC_FREQUENCY 40750000 /* 0x026DCBB0 */ +#define QHD_H_SYNC ( 96 - 1) +#define QHD_H_FRONT_PORCH ( 32 - 1) +#define QHD_H_BACK_PORCH (128 - 1) +#define QHD_V_SYNC ( 5 - 1) +#define QHD_V_FRONT_PORCH ( 3 - 1) +#define QHD_V_BACK_PORCH ( 14 - 1) + +// WSVGA Mode: 1024 x 600 +#define WSVGA_H_RES_PIXELS 1024 +#define WSVGA_V_RES_PIXELS 600 +#define WSVGA_OSC_FREQUENCY 49000000 /* 0x02EBAE40 */ +#define WSVGA_H_SYNC (104 - 1) +#define WSVGA_H_FRONT_PORCH ( 40 - 1) +#define WSVGA_H_BACK_PORCH (144 - 1) +#define WSVGA_V_SYNC ( 10 - 1) +#define WSVGA_V_FRONT_PORCH ( 3 - 1) +#define WSVGA_V_BACK_PORCH ( 11 - 1) + +// HD720 Mode: 1280 x 720 +#define HD720_H_RES_PIXELS 1280 +#define HD720_V_RES_PIXELS 720 +#define HD720_OSC_FREQUENCY 74500000 /* 0x0470C7A0 */ +#define HD720_H_SYNC (128 - 1) +#define HD720_H_FRONT_PORCH ( 64 - 1) +#define HD720_H_BACK_PORCH (192 - 1) +#define HD720_V_SYNC ( 5 - 1) +#define HD720_V_FRONT_PORCH ( 3 - 1) +#define HD720_V_BACK_PORCH ( 20 - 1) + +// WXGA Mode: 1280 x 800 +#define WXGA_H_RES_PIXELS 1280 +#define WXGA_V_RES_PIXELS 800 +#define WXGA_OSC_FREQUENCY 83500000 /* 0x04FA1BE0 */ +#define WXGA_H_SYNC (128 - 1) +#define WXGA_H_FRONT_PORCH ( 72 - 1) +#define WXGA_H_BACK_PORCH (200 - 1) +#define WXGA_V_SYNC ( 6 - 1) +#define WXGA_V_FRONT_PORCH ( 3 - 1) +#define WXGA_V_BACK_PORCH ( 22 - 1) + // Colour Masks #define LCD_24BPP_RED_MASK 0x00FF0000 #define LCD_24BPP_GREEN_MASK 0x0000FF00 --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:16 +0000 Message-Id: <20171222183418.8616-12-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 11/13] ArmPlatformPkg: Reserving framebuffer at build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Currently framebuffer memory is either reserved in special VRAM or dynamically allocated using boot services memory allocation functions. When allocated using boot services calls the memory has to be allocated as EfiBootServicesData. Unfortunately failures have been seen with this case. There is also an unfortunate lack of control on the placement of the framebuffer. This change introduces two PCDs, PcdArmLcdFrameBufferBase and PcdArmLcdFrameBufferSize which enable build time reservation of the framebuffer, avoiding the need to allocate dynamically. This allows the framebuffer to appear as "I/O memory" outside of the normal RAM map, which is similar to the "VRAM" case. This change has no impact on current code, only enables the option of build time reservation of framebuffers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmPlatformPkg.dec | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 9a61e4a511024c80e787500de5038779363f0d95..a887ffcfd9f3b168bfb19ff0a84= e310c7891b527 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -93,6 +93,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 =20 + ## If set, frame buffer memory will be reserved and mapped in the system= RAM + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x0|UINT32|0x0000= 0043 + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x0000= 0044 + ## PL180 MCI gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x= 00000028 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00= 000029 --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967700915187.02505327034783; Fri, 22 Dec 2017 10:35:00 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 95E03221ED773; Fri, 22 Dec 2017 10:29:46 -0800 (PST) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ED3D822225C1F for ; Fri, 22 Dec 2017 10:29:37 -0800 (PST) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.25.75]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id vBMIYOYh007680; Fri, 22 Dec 2017 18:34:25 GMT X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:17 +0000 Message-Id: <20171222183418.8616-13-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH v2 12/13] ArmPlatformPkg: New DP500/DP550/DP650 GOP driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds support for the ARM Mali DP500/DP500/DP650 display processors using the GOP protocol. It has been tested on FVP base models + DP550 support. This change adds platform independant LcdHwLib library. A corresponding platform specific library will be submitted to edk-platforms/Platform/ARM/VExpressPkg. This change does not modify functionality provided by PL111 or HDLCD. This LcdHwLib implementation should be suitable for those platforms that implement ARM Mali DP500/DP550/DP650 replacing PL111/HDLCD. Only graphics layer of the ARM Mali DP is configured for rendering the RGB/BGR format frame buffer to satisfy the UEFI GOP requirements Other layers e.g. video layers are not configured. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmPlatformPkg.dec | 4 + ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf | 44 +++ ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h | 243 ++++++++++++ ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c | 414 ++++++++++++++++++++ 4 files changed, 705 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index a887ffcfd9f3b168bfb19ff0a84e310c7891b527..a05cf59fbe6278bc69a674f128a= 4349477052e3d 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -93,6 +93,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 =20 + ## ARM Mali Display Processor DP500/DP550/DP650 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x0= 0000051 + ## If set, frame buffer memory will be reserved and mapped in the system= RAM gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x0|UINT32|0x0000= 0043 gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x0000= 0044 diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf b/ArmPlatformPk= g/Library/ArmMaliDp/ArmMaliDp.inf new file mode 100644 index 0000000000000000000000000000000000000000..461b194b2719d1b3761bee2bbb0= e3a245d72fdc1 --- /dev/null +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf @@ -0,0 +1,44 @@ +#/** @file ArmMaliDp.inf +# +# Component description file for ArmMaliDp module +# +# Copyright (c) 2017, ARM Ltd. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmMaliDp + FILE_GUID =3D E724AAF7-19E2-40A3-BAE1-D82A7C8B7A76 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdHwLib + +[Sources.common] + ArmMaliDp.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + LcdPlatformLib + UefiLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase + diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h b/ArmPlatformPkg/= Library/ArmMaliDp/ArmMaliDp.h new file mode 100644 index 0000000000000000000000000000000000000000..ca071093ebb6b0da8ace50ab57d= 3506b86d53fe9 --- /dev/null +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h @@ -0,0 +1,243 @@ +/** @file + + This header file contains the platform independent parts of ARM Mali DP + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef ARMMALIDP_H_ +#define ARMMALIDP_H_ + +#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBas= e)) + +// MALI DP Ids +#define MALIDP_NOT_PRESENT 0xFFF +#define MALIDP_500 0x500 +#define MALIDP_550 0x550 +#define MALIDP_650 0x650 + +// DP500 Peripheral Ids +#define DP500_ID_PART_0 0x00 +#define DP500_ID_DES_0 0xB +#define DP500_ID_PART_1 0x5 + +#define DP500_ID_REVISION 0x1 +#define DP500_ID_JEDEC 0x1 +#define DP500_ID_DES_1 0x3 + +#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0) +#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \ + | DP500_ID_PART_1) +#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \ + | (DP500_ID_JEDEC << 3) \ + | (DP500_ID_DES_1)) + +// DP550 Peripheral Ids +#define DP550_ID_PART_0 0x50 +#define DP550_ID_DES_0 0xB +#define DP550_ID_PART_1 0x5 + +#define DP550_ID_REVISION 0x0 +#define DP550_ID_JEDEC 0x1 +#define DP550_ID_DES_1 0x3 + +#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0) +#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \ + | DP550_ID_PART_1) +#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \ + | (DP550_ID_JEDEC << 3) \ + | (DP550_ID_DES_1)) + +// DP650 Peripheral Ids +#define DP650_ID_PART_0 0x50 +#define DP650_ID_DES_0 0xB +#define DP650_ID_PART_1 0x6 + +#define DP650_ID_REVISION 0x0 +#define DP650_ID_JEDEC 0x1 +#define DP650_ID_DES_1 0x3 + +#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0) +#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \ + | DP650_ID_PART_1) +#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \ + | (DP650_ID_JEDEC << 3) \ + | (DP650_ID_DES_1)) + +// Display Engine (DE) control register offsets for DP550/DP650 +#define DP_DE_STATUS 0x00000 +#define DP_DE_IRQ_SET 0x00004 +#define DP_DE_IRQ_MASK 0x00008 +#define DP_DE_IRQ_CLEAR 0x0000C +#define DP_DE_CONTROL 0x00010 +#define DP_DE_PROG_LINE 0x00014 +#define DP_DE_AXI_CONTROL 0x00018 +#define DP_DE_AXI_QOS 0x0001C +#define DP_DE_DISPLAY_FUNCTION 0x00020 + +#define DP_DE_H_INTERVALS 0x00030 +#define DP_DE_V_INTERVALS 0x00034 +#define DP_DE_SYNC_CONTROL 0x00038 +#define DP_DE_HV_ACTIVESIZE 0x0003C +#define DP_DE_DISPLAY_SIDEBAND 0x00040 +#define DP_DE_BACKGROUND_COLOR 0x00044 +#define DP_DE_DISPLAY_SPLIT 0x00048 +#define DP_DE_OUTPUT_DEPTH 0x0004C + +// Display Engine (DE) control register offsets for DP500 +#define DP_DE_DP500_CORE_ID 0x00018 +#define DP_DE_DP500_CONTROL 0x0000C +#define DP_DE_DP500_PROG_LINE 0x00010 +#define DP_DE_DP500_H_INTERVALS 0x00028 +#define DP_DE_DP500_V_INTERVALS 0x0002C +#define DP_DE_DP500_SYNC_CONTROL 0x00030 +#define DP_DE_DP500_HV_ACTIVESIZE 0x00034 +#define DP_DE_DP500_BG_COLOR_RG 0x0003C +#define DP_DE_DP500_BG_COLOR_B 0x00040 + +/* Display Engine (DE) graphics layer (LG) register offsets + * NOTE: For DP500 it will be LG2. + */ +#define DE_LG_OFFSET 0x00300 +#define DP_DE_LG_FORMAT (DE_LG_OFFSET) +#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04) +#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08) +#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C) +#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10) +#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14) +#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18) +#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C) +#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20) +#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C) +#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30) +#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48) + +// Display core (DC) control register offsets. +#define DP_DC_OFFSET 0x0C000 +#define DP_DC_STATUS (DP_DC_OFFSET + 0x00) +#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04) +#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08) +#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C) +#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10) +#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14) +#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18) + +// DP500 has a global configuration register. +#define DP_DP500_CONFIG_VALID (0xF00) + +// Display core ID register offsets. +#define DP_DC_ID_OFFSET 0x0FF00 +#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0) +#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4) +#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0) +#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4) +#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8) +#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0) +#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4) +#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8) +#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC) + +#define DP_DP500_ID_OFFSET 0x0F00 +#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0) +#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4) +#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0) +#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4) +#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8) +#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0) +#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4) +#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8) +#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC) + +// Display status configuration mode activation flag +#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16) + +// Display core control configuration mode +#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18) +#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17) +#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16) + +#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16) +#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17) + +// Display core configuration valid register +#define DP_DC_CONFIG_VALID_CVAL (0x1U) + +// DC_CORE_ID +// Display core version register PRODUCT_ID +#define DP_DC_CORE_ID_SHIFT 16 +#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT + +// Timing settings +#define DP_DE_HBACKPORCH_SHIFT 16 +#define DP_DE_VBACKPORCH_SHIFT 16 +#define DP_DE_VSP_SHIFT 28 +#define DP_DE_VSYNCWIDTH_SHIFT 16 +#define DP_DE_HSP_SHIFT 13 +#define DP_DE_V_ACTIVE_SHIFT 16 + +// BACKGROUND_COLOR +#define DP_DE_BG_R_PIXEL_SHIFT 16 +#define DP_DE_BG_G_PIXEL_SHIFT 8 + +//Graphics layer LG_FORMAT Pixel Format +#define DP_PIXEL_FORMAT_ARGB_8888 0x8 +#define DP_PIXEL_FORMAT_ABGR_8888 0x9 +#define DP_PIXEL_FORMAT_RGBA_8888 0xA +#define DP_PIXEL_FORMAT_BGRA_8888 0xB +#define DP_PIXEL_FORMAT_XRGB_8888 0x10 +#define DP_PIXEL_FORMAT_XBGR_8888 0x11 +#define DP_PIXEL_FORMAT_RGBX_8888 0x12 +#define DP_PIXEL_FORMAT_BGRX_8888 0x13 +#define DP_PIXEL_FORMAT_RGB_888 0x18 +#define DP_PIXEL_FORMAT_BGR_888 0x19 + +// DP500 format code are different than DP550/DP650 +#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2 +#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3 +#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4 +#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5 + +// Graphics layer LG_PTR_LOW and LG_PTR_HIGH +#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU +#define DP_DE_LG_PTR_HIGH_SHIFT 32 + +// Graphics layer LG_CONTROL register characteristics +#define DP_DE_LG_L_ALPHA_SHIFT 16 +#define DP_DE_LG_CHK_SHIFT 15 +#define DP_DE_LG_PMUL_SHIFT 14 +#define DP_DE_LG_COM_SHIFT 12 +#define DP_DE_LG_VFP_SHIFT 11 +#define DP_DE_LG_HFP_SHIFT 10 +#define DP_DE_LG_ROTATION_SHIFT 8 + +#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U +#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U +#define DP_DE_LG_LAYER_BLEND_BG 0x2U +#define DP_DE_LG_PIXEL_BLEND_BG 0x3U +#define DP_DE_LG_ENABLE 0x1U + +// Graphics layer LG_IN_SIZE register characteristics +#define DP_DE_LG_V_IN_SIZE_SHIFT 16 + +// Graphics layer LG_CMP_SIZE register characteristics +#define DP_DE_LG_V_CMP_SIZE_SHIFT 16 +#define DP_DE_LG_V_OFFSET_SHIFT 16 + +// Helper display timing macro functions. +#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hf= p) +#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vf= p) +#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hs= w) +#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Ho= r) + +// Helper layer graphics macros. +#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | = Hor) +#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) |= Hor) + +#endif /* ARMMALIDP_H_ */ diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c b/ArmPlatformPkg/= Library/ArmMaliDp/ArmMaliDp.c new file mode 100644 index 0000000000000000000000000000000000000000..804c292060bef9851dd56bdc606= 64027df2c3b6a --- /dev/null +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c @@ -0,0 +1,414 @@ +/** @file + + ARM Mali DP 500/550/650 display controller driver + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include + +#include "ArmMaliDp.h" + +// CORE_ID of the MALI DP +STATIC UINT32 mDpDeviceId; + +/** Disable the graphics layer + + This is done by clearing the EN bit of the LG_CONTROL register. +**/ +STATIC +VOID +LayerGraphicsDisable (VOID) +{ + MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE); +} + +/** Enable the graphics layer + + This is done by setting the EN bit of the LG_CONTROL register. +**/ +STATIC +VOID +LayerGraphicsEnable (VOID) +{ + MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE); +} + +/** Set the frame address of the graphics layer. + + @param[in] FrameBaseAddress Address of the data buffer to be used as + a frame buffer. +**/ +STATIC +VOID +LayerGraphicsSetFrame ( + IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress + ) +{ + // Disable the graphics layer. + LayerGraphicsDisable (); + + // Set up memory address of the data buffer for graphics layer. + // write lower bits of the address. + MmioWrite32 ( + DP_BASE + DP_DE_LG_PTR_LOW, + DP_DE_LG_PTR_LOW_MASK & FrameBaseAddress + ); + + // Write higher bits of the address. + MmioWrite32 ( + DP_BASE + DP_DE_LG_PTR_HIGH, + (UINT32)(FrameBaseAddress >> DP_DE_LG_PTR_HIGH_SHIFT) + ); + + // Enable the graphics layer. + LayerGraphicsEnable (); +} + +/** Configures various graphics layer characteristics. + + @param[in] UefiGfxPixelFormat This must be either + PixelBlueGreenRedReserved8BitPerColor + OR + PixelRedGreenBlueReserved8BitPerColor + @param[in] HRes Horizontal resolution of the graphics lay= er. + @param[in] VRes Vertical resolution of the graphics layer. +**/ +STATIC +VOID +LayerGraphicsConfig ( + IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat, + IN CONST UINT32 HRes, + IN CONST UINT32 VRes + ) +{ + UINT32 PixelFormat; + + // Disable the graphics layer before configuring any settings. + LayerGraphicsDisable (); + + // Setup graphics layer size. + MmioWrite32 (DP_BASE + DP_DE_LG_IN_SIZE, FRAME_IN_SIZE (HRes, VRes)); + + // Setup graphics layer composition size. + MmioWrite32 (DP_BASE + DP_DE_LG_CMP_SIZE, FRAME_CMP_SIZE (HRes, VRes)); + + // Setup memory stride (total visible pixels on a line * 4). + MmioWrite32 (DP_BASE + DP_DE_LG_H_STRIDE, (HRes * sizeof (UINT32))); + + // Set the format. + + // In PixelBlueGreenRedReserved8BitPerColor format, byte 0 represents bl= ue, + // byte 1 represents green, byte 2 represents red, and byte 3 is reserved + // which is equivalent to XRGB format of the DP500/DP550/DP650. Whereas + // PixelRedGreenBlueReserved8BitPerColor is equivalent to XBGR of the + // DP500/DP550/DP650. + if (UefiGfxPixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { + PixelFormat =3D (mDpDeviceId =3D=3D MALIDP_500) ? DP_PIXEL_FORMAT_DP50= 0_XRGB_8888 + : DP_PIXEL_FORMAT_XRGB_8888; + } else { + PixelFormat =3D (mDpDeviceId =3D=3D MALIDP_500) ? DP_PIXEL_FORMAT_DP50= 0_XBGR_8888 + : DP_PIXEL_FORMAT_XBGR_8888; + } + + MmioWrite32 (DP_BASE + DP_DE_LG_FORMAT, PixelFormat); + + // Enable graphics layer. + LayerGraphicsEnable (); +} + +/** Configure timing information of the display. + + @param[in] Horizontal Pointer to horizontal timing parameters. + (Resolution, Sync, Back porch, Front por= ch) + @param[in] Vertical Pointer to vertical timing parameters. + (Resolution, Sync, Back porch, Front por= ch) +**/ +STATIC +VOID +SetDisplayEngineTiming ( + IN CONST SCAN_TIMINGS * CONST Horizontal, + IN CONST SCAN_TIMINGS * CONST Vertical + ) +{ + UINTN RegHIntervals; + UINTN RegVIntervals; + UINTN RegSyncControl; + UINTN RegHVActiveSize; + + if (mDpDeviceId =3D=3D MALIDP_500) { + // MALI DP500 timing registers. + RegHIntervals =3D DP_BASE + DP_DE_DP500_H_INTERVALS; + RegVIntervals =3D DP_BASE + DP_DE_DP500_V_INTERVALS; + RegSyncControl =3D DP_BASE + DP_DE_DP500_SYNC_CONTROL; + RegHVActiveSize =3D DP_BASE + DP_DE_DP500_HV_ACTIVESIZE; + } else { + // MALI DP550/DP650 timing registers. + RegHIntervals =3D DP_BASE + DP_DE_H_INTERVALS; + RegVIntervals =3D DP_BASE + DP_DE_V_INTERVALS; + RegSyncControl =3D DP_BASE + DP_DE_SYNC_CONTROL; + RegHVActiveSize =3D DP_BASE + DP_DE_HV_ACTIVESIZE; + } + + // Horizontal back porch and front porch. + MmioWrite32 ( + RegHIntervals, + H_INTERVALS (Horizontal->FrontPorch, Horizontal->BackPorch) + ); + + // Vertical back porch and front porch. + MmioWrite32 ( + RegVIntervals, + V_INTERVALS (Vertical->FrontPorch, Vertical->BackPorch) + ); + + // Sync control, Horizontal and Vertical sync. + MmioWrite32 ( + RegSyncControl, + SYNC_WIDTH (Horizontal->Sync, Vertical->Sync) + ); + + // Set up Horizontal and Vertical area size. + MmioWrite32 ( + RegHVActiveSize, + HV_ACTIVE (Horizontal->Resolution, Vertical->Resolution) + ); +} + +/** Return CORE_ID of the ARM Mali DP. + + @retval 0xFFF No Mali DP found. + @retval 0x500 Mali DP core id for DP500. + @retval 0x550 Mali DP core id for DP550. + @retval 0x650 Mali DP core id for DP650. +**/ +STATIC +UINT32 +ArmMaliDpGetCoreId ( + ) +{ + UINT32 DpCoreId; + + // First check for DP500 as register offset for DP550/DP650 CORE_ID + // is beyond 3K/4K register space of the DP500. + DpCoreId =3D MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID); + DpCoreId >>=3D DP_DE_DP500_CORE_ID_SHIFT; + + if (DpCoreId =3D=3D MALIDP_500) { + return DpCoreId; + } + + // Check for DP550 or DP650. + DpCoreId =3D MmioRead32 (DP_BASE + DP_DC_CORE_ID); + DpCoreId >>=3D DP_DC_CORE_ID_SHIFT; + + if (DpCoreId =3D=3D MALIDP_550 + || DpCoreId =3D=3D MALIDP_650) { + return DpCoreId; + } + + return MALIDP_NOT_PRESENT; +} + +/** Check for presence of MALI. + + This function returns success if the platform implements + DP500/DP550/DP650 ARM Mali display processor. + + @retval EFI_SUCCESS DP500/DP550/DP650 display processor found + on the platform. + @retval EFI_NOT_FOUND DP500/DP550/DP650 display processor not fo= und + on the platform. +**/ +EFI_STATUS +LcdIdentify (VOID) +{ +#if (DP_BASE =3D=3D 0) +#error ARM Mali DP peripheral base address is invalid +#endif + + DEBUG ((DEBUG_WARN, + "Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n", + DP_BASE + )); + + if (mDpDeviceId =3D=3D 0) { + mDpDeviceId =3D ArmMaliDpGetCoreId (); + } + + if (mDpDeviceId =3D=3D MALIDP_NOT_PRESENT) { + DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId)); + return EFI_SUCCESS; +} + +/** Initialize platform display. + + @param[in] FrameBaseAddress Address of the frame buffer. + + @retval EFI_SUCCESS Display initialization successful. + @retval !(EFI_SUCCESS) Display initialization failure. +**/ +EFI_STATUS +LcdInitialize ( + IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress + ) +{ + DEBUG ((DEBUG_WARN, "Frame buffer base address =3D %p\n", FrameBaseAddre= ss)); + + if (mDpDeviceId =3D=3D 0) { + mDpDeviceId =3D ArmMaliDpGetCoreId (); + } + + if (mDpDeviceId =3D=3D MALIDP_NOT_PRESENT) { + DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization failed," + "no ARM Mali DP present\n")); + return EFI_NOT_FOUND; + } + + // We are using graphics layer of the Mali DP as a main frame buffer. + LayerGraphicsSetFrame (FrameBaseAddress); + + return EFI_SUCCESS; +} + +/** Set ARM Mali DP in cofiguration mode. + + The ARM Mali DP must be in the configuration mode for + configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL + and HV_ACTIVESIZE. +**/ +STATIC +VOID +SetConfigurationMode (VOID) +{ + // Request configuration Mode. + if (mDpDeviceId =3D=3D MALIDP_500) { + MmioOr32 (DP_BASE + DP_DE_DP500_CONTROL, DP_DE_DP500_CONTROL_CONFIG_REQ= ); + } else { + MmioOr32 (DP_BASE + DP_DC_CONTROL, DP_DC_CONTROL_CM_ACTIVE); + } +} + +/** Set ARM Mali DP in normal mode. + + Normal mode is the main operating mode of the display processor + in which display layer data is fetched from frame buffer and + displayed. +**/ +STATIC +VOID +SetNormalMode (VOID) +{ + // Disable configuration Mode. + if (mDpDeviceId =3D=3D MALIDP_500) { + MmioAnd32 (DP_BASE + DP_DE_DP500_CONTROL, ~DP_DE_DP500_CONTROL_CONFIG_R= EQ); + } else { + MmioAnd32 (DP_BASE + DP_DC_CONTROL, ~DP_DC_CONTROL_CM_ACTIVE); + } +} + +/** Set the global configuration valid flag. + + Any new configuration parameters written to the display engine are not + activated until the global configuration valid flag is set in the + CONFIG_VALID register. +**/ +STATIC +VOID +SetConfigValid (VOID) +{ + if (mDpDeviceId =3D=3D MALIDP_500) { + MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID); + } else { + MmioOr32 (DP_BASE + DP_DC_CONFIG_VALID, DP_DC_CONFIG_VALID); + } +} + +/** Set requested mode of the display. + + @param[in] ModeNumber Display mode number. + + @retval EFI_SUCCESS Display mode set successful. + @retval EFI_DEVICE_ERROR Display mode not found/supported. +**/ +EFI_STATUS +LcdSetMode ( + IN CONST UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + CONST SCAN_TIMINGS *Horizontal; + CONST SCAN_TIMINGS *Vertical; + + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + + // Get the display mode timings and other relevant information. + Status =3D LcdPlatformGetTimings ( + ModeNumber, + &Horizontal, + &Vertical + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + + // Get the pixel format information. + Status =3D LcdPlatformQueryMode (ModeNumber, &ModeInfo); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Request configuration mode. + SetConfigurationMode (); + + // Configure the graphics layer. + LayerGraphicsConfig ( + ModeInfo.PixelFormat, + Horizontal->Resolution, + Vertical->Resolution + ); + + // Set the display engine timings. + SetDisplayEngineTiming (Horizontal, Vertical); + + // After configuration, set Mali DP in normal mode. + SetNormalMode (); + + // Any parameters written to the display engine are not activated until + // CONFIG_VALID is set. + SetConfigValid (); + + return EFI_SUCCESS; +} + +/** This function de-initializes the display. + +**/ +VOID +LcdShutdown (VOID) +{ + // Disable graphics layer. + LayerGraphicsDisable (); +} --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 07:10:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513967704137592.2355246572649; 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receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Fri, 22 Dec 2017 18:34:18 +0000 Message-Id: <20171222183418.8616-14-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171222183418.8616-1-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 13/13] ArmPlatformPkg: Introduce SCMI protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com Content-Type: multipart/mixed; boundary="===============2861417563010324147==" Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 --===============2861417563010324147== Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change introduces a new SCMI protocol driver for Arm Platforms. The driver currently supports only clock and performance management protocols. Other protocols will be added as and when needed. Clock management protocol is used to configure the HDLCD clock on Juno platforms. Whereas performance management protocol allows adjustment of various performance domains to evaluate performance of the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak --- ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf | 4= 8 ++ ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h | 2= 9 ++ ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h | 6= 9 +++ ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h | 3= 9 ++ ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiDxe.h | 4= 1 ++ ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPrivate.h | 17= 4 ++++++++ ArmPlatformPkg/Include/Drivers/ArmScmi.h | 2= 7 ++ ArmPlatformPkg/Include/Drivers/ArmScmiBaseProtocol.h | 18= 2 ++++++++ ArmPlatformPkg/Include/Drivers/ArmScmiClockProtocol.h | 22= 5 ++++++++++ ArmPlatformPkg/Include/Drivers/ArmScmiPerformanceProtocol.h | 27= 4 ++++++++++++ ArmPlatformPkg/Include/Library/ArmMtl.h | 13= 2 ++++++ ArmPlatformPkg/Drivers/ArmScmiDxe/Scmi.c | 26= 1 +++++++++++ ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c | 32= 0 ++++++++++++++ ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c | 41= 9 ++++++++++++++++++ ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiDxe.c | 13= 5 ++++++ ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c | 45= 7 ++++++++++++++++++++ 16 files changed, 2832 insertions(+) diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf b/ArmPlatform= Pkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf new file mode 100644 index 0000000000000000000000000000000000000000..ad7c363c9d6621df36fb7beddff= 9e2ae28127c52 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2017, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# System Control and Management Interface V1.0 +# http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ +# DEN0056A_System_Control_and_Management_Interface.pdf +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D ArmScmiDxe + FILE_GUID =3D 9585984C-F027-45E9-AFDF-ADAA6DFAAAC7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ArmScmiDxeEntryPoint + +[Sources.common] + Scmi.c + ScmiBaseProtocol.c + ScmiClockProtocol.c + ScmiDxe.c + ScmiPerformanceProtocol.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + ArmMtl + DebugLib + IoLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Depex] + TRUE + diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h= b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h new file mode 100644 index 0000000000000000000000000000000000000000..88d47b9efb49f02dbadd0b6d76d= ac7a991df2124 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h @@ -0,0 +1,29 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ +#define ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ + +// Return values of BASE_DISCOVER_LIST_PROTOCOLS command. +typedef struct { + UINT32 NumProtocols; + // Array of four protocols in each element + // Total elements =3D 1 + (NumProtocols-1)/4 + UINT8 Protocols[]; +} BASE_DISCOVER_LIST; + +#endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */ diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.= h b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h new file mode 100644 index 0000000000000000000000000000000000000000..2807b6b476ac1b8cf821a29ca7a= 59a78e9188c52 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h @@ -0,0 +1,69 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ +#define ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ + +#pragma pack(1) + +// Clock rate in two 32bit words. +typedef struct { + UINT32 Low; + UINT32 High; +} CLOCK_RATE_DWORD; + +// Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[= 12] +#define RATE_FORMAT_SHIFT 12 +#define RATE_FORMAT_MASK 0x0001 +#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \ + & RATE_FORMAT_MASK) + +// Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16] +#define NUM_REMAIN_RATES_SHIFT 16 +#define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHI= FT)) + +// Number of rates that are returned by a call.to the SCP, RatesFlag Bits[= 11:0] +#define NUM_RATES_MASK 0x0FFF +#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK) + +// Return values for the CLOCK_DESCRIBER_RATE command. +typedef struct { + UINT32 NumRatesFlags; + CLOCK_RATE_DWORD Rates[]; +} CLOCK_DESCRIBE_RATES; + +#define CLOCK_SET_DEFAULT_FLAGS 0 + +// Message parameters for CLOCK_RATE_SET command. +typedef struct { + UINT32 Flags; + UINT32 ClockId; + CLOCK_RATE_DWORD Rate; +} CLOCK_RATE_SET_ATTRIBUTES; + +// if ClockAttr Bit[0] is set then clock device is enabled. +#define CLOCK_ENABLE_MASK 0x1 +#define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) =3D=3D = 1) + +typedef struct { + UINT32 Attributes; + UINT8 ClockName[SCMI_MAX_STR_LEN]; +} CLOCK_ATTRIBUTES; + +#pragma pack() + +#endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */ diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPr= ivate.h b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPriva= te.h new file mode 100644 index 0000000000000000000000000000000000000000..99fe80ae30bc818edef9125e5e8= a2d11322feb41 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h @@ -0,0 +1,39 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ +#define ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ + +#include + +// Number of performance levels returned by a call to the SCP, Lvls Bits[1= 1:0] +#define NUM_PERF_LEVELS_MASK 0x0FFF +#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK) + +// Number of performance levels remaining after a call to the SCP, Lvls Bi= ts[31:16] +#define NUM_REMAIN_PERF_LEVELS_SHIFT 16 +#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT) + +/** Return values for SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS command. + SCMI Spec =EF=BF=BD 4.5.2.5 +**/ +typedef struct { + UINT32 NumLevels; + SCMI_PERFORMANCE_LEVEL PerfLevel[]; // Offset to array of performance le= vels +} PERF_DESCRIBE_LEVELS; + +#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */ diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiDxe.h b/ArmPlatformPkg/D= rivers/ArmScmiDxe/ScmiDxe.h new file mode 100644 index 0000000000000000000000000000000000000000..a2ce4bf9022cee79e0486db3cf9= b4fdddf481081 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiDxe.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ +#ifndef SCMI_DXE_H_ +#define SCMI_DXE_H_ + +#define MAX_PROTOCOLS 6 +#define PROTOCOL_ID_MASK 0xF +#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN + +/** Pointer to protocol initialization function. + + @param[in] Handle A pointer to the EFI_HANDLE on which the protocol + interface is to be installed. + + @retval EFI_SUCCESS Protocol interface installed successfully. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PROTOCOL_INIT_FXN)( + IN EFI_HANDLE *Handle + ); + +typedef struct { + SCMI_PROTOCOL_INIT_FXN Init; +} SCMI_PROTOCOL_INIT_TABLE; + +#endif /* SCMI_DXE_H_ */ diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPrivate.h b/ArmPlatformP= kg/Drivers/ArmScmiDxe/ScmiPrivate.h new file mode 100644 index 0000000000000000000000000000000000000000..ca3a712c1afd3e3bd25f831f57a= ab7e6bff1cddb --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPrivate.h @@ -0,0 +1,174 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ +#ifndef SCMI_PRIVATE_H_ +#define SCMI_PRIVATE_H_ + +// SCMI protocol IDs. +typedef enum { + SCMI_PROTOCOL_ID_BASE =3D 0x10, + SCMI_PROTOCOL_ID_POWER_DOMAIN =3D 0x11, + SCMI_PROTOCOL_ID_SYSTEM_POWER =3D 0x12, + SCMI_PROTOCOL_ID_PERFORMANCE =3D 0x13, + SCMI_PROTOCOL_ID_CLOCK =3D 0x14, + SCMI_PROTOCOL_ID_SENSOR =3D 0x15 +} SCMI_PROTOCOL_ID; + +// SCMI message types. +typedef enum { + SCMI_MESSAGE_TYPE_COMMAND =3D 0, + SCMI_MESSAGE_TYPE_DELAYED_RESPONSE =3D 2, // Skipping 1 is deliberate. + SCMI_MESSAGE_TYPE_NOTIFICATION =3D 3 +} SCMI_MESSAGE_TYPE; + +// SCMI response error codes. +typedef enum { + SCMI_SUCCESS =3D 0, + SCMI_NOT_SUPPORTED =3D -1, + SCMI_INVALID_PARAMETERS =3D -2, + SCMI_DENIED =3D -3, + SCMI_NOT_FOUND =3D -4, + SCMI_OUT_OF_RANGE =3D -5, + SCMI_BUSY =3D -6, + SCMI_COMMS_ERROR =3D -7, + SCMI_GENERIC_ERROR =3D -8, + SCMI_HARDWARE_ERROR =3D -9, + SCMI_PROTOCOL_ERROR =3D -10 +} SCMI_STATUS; + +// SCMI message IDs common to all protocols. +typedef enum { + SCMI_MESSAGE_ID_PROTOCOL_VERSION =3D 0x0, + SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES =3D 0x1, + SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES =3D 0x2 +} SCMI_MESSAGE_ID; + +// Not defined in SCMI specification but will help to identify a message. +typedef struct { + SCMI_PROTOCOL_ID ProtocolId; + UINT32 MessageId; +} SCMI_COMMAND; + +#pragma pack(1) + +// Response to a SCMI command. +typedef struct { + INT32 Status; + UINT32 ReturnValues[]; +} SCMI_MESSAGE_RESPONSE; + +// Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10] +#define MESSAGE_TYPE_SHIFT 8 +#define PROTOCOL_ID_SHIFT 10 +#define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \ + MsgType << MESSAGE_TYPE_SHIFT \ + | ProtocolId << PROTOCOL_ID_SHIFT \ + | MsgId \ + ) +// SCMI message header. +typedef struct { + UINT32 MessageHeader; +} SCMI_MESSAGE_HEADER; + +#pragma pack() + +/** Return a pointer to the message payload. + + @param[out] Payload Holds pointer to the message payload. + + @retval EFI_SUCCESS Payload holds a valid message payload pointe= r. + @retval EFI_TIMEOUT Time out error if MTL channel is busy. + @retval EFI_UNSUPPORTED If MTL channel is unsupported. +**/ +EFI_STATUS +ScmiCommandGetPayload ( + OUT UINT32** Payload + ); + +/** Execute a SCMI command and receive a response. + + This function uses a MTL channel to transfer message to SCP + and waits for a response. + + @param[in] Command Pointer to the SCMI command (Protocol ID + and Message ID) + + @param[in,out] PayloadLength SCMI command message length. + + @param[out] OPTIONAL ReturnValues Pointer to SCMI response. + + @retval OUT EFI_SUCCESS Command sent and message received successf= ully. + @retval OUT EFI_UNSUPPORTED Channel not supported. + @retval OUT EFI_TIMEOUT Timeout on the channel. + @retval OUT EFI_DEVICE_ERROR Channel not ready. + @retval OUT EFI_DEVICE_ERROR Message Header corrupted. + @retval OUT EFI_DEVICE_ERROR SCMI error. +**/ +EFI_STATUS +ScmiCommandExecute ( + IN SCMI_COMMAND *Command, + IN OUT UINT32 *PayloadLength, + OUT UINT32 **ReturnValues OPTIONAL + ); + +/** Return protocol version from SCP for a given protocol ID. + + @param[in] Protocol ID Protocol ID. + @param[out] Version Pointer to version of the protocol. + + @retval EFI_SUCCESS Version holds a valid version received + from the SCP. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +ScmiGetProtocolVersion ( + IN SCMI_PROTOCOL_ID ProtocolId, + OUT UINT32 *Version + ); + +/** Return protocol attributes from SCP for a given protocol ID. + + @param[in] Protocol ID Protocol ID. + @param[out] ReturnValues Pointer to attributes of the protocol. + + @retval EFI_SUCCESS ReturnValues points to protocol attributes. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +ScmiGetProtocolAttributes ( + IN SCMI_PROTOCOL_ID ProtocolId, + OUT UINT32 **ReturnValues + ); + +/** Return protocol message attributes from SCP for a given protocol ID. + + @param[in] Protocol ID Protocol ID. + + @param[out] Attributes Pointer to attributes of the protocol. + + @retval EFI_SUCCESS ReturnValues points to protocol message attrib= utes. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +ScmiGetProtocolMessageAttributes ( + IN SCMI_PROTOCOL_ID ProtocolId, + OUT UINT32 **ReturnValues + ); + +#endif /* SCMI_PRIVATE_H_ */ diff --git a/ArmPlatformPkg/Include/Drivers/ArmScmi.h b/ArmPlatformPkg/Incl= ude/Drivers/ArmScmi.h new file mode 100644 index 0000000000000000000000000000000000000000..04ea3de5b34157ed459ee47440a= bbcaa7114e93a --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/ArmScmi.h @@ -0,0 +1,27 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_H_ +#define ARM_SCMI_H_ + +/* As per SCMI specification, maximum allowed ASCII string length + for various return values/parameters of a SCMI message. +*/ +#define SCMI_MAX_STR_LEN 16 + +#endif /* ARM_SCMI_H_ */ + diff --git a/ArmPlatformPkg/Include/Drivers/ArmScmiBaseProtocol.h b/ArmPlat= formPkg/Include/Drivers/ArmScmiBaseProtocol.h new file mode 100644 index 0000000000000000000000000000000000000000..d8fab57fc354f14e79287520f6c= 8f05eb1eff141 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/ArmScmiBaseProtocol.h @@ -0,0 +1,182 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_BASE_PROTOCOL_H_ +#define ARM_SCMI_BASE_PROTOCOL_H_ + +#include + +#define BASE_PROTOCOL_VERSION 0x10000 + +#define NUM_PROTOCOL_MASK 0xFFU +#define NUM_AGENT_MASK 0xFFU + +#define NUM_AGENT_SHIFT 0x8 + +// Returns total protocols that are implemented (excluding the Base protoc= ol) +#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK) + +// Returns Number of agents in the system. +#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_= MASK) + +#define ARM_SCMI_BASE_PROTOCOL_GUID { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f,= 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } } + +extern EFI_GUID gArmScmiBaseProtocolGuid; + +typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL; + +/** Return version of the Base protocol supported by SCP firmware. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] Version Version of the supported SCMI Base protocol. + + @retval EFI_SUCCESS The version of the protocol is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_BASE_GET_VERSION) ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT32 *Version + ); + +/** Return total number of SCMI protocols supported by the SCP firmware. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] TotalProtocols Total number of SCMI protocols supported. + + @retval EFI_SUCCESS Total number of protocols supported are return= ed. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT32 *TotalProtocols + ); + +/** Return vendor name. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] VendorIdentifier Null terminated ASCII string of up to + 16 bytes with a vendor name. + + @retval EFI_SUCCESS VendorIdentifier is returned. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] + ); + +/** Return sub vendor name. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] VendorIdentifier Null terminated ASCII string of up to + 16 bytes with a vendor name. + + @retval EFI_SUCCESS VendorIdentifier is returned. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] + ); + +/** Return implementation version. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] ImplementationVersion Vendor specific implementation version. + + @retval EFI_SUCCESS Implementation version is returned. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT32 *ImplementationVersion + ); + +/** Return list of protocols. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] ProtocolListSize Size of the ProtocolList. + + @param[out] ProtocolList Protocol list. + + @retval EFI_SUCCESS List of protocols is returned. + @retval EFI_BUFFER_TOO_SMALL ProtocolListSize is too small for the resul= t. + It has been updated to the size needed. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) ( + IN SCMI_BASE_PROTOCOL *This, + IN OUT UINT32 *ProtocolListSize, + OUT UINT8 *ProtocolList + ); + +// Base protocol. +typedef struct _SCMI_BASE_PROTOCOL { + SCMI_BASE_GET_VERSION GetVersion; + SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols; + SCMI_BASE_DISCOVER_VENDOR DiscoverVendor; + SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor; + SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion; + SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols; +} SCMI_BASE_PROTOCOL; + +// SCMI Message IDs for Base protocol. +typedef enum { + SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR =3D 0x3, + SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR =3D 0x4, + SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION =3D 0x5, + SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS =3D 0x6 +} SCMI_MESSAGE_ID_BASE; + +/** Initialize Base protocol and install protocol on a given handle. + + @param[in] Handle Handle to install Base protocol. + + @retval EFI_SUCCESS Base protocol interface installed + successfully. +**/ +EFI_STATUS +ScmiBaseProtocolInit ( + IN OUT EFI_HANDLE* Handle + ); + +#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */ + diff --git a/ArmPlatformPkg/Include/Drivers/ArmScmiClockProtocol.h b/ArmPla= tformPkg/Include/Drivers/ArmScmiClockProtocol.h new file mode 100644 index 0000000000000000000000000000000000000000..a97728e4dfe8efc3cd8dc29dc94= 987c1cc6c6a80 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/ArmScmiClockProtocol.h @@ -0,0 +1,225 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_CLOCK_PROTOCOL_H_ +#define ARM_SCMI_CLOCK_PROTOCOL_H_ + +#include + +#define ARM_SCMI_CLOCK_PROTOCOL_GUID { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9,= 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } } + +extern EFI_GUID gArmScmiClockProtocolGuid; + +// Message Type for clock management protocol. +typedef enum { + SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES =3D 0x3, + SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES =3D 0x4, + SCMI_MESSAGE_ID_CLOCK_RATE_SET =3D 0x5, + SCMI_MESSAGE_ID_CLOCK_RATE_GET =3D 0x6, + SCMI_MESSAGE_ID_CLOCK_CONFIG_SET =3D 0x7 +} SCMI_MESSAGE_ID_CLOCK; + +typedef enum { + SCMI_CLOCK_RATE_FORMAT_DISCRETE, // Non-linear range. + SCMI_CLOCK_RATE_FORMAT_LINEAR // Linear range. +} SCMI_CLOCK_RATE_FORMAT; + +// Clock management protocol version. +#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000 + +#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU +#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16 +#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU + +// Total pending asynchronous clock rates changes supported by the SCP, At= tr Bits[23:16] +#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( = \ + (Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHI= FT) \ + && SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK) + +// Total of clock devices supported by the SCP, Attr Bits[15:0] +#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_N= UM_CLOCKS_MASK) + +#pragma pack(1) + +/* Depending on the format (linear/non-linear) supported by a clock device + either Rate or Min/Max/Step triplet is valid. +*/ +typedef struct { + union { + UINT64 Min; + UINT64 Rate; + }; + UINT64 Max; + UINT64 Step; +} SCMI_CLOCK_RATE; + +#pragma pack() + +typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL; + +// Protocol Interface functions. + +/** Return version of the clock management protocol supported by SCP firmw= are. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + + @param[out] Version Version of the supported SCMI Clock management prot= ocol. + + @retval EFI_SUCCESS The version is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_GET_VERSION) ( + IN SCMI_CLOCK_PROTOCOL *This, + OUT UINT32 *Version + ); + +/** Return total number of clock devices supported by the clock management + protocol. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + + @param[out] TotalClocks Total number of clocks supported. + + @retval EFI_SUCCESS Total number of clocks supported is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) ( + IN SCMI_CLOCK_PROTOCOL *This, + OUT UINT32 *TotalClocks + ); + +/** Return attributes of a clock device. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + + @param[out] Enabled If TRUE, the clock device is enabled. + @param[out] ClockAsciiName A NULL terminated ASCII string with the clock + name, of up to 16 bytes. + + @retval EFI_SUCCESS Clock device attributes are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + OUT BOOLEAN *Enabled, + OUT CHAR8 *ClockAsciiName + ); + +/** Return list of rates supported by a given clock device. + + @param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + + @param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device + supports range of clock rates which are non-line= ar. + + SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supp= orts + range of linear clock rates from Min to Max in s= teps. + + @param[out] TotalRates Total number of rates. + + @param[in,out] RateArraySize Size of the RateArray. + + @param[out] RateArray List of clock rates. + + @retval EFI_SUCCESS List of clock rates are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval EFI_BUFFER_TOO_SMALL RateArraySize is too small for the result. + It has been updated to the size needed. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + OUT SCMI_CLOCK_RATE_FORMAT *Format, + OUT UINT32 *TotalRates, + IN OUT UINT32 *RateArraySize, + OUT SCMI_CLOCK_RATE *RateArray + ); + +/** Get clock rate. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + + @param[out] Rate Clock rate. + + @retval EFI_SUCCESS Clock rate is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_RATE_GET) ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + OUT UINT64 *Rate + ); + +/** Set clock rate. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + @param[in] Rate Clock rate. + + @retval EFI_SUCCESS Clock rate set success. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_RATE_SET) ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + IN UINT64 Rate + ); + +typedef struct _SCMI_CLOCK_PROTOCOL { + SCMI_CLOCK_GET_VERSION GetVersion; + SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks; + SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes; + SCMI_CLOCK_DESCRIBE_RATES DescribeRates; + SCMI_CLOCK_RATE_GET RateGet; + SCMI_CLOCK_RATE_SET RateSet; +} SCMI_CLOCK_PROTOCOL; + +/** Initialize clock management protocol and install protocol on a given h= andle. + + @param[in] Handle Handle to install clock management protoc= ol. + + @retval EFI_SUCCESS Clock protocol interface installed succes= sfully. +**/ +EFI_STATUS +ScmiClockProtocolInit ( + IN EFI_HANDLE *Handle + ); + +#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */ + diff --git a/ArmPlatformPkg/Include/Drivers/ArmScmiPerformanceProtocol.h b/= ArmPlatformPkg/Include/Drivers/ArmScmiPerformanceProtocol.h new file mode 100644 index 0000000000000000000000000000000000000000..cb4aa6bf71df86cfd7a0dabb354= 112c5a38c978f --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/ArmScmiPerformanceProtocol.h @@ -0,0 +1,274 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_SCMI_PERFORMANCE_PROTOCOL_H_ +#define ARM_SCMI_PERFORMANCE_PROTOCOL_H_ + +#include + +#define PERFORMANCE_PROTOCOL_VERSION 0x10000 + +#define ARM_SCMI_PERFORMANCE_PROTOCOL_GUID { 0x9b8ba84, 0x3dd3, 0x49a6, {= 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } } + +extern EFI_GUID gArmScmiPerformanceProtocolGuid; + +typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL; + +#pragma pack(1) + +#define POWER_IN_MW_SHIFT 16 +#define POWER_IN_MW_MASK 0x1 +#define NUM_PERF_DOMAINS_MASK 0xFFFF + +// Total number of performance domains, Attr Bits [15:0] +#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK) +// Power values expressed in mW, Attr Bit [16] +#define SCMI_PERF_POWER_IN_MW(Attr) ((Attr >> POWER_IN_MW_SHIFT) \ + & POWER_IN_MW_MASK) + +// Performance protocol attributes return values. +typedef struct { + UINT32 Attributes; + UINT64 StatisticsAddress; + UINT32 StatisticsLen; +} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES; + +#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1) +#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1) +#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1) +#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1) +#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF) + +// Performance protocol domain attributes. +typedef struct { + UINT32 Attributes; + UINT32 RateLimit; + UINT32 SustainedFreq; + UINT32 SustainedPerfLevel; + UINT8 Name[SCMI_MAX_STR_LEN]; +} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES; + +// Worst case latency in microseconds, Bits[15:0] +#define PERF_LATENCY_MASK 0xFFFF +#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY= _MASK) + +// Performance protocol performance level. +typedef struct { + UINT32 Level; + UINT32 PowerCost; + UINT32 Latency; +} SCMI_PERFORMANCE_LEVEL; + +// Performance protocol performance limit. +typedef struct { + UINT32 RangeMax; + UINT32 RangeMin; +} SCMI_PERFORMANCE_LIMITS; + +#pragma pack() + +/** Return version of the performance management protocol supported by SCP. + firmware. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + + @param[out] Version Version of the supported SCMI performance manageme= nt + protocol. + + @retval EFI_SUCCESS The version is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + OUT UINT32 *Version + ); + +/** Return protocol attributes of the performance management protocol. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + + @param[out] Attributes Protocol attributes. + + @retval EFI_SUCCESS Protocol attributes are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes + + ); + +/** Return performance domain attributes. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] Attributes Performance domain attributes. + + @retval EFI_SUCCESS Domain attributes are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes + ); + +/** Return list of performance domain levels of a given domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] NumLevels Total number of levels a domain can support. + + @param[in,out] LevelArraySize Size of the performance level array. + + @param[out] LevelArray Array of the performance levels. + + @retval EFI_SUCCESS Domain levels are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval EFI_BUFFER_TOO_SMALL LevelArraySize is too small for the result. + It has been updated to the size needed. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + OUT UINT32 *NumLevels, + IN OUT UINT32 *LevelArraySize, + OUT SCMI_PERFORMANCE_LEVEL *LevelArray + ); + +/** Set performance limits of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + @param[in] Limit Performance limit to set. + + @retval EFI_SUCCESS Performance limits set successfully. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + IN SCMI_PERFORMANCE_LIMITS *Limits + ); + +/** Get performance limits of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] Limit Performance Limits of the domain. + + @retval EFI_SUCCESS Performance limits are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) ( + SCMI_PERFORMANCE_PROTOCOL *This, + UINT32 DomainId, + SCMI_PERFORMANCE_LIMITS *Limits + ); + +/** Set performance level of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + @param[in] Level Performance level of the domain. + + @retval EFI_SUCCESS Performance level set successfully. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + IN UINT32 Level + ); + +/** Get performance level of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] Level Performance level of the domain. + + @retval EFI_SUCCESS Performance level got successfully. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + OUT UINT32 *Level + ); + +typedef struct _SCMI_PERFORMANCE_PROTOCOL { + SCMI_PERFORMANCE_GET_VERSION GetVersion; + SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes; + SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes; + SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels; + SCMI_PERFORMANCE_LIMITS_SET LimitsSet; + SCMI_PERFORMANCE_LIMITS_GET LimitsGet; + SCMI_PERFORMANCE_LEVEL_SET LevelSet; + SCMI_PERFORMANCE_LEVEL_GET LevelGet; +} SCMI_PERFORMANCE_PROTOCOL; + +typedef enum { + SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES =3D 0x3, + SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS =3D 0x4, + SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET =3D 0x5, + SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET =3D 0x6, + SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET =3D 0x7, + SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET =3D 0x8, +} SCMI_MESSAGE_ID_PERFORMANCE; + +/** Initialize performance management protocol and install on a given Hand= le. + + @param[in] Handle Handle to install performance management + protocol. + + @retval EFI_SUCCESS Performance protocol installed successful= ly. +**/ +EFI_STATUS +ScmiPerformanceProtocolInit ( + IN EFI_HANDLE* Handle + ); + +#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */ + diff --git a/ArmPlatformPkg/Include/Library/ArmMtl.h b/ArmPlatformPkg/Inclu= de/Library/ArmMtl.h new file mode 100644 index 0000000000000000000000000000000000000000..9be65cfa0a1dcf0d984f29e5d95= aedf5e0afac2b --- /dev/null +++ b/ArmPlatformPkg/Include/Library/ArmMtl.h @@ -0,0 +1,132 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef ARM_MTL_H_ +#define ARM_MTL_H_ + +// Ideally we don't need packed struct. However we can't rely on compilers +#pragma pack(1) + +typedef struct { + UINT32 Reserved1; + UINT32 ChannelStatus; + UINT64 Reserved2; + UINT32 Flags; + UINT32 Length; + UINT32 MessageHeader; + UINT32 Payload[]; // size less object gives offset to payload. +} MTL_MAILBOX; + +#pragma pack() + +// Channel Type, Low-priority, and High-priority +typedef enum { + MTL_CHANNEL_TYPE_LOW =3D 0, + MTL_CHANNEL_TYPE_HIGH =3D 1 +} MTL_CHANNEL_TYPE; + +typedef struct { + UINT64 PhysicalAddress; + UINT32 ModifyMask; + UINT32 PreserveMask; +} MTL_DOORBELL; + +typedef struct { + MTL_CHANNEL_TYPE ChannelType; + MTL_MAILBOX * CONST MailBox; + MTL_DOORBELL DoorBell; +} MTL_CHANNEL; + +/** Wait until channel is free. + + @param[in] Channel Pointer to a channel. + @param[in] TimeOutInMicroSeconds Time out in micro seconds. + + @retval EFI_SUCCESS Channel is free. + @retval EFI_TIMOUT Timeout error. +**/ +EFI_STATUS +MtlWaitUntilChannelFree ( + IN MTL_CHANNEL *Channel, + IN UINT64 TimeOutInMicroSeconds + ); + +/** Return the address of the message payload. + + @param[in] Channel Pointer to a channel. + + @retval UINT32* Pointer to the payload. +**/ +UINT32* +MtlGetChannelPayload ( + IN MTL_CHANNEL *Channel + ); + +/** Return pointer to a channel for the requested channel type. + + @param[in] ChannelType ChannelType, Low or High priority channel. + MTL_CHANNEL_TYPE_LOW or + MTL_CHANNEL_TYPE_HIGH + + @param[out] Channel Holds pointer to the channel. + + @retval EFI_SUCCESS Pointer to channel is returned. + @retval EFI_UNSUPPORTED Requested channel type not supported. +**/ +EFI_STATUS +MtlGetChannel ( + IN MTL_CHANNEL_TYPE ChannelType, + OUT MTL_CHANNEL **Channel + ); + + +/** Mark the channel busy and ring the doorbell. + + @param[in] Channel Pointer to a channel. + @param[in] MessageHeader Message header. + + @param[out] PayloadLength Message length. + + @retval EFI_SUCCESS Message sent successfully. + @retval EFI_DEVICE_ERROR Channel is busy. +**/ +EFI_STATUS +MtlSendMessage ( + IN MTL_CHANNEL *Channel, + IN UINT32 MessageHeader, + OUT UINT32 PayloadLength + ); + +/** Wait for a response on a channel. + + If channel is free after sending message, it implies SCP responded + with a response on the channel. + + @param[in] Channel Pointer to a channel. + + @retval EFI_SUCCESS Message received successfully. + @retval EFI_TIMOUT Timeout error. +**/ +EFI_STATUS +MtlReceiveMessage ( + IN MTL_CHANNEL *Channel, + OUT UINT32 *MessageHeader, + OUT UINT32 *PayloadLength + ); + +#endif /* ARM_MTL_H_ */ + diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/Scmi.c b/ArmPlatformPkg/Driv= ers/ArmScmiDxe/Scmi.c new file mode 100644 index 0000000000000000000000000000000000000000..8abbd90ce7bd5420cf81f89a468= 0e5563d7af085 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/Scmi.c @@ -0,0 +1,261 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include +#include + +#include "ScmiPrivate.h" + +// SCMI Specification 1.0 +#define MAX_PROTOCOLS 6 + +#define PROTOCOL_MASK 0xF + +// Arbitrary timeout value 20ms. +#define RESPONSE_TIMEOUT 20000 + +/** Return a pointer to the message payload. + + @param[out] Payload Holds pointer to the message payload. + + @retval EFI_SUCCESS Payload holds a valid message payload pointe= r. + @retval EFI_TIMEOUT Time out error if MTL channel is busy. + @retval EFI_UNSUPPORTED If MTL channel is unsupported. +**/ +EFI_STATUS +ScmiCommandGetPayload ( + OUT UINT32** Payload + ) +{ + EFI_STATUS Status; + MTL_CHANNEL *Channel; + + // Get handle to the Channel. + Status =3D MtlGetChannel (MTL_CHANNEL_TYPE_LOW, &Channel); + if (EFI_ERROR (Status)) { + return Status; + } + + // Payload will not be populated until channel is free. + Status =3D MtlWaitUntilChannelFree (Channel, RESPONSE_TIMEOUT); + if (EFI_ERROR (Status)) { + return Status; + } + + // Get the address of the payload. + *Payload =3D MtlGetChannelPayload (Channel); + + return EFI_SUCCESS; +} + +/** Execute a SCMI command and receive a response. + + This function uses a MTL channel to transfer message to SCP + and waits for a response. + + @param[in] Command Pointer to the SCMI command (Protocol ID + and Message ID) + + @param[in,out] PayloadLength SCMI command message length. + + @param[out] OPTIONAL ReturnValues Pointer to SCMI response. + + @retval OUT EFI_SUCCESS Command sent and message received successf= ully. + @retval OUT EFI_UNSUPPORTED Channel not supported. + @retval OUT EFI_TIMEOUT Timeout on the channel. + @retval OUT EFI_DEVICE_ERROR Channel not ready. + @retval OUT EFI_DEVICE_ERROR Message Header corrupted. + @retval OUT EFI_DEVICE_ERROR SCMI error. +**/ +EFI_STATUS +ScmiCommandExecute ( + IN SCMI_COMMAND *Command, + IN OUT UINT32 *PayloadLength, + OUT UINT32 **ReturnValues OPTIONAL + ) +{ + EFI_STATUS Status; + SCMI_MESSAGE_RESPONSE *Response; + UINT32 MessageHeader; + UINT32 ResponseHeader; + MTL_CHANNEL *Channel; + + ASSERT (PayloadLength !=3D NULL); + + Status =3D MtlGetChannel (MTL_CHANNEL_TYPE_LOW, &Channel); + if (EFI_ERROR (Status)) { + return Status; + } + + // Fill in message header. + MessageHeader =3D SCMI_MESSAGE_HEADER (Command->MessageId, + SCMI_MESSAGE_TYPE_COMMAND, + Command->ProtocolId + ); + + // Send payload using MTL channel. + Status =3D MtlSendMessage ( + Channel, + MessageHeader, + *PayloadLength + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Wait for the response on the channel. + Status =3D MtlReceiveMessage (Channel, &ResponseHeader, PayloadLength); + if (EFI_ERROR (Status)) { + return Status; + } + + // SCMI must return MessageHeader unmodified. + if (MessageHeader !=3D ResponseHeader) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + Response =3D (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel); + + if (Response->Status !=3D SCMI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId =3D 0x%x, MessageId =3D 0= x%x, error =3D %d\n", + Command->ProtocolId, + Command->MessageId, + Response->Status + )); + + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + if (ReturnValues !=3D NULL) { + *ReturnValues =3D Response->ReturnValues; + } + + return EFI_SUCCESS; +} + +/** Internal common function useful for common protocol discovery messages. + + @param[in] ProtocolId Protocol Id of the the protocol. + @param[in] MesaageId Message Id of the message. + + @param[out] ReturnValues SCMI response return values. + + @retval EFI_SUCCESS Success with valid return values. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ScmiProtocolDiscoveryCommon ( + IN SCMI_PROTOCOL_ID ProtocolId, + IN SCMI_MESSAGE_ID MessageId, + OUT UINT32 **ReturnValues + ) +{ + SCMI_COMMAND Command; + UINT32 PayloadLength =3D 0; + + Command.ProtocolId =3D ProtocolId; + Command.MessageId =3D MessageId; + + return ScmiCommandExecute ( + &Command, + &PayloadLength, + ReturnValues + ); +} + +/** Return protocol version from SCP for a given protocol ID. + + @param[in] Protocol ID Protocol ID. + @param[out] Version Pointer to version of the protocol. + + @retval EFI_SUCCESS Version holds a valid version received + from the SCP. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +ScmiGetProtocolVersion ( + IN SCMI_PROTOCOL_ID ProtocolId, + OUT UINT32 *Version + ) +{ + EFI_STATUS Status; + UINT32 *ProtocolVersion; + + Status =3D ScmiProtocolDiscoveryCommon ( + ProtocolId, + SCMI_MESSAGE_ID_PROTOCOL_VERSION, + (UINT32**)&ProtocolVersion + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *Version =3D *ProtocolVersion; + + return EFI_SUCCESS; +} + +/** Return protocol attributes from SCP for a given protocol ID. + + @param[in] Protocol ID Protocol ID. + @param[out] ReturnValues Pointer to attributes of the protocol. + + @retval EFI_SUCCESS ReturnValues points to protocol attributes. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +ScmiGetProtocolAttributes ( + IN SCMI_PROTOCOL_ID ProtocolId, + OUT UINT32 **ReturnValues + ) +{ + return ScmiProtocolDiscoveryCommon ( + ProtocolId, + SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES, + ReturnValues + ); +} + +/** Return protocol message attributes from SCP for a given protocol ID. + + @param[in] Protocol ID Protocol ID. + @param[out] Attributes Pointer to attributes of the protocol. + + @retval EFI_SUCCESS ReturnValues points to protocol message attrib= utes. + @retval EFI_DEVICE_ERROR SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +ScmiGetProtocolMessageAttributes ( + IN SCMI_PROTOCOL_ID ProtocolId, + OUT UINT32 **ReturnValues + ) +{ + return ScmiProtocolDiscoveryCommon ( + ProtocolId, + SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES, + ReturnValues + ); +} diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c b/ArmPlat= formPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c new file mode 100644 index 0000000000000000000000000000000000000000..144df459e9238b5e08c87ad1299= 9a5491679d1fb --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c @@ -0,0 +1,320 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include +#include + +#include "ArmScmiBaseProtocolPrivate.h" +#include "ScmiPrivate.h" + +EFI_GUID gArmScmiBaseProtocolGuid =3D ARM_SCMI_BASE_PROTOCOL_GUID; + +/** Return version of the Base protocol supported by SCP firmware. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] Version Version of the supported SCMI Base protocol. + + @retval EFI_SUCCESS The version of the protocol is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +BaseGetVersion ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT32 *Version + ) +{ + return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_BASE, Version); +} + +/** Return total number of SCMI protocols supported by the SCP firmware. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] TotalProtocols Total number of SCMI protocols supported. + + @retval EFI_SUCCESS Total number of protocols supported are return= ed. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +BaseGetTotalProtocols ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT32 *TotalProtocols + ) +{ + EFI_STATUS Status; + UINT32 *ReturnValues; + + Status =3D ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_BASE, &ReturnValu= es); + if (EFI_ERROR (Status)) { + return Status; + } + + *TotalProtocols =3D SCMI_TOTAL_PROTOCOLS (ReturnValues[0]); + + return EFI_SUCCESS; +} + +/** Common function which returns vendor details. + + @param[in] MessageId SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR + OR + SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR + + @param[out] VendorIdentifier ASCII name of the vendor/subvendor. + + @retval EFI_SUCCESS VendorIdentifier is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +BaseDiscoverVendorDetails ( + IN SCMI_MESSAGE_ID_BASE MessageId, + OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] + ) +{ + EFI_STATUS Status; + UINT32 *ReturnValues; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_BASE; + Cmd.MessageId =3D MessageId; + + PayloadLength =3D 0; + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + &ReturnValues + ); + if (EFI_ERROR (Status)) { + return Status; + } + + AsciiStrCpyS ( + (CHAR8*)VendorIdentifier, + SCMI_MAX_STR_LEN, + (CONST CHAR8*)ReturnValues + ); + + return EFI_SUCCESS; +} + +/** Return vendor name. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] VendorIdentifier Null terminated ASCII string of up to + 16 bytes with a vendor name. + + @retval EFI_SUCCESS VendorIdentifier is returned. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +BaseDiscoverVendor ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] + ) +{ + return BaseDiscoverVendorDetails ( + SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR, + VendorIdentifier + ); +} + +/** Return sub vendor name. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] VendorIdentifier Null terminated ASCII string of up to + 16 bytes with a sub vendor name. + + @retval EFI_SUCCESS VendorIdentifier is returned. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +BaseDiscoverSubVendor ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN] + ) +{ + return BaseDiscoverVendorDetails ( + SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR, + VendorIdentifier + ); +} + +/** Return implementation version. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] ImplementationVersion Vendor specific implementation version. + + @retval EFI_SUCCESS Implementation version is returned. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +BaseDiscoverImplVersion ( + IN SCMI_BASE_PROTOCOL *This, + OUT UINT32 *ImplementationVersion + ) +{ + EFI_STATUS Status; + UINT32 *ReturnValues; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_BASE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION; + + PayloadLength =3D 0; + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + &ReturnValues + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *ImplementationVersion =3D ReturnValues[0]; + + return EFI_SUCCESS; +} + +/** Return list of protocols. + + @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance. + + @param[out] ProtocolListSize Size of the ProtocolList. + + @param[out] ProtocolList Protocol list. + + @retval EFI_SUCCESS List of protocols is returned. + @retval EFI_BUFFER_TOO_SMALL ProtocolListSize is too small for the resul= t. + It has been updated to the size needed. + @retval EFI_DEVICE_ERROR SCP returns a SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +BaseDiscoverListProtocols ( + IN SCMI_BASE_PROTOCOL *This, + IN OUT UINT32 *ProtocolListSize, + OUT UINT8 *ProtocolList + ) +{ + EFI_STATUS Status; + UINT32 TotalProtocols; + UINT32 *MessageParams; + BASE_DISCOVER_LIST *DiscoverList; + UINT32 Skip; + UINT32 Index; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + UINT32 RequiredSize; + + Status =3D BaseGetTotalProtocols (This, &TotalProtocols); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + RequiredSize =3D sizeof (UINT8) * TotalProtocols; + if (*ProtocolListSize < RequiredSize) { + *ProtocolListSize =3D RequiredSize; + return EFI_BUFFER_TOO_SMALL; + } + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_BASE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS; + + Skip =3D 0; + + while (Skip < TotalProtocols) { + + *MessageParams =3D Skip; + + // Note PayloadLength is a IN/OUT parameter. + PayloadLength =3D sizeof (Skip); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + (UINT32**)&DiscoverList + ); + if (EFI_ERROR (Status)) { + return Status; + } + + for (Index =3D 0; Index < DiscoverList->NumProtocols; Index++) { + ProtocolList[Skip++] =3D DiscoverList->Protocols[Index]; + } + } + + *ProtocolListSize =3D RequiredSize; + + return EFI_SUCCESS; +} + +// Instance of the SCMI Base protocol. +STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol =3D { + BaseGetVersion, + BaseGetTotalProtocols, + BaseDiscoverVendor, + BaseDiscoverSubVendor, + BaseDiscoverImplVersion, + BaseDiscoverListProtocols +}; + +/** Initialize Base protocol and install protocol on a given handle. + + @param[in] Handle Handle to install Base protocol. + + @retval EFI_SUCCESS Base protocol interface installed + successfully. +**/ +EFI_STATUS +ScmiBaseProtocolInit ( + IN OUT EFI_HANDLE* Handle + ) +{ + return gBS->InstallMultipleProtocolInterfaces ( + Handle, + &gArmScmiBaseProtocolGuid, + &BaseProtocol, + NULL + ); +} diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c b/ArmPla= tformPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c new file mode 100644 index 0000000000000000000000000000000000000000..895f3f6c5dccbd24e98ed73fa08= c41a369d83f43 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c @@ -0,0 +1,419 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ +#include +#include +#include +#include + +#include "ArmScmiClockProtocolPrivate.h" +#include "ScmiPrivate.h" + +EFI_GUID gArmScmiClockProtocolGuid =3D ARM_SCMI_CLOCK_PROTOCOL_GUID; + +/** Convert to 64 bit value from two 32 bit words. + + @param[in] Low Lower 32 bits. + @param[in] High Higher 32 bits. + + @retval UINT64 64 bit value. +**/ +STATIC +UINT64 +ConvertTo64Bit ( + IN UINT32 Low, + IN UINT32 High + ) +{ + return (Low | ((UINT64)High << 32)); +} + +/** Return version of the clock management protocol supported by SCP firmw= are. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + + @param[out] Version Version of the supported SCMI Clock management prot= ocol. + + @retval EFI_SUCCESS The version is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockGetVersion ( + IN SCMI_CLOCK_PROTOCOL *This, + OUT UINT32 *Version + ) +{ + return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_CLOCK, Version); +} + +/** Return total number of clock devices supported by the clock management + protocol. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + + @param[out] TotalClocks Total number of clocks supported. + + @retval EFI_SUCCESS Total number of clocks supported is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockGetTotalClocks ( + IN SCMI_CLOCK_PROTOCOL *This, + OUT UINT32 *TotalClocks + ) +{ + EFI_STATUS Status; + UINT32 *ReturnValues; + + Status =3D ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_CLOCK, &ReturnVal= ues); + if (EFI_ERROR (Status)) { + return Status; + } + + *TotalClocks =3D SCMI_CLOCK_PROTOCOL_TOTAL_CLKS (ReturnValues[0]); + + return EFI_SUCCESS; +} + +/** Return attributes of a clock device. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + + @param[out] Enabled If TRUE, the clock device is enabled. + @param[out] ClockAsciiName A NULL terminated ASCII string with the clock + name, of up to 16 bytes. + + @retval EFI_SUCCESS Clock device attributes are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockGetClockAttributes ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + OUT BOOLEAN *Enabled, + OUT CHAR8 *ClockAsciiName + ) +{ + EFI_STATUS Status; + + UINT32 *MessageParams; + CLOCK_ATTRIBUTES *ClockAttributes; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageParams =3D ClockId; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_CLOCK; + Cmd.MessageId =3D SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES; + + PayloadLength =3D sizeof (ClockId); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + (UINT32**)&ClockAttributes + ); + if (EFI_ERROR (Status)) { + return Status; + } + // TRUE if bit 0 of ClockAttributes->Attributes is set. + *Enabled =3D CLOCK_ENABLED (ClockAttributes->Attributes); + + AsciiStrCpyS ( + ClockAsciiName, + SCMI_MAX_STR_LEN, + (CONST CHAR8*)ClockAttributes->ClockName + ); + + return EFI_SUCCESS; +} + +/** Return list of rates supported by a given clock device. + + @param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + + @param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device + supports range of clock rates which are non-line= ar. + + SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supp= orts + range of linear clock rates from Min to Max in s= teps. + + @param[out] TotalRates Total number of rates. + + @param[in,out] RateArraySize Size of the RateArray. + + @param[out] RateArray List of clock rates. + + @retval EFI_SUCCESS List of clock rates is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval EFI_BUFFER_TOO_SMALL RateArraySize is too small for the result. + It has been updated to the size needed. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockDescribeRates ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + OUT SCMI_CLOCK_RATE_FORMAT *Format, + OUT UINT32 *TotalRates, + IN OUT UINT32 *RateArraySize, + OUT SCMI_CLOCK_RATE *RateArray + ) +{ + EFI_STATUS Status; + + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + UINT32 *MessageParams; + CLOCK_DESCRIBE_RATES *DescribeRates; + CLOCK_RATE_DWORD *Rate; + + UINT32 RequiredArraySize =3D 0; + UINT32 RateIndex =3D 0; + UINT32 RateNo; + UINT32 RateOffset; + + *TotalRates =3D 0; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_CLOCK; + Cmd.MessageId =3D SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES; + + *MessageParams++ =3D ClockId; + + do { + + *MessageParams =3D RateIndex; + + // Set Payload length, note PayloadLength is a IN/OUT parameter. + PayloadLength =3D sizeof (ClockId) + sizeof (RateIndex); + + // Execute and wait for response on a SCMI channel. + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + (UINT32**)&DescribeRates + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (*TotalRates =3D=3D 0) { + // In the first iteration we will get number of returned rates and n= umber + // of remaining rates. With this information calculate required size + // for rate array. If provided RateArraySize is less, return an + // error. + + *Format =3D RATE_FORMAT (DescribeRates->NumRatesFlags); + + *TotalRates =3D NUM_RATES (DescribeRates->NumRatesFlags) + + NUM_REMAIN_RATES (DescribeRates->NumRatesFlags); + + if (*Format =3D=3D SCMI_CLOCK_RATE_FORMAT_DISCRETE) { + RequiredArraySize =3D (*TotalRates) * sizeof (UINT64); + } else { + // We need to return triplet of 64 bit value for each rate + RequiredArraySize =3D (*TotalRates) * 3 * sizeof (UINT64); + } + + if (RequiredArraySize > (*RateArraySize)) { + *RateArraySize =3D RequiredArraySize; + return EFI_BUFFER_TOO_SMALL; + } + } + + RateOffset =3D 0; + + if (*Format =3D=3D SCMI_CLOCK_RATE_FORMAT_DISCRETE) { + for (RateNo =3D 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags)= ; RateNo++) { + Rate =3D &DescribeRates->Rates[RateOffset++]; + // Non-linear discrete rates. + RateArray[RateIndex++].Rate =3D ConvertTo64Bit (Rate->Low, Rate->H= igh); + } + } else { + for (RateNo =3D 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags)= ; RateNo++) { + // Linear clock rates from minimum to maximum in steps + // Minimum clock rate. + Rate =3D &DescribeRates->Rates[RateOffset++]; + RateArray[RateIndex].Min =3D ConvertTo64Bit (Rate->Low, Rate->High= ); + + Rate =3D &DescribeRates->Rates[RateOffset++]; + // Maximum clock rate. + RateArray[RateIndex].Max =3D ConvertTo64Bit (Rate->Low, Rate->High= ); + + Rate =3D &DescribeRates->Rates[RateOffset++]; + // Step. + RateArray[RateIndex++].Step =3D ConvertTo64Bit (Rate->Low, Rate->H= igh); + } + } + } while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) !=3D 0); + + // Update RateArraySize with RequiredArraySize. + *RateArraySize =3D RequiredArraySize; + + return EFI_SUCCESS; +} + +/** Get clock rate. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + + @param[out] Rate Clock rate. + + @retval EFI_SUCCESS Clock rate is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockRateGet ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + OUT UINT64 *Rate + ) +{ + EFI_STATUS Status; + + UINT32 *MessageParams; + CLOCK_RATE_DWORD *ClockRate; + SCMI_COMMAND Cmd; + + UINT32 PayloadLength; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + // Fill arguments for clock protocol command. + *MessageParams =3D ClockId; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_CLOCK; + Cmd.MessageId =3D SCMI_MESSAGE_ID_CLOCK_RATE_GET; + + PayloadLength =3D sizeof (ClockId); + + // Execute and wait for response on a SCMI channel. + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + (UINT32**)&ClockRate + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *Rate =3D ((UINT64)ClockRate->High << 32) | ClockRate->Low; + + return EFI_SUCCESS; +} + +/** Set clock rate. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + @param[in] Rate Clock rate. + + @retval EFI_SUCCESS Clock rate set success. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockRateSet ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + IN UINT64 Rate + ) +{ + EFI_STATUS Status; + CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + + Status =3D ScmiCommandGetPayload ((UINT32**)&ClockRateSetAttributes); + if (EFI_ERROR (Status)) { + return Status; + } + + // Fill arguments for clock protocol command. + ClockRateSetAttributes->ClockId =3D ClockId; + ClockRateSetAttributes->Flags =3D CLOCK_SET_DEFAULT_FLAGS; + ClockRateSetAttributes->Rate.Low =3D (UINT32)Rate; + ClockRateSetAttributes->Rate.High =3D (UINT32)(Rate >> 32); + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_CLOCK; + Cmd.MessageId =3D SCMI_MESSAGE_ID_CLOCK_RATE_SET; + + PayloadLength =3D sizeof (CLOCK_RATE_SET_ATTRIBUTES); + + // Execute and wait for response on a SCMI channel. + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + NULL + ); + + return Status; +} + +// Instance of the SCMI clock management protocol. +STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol =3D { + ClockGetVersion, + ClockGetTotalClocks, + ClockGetClockAttributes, + ClockDescribeRates, + ClockRateGet, + ClockRateSet + }; + +/** Initialize clock management protocol and install protocol on a given h= andle. + + @param[in] Handle Handle to install clock management protoc= ol. + + @retval EFI_SUCCESS Clock protocol interface installed succes= sfully. +**/ +EFI_STATUS +ScmiClockProtocolInit ( + IN EFI_HANDLE* Handle + ) +{ + return gBS->InstallMultipleProtocolInterfaces ( + Handle, + &gArmScmiClockProtocolGuid, + &ScmiClockProtocol, + NULL + ); +} diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiDxe.c b/ArmPlatformPkg/D= rivers/ArmScmiDxe/ScmiDxe.c new file mode 100644 index 0000000000000000000000000000000000000000..b11d232d7e910f7ed0a165fb4e2= 2e207c2c3e607 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiDxe.c @@ -0,0 +1,135 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "ScmiPrivate.h" +#include "ScmiDxe.h" + +STATIC CONST SCMI_PROTOCOL_INIT_TABLE ProtocolInitFxns[MAX_PROTOCOLS] =3D { + { ScmiBaseProtocolInit }, + { NULL }, + { NULL }, + { ScmiPerformanceProtocolInit }, + { ScmiClockProtocolInit }, + { NULL } +}; + +/** ARM SCMI driver entry point function. + + This function installs the SCMI Base protocol and a list of other + protocols is queried using the Base protocol. If protocol is supported, + driver will call each protocol init function to install the protocol on + the ImageHandle. + + @param[in] ImageHandle Handle to this EFI Image which will be used to + install Base, Clock and Performance protocols. + @param[in] SystemTable A pointer to boot time system table. + + @retval EFI_SUCCESS Driver initalized successfully. + @retval EFI_UNSUPPORTED If SCMI base protocol version is not supported. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +EFIAPI +ArmScmiDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SCMI_BASE_PROTOCOL *BaseProtocol; + UINT32 Version; + UINT32 Index; + UINT32 NumProtocols; + UINT32 ProtocolNo; + UINT8 SupportedList[MAX_PROTOCOLS]; + UINT32 SupportedListSize =3D sizeof (SupportedList); + + ProtocolNo =3D SCMI_PROTOCOL_ID_BASE & PROTOCOL_ID_MASK; + + // Every SCMI implementation must implement the base protocol. + Status =3D ProtocolInitFxns[ProtocolNo].Init (&ImageHandle); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + Status =3D gBS->LocateProtocol ( + &gArmScmiBaseProtocolGuid, + NULL, + (VOID**)&BaseProtocol + ); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + // Get SCMI Base protocol version. + Status =3D BaseProtocol->GetVersion (BaseProtocol, &Version); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + if (Version !=3D BASE_PROTOCOL_VERSION) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // Apart from Base protocol, SCMI may implement various other protocols, + // query total protocols implemented by the SCP firmware. + NumProtocols =3D 0; + Status =3D BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + ASSERT (NumProtocols !=3D 0); + + // Get the list of protocols supported by SCP firmware on the platform. + Status =3D BaseProtocol->DiscoverListProtocols ( + BaseProtocol, + &SupportedListSize, + SupportedList + ); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + // Install supported protocol on ImageHandle. + for (Index =3D 0; Index < NumProtocols; Index++) { + ProtocolNo =3D SupportedList[Index] & PROTOCOL_ID_MASK; + if (ProtocolInitFxns[ProtocolNo].Init !=3D NULL) { + Status =3D ProtocolInitFxns[ProtocolNo].Init (&ImageHandle); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + } + } + + return EFI_SUCCESS; +} diff --git a/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c b/= ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c new file mode 100644 index 0000000000000000000000000000000000000000..3946dc21005430c430605bf60fb= 40fb99e2a0178 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c @@ -0,0 +1,457 @@ +/** @file + + Copyright (c) 2017, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include + +#include "ArmScmiPerformanceProtocolPrivate.h" +#include "ScmiPrivate.h" + +EFI_GUID gArmScmiPerformanceProtocolGuid =3D ARM_SCMI_PERFORMANCE_PROTOCOL= _GUID; + +/** Return version of the performance management protocol supported by SCP. + firmware. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + + @param[out] Version Version of the supported SCMI performance manageme= nt + protocol. + + @retval EFI_SUCCESS The version is returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +PerformanceGetVersion ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + OUT UINT32 *Version + ) +{ + return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_PERFORMANCE, Version); +} + +/** Return protocol attributes of the performance management protocol. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + + @param[out] Attributes Protocol attributes. + + @retval EFI_SUCCESS Protocol attributes are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +PerformanceGetAttributes ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes + ) +{ + EFI_STATUS Status; + UINT32* ReturnValues; + + Status =3D ScmiGetProtocolAttributes ( + SCMI_PROTOCOL_ID_PERFORMANCE, + &ReturnValues + ); + if (EFI_ERROR (Status)) { + return Status; + } + + memcpy ( + Attributes, + ReturnValues, + sizeof (SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES) + ); + + return EFI_SUCCESS; +} + +/** Return performance domain attributes. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] Attributes Performance domain attributes. + + @retval EFI_SUCCESS Domain attributes are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +PerformanceDomainAttributes ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes + ) +{ + EFI_STATUS Status; + UINT32 *MessageParams; + UINT32 *ReturnValues; + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageParams =3D DomainId; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_PERFORMANCE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES; + + PayloadLength =3D sizeof (DomainId); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + &ReturnValues + ); + if (EFI_ERROR (Status)) { + return Status; + } + + memcpy ( + DomainAttributes, + ReturnValues, + sizeof (SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES) + ); + + return EFI_SUCCESS; +} + +/** Return list of performance domain levels of a given domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] NumLevels Total number of levels a domain can support. + + @param[in,out] LevelArraySize Size of the performance level array. + + @param[out] LevelArray Array of the performance levels. + + @retval EFI_SUCCESS Domain levels are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval EFI_BUFFER_TOO_SMALL LevelArraySize is too small for the result. + It has been updated to the size needed. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +PerformanceDescribeLevels ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + OUT UINT32 *NumLevels, + IN OUT UINT32 *LevelArraySize, + OUT SCMI_PERFORMANCE_LEVEL *LevelArray + ) +{ + EFI_STATUS Status; + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + UINT32* MessageParams; + UINT32 LevelIndex; + UINT32 RequiredSize; + UINT32 LevelNo; + + PERF_DESCRIBE_LEVELS *Levels; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + LevelIndex =3D 0; + RequiredSize =3D 0; + + *MessageParams++ =3D DomainId; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_PERFORMANCE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS; + + do { + + *MessageParams =3D LevelIndex; + + // Note, PayloadLength is an IN/OUT parameter. + PayloadLength =3D sizeof (DomainId) + sizeof (LevelIndex); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + (UINT32**)&Levels + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (RequiredSize =3D=3D 0) { + *NumLevels =3D NUM_PERF_LEVELS (Levels->NumLevels) + + NUM_REMAIN_PERF_LEVELS (Levels->NumLevels); + RequiredSize =3D (*NumLevels) * sizeof (SCMI_PERFORMANCE_LEVEL); + + if (RequiredSize > (*LevelArraySize)) { + // Update LevelArraySize with required size. + *LevelArraySize =3D RequiredSize; + return EFI_BUFFER_TOO_SMALL; + } + } + + for (LevelNo =3D 0; + LevelNo < NUM_PERF_LEVELS (Levels->NumLevels); + LevelNo++) { + memcpy ( + &LevelArray[LevelIndex++], + &Levels->PerfLevel[LevelNo], + sizeof (SCMI_PERFORMANCE_LEVEL) + ); + } + + } while (NUM_REMAIN_PERF_LEVELS (Levels->NumLevels) !=3D 0); + + *LevelArraySize =3D RequiredSize; + + return EFI_SUCCESS; +} + +/** Set performance limits of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + @param[in] Limit Performance limit to set. + + @retval EFI_SUCCESS Performance limits set successfully. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +PerformanceLimitsSet ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + IN SCMI_PERFORMANCE_LIMITS *Limits + ) +{ + EFI_STATUS Status; + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + UINT32 *MessageParams; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageParams++ =3D DomainId; + *MessageParams++ =3D Limits->RangeMax; + *MessageParams =3D Limits->RangeMin; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_PERFORMANCE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET; + + PayloadLength =3D sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + NULL + ); + + return Status; +} + +/** Get performance limits of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] Limit Performance Limits of the domain. + + @retval EFI_SUCCESS Performance limits are returned. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +PerformanceLimitsGet ( + SCMI_PERFORMANCE_PROTOCOL *This, + UINT32 DomainId, + SCMI_PERFORMANCE_LIMITS *Limits + ) +{ + EFI_STATUS Status; + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + UINT32 *MessageParams; + + SCMI_PERFORMANCE_LIMITS *ReturnValues; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageParams =3D DomainId; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_PERFORMANCE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET; + + PayloadLength =3D sizeof (DomainId); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + (UINT32**)&ReturnValues + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Limits->RangeMax =3D ReturnValues->RangeMax; + Limits->RangeMin =3D ReturnValues->RangeMin; + + return EFI_SUCCESS; +} + +/** Set performance level of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + @param[in] Level Performance level of the domain. + + @retval EFI_SUCCESS Performance level set successfully. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +PerformanceLevelSet ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + IN UINT32 Level + ) +{ + EFI_STATUS Status; + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + UINT32 *MessageParams; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageParams++ =3D DomainId; + *MessageParams =3D Level; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_PERFORMANCE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET; + + PayloadLength =3D sizeof (DomainId) + sizeof (Level); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + NULL + ); + + return Status; +} + +/** Get performance level of a domain. + + @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance. + @param[in] DomainId Identifier for the performance domain. + + @param[out] Level Performance level of the domain. + + @retval EFI_SUCCESS Performance level got successfully. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +EFI_STATUS +PerformanceLevelGet ( + IN SCMI_PERFORMANCE_PROTOCOL *This, + IN UINT32 DomainId, + OUT UINT32 *Level + ) +{ + EFI_STATUS Status; + UINT32 PayloadLength; + SCMI_COMMAND Cmd; + UINT32 *ReturnValues; + UINT32 *MessageParams; + + Status =3D ScmiCommandGetPayload (&MessageParams); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageParams =3D DomainId; + + Cmd.ProtocolId =3D SCMI_PROTOCOL_ID_PERFORMANCE; + Cmd.MessageId =3D SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET; + + PayloadLength =3D sizeof (DomainId); + + Status =3D ScmiCommandExecute ( + &Cmd, + &PayloadLength, + &ReturnValues + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *Level =3D *ReturnValues; + + return EFI_SUCCESS; +} + +// Instance of the SCMI performance management protocol. +STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol =3D { + PerformanceGetVersion, + PerformanceGetAttributes, + PerformanceDomainAttributes, + PerformanceDescribeLevels, + PerformanceLimitsSet, + PerformanceLimitsGet, + PerformanceLevelSet, + PerformanceLevelGet +}; + +/** Initialize performance management protocol and install on a given Hand= le. + + @param[in] Handle Handle to install performance management + protocol. + + @retval EFI_SUCCESS Performance protocol installed successful= ly. +**/ +EFI_STATUS +ScmiPerformanceProtocolInit ( + IN EFI_HANDLE* Handle + ) +{ + return gBS->InstallMultipleProtocolInterfaces ( + Handle, + &gArmScmiPerformanceProtocolGuid, + &PerformanceProtocol, + NULL + ); +} --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") --===============2861417563010324147== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel --===============2861417563010324147==--