From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513075105282389.0877190460923; Tue, 12 Dec 2017 02:38:25 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BCB98220EE10F; Tue, 12 Dec 2017 02:33:45 -0800 (PST) Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3906421B02825 for ; Tue, 12 Dec 2017 02:33:43 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id o2so20598044wro.5 for ; Tue, 12 Dec 2017 02:38:21 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:16 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3VswnviTEPXlAq8N1iExsXHH82qIEwaGOOgQ5L8fIt4=; b=PXxxdweK9aGbHya/yDIoFvVIyQbSAPenKCHPUKf+2jIrSG6pMhFsAMOvrjKs3VlGWO azzfGT6YuEY2wx3CyP8PZLUoeeJQ416LbWRGEys7Q/c5P56aKtNZ19TiGbxCL4jy5uPm GIkSlmI95hYgTKtDniRs5ISCNvkf0Eq6fHtug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3VswnviTEPXlAq8N1iExsXHH82qIEwaGOOgQ5L8fIt4=; b=tt6xFNAKVF+zXD3FOQoBZHaKNUne40q2X6EpY6+xOQBSMBmECgk0Jt+z/pCDS1fQ+4 masMbO6/pfmXkF70Qvzeu7JXpaBDg9+n/4zoTJX7CVcFlYY8JXBTtrG7s8EKgOZZN6Xd 9aaIvUscKzEt8fuiNDaUBDYtYUqG0mjVi76EuqeDOgUxz17NhKKBaTEDedQgPgCVJ4IW SN7gHoid0KFjLNCKP/RGjalZ9ucPGPzNXnCxJbTtoHcRBVgtVBskWPd5q768Prrr9HNY NTz82RjNUbpa2bNbbEPKbvPOx7Nniwv2lBTUvFxLQHqOB34LTLpWfh1vJQQ2xKnBddOW yYBg== X-Gm-Message-State: AKGB3mJVDjMqbiOQGmawHkayt5xtg9fydPyNDD/f+GE56Wo63ydWVslL cBsjIjOstb1/YFc/ZYZCZ5UZuodW0gU= X-Google-Smtp-Source: ACJfBottGBZXc8uIZin1Mfb477kp9NqSw7+acH2zJHrhcPbaB+LfAqONfCqdsk0dQk6kZ0tWMBo/IA== X-Received: by 10.223.150.175 with SMTP id u44mr3531195wrb.115.1513075097095; Tue, 12 Dec 2017 02:38:17 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:00 +0000 Message-Id: <20171212103807.18836-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/8] Silicon/SynQuacer: enable CPU idle states in device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" It appears that whatever was preventing us from using CPU idle with PSCI low power states has disappeared, so let's enable the low power states in the DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 48 ++++++++++-----= ----- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index ec784c70afe7..c9fee5d1f350 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -47,168 +47,168 @@ compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x0>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x1>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2: cpu@100 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x100>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3: cpu@101 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x101>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4: cpu@200 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x200>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5: cpu@201 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x201>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6: cpu@300 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x300>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7: cpu@301 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x301>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU8: cpu@400 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x400>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU9: cpu@401 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x401>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU10: cpu@500 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x500>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU11: cpu@501 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x501>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU12: cpu@600 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x600>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU13: cpu@601 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x601>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU14: cpu@700 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x700>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU15: cpu@701 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x701>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU16: cpu@800 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x800>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU17: cpu@801 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x801>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU18: cpu@900 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x900>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU19: cpu@901 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0x901>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU20: cpu@a00 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0xa00>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU21: cpu@a01 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0xa01>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU22: cpu@b00 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0xb00>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU23: cpu@b01 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53","arm,armv8"; reg =3D <0xb01>; enable-method =3D "psci"; - //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; =20 cpu-map { --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513075103818179.2529810476534; Tue, 12 Dec 2017 02:38:23 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 78287220EE10B; Tue, 12 Dec 2017 02:33:44 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A0D6C21B02825 for ; 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Tue, 12 Dec 2017 02:38:19 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:01 +0000 Message-Id: <20171212103807.18836-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/8] Platform/Socionext/SynQuacer: expose build number as firmware version X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Expose the contents of the .DSC macro BUILD_NUMBER via the PCD gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString (if > 1), and as the FMP system firmware version (for capsule update). Also, set the firmware vendor to 'Linaro Enterprise Group', to distinguish our builds from builds by other parties. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc = | 8 +++++++- Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDes= criptor.inf | 1 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDes= criptorTable.aslc | 6 ++++-- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc = | 8 +++++++- Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmw= areDescriptor.inf | 1 + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmw= areDescriptorTable.aslc | 6 ++++-- 6 files changed, 24 insertions(+), 6 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 8fbd7b2d908f..5ec26f9cdd34 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -26,6 +26,7 @@ [Defines] BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Platform/Socionext/DeveloperBox/Devel= operBox.fdf + BUILD_NUMBER =3D 1 =20 [BuildOptions] RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_S= OURCE=3D0 @@ -222,7 +223,7 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE =20 [PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Linaro Enterprise Gro= up" =20 # non-secure SRAM gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 @@ -384,6 +385,11 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the vars= tore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 =20 +!if $(BUILD_NUMBER) > 1 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER= )" +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 diff --git a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/Syste= mFirmwareDescriptor.inf b/Platform/Socionext/DeveloperBox/SystemFirmwareDes= criptor/SystemFirmwareDescriptor.inf index f5272c0f0d37..95a5e482a713 100644 --- a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwa= reDescriptor.inf +++ b/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwa= reDescriptor.inf @@ -38,6 +38,7 @@ [LibraryClasses] =20 [FixedPcd] gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision =20 [Pcd] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor diff --git a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/Syste= mFirmwareDescriptorTable.aslc b/Platform/Socionext/DeveloperBox/SystemFirmw= areDescriptor/SystemFirmwareDescriptorTable.aslc index bc47e696da7a..fb69de078313 100644 --- a/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwa= reDescriptorTable.aslc +++ b/Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwa= reDescriptorTable.aslc @@ -21,8 +21,10 @@ #define PACKAGE_VERSION 0xFFFFFFFF #define PACKAGE_VERSION_STRING L"Unknown" =20 -#define CURRENT_FIRMWARE_VERSION 0x00000001 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000001" +#define __BUILD_STRING(x) L ## #x +#define BUILD_STRING(x) L"build #" __BUILD_STRING(x) +#define CURRENT_FIRMWARE_VERSION FixedPcdGet32 (PcdFirmwareRevi= sion) +#define CURRENT_FIRMWARE_VERSION_STRING BUILD_STRING (FixedPcdGet32 (P= cdFirmwareRevision)) #define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 =20 #define IMAGE_ID SIGNATURE_64('S', 'N', 'D', 'E= ', 'V', 'B', 'O', 'X') diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 895d3b09fdc9..bc8ddd452d4b 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -26,6 +26,7 @@ [Defines] BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Platform/Socionext/SynQuacerEvalBoard= /SynQuacerEvalBoard.fdf + BUILD_NUMBER =3D 1 =20 [BuildOptions] RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_S= OURCE=3D0 @@ -214,7 +215,7 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE =20 [PcdsFixedAtBuild.common] - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Linaro Enterprise Gro= up" =20 # non-secure SRAM gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 @@ -372,6 +373,11 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the vars= tore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 =20 +!if $(BUILD_NUMBER) > 1 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER= )" +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 diff --git a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor= /SystemFirmwareDescriptor.inf b/Platform/Socionext/SynQuacerEvalBoard/Syste= mFirmwareDescriptor/SystemFirmwareDescriptor.inf index f5272c0f0d37..95a5e482a713 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/System= FirmwareDescriptor.inf +++ b/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/System= FirmwareDescriptor.inf @@ -38,6 +38,7 @@ [LibraryClasses] =20 [FixedPcd] gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision =20 [Pcd] gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor diff --git a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor= /SystemFirmwareDescriptorTable.aslc b/Platform/Socionext/SynQuacerEvalBoard= /SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc index 3413f76f95c7..daf26c79dff1 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/System= FirmwareDescriptorTable.aslc +++ b/Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/System= FirmwareDescriptorTable.aslc @@ -21,8 +21,10 @@ #define PACKAGE_VERSION 0xFFFFFFFF #define PACKAGE_VERSION_STRING L"Unknown" =20 -#define CURRENT_FIRMWARE_VERSION 0x00000001 -#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000001" +#define __BUILD_STRING(x) L ## #x +#define BUILD_STRING(x) L"build #" __BUILD_STRING(x) +#define CURRENT_FIRMWARE_VERSION FixedPcdGet32 (PcdFirmwareRevi= sion) +#define CURRENT_FIRMWARE_VERSION_STRING BUILD_STRING (FixedPcdGet32 (P= cdFirmwareRevision)) #define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 =20 #define IMAGE_ID SIGNATURE_64('S', 'N', 'I', 'S= ', 'Y', 'N', 'Q', 'U') --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513075107529356.8927488196707; Tue, 12 Dec 2017 02:38:27 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 07899220EE111; Tue, 12 Dec 2017 02:33:46 -0800 (PST) Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 167D621B02832 for ; Tue, 12 Dec 2017 02:33:44 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id q9so20586997wre.7 for ; Tue, 12 Dec 2017 02:38:23 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:21 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KSsqfg8scmXSSTjNPYjvYQRQBTDdn798CCzXzjKRz1A=; b=V76rLpFzrLbqwjRVFGpH647CQ9PpSP7JdZcdJcosC7vh0fFWIiWuwse1sgP+Dd3jtx r1deuKI3yUiLfVyO5fJ9Al0ixVnlJuDPJVKiFrlYWm+LGd3eDs9SUxKalYpfMfZ37jU8 ZLvxaaZKUMbzasQQGpggL6RLec9Eif5+PVlAE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KSsqfg8scmXSSTjNPYjvYQRQBTDdn798CCzXzjKRz1A=; b=OV4TrV9G6reN4A/rJRxieqxhwbyjHSz4tFetddDca1WmXWC3tMe8QvugYTuiCm6yNs IlILNss1tn/d1qDedeWS5SHoQ5/RDmx25BJI0g4TRE6a7J54G7x/WBZLMSm0qj+vlvgW RVvuDuugdLAhY0QcHrKa2b/XgNPflCf0PrtgfglwLVWiQt4b8/IcdAmc9rI/ilyVDyc2 Gbsm67WcABYDfvX6j8GgmYzGxdBbgpxpDoOscvn5bk9uf5h0rdnGrbySkGw8qVmaGen/ sJqxyJG9kSeOpvEIsO4ZFQs/pI/ooZN+r66VQqX/dFz65EOCJLzKXKR8JnLPXPl4k1xr W5wA== X-Gm-Message-State: AKGB3mLtOdAK6COmya9ALLDffPmMCkHrK0GZEmtgSShChhNC/o5eGqLS yeaLYoLWVtGySjD+kjxurrN8hZKdZ+g= X-Google-Smtp-Source: ACJfBotq0RvVTurgVdbrIR/9RrGE3AkzIshyAkQ/0WCxX+1BtZzFIDIOcCmJ7BBD5mH+KU1EEO1KxQ== X-Received: by 10.223.136.38 with SMTP id d35mr3439705wrd.36.1513075101897; Tue, 12 Dec 2017 02:38:21 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:02 +0000 Message-Id: <20171212103807.18836-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/8] Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST# X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Attempt to adhere more closely to the PCIe spec by ensuring that PERST# remains asserted for at least 100 ms. Give it a good margin, and delay for 150 ms; the additional boot time delay is not going to be noticeable by anyone anyway. So split the init routine in a pre and post part, and put the delay in the middle so we only need to do it once. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLib.inf | 1 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLibConstructor.c | 46 +++++++++++++++----- 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuac= erPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 08484f4f8b1a..5d87727c73ba 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf @@ -45,6 +45,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + UefiBootServicesTableLib =20 [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Librar= y/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e63b3a4bb23b..3da94945f96a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include =20 @@ -176,6 +177,8 @@ SnPcieSetData ( } =20 MmioWrite32 (Base + Offset, Data); + + ArmDataMemoryBarrier (); } =20 STATIC @@ -194,6 +197,8 @@ SnPcieReadData ( Shift++; } =20 + ArmDataMemoryBarrier (); + return (MmioRead32 (Base + Offset) >> Shift) & Mask; } =20 @@ -219,12 +224,8 @@ SnDbiRoWrEn ( =20 STATIC VOID -PciInitController ( - IN EFI_PHYSICAL_ADDRESS ExsBase, - IN EFI_PHYSICAL_ADDRESS DbiBase, - IN EFI_PHYSICAL_ADDRESS ConfigBase, - IN EFI_PHYSICAL_ADDRESS IoMemBase, - IN CONST PCI_ROOT_BRIDGE *RootBridge +PciInitControllerPre ( + IN EFI_PHYSICAL_ADDRESS ExsBase ) { SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0); @@ -256,7 +257,18 @@ PciInitController ( =20 // 3: Set device_type (RC) SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4); +} =20 +STATIC +VOID +PciInitControllerPost ( + IN EFI_PHYSICAL_ADDRESS ExsBase, + IN EFI_PHYSICAL_ADDRESS DbiBase, + IN EFI_PHYSICAL_ADDRESS ConfigBase, + IN EFI_PHYSICAL_ADDRESS IoMemBase, + IN CONST PCI_ROOT_BRIDGE *RootBridge + ) +{ // 4: Set Bifurcation 1=3Ddisable 4=3Dable // 5: Supply Reference (It has executed) // 6: Wait for 10usec (Reference Clocks is stable) @@ -389,11 +401,23 @@ SynQuacerPciHostBridgeLibConstructor ( } =20 for (Idx =3D 0; Idx < Count; Idx++) { - PciInitController (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } + + // + // The PCIe spec requires that PERST# is asserted for at least 100 ms af= ter + // the power and clocks have become stable. So let's give a bit or margi= n, + // and stall for 150 ms between asserting PERST# on both controllers and + // de-asserting it again. + // + gBS->Stall (150 * 1000); + + for (Idx =3D 0; Idx < Count; Idx++) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &RootBridges[Idx]); } =20 return EFI_SUCCESS; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513075112184198.11365298858334; Tue, 12 Dec 2017 02:38:32 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 482EA220EE10D; Tue, 12 Dec 2017 02:33:49 -0800 (PST) Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90E5221A1099A for ; Tue, 12 Dec 2017 02:33:47 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id v22so20613913wrb.0 for ; Tue, 12 Dec 2017 02:38:26 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:23 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bTc5NTsvQOhQTmLQ79mDAauv6Ow4Y56JpzkqRRIqdDo=; b=U/iQDIGceXmC2wREJwHCfOLktnkUnSJelpGwpeWgGUKnhIavovtKMHAkt0GcbPbiSl nXPBi2IIzeDPNLeQ8v3NTV5ga+tSIqtXaz75mDqoZ5+UvG6DZVERR3Iac+/dfDwaF3Wv ogUEHhNPVk6YzO4gaR6oxU3K8gIT34BmKGG/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bTc5NTsvQOhQTmLQ79mDAauv6Ow4Y56JpzkqRRIqdDo=; b=K0sFXvqU/3eGb+YzCSiW2/g41t9/OoklesWL1dofJnhk7RdcpHvFov1isg7RbiPZTd EjHlnrgPuuNsjgxgBDcBshzbIN1acg6D4zsYeRpf2nsjS3Rx4AmlwcOYqvo6v+Vs11xv 3UxP3xp6S8uN/Xppo5/GkC2opv5qtgJ0MiKAYlbavIJZ0IHIanSu+YxZzADow5BEJY6b VTeZo3vv7G0DFGkIvw0f4qfxhlcAtruUuRzQIcBilWDP5RfVljztxRu4jeSgEykXnRN0 Qesd5tfB+Rqf5ZFS9PpEvwHlRWuUzjTpkz+1v1PY8J+AnKBEMBSKx7RGT63Vdvspv8M0 GivA== X-Gm-Message-State: AKGB3mIY0XGIVj8hJs98DZAQA6mqCtd7ijFIfpiRNi2Qbz3ItHF4CRVz a3D56wrUdRTSHOVjfKJiYm46nse/uq4= X-Google-Smtp-Source: ACJfBosGJ1q/XXfy5UVB03az7UPqELKGNkLW0dXiiGDg0MNCUMT4hmEN3TgpBusPdgHOyXPDUmRKFw== X-Received: by 10.223.195.136 with SMTP id p8mr3654182wrf.4.1513075104383; Tue, 12 Dec 2017 02:38:24 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:03 +0000 Message-Id: <20171212103807.18836-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/8] Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to accommodate the EVB, whose PCIe RC #0 should not be touched by software if no card is inserted, add a PCD that tells the PCIe driver code which RCs should be initialized and exposed to the PCI host bridge driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLib.c | 19 ++++++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLib.inf | 3 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLibConstructor.c | 30 +++++++++----------- Silicon/Socionext/SynQuacer/SynQuacer.dec = | 4 +++ 4 files changed, 36 insertions(+), 20 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacer= PciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 42cdce24b2c4..596862baf469 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.c @@ -92,7 +92,7 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { #define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PM= EM #endif =20 -STATIC PCI_ROOT_BRIDGE mPciRootBridges[] =3D { +PCI_ROOT_BRIDGE mPciRootBridges[] =3D { { 0, // Segment 0, // Supports @@ -149,9 +149,20 @@ PciHostBridgeGetRootBridges ( OUT UINTN *Count ) { - *Count =3D ARRAY_SIZE (mPciRootBridges); - - return mPciRootBridges; + switch (PcdGet8 (PcdPcieEnableMask)) { + default: + ASSERT (FALSE); + case 0x0: + *Count =3D 0; + return NULL; + case 0x1: + case 0x2: + *Count =3D 1; + return &mPciRootBridges[PcdGet8 (PcdPcieEnableMask) - 1]; + case 0x3: + *Count =3D ARRAY_SIZE (mPciRootBridges); + return mPciRootBridges; + } } =20 /** diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuac= erPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 5d87727c73ba..27fcba034418 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLib.inf @@ -49,3 +49,6 @@ [LibraryClasses] =20 [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation + +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Librar= y/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 3da94945f96a..bea40e3dcfe8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c @@ -120,6 +120,8 @@ #define MISC_CONTROL_1_OFF 0x8BC #define DBI_RO_WR_EN BIT0 =20 +extern PCI_ROOT_BRIDGE mPciRootBridges[]; + STATIC VOID ConfigureWindow ( @@ -390,18 +392,12 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - PCI_ROOT_BRIDGE *RootBridges; - UINTN Count; UINTN Idx; =20 - RootBridges =3D PciHostBridgeGetRootBridges (&Count); - ASSERT (Count =3D=3D ARRAY_SIZE(mBaseAddresses)); - if (Count !=3D ARRAY_SIZE(mBaseAddresses)) { - return EFI_INVALID_PARAMETER; - } - - for (Idx =3D 0; Idx < Count; Idx++) { - PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + for (Idx =3D 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } } =20 // @@ -412,12 +408,14 @@ SynQuacerPciHostBridgeLibConstructor ( // gBS->Stall (150 * 1000); =20 - for (Idx =3D 0; Idx < Count; Idx++) { - PciInitControllerPost (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + for (Idx =3D 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &mPciRootBridges[Idx]); + } } =20 return EFI_SUCCESS; diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index 02dd6ac417f9..2e18cb33346d 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -38,3 +38,7 @@ [PcdsFixedAtBuild] gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 =20 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005 + +[PcdsPatchableInModule, PcdsDynamic] + # Enable both RC #0 and RC #1 by default + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 12 Dec 2017 02:38:25 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3TL11bag/iZYHBcdSH5KCpn14J17x6tyE5z4O+tavlw=; b=fqR5O+5gzjsWUkBFGxQdoVWYa/Pt/27gK8DSDpkb/2wEbet0E07gjvRMrQfO9v8O5L WEL7XWm/KBNg76wq2ftVJG/3chsYfoM1OE1b91YmHedT98XSHrOTo7FzflJgMZWG4Qkv LVZbTmARL9fC7QlQgfu6Xn/1yMPW5mtVivzwg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3TL11bag/iZYHBcdSH5KCpn14J17x6tyE5z4O+tavlw=; b=V915iPRuiOfcJeXRPKuAp7u63RNQS2N1wNilFbk1XXh1q3/qh2UdeZEN/B6OclffwU ydj/txOBpUBvn8oGJalJ97DsjY4NaiYhMo/+/gag66xqFdgHeHg81CxLpR/0f5NeJrT7 V9p6/pZShbdY1bnFHOwrwyEhRpVhuF4u1C3lu68VNg08UsdUpiruqi8PwWykas525TId E5Flqwbmpe8uTqKmB+vbFfKc580JaMqIsr+ZNn0zNovJBDjJh51hhh3WETnG69KBXKqP +0kRqWSPsCKBmA88XPDrr1yQMlqKfkGOGQm5KVVlOvHOE/RxtlQSJtuxeq3enVj84g1W koPg== X-Gm-Message-State: AKGB3mIkRHqcGQJTeyGHvO5gIvIvQLwQHaiZ1WYRdU9KcNeWZA/CJJvc GEehf9pk0FD5cixaZPjIw5XIUt6DT2s= X-Google-Smtp-Source: ACJfBotgL/x1eIGIoOoTARBN6s2l/13QdFgD7Ddn+rkwgvDVnkRFKExwcwOYnqKm6ESyD97MNZLXqQ== X-Received: by 10.223.156.202 with SMTP id h10mr1700685wre.174.1513075106702; Tue, 12 Dec 2017 02:38:26 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:04 +0000 Message-Id: <20171212103807.18836-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 5/8] Silicon/SynQuacer: disable PCI RC #0 DT node if disabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If PCIe RC #0 is not enabled (due to the fact that the slot is not populated), set its DT node 'status' property to 'disabled' so that the OS will not attempt to attach to it. This means we will need to switch from the default DtPlatformDtbLoaderLib to a special one for our platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc = | 8 +- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc = | 3 +- Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoad= erLib.c | 94 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoad= erLib.inf | 42 +++++++++ 4 files changed, 141 insertions(+), 6 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 5ec26f9cdd34..80728fedbc20 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -160,7 +160,8 @@ [LibraryClasses.common.DXE_CORE] PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf =20 [LibraryClasses.common.DXE_DRIVER] - DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa= ult/DxeDtPlatformDtbLoaderLibDefault.inf + DtPlatformDtbLoaderLib|Silicon/Socionext/SynQuacer/Library/SynQuacerDtbL= oaderLib/SynQuacerDtbLoaderLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf =20 @@ -611,10 +612,7 @@ [Components.common] # # Console preference selection # - EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf { - - FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf - } + EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf =20 # # DT support diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index bc8ddd452d4b..c71425664bdc 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -159,7 +159,8 @@ [LibraryClasses.common.DXE_CORE] PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf =20 [LibraryClasses.common.DXE_DRIVER] - DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa= ult/DxeDtPlatformDtbLoaderLibDefault.inf + DtPlatformDtbLoaderLib|Silicon/Socionext/SynQuacer/Library/SynQuacerDtbL= oaderLib/SynQuacerDtbLoaderLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf =20 diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQ= uacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoade= rLib/SynQuacerDtbLoaderLib.c new file mode 100644 index 000000000000..a93a6027e64d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.c @@ -0,0 +1,94 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include + +#define DTB_PADDING 64 + +STATIC +VOID +DisableDtNode ( + IN VOID *Dtb, + IN CONST CHAR8 *NodePath + ) +{ + INT32 Node; + INT32 Rc; + + Node =3D fdt_path_offset (Dtb, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Node))); + return; + } + Rc =3D fdt_setprop_string (Dtb, Node, "status", "disabled"); + if (Rc < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': = %a\n", + __FUNCTION__, NodePath, fdt_strerror (Rc))); + } +} + +/** + Return a pool allocated copy of the DTB image that is appropriate for + booting the current platform via DT. + + @param[out] Dtb Pointer to the DTB copy + @param[out] DtbSize Size of the DTB copy + + @retval EFI_SUCCESS Operation completed successfully + @retval EFI_NOT_FOUND No suitable DTB image could be locat= ed + @retval EFI_OUT_OF_RESOURCES No pool memory available + +**/ +EFI_STATUS +EFIAPI +DtPlatformLoadDtb ( + OUT VOID **Dtb, + OUT UINTN *DtbSize + ) +{ + EFI_STATUS Status; + VOID *OrigDtb; + VOID *CopyDtb; + UINTN OrigDtbSize; + + Status =3D GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, + EFI_SECTION_RAW, 0, &OrigDtb, &OrigDtbSize); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + CopyDtb =3D AllocateCopyPool (OrigDtbSize + DTB_PADDING, OrigDtb); + if (CopyDtb =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { + DisableDtNode (CopyDtb, "/pcie@60000000"); + } + if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { + DisableDtNode (CopyDtb, "/pcie@70000000"); + } + + *Dtb =3D CopyDtb; + *DtbSize =3D OrigDtbSize + DTB_PADDING; + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQ= uacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoa= derLib/SynQuacerDtbLoaderLib.inf new file mode 100644 index 000000000000..e1f564f73078 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.inf @@ -0,0 +1,42 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SynQuacerDtbLoaderLib + FILE_GUID =3D 59df69c4-8724-4e49-8974-d0691364338c + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D DtPlatformDtbLoaderLib|DXE_DRIVER + +[Sources] + SynQuacerDtbLoaderLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + BaseLib + DebugLib + DxeServicesLib + FdtLib + MemoryAllocationLib + +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask + +[Guids] + gDtPlatformDefaultDtbFileGuid --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513075115568770.8018802159419; Tue, 12 Dec 2017 02:38:35 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C195C220EE119; Tue, 12 Dec 2017 02:33:52 -0800 (PST) Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA6BC220EE115 for ; Tue, 12 Dec 2017 02:33:51 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id x49so20562434wrb.13 for ; Tue, 12 Dec 2017 02:38:30 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:27 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PU7ms/RrRVJMKOJrexx0EuB55mzzfnUUIroAJi4CSqY=; b=akSdxwqzUugnEqQbLOIMDNr9IKV2vo+VCWY8nWoczdD+bw6UNSQvZ3tRgfrRT/11e8 0Aq9mYkIeb9bN5HoclRq4eoFitAazUhXdq+2JEBiRLYofY03TXVr6vPonBX138rQJRGx Q6uWer02cRAIuczaerN3dWH4bRDtLUqOypZ5o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PU7ms/RrRVJMKOJrexx0EuB55mzzfnUUIroAJi4CSqY=; b=Gjkk9oMZ2Ydk7Z+animfgB2gI04Om+TfsW+OLAow67xdYqmZFVX/c3w8ubm0n7Yfpr 12uFGG84LHHirYcC/Y/7BxkOpNuIVXXi/CYMrHZwan3fd5Y+FSSFDTCSrv+YZVpDW2ev vu1UBAWWmel6pWxrpRU2NKHMGWkSZVgoGzYPUoq1vn+YriuPXU3ngaBi7u6b4zvMiFbk myX8pt8kKZwLc7LUXU1rnXagAbMbbl8NjVScRQ6EF2cFMF4RnkKcUWPzsomWb5WAvCc3 HKiEt94PZ1u1PA4vU8P8aPot8mYiNv/PbGFRXpwS38R9mAhBRlcII8EUf2e8HnoUNXPq /nIA== X-Gm-Message-State: AKGB3mIDoWq+QY6dVTK+mZY6oovHoIy2sBqBwShiQqBrtUm/AMsOhOwV pd9cGr66ZNj1i+Eok97H8rFCh0zo4CA= X-Google-Smtp-Source: ACJfBotTjVywUDK4SrU4CesiPhQ12eg1Lh57LB2T1Y8Lmc5rif8P0D7XSwm3V5WVFUmUp0zHuUzPbw== X-Received: by 10.223.175.49 with SMTP id z46mr3387635wrc.12.1513075108814; Tue, 12 Dec 2017 02:38:28 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:05 +0000 Message-Id: <20171212103807.18836-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 6/8] Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The EVB does not boot if PCI RC #0 has no card inserted, and will hang in the PCIe initialization code. So let's check the presence detect GPIO, and only enable PCI RC #0 if it is asserted. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc = | 7 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatf= ormPeiLib.c | 70 ++++++++++++++------ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatf= ormPeiLib.inf | 2 + Silicon/Socionext/SynQuacer/SynQuacer.dec = | 1 + 4 files changed, 59 insertions(+), 21 deletions(-) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index c71425664bdc..917632c2b4c1 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -374,6 +374,10 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the vars= tore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 =20 + # On the EVB, PCIe RC #0 should not be enabled from software if no card + # was inserted, or the boot will hang. + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|15 + !if $(BUILD_NUMBER) > 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER= )" !endif @@ -395,6 +399,9 @@ [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF =20 + # enable RC #1 only by default, RC #0 will be enabled if an endpoint is = detected + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x2 + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/Sy= nQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlat= formPeiLib/SynQuacerPlatformPeiLib.c index e4aec8b09169..7c529a22c6ef 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacer= PlatformPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacer= PlatformPeiLib.c @@ -24,7 +24,10 @@ #include #include =20 -#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED MAX_UINT8 +#define GPIO_NOT_IMPLEMENTED MAX_UINT8 + +#define CLEAR_SETTINGS_GPIO_ASSERTED 1 +#define PCIE_GPIO_CARD_PRESENT 0 =20 STATIC CONST DRAM_INFO *mDramInfo =3D (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBa= se); @@ -100,6 +103,35 @@ STATIC CONST EFI_PEI_PPI_DESCRIPTOR mDramInfoPpiDescri= ptor =3D { &mDramInfoPpi }; =20 +STATIC +EFI_STATUS +ReadGpioInput ( + IN EMBEDDED_GPIO_PPI *Gpio, + IN UINT8 Pin, + OUT UINTN *Value + ) +{ + EFI_STATUS Status; + + if (Pin =3D=3D GPIO_NOT_IMPLEMENTED) { + return EFI_NOT_FOUND; + } + + Status =3D Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to set GPIO %d as input - %r\n", + __FUNCTION__, Pin, Status)); + return Status; + } + + Status =3D Gpio->Get (Gpio, Pin, Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to get GPIO %d state - %r\n", + __FUNCTION__, Pin, Status)); + } + return Status; +} + EFI_STATUS EFIAPI PlatformPeim ( @@ -109,30 +141,26 @@ PlatformPeim ( EMBEDDED_GPIO_PPI *Gpio; EFI_STATUS Status; UINTN Value; - UINT8 Pin; =20 ASSERT (mDramInfo->NumRegions > 0); =20 - Pin =3D FixedPcdGet8 (PcdClearSettingsGpioPin); - if (Pin !=3D CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) { - Status =3D PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, - (VOID **)&Gpio); - ASSERT_EFI_ERROR (Status); + Status =3D PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, + (VOID **)&Gpio); + ASSERT_EFI_ERROR (Status); =20 - Status =3D Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n", - __FUNCTION__, Status)); - } else { - Status =3D Gpio->Get (Gpio, Pin, &Value); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n", - __FUNCTION__, Status)); - } else if (Value > 0) { - DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); - PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); - } - } + Status =3D ReadGpioInput (Gpio, FixedPcdGet8 (PcdClearSettingsGpioPin), = &Value); + if (!EFI_ERROR (Status) && Value =3D=3D CLEAR_SETTINGS_GPIO_ASSERTED) { + DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); + PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); + } + + Status =3D ReadGpioInput (Gpio, FixedPcdGet8 (PcdPcie0PresenceDetectGpio= Pin), + &Value); + if (!EFI_ERROR (Status) && Value =3D=3D PCIE_GPIO_CARD_PRESENT) { + DEBUG ((DEBUG_INFO, + "%a: card detected in PCIe RC #0, enabling\n", __FUNCTION__)); + Status =3D PcdSet8S (PcdPcieEnableMask, PcdGet8 (PcdPcieEnableMask) | = BIT0); + ASSERT_EFI_ERROR (Status); } =20 // diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/Sy= nQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPl= atformPeiLib/SynQuacerPlatformPeiLib.inf index a6501fb205e1..eb6a5bf9ac1a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacer= PlatformPeiLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacer= PlatformPeiLib.inf @@ -43,6 +43,7 @@ [FixedPcd] gArmTokenSpaceGuid.PcdFvSize gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin gSynQuacerTokenSpaceGuid.PcdDramInfoBase + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin =20 [Ppis] gEdkiiEmbeddedGpioPpiGuid ## CONSUMES @@ -51,6 +52,7 @@ [Ppis] [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask =20 [Depex] gEdkiiEmbeddedGpioPpiGuid diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index 2e18cb33346d..a21f12b5bc32 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -36,6 +36,7 @@ [PcdsFixedAtBuild] =20 # GPIO pin index [0 .. 31] or MAX_UINT8 for not implemented gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|0xFF|UINT8|0x0000= 0006 =20 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005 =20 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Masahisa KOJIMA In order to be able to use UART #0 on the DeveloperBox's 96boards low speed connector, expose it to the OS by adding a node to the device tree. This requires a CM3 firmware build that makes the SCP detach from the serial port after boot. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Masahisa KOJIMA Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index c9fee5d1f350..37a3981f0360 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -440,6 +440,15 @@ clock-names =3D "uartclk", "apb_pclk"; }; =20 + fuart: fuart@51040000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x51040000 0x0 0x1000>; + interrupts =3D ; + clock-frequency =3D <62500000>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + }; + clk_netsec: refclk125mhz { compatible =3D "fixed-clock"; clock-frequency =3D <125000000>; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 07:52:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" For some reason, the Asmedia 118x PCIe switch needs a little help to make sure that the downstream links train at Gen2 speed. So add a PCI I/O protocol notifier that implements this for each PCIe downstream port that is present on the system. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++= ++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++= ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + 4 files changed, 184 insertions(+), 9 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c b/Silic= on/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c new file mode 100644 index 000000000000..b069b42d0a42 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c @@ -0,0 +1,140 @@ + /** @file + SynQuacer DXE platform driver - PCIe support + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "PlatformDxe.h" + +#define ASMEDIA_VID 0x1b21 +#define ASM1182E_PID 0x1182 +#define ASM1184E_PID 0x1184 + +#define ASM118x_PCIE_CAPABILITY_OFFSET 0x80 +#define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSE= T + \ + OFFSET_OF (PCI_CAPABILITY_PCI= EXP, \ + LinkControl)) + +STATIC VOID *mPciProtocolNotifyRegistration; +STATIC EFI_EVENT mPciProtocolNotifyEvent; + +#pragma pack(1) +typedef struct { + EFI_PCI_CAPABILITY_HDR CapHdr; + PCI_REG_PCIE_CAPABILITY Pcie; +} PCIE_CAP; +#pragma pack() + +STATIC +VOID +RetrainAsm1184eDownstreamPort ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT16 PciVidPid[2]; + EFI_STATUS Status; + PCIE_CAP Cap; + PCI_REG_PCIE_LINK_CONTROL LinkControl; + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OF= FSET, + ARRAY_SIZE (PciVidPid), &PciVidPid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", + __FUNCTION__, Status)); + return; + } + + if (PciVidPid[0] !=3D ASMEDIA_VID || + (PciVidPid[1] !=3D ASM1182E_PID && PciVidPid[1] !=3D ASM1184E_PID)) { + return; + } + + // + // The upstream and downstream ports share the same PID/VID, so check + // the port type. This assumes the PCIe Express capability block lives + // at offset 0x80 in the port's config space, which is known to be the + // case for these particular chips. + // + ASSERT (sizeof (Cap) =3D=3D sizeof (UINT32)); + ASSERT (sizeof (LinkControl) =3D=3D sizeof (UINT16)); + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, + ASM118x_PCIE_CAPABILITY_OFFSET, 1, &Cap); + ASSERT_EFI_ERROR (Status); + ASSERT (Cap.CapHdr.CapabilityID =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP); + + if (Cap.Pcie.Bits.DevicePortType !=3D PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_P= ORT) { + return; + } + + DEBUG ((DEBUG_INFO, "%a: retraining ASM1184x downstream PCIe port\n", + __FUNCTION__)); + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, + ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl); + ASSERT_EFI_ERROR (Status); + + LinkControl.Bits.RetrainLink =3D 1; + + Status =3D PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, + ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID +EFIAPI +OnPciIoProtocolNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + EFI_STATUS Status; + EFI_HANDLE HandleBuffer; + UINTN BufferSize; + + while (TRUE) { + BufferSize =3D sizeof (EFI_HANDLE); + Status =3D gBS->LocateHandle (ByRegisterNotify, NULL, + mPciProtocolNotifyRegistration, &BufferSize, &HandleBu= ffer); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D gBS->HandleProtocol (HandleBuffer, &gEfiPciIoProtocolGuid, + (VOID **)&PciIo); + ASSERT_EFI_ERROR (Status); + + // + // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its + // 2-port sibling of which samples were used in development) needs a + // little nudge to get it to train the downstream links at Gen2 speed. + // + RetrainAsm1184eDownstreamPort (PciIo); + } +} + +EFI_STATUS +EFIAPI +RegisterPcieNotifier ( + VOID + ) +{ + mPciProtocolNotifyEvent =3D EfiCreateProtocolNotifyEvent ( + &gEfiPciIoProtocolGuid, + TPL_CALLBACK, + OnPciIoProtocolNotify, + NULL, + &mPciProtocolNotifyRegistration); + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index e58a2093eb49..098a4dbd324e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -12,15 +12,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. **/ =20 -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "PlatformDxe.h" =20 STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] =3D { { @@ -202,5 +194,8 @@ PlatformDxeEntryPoint ( =20 SmmuEnableCoherentDma (); =20 + Status =3D RegisterPcieNotifier (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h new file mode 100644 index 000000000000..d1dad2a3eace --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -0,0 +1,37 @@ +/** @file + SynQuacer DXE platform driver. + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __PLATFORM_DXE_H__ +#define __PLATFORM_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +RegisterPcieNotifier ( + VOID + ); + +#endif diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 00c1130906c4..84498eaddcef 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,6 +23,7 @@ [Defines] ENTRY_POINT =3D PlatformDxeEntryPoint =20 [Sources] + Pcie.c PlatformDxe.c =20 [Packages] @@ -41,6 +42,7 @@ [LibraryClasses] MemoryAllocationLib UefiBootServicesTableLib UefiDriverEntryPoint + UefiLib =20 [Guids] gFdtTableGuid @@ -50,6 +52,7 @@ [Guids] =20 [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEfiPciIoProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES =20 [FixedPcd] --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel