From nobody Sat May 4 04:59:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512742007235690.7367616198428; Fri, 8 Dec 2017 06:06:47 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 23A932217CE4D; Fri, 8 Dec 2017 06:02:12 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D3AF92217CE47 for ; Fri, 8 Dec 2017 06:02:09 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id f9so3422446wmh.0 for ; Fri, 08 Dec 2017 06:06:44 -0800 (PST) Received: from localhost.localdomain ([84.203.66.92]) by smtp.gmail.com with ESMTPSA id c33sm3423442edd.36.2017.12.08.06.06.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 06:06:41 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7FLTjc7q/aV2jLiFcb5mmv/TIY+jnBimvLwTAJbUE+Q=; b=X++kYcG67YQwnYRZr6FKJP774eMfXytFwvhhOpWq4FwTHiuwwyrDLm8gIyKHJYjtHJ S4lPBi/MWxw5Jq1YAxJ4iCLBseeacyRFZZ1N8f2VUKuJXX2hmn3FMkPuyifyjKTFLW5L zJwGqpRjE9ZZt4sHirhd6N02c6ZCoIxxVp/UoTVUPWowEzjCr716XX93xc7KfbcylZOa zdKIzyWKT6KRqBiM8WjYANP2FSiXL5kQstSLGgp+I11b+lc6NfRJ9rbgqN3mGz/WAyG8 YQXbEi5QfAoWKE9yUKjm7WjMm6AB0G6vWe7GNM5XgHffj0meI+zUk+0GqCMlivCzbC39 dnjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7FLTjc7q/aV2jLiFcb5mmv/TIY+jnBimvLwTAJbUE+Q=; b=TATWYNRqL0e7saPSoQWVWWthDWs48Sv88uuW0u05Dhv/MAXmJUONZLs3knMMOJoElY FjhuEhDaxHs6kleHJMwyG6ujEsctMXTSdzMGgs3T2cUFj2V2/HhZuZ5SaJtfqy963ZWf NJ5gfmcCq/6Y6u/UIPgluD2d6XnMDWquIDdVEL4vD7b0iqrsb5KGDpBwj0AuLby7+oG8 iAaPspApPcfOwnauEiEDiru+3Apg3jPm+vZO5FpLU63fhmXAbQO8zxRVjePraO8iw4Np ES/sJG1A+54fMKgGgjcNskXDvpySBa+8kl+plJwJjizZea1+7NxFBHMrNekviW5FzW3C 8B3g== X-Gm-Message-State: AJaThX7u4QcbAIF/n9koe6zayqGLtsl9mRzgT3xzcQ3rSJjPOUqcTnyd 5bXeQ9fk2u+XHyiTBc9e8miL4sNJh1k= X-Google-Smtp-Source: AGs4zMZm94H8iJ5kUD2ZtQVA7Tm/6S3IIhnmmaEwa7GJm83daWaBE4mp1Afj7GhQM49cc8yr4hlK+Q== X-Received: by 10.80.245.237 with SMTP id x42mr50273921edm.80.1512742002488; Fri, 08 Dec 2017 06:06:42 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 14:06:26 +0000 Message-Id: <20171208140631.4252-2-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20171208140631.4252-1-pete@akeo.ie> References: <20171208140631.4252-1-pete@akeo.ie> Subject: [edk2] [PATCH v3 1/6] MdePkg: Disable some Level 4 warnings for VS2017/ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" We disable the exact same warnings as IA32 and X64. Also create a dummy macro for PRESERVE8, as this is not supported by the Microsoft ARM assembler. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Include/Arm/ProcessorBind.h | 96 +++++++++++++++----- 1 file changed, 75 insertions(+), 21 deletions(-) diff --git a/MdePkg/Include/Arm/ProcessorBind.h b/MdePkg/Include/Arm/Proces= sorBind.h index dde1fd1152ba..0700e4a4c50a 100644 --- a/MdePkg/Include/Arm/ProcessorBind.h +++ b/MdePkg/Include/Arm/ProcessorBind.h @@ -1,15 +1,15 @@ /** @file Processor or Compiler specific defines and types for ARM. =20 - Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- This program and the accompanying materials =20 - are licensed and made available under the terms and conditions of the BS= D License =20 - which accompanies this distribution. The full text of the license may b= e found at =20 - http://opensource.org/licenses/bsd-license.php = =20 + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php =20 - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, = =20 - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ =20 @@ -28,14 +28,63 @@ #pragma pack() #endif =20 +#if defined(_MSC_EXTENSIONS) + // -// RVCT does not support the __builtin_unreachable() macro +// Disable some level 4 compilation warnings (same as IA32 and X64) // -#ifdef __ARMCC_VERSION + +// +// Disabling bitfield type checking warnings. +// +#pragma warning ( disable : 4214 ) + +// +// Disabling the unreferenced formal parameter warnings. +// +#pragma warning ( disable : 4100 ) + +// +// Disable slightly different base types warning as CHAR8 * can not be set +// to a constant string. +// +#pragma warning ( disable : 4057 ) + +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this war= ning +// +#pragma warning ( disable : 4127 ) + +// +// This warning is caused by functions defined but not used. For precompil= ed header only. +// +#pragma warning ( disable : 4505 ) + +// +// This warning is caused by empty (after preprocessing) source file. For = precompiled header only. +// +#pragma warning ( disable : 4206 ) + +// +// Disable 'potentially uninitialized local variable X used' warnings +// +#pragma warning ( disable : 4701 ) + +// +// Disable 'potentially uninitialized local pointer variable X used' warni= ngs +// +#pragma warning ( disable : 4703 ) + +#endif + +// +// RVCT and MSFT don't support the __builtin_unreachable() macro +// +#if defined(__ARMCC_VERSION) || defined(_MSC_EXTENSIONS) #define UNREACHABLE() #endif =20 -#if _MSC_EXTENSIONS=20 +#if defined(_MSC_EXTENSIONS) // // use Microsoft* C compiler dependent integer width types // @@ -52,7 +101,7 @@ typedef signed char INT8; #else // - // Assume standard ARM alignment.=20 + // Assume standard ARM alignment. // Need to check portability of long long // typedef unsigned long long UINT64; @@ -121,7 +170,7 @@ typedef INT32 INTN; // use the correct C calling convention. All protocol member functions and // EFI intrinsics are required to modify their member functions with EFIAP= I. // -#define EFIAPI =20 +#define EFIAPI =20 // When compiling with Clang, we still use GNU as for the assembler, so we= still // need to define the GCC_ASM* macros. @@ -142,34 +191,39 @@ typedef INT32 INTN; =20 #define GCC_ASM_EXPORT(func__) \ .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function =20 + .type ASM_PFX(func__), %function =20 #define GCC_ASM_IMPORT(func__) \ .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - =20 + #else // - // .type not supported by Apple Xcode tools=20 + // .type not supported by Apple Xcode tools // - #define INTERWORK_FUNC(func__) =20 + #define INTERWORK_FUNC(func__) =20 #define GCC_ASM_EXPORT(func__) \ .globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \ - =20 - #define GCC_ASM_IMPORT(name) =20 + + #define GCC_ASM_IMPORT(name) =20 #endif +#elif defined(_MSC_EXTENSIONS) + // + // PRESERVE8 is not supported by the MSFT assembler. + // + #define PRESERVE8 #endif =20 /** Return the pointer to the first instruction of a function given a functi= on pointer. - On ARM CPU architectures, these two pointer values are the same,=20 + On ARM CPU architectures, these two pointer values are the same, so the implementation of this macro is very simple. - =20 + @param FunctionPointer A pointer to a function. =20 @return The pointer to the first instruction of a function given a funct= ion pointer. - =20 + **/ #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoin= ter) =20 --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:59:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf | 5 +++-- MdePkg/Library/BaseStackCheckLib/BaseStackCheckNull.c | 18 ++++++++++++++= ++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf b/MdePk= g/Library/BaseStackCheckLib/BaseStackCheckLib.inf index d02d97107b08..e280651b1199 100644 --- a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf +++ b/MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf @@ -30,8 +30,9 @@ [Defines] # =20 [Sources] - BaseStackCheckGcc.c | GCC - BaseStackCheckGcc.c | RVCT + BaseStackCheckGcc.c | GCC + BaseStackCheckGcc.c | RVCT + BaseStackCheckNull.c | MSFT =20 [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseStackCheckLib/BaseStackCheckNull.c b/MdePkg= /Library/BaseStackCheckLib/BaseStackCheckNull.c new file mode 100644 index 000000000000..fb2f65929d3e --- /dev/null +++ b/MdePkg/Library/BaseStackCheckLib/BaseStackCheckNull.c @@ -0,0 +1,18 @@ +/*++ + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +Abstract: + + This file is purely empty as a work around for BaseStackCheck to pass MS= VC build. + +**/ + +extern int __BaseStackCheckNull; --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:59:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512742036067234.1348841227865; Fri, 8 Dec 2017 06:07:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9E22B2217CE51; Fri, 8 Dec 2017 06:02:40 -0800 (PST) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67D082217CE3E for ; Fri, 8 Dec 2017 06:02:38 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id b76so3414926wmg.1 for ; Fri, 08 Dec 2017 06:07:12 -0800 (PST) Received: from localhost.localdomain ([84.203.66.92]) by smtp.gmail.com with ESMTPSA id c33sm3423442edd.36.2017.12.08.06.06.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 06:07:10 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0ZzR5sPR260w4xnhjRzzX3h6B2UcluifRnrDl9XPWqY=; b=FwHuezrsaSixJpz/vICouhLAEeluEvfUeAAsenMqPq3XMHirsa3P9GHcGXDKVvKxFF eLIzSWlqn4feuZuY8sQ14CKJfOP+mh3GxHDHmTDvVD3HFSJeb5vMxxLFhIM3wv3nPvv9 kg5k/jKVbQcHCtYt+KLgcLi0SKQ1iaGjQw+kpby9Hkbf4vbOlg6eCCe+nYJdrB7UreXZ 3maDgyeACL1toVKI1t+/6h8I0UkNuZ6Pykyg6Yx0Fn78prpv6ww1jCPt8dTFeSmk3hph 8j5ErF8ojDv/58NnnhhchOLKk4/qKkZHChfeFhnzlwY1v4431OMgmCFDoFnD8szPTWkK z82Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0ZzR5sPR260w4xnhjRzzX3h6B2UcluifRnrDl9XPWqY=; b=YExDs3ZVpj1pTXUL6Mw8Kp0qQdW0ycCjxSZcf8tRYo7D6V4LMqI4ru5/XFCles6t5Q 9TfB0Yim36vqLd88tVQRU9AC/biGf03JJFRduD89KnTc+Qlf09JgJHxhDZoxswHWr29t H4u5uMNfcaw8ytLlz7LNTqWn3Qmc+RxyPNa2aMpMFOP/zWUjLc3HRZCghF00AxNAGpnr T3/SYMwZ5x7q+35mucIbfySZ/fl9CdqRC9AY3r6U3OnR3WKITQN8/iCCWB0ic0SSxCIg JvmQWf+UF4uAo2wcXRO6Hhc2Erzfv2GBAkWGrY3jGuPC+etdcWKJ4rVvAXKxXxz79bam ViFA== X-Gm-Message-State: AJaThX6BEmGrBygcLMew4EwReYtyqOgb/rEMxlltv/hkeAhk56LgDtuc +zvPSUo2T3l00L8oie14nobDfs90nrg= X-Google-Smtp-Source: AGs4zMYs7eY9Kslj4pdHUo3Xju/M2wCBF9oW/Ui5RjXuRH6oKmMW8WavP7sE3uF9n5O49ylfMqjDDg== X-Received: by 10.80.204.197 with SMTP id b5mr50474222edj.249.1512742031189; Fri, 08 Dec 2017 06:07:11 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 14:06:28 +0000 Message-Id: <20171208140631.4252-4-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20171208140631.4252-1-pete@akeo.ie> References: <20171208140631.4252-1-pete@akeo.ie> Subject: [edk2] [PATCH v3 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Most of the RVCT assembly can be reused as is for MSFT except for CpuBreakpoint.asm, which we need to force to Arm mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- MdePkg/Library/BaseLib/BaseLib.inf | 16 +++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Library/= BaseLib/Arm/CpuBreakpoint.asm index 8a8065159bf2..2e508d6f1ad8 100644 --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm @@ -16,7 +16,10 @@ =20 EXPORT CpuBreakpoint =20 - AREA Cpu_Breakpoint, CODE, READONLY +; Force ARM mode for this section, as MSFT assembler defaults to THUMB + AREA Cpu_Breakpoint, CODE, READONLY, ARM + + ARM =20 ;/** ; Generates a breakpoint on the CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 320ac457ea3d..a81d56f61421 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -821,8 +821,9 @@ [Sources.EBC] [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c - Math64.c | RVCT=20 - =20 + Math64.c | RVCT + Math64.c | MSFT + Arm/SwitchStack.asm | RVCT Arm/SetJumpLongJump.asm | RVCT Arm/DisableInterrupts.asm | RVCT @@ -831,7 +832,16 @@ [Sources.ARM] Arm/CpuPause.asm | RVCT Arm/CpuBreakpoint.asm | RVCT Arm/MemoryFence.asm | RVCT -=20 + + Arm/SwitchStack.asm | MSFT + Arm/SetJumpLongJump.asm | MSFT + Arm/DisableInterrupts.asm | MSFT + Arm/EnableInterrupts.asm | MSFT + Arm/GetInterruptsState.asm | MSFT + Arm/CpuPause.asm | MSFT + Arm/CpuBreakpoint.asm | MSFT + Arm/MemoryFence.asm | MSFT + Arm/Math64.S | GCC Arm/SwitchStack.S | GCC Arm/EnableInterrupts.S | GCC --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:59:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Introduce CRT assembly replacements for __rt_sdiv, __rt_udiv, __rt_udiv64, __rt_sdiv64, __rt_srsh, memcpy and memset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- ArmPkg/Library/CompilerIntrinsicsLib/Arm/rtdiv.asm | 255 +++++= +++++++++++++++ ArmPkg/Library/CompilerIntrinsicsLib/Arm/rtsrsh.asm | 45 ++++ ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 13 +- ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c | 34 +++ ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c | 33 +++ 5 files changed, 378 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/rtdiv.asm b/ArmPkg/Li= brary/CompilerIntrinsicsLib/Arm/rtdiv.asm new file mode 100644 index 000000000000..096dc6317318 --- /dev/null +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/rtdiv.asm @@ -0,0 +1,255 @@ +///** @file +// +// This code provides replacement for MSVC CRT division functions +// +// Copyright (c) 2017, Pete Batard. All rights reserved.
+// Based on generated assembly of ReactOS' sdk/lib/crt/math/arm/__rt_###d= iv.c, +// Copyright (c) Timo Kreuzer. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +//**/ + + EXPORT _fltused + EXPORT __brkdiv0 + + EXPORT __rt_sdiv + EXPORT __rt_udiv + EXPORT __rt_udiv64 + EXPORT __rt_sdiv64 + + AREA Math, CODE, READONLY + +_fltused + dcd 0x9875 + +__brkdiv0 + udf #249 + +// +// uint64_t __rt_udiv(uint32_t divisor, uint32_t dividend) +// + +__rt_udiv + cmp r0, #0 + beq __brkdiv0 + push {r3-r5,lr} + mov r5,r0 + mov r4,r1 + cmp r5,r4 + it hi + movhi r0,#0 + bhi __rt_udiv_label3 + clz r2,r5 + clz r3,r4 + subs r3,r2,r3 + movs r1,#1 + lsl r2,r5,r3 + lsl r3,r1,r3 + movs r0,#0 +__rt_udiv_label1 + cmp r4,r2 + bcc __rt_udiv_label2 + orrs r0,r0,r3 + subs r4,r4,r2 +__rt_udiv_label2 + lsrs r2,r2,#1 + lsrs r3,r3,#1 + bne __rt_udiv_label1 +__rt_udiv_label3 + mov r1,r4 + pop {r3-r5,pc} + +// +// uint64_t __rt_sdiv(int32_t divisor, int32_t dividend) +// + +__rt_sdiv + cmp r0, #0 + beq __brkdiv0 + push {r4-r6,lr} + mov r4,r1 + ands r6,r0,#0x80000000 + it ne + rsbne r4,r4,#0 + mov r5,r0 + rsbs r5,r5,#0 + cmp r5,r4 + it hi + movhi r0,#0 + bhi __rt_sdiv_label3 + clz r2,r5 + clz r3,r4 + subs r3,r2,r3 + movs r1,#1 + lsl r2,r5,r3 + lsl r3,r1,r3 + movs r0,#0 +__rt_sdiv_label1 + cmp r4,r2 + bcc __rt_sdiv_label2 + orrs r0,r0,r3 + subs r4,r4,r2 +__rt_sdiv_label2 + lsrs r2,r2,#1 + lsrs r3,r3,#1 + bne __rt_sdiv_label1 +__rt_sdiv_label3 + cbz r6,__rt_sdiv_label4 + rsbs r4,r4,#0 +__rt_sdiv_label4 + mov r1,r4 + pop {r4-r6,pc} + +// +// typedef struct { +// uint64_t quotient; +// uint64_t modulus; +// } udiv64_result_t; +// +// void __rt_udiv64_internal(udiv64_result_t *result, uint64_t divisor, ui= nt64_t dividend) +// + +__rt_udiv64_internal + orrs r1,r2,r3 + beq __brkdiv0 + push {r4-r8,lr} + mov r7,r3 + mov r6,r2 + mov r4,r0 + ldrd r0,r5,[sp,#0x18] + cmp r7,r5 + bcc __rt_udiv64_internal_label2 + bhi __rt_udiv64_internal_label1 + cmp r6,r0 + bls __rt_udiv64_internal_label2 +__rt_udiv64_internal_label1 + movs r3,#0 + strd r3,r3,[r4] + b __rt_udiv64_internal_label8 +__rt_udiv64_internal_label2 + clz r2,r7 + cmp r2,#0x20 + bne __rt_udiv64_internal_label3 + clz r3,r6 + add r2,r2,r3 +__rt_udiv64_internal_label3 + clz r1,r5 ; + cmp r1,#0x20 + bne __rt_udiv64_internal_label4 + clz r3,r0 + add r1,r1,r3 +__rt_udiv64_internal_label4 + subs r1,r2,r1 + rsb r3,r1,#0x20 + lsr r3,r6,r3 + lsl r2,r7,r1 + orrs r2,r2,r3 + sub r3,r1,#0x20 + lsl r3,r6,r3 + orrs r2,r2,r3 + lsl r7,r6,r1 + sub r3,r1,#0x20 + movs r6,#1 + lsls r6,r6,r3 + movs r3,#1 + mov lr,#0 + lsl r1,r3,r1 + mov r8,lr +__rt_udiv64_internal_label5 + cmp r5,r2 + bcc __rt_udiv64_internal_label7 + bhi __rt_udiv64_internal_label6 + cmp r0,r7 + bcc __rt_udiv64_internal_label7 +__rt_udiv64_internal_label6 + subs r0,r0,r7 + sbcs r5,r5,r2 + orr lr,lr,r1 + orr r8,r8,r6 +__rt_udiv64_internal_label7 + lsls r3,r2,#0x1F + orr r7,r3,r7,lsr #1 + lsls r3,r6,#0x1F + orr r1,r3,r1,lsr #1 + lsrs r6,r6,#1 + lsrs r2,r2,#1 + orrs r3,r1,r6 + bne __rt_udiv64_internal_label5 + strd lr,r8,[r4] +__rt_udiv64_internal_label8 + str r5,[r4,#0xC] + str r0,[r4,#8] + pop {r4-r8,pc} + +// +// {int64_t, int64_t} __rt_sdiv64(int64_t divisor, int64_t dividend) +// + +__rt_sdiv64 + push {r4-r6,lr} + sub sp,sp,#0x18 + and r6,r1,#0x80000000 + movs r4,r6 + mov r5,r0 + beq __rt_sdiv64_label1 + movs r0,#0 + rsbs r2,r2,#0 + sbc r3,r0,r3 +__rt_sdiv64_label1 + movs r4,r6 + beq __rt_sdiv64_label2 + movs r0,#0 + rsbs r5,r5,#0 + sbc r1,r0,r1 +__rt_sdiv64_label2 + str r2,[sp] + str r3,[sp,#4] + mov r3,r1 + mov r2,r5 + add r0,sp,#8 + bl __rt_udiv64_internal + movs r3,r6 + beq __rt_sdiv64_label3 + ldrd r3,r2,[sp,#0x10] + movs r1,#0 + rsbs r3,r3,#0 + sbcs r1,r1,r2 + b __rt_sdiv64_label4 +__rt_sdiv64_label3 + ldrd r3,r1,[sp,#0x10] +__rt_sdiv64_label4 + mov r2,r3 + ldr r0,[sp,#8] + mov r3,r1 + ldr r1,[sp,#0xC] + add sp,sp,#0x18 + pop {r4-r6,pc} + +// +// {uint64_t, uint64_t} __rt_udiv64(uint64_t divisor, uint64_t dividend) +// + +__rt_udiv64 + push {r4,r5,lr} + sub sp,sp,#0x1C + mov r4,r2 + mov r2,r0 + mov r5,r3 + add r0,sp,#8 + mov r3,r1 + str r4,[sp] + str r5,[sp,#4] + bl __rt_udiv64_internal + ldrd r2,r3,[sp,#0x10] + ldrd r0,r1,[sp,#8] + add sp,sp,#0x1C + pop {r4,r5,pc} + + END diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/rtsrsh.asm b/ArmPkg/L= ibrary/CompilerIntrinsicsLib/Arm/rtsrsh.asm new file mode 100644 index 000000000000..2332dda823f2 --- /dev/null +++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/rtsrsh.asm @@ -0,0 +1,45 @@ +///** @file +// +// This code provides replacement for MSVC CRT __rt_srsh +// +// Copyright (c) Timo Kreuzer. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +//**/ + + EXPORT __rt_srsh + + AREA Math, CODE, READONLY + +// +// int64_t __rt_srsh(int64_t value, uint32_t shift); +// + +__rt_srsh + rsbs r3, r2, #32 + bmi __rt_srsh_label1 + lsr r0, r0, r2 + lsl r3, r1, r3 + orr r0, r0, r3 + asr r1, r1, r2 + bx lr +__rt_srsh_label1 + cmp r2, 64 + bhs __rt_srsh_label2 + sub r3, r2, #32 + asr r0, r1, r3 + asr r1, r1, #32 + bx lr +__rt_srsh_label2 + asr r1, r1, #32 + mov r0, r1 + bx lr + + END diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf= b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf index 44333141a70a..0dacc5e5117d 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf +++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf @@ -23,8 +23,12 @@ [Defines] LIBRARY_CLASS =3D CompilerIntrinsicsLib =20 [Sources] - memcpy.c - memset.c + memcpy.c | RVCT + memcpy.c | GCC + memcpy_ms.c | MSFT + memset.c | RVCT + memset.c | GCC + memset_ms.c | MSFT =20 [Sources.ARM] Arm/mullu.asm | RVCT @@ -94,6 +98,8 @@ [Sources.ARM] Arm/llsr.S | GCC Arm/llsl.S | GCC =20 + Arm/rtdiv.asm | MSFT + Arm/rtsrsh.asm | MSFT =20 [Packages] MdePkg/MdePkg.dec @@ -101,3 +107,6 @@ [Packages] =20 [LibraryClasses] =20 +[BuildOptions] + MSFT:*_*_ARM_CC_FLAGS =3D /GL- + MSFT:*_*_AARCH64_CC_FLAGS =3D /GL- diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c b/ArmPkg/Libr= ary/CompilerIntrinsicsLib/memcpy_ms.c new file mode 100644 index 000000000000..90bbbb930d31 --- /dev/null +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c @@ -0,0 +1,34 @@ +//------------------------------------------------------------------------= ------ +// +// Copyright (c) 2017, Pete Batard. All rights reserved.
+// +// This program and the accompanying materials are licensed and made +// available under the terms and conditions of the BSD License which +// accompanies this distribution. The full text of the license may be +// found at http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +// IMPLIED. +// +//------------------------------------------------------------------------= ------ + +#if defined(_M_ARM64) +typedef unsigned __int64 size_t; +#else +typedef unsigned __int32 size_t; +#endif + +void* memcpy(void *, const void *, size_t); +#pragma intrinsic(memcpy) +#pragma function(memcpy) +void* memcpy(void *dest, const void *src, size_t n) +{ + unsigned char *d =3D dest; + unsigned char const *s =3D src; + + while (n--) + *d++ =3D *s++; + + return dest; +} diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c b/ArmPkg/Libr= ary/CompilerIntrinsicsLib/memset_ms.c new file mode 100644 index 000000000000..64205e5d1012 --- /dev/null +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------ +// +// Copyright (c) 2017, Pete Batard. All rights reserved.
+// +// This program and the accompanying materials are licensed and made +// available under the terms and conditions of the BSD License which +// accompanies this distribution. The full text of the license may be +// found at http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +// IMPLIED. +// +//------------------------------------------------------------------------= ------ + +#if defined(_M_ARM64) +typedef unsigned __int64 size_t; +#else +typedef unsigned __int32 size_t; +#endif + +void* memset(void *, int, size_t); +#pragma intrinsic(memset) +#pragma function(memset) +void *memset(void *s, int c, size_t n) +{ + unsigned char *d =3D s; + + while (n--) + *d++ =3D (unsigned char)c; + + return s; +} --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:59:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512742066276582.2472726904285; Fri, 8 Dec 2017 06:07:46 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2AAA92217CE4D; Fri, 8 Dec 2017 06:03:11 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 22E012217CE3E for ; Fri, 8 Dec 2017 06:03:10 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id l141so3495750wmg.1 for ; Fri, 08 Dec 2017 06:07:44 -0800 (PST) Received: from localhost.localdomain ([84.203.66.92]) by smtp.gmail.com with ESMTPSA id c33sm3423442edd.36.2017.12.08.06.07.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 06:07:42 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6uGsx09Moxlje/UZ5Hx9/V3qszP2nhoPszGNmatid/A=; b=UGnqYkOiQ0AX9GviCv/fXF6GnE/C+zF5sBDYKGLf+REeEy/HGSsrMJzXv7g4Pj+uod ypvH7x6yuQAsi/iEe7T0NOHAhfXLt+hXnW0Dtratk4l+eQApH8D2JEXAL3DmSlM70Bji Z0ze/f9+V5CNyiqa7ejMQj9ZClJydQkU2/zMRlpEyQUMVj44SLzV4vnmWl4acMnVbFgW rcT+7dPRryOTg1GZ8VJy0duzEYu2WVoWdwT7tlonsevdCRtBX2pxgX3ANp/zjHzcNWoJ pGYcL1TMEKTlGz5GOXrboSVAxk/pnBivQuv31D3r93FYrC9YIf5weA7yZlBAO3BqGPJT HTew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6uGsx09Moxlje/UZ5Hx9/V3qszP2nhoPszGNmatid/A=; b=a/X2OKpYWhxXvSqakwtRacJpEQHoxSID5w9iVaSvUqu0PamofzevLw2rAAHA7j1YxJ kkxr0Eg1WwFgN1Ilw1ErrqcP2Jl2OA4SeqrMELsH9yR0diS8Yr9I7mXYXohjIWPUfqBU n2Z41uGkGtXRqu3CWnWGkYbP/SyGyFSXnBY66XeVnqjjzyqaEsbO29HVLjgn8kidweAs qXT3GVtcTfIqj2yGOphQmYiFN7iJuuFReu3OH8tLRD++r//4jCRoIGcoRBpHq0rdlfwB QrcX9O71etpJmnspCAEYNS++OSyz64r/5Z44+V2BBLNb+qzWhBCv75INcxaHFnDTgV/V RiYg== X-Gm-Message-State: AJaThX6/u5otzzuDcVlReotXxfpqJXXuCREiQHtfCsWXW3xGrngHus4v JCV1TiEX6D8PeGN/lK/IEX9uZJOOB+g= X-Google-Smtp-Source: AGs4zMZxWV6ApNuFbyNIVv7On8fQyxrpdEa8QhwNQFnRnc/wctM2PJc4gUMVptg2Jw2URir6Ums3AA== X-Received: by 10.80.205.156 with SMTP id p28mr51074779edi.255.1512742062942; Fri, 08 Dec 2017 06:07:42 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 14:06:30 +0000 Message-Id: <20171208140631.4252-6-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20171208140631.4252-1-pete@akeo.ie> References: <20171208140631.4252-1-pete@akeo.ie> Subject: [edk2] [PATCH v3 5/6] MdePkg/Include: Add VA list support for VS2017/ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" VA_START, VA_END and VA_COPY are the same as the generic macros. VA_ARG was reverse engineered from MS ARM assembly output. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Include/Base.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index 02140a5ac2ee..f3467ecdc22f 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -631,6 +631,19 @@ struct _LIST_ENTRY { =20 #define VA_COPY(Dest, Start) __va_copy (Dest, Start) =20 +#elif defined(_M_ARM) +// +// MSFT ARM variable argument list support. +// Same as the generic macros below, except for VA_ARG that needs extra ad= justment. +// + +typedef char* VA_LIST; + +#define VA_START(Marker, Parameter) (Marker =3D (VA_LIST) ((UINTN) & (= Parameter) + _INT_SIZE_OF(Parameter))) +#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker +=3D _INT_SIZE= _OF(TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE))) +#define VA_END(Marker) (Marker =3D (VA_LIST) 0) +#define VA_COPY(Dest, Start) ((void)((Dest) =3D (Start))) + #elif defined(__GNUC__) =20 #if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS) --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:59:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y6TjbDPOKmUDprMRvYmii54Co4euuwGNrMKE4VILGQA=; b=VN+yoCO7nweq28a0gtbRa9U5r9xBN1AI6Llsgi7w4SDpmqd/7wqdlroeT3Yd9uK/TW vffluFn4qhkn3WgeHdYjzYdbnpMT80vE1okh9lmW20eeNXja54v+U7pc92IqlCnSzQrs qLqElSobIg6xio3afppbQ16NNzmNih9lFNDQvh31r6ILVBIDWD/CLez0tOHo01+kJTKl uUjjEzOot2zW1ZB6kVinzWfTWkdkR+N/C+4rHe/vIK+QJHGEOodn+eX2Ow2u6RY1HikM MJQJiqedseodiQwDgpLazHN95nIvHFP+jCN6KC7O7lovFK2pXENm4a9vFEnh5Cam/HVy Z0mg== X-Gm-Message-State: AJaThX6a8JbYF4dIf1VT0lXc58pBmCu9sElEa24eSyOIDAdB8Ul79h0p 6yIXMKdshOTaKErIxiR+IIVfSjC8QLw= X-Google-Smtp-Source: AGs4zMb44ToRZt3lvFbWigb9wtZBzOvjNEAQ0S2eLwHtF8HEv5Q0ebZibXUBJ0I1VE1pvI9QYAAhCg== X-Received: by 10.80.230.143 with SMTP id z15mr51919962edm.106.1512742079497; Fri, 08 Dec 2017 06:07:59 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Date: Fri, 8 Dec 2017 14:06:31 +0000 Message-Id: <20171208140631.4252-7-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20171208140631.4252-1-pete@akeo.ie> References: <20171208140631.4252-1-pete@akeo.ie> Subject: [edk2] [PATCH v3 6/6] BaseTools/Conf: Add VS2017/ARM support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: liming.gao@intel.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" We duplicate the Assembly-Code-File section from build_rule.template because --convert-hex cannot be used with the MSFT ARM assembler. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- BaseTools/Conf/build_rule.template | 31 +++++++++++++++++++- BaseTools/Conf/tools_def.template | 31 ++++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule= .template index 3e6aa8ff0f34..6ea14fb7aa02 100755 --- a/BaseTools/Conf/build_rule.template +++ b/BaseTools/Conf/build_rule.template @@ -182,7 +182,6 @@ =20 =20 - [Assembly-Code-File.COMMON.COMMON] ?.asm, ?.Asm, ?.ASM @@ -207,6 +206,36 @@ # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iii =20 +[Assembly-Code-File.COMMON.ARM] + # Remove --convert-hex for ARM as it breaks MSFT assemblers + + ?.asm, ?.Asm, ?.ASM + + + ?.S, ?.s + + + $(MAKE_FILE) + + + $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj + + + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i + Trim --source-code --convert-hex --trim-long -o ${d_path}(+)${s_ba= se}.iii ${d_path}(+)${s_base}.i + "$(ASM)" /Fo${dst} $(ASM_FLAGS) /I${s_path} $(INC) ${d_path}(+)${s= _base}.iii + + + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i + Trim --source-code --trim-long -o ${d_path}(+)${s_base}.iii ${d_pa= th}(+)${s_base}.i + "$(ASM)" /Fo${dst} $(ASM_FLAGS) /I${s_path} $(INC) ${d_path}(+)${s= _base}.iii + + + "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i + Trim --trim-long --source-code -o ${d_path}(+)${s_base}.iii ${d_pa= th}(+)${s_base}.i + # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing is= sues + "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iii + [Nasm-Assembly-Code-File.COMMON.COMMON] ?.nasm diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 91b135c2e569..0bf30f05756f 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -79,6 +79,7 @@ DEFINE VS2017_HOST =3D x86 DEFINE VS2017_BIN_HOST =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\DEF(VS2= 017_HOST) DEFINE VS2017_BIN_IA32 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x86 DEFINE VS2017_BIN_X64 =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x64 +DEFINE VS2017_BIN_ARM =3D DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\arm =20 DEFINE WINSDK_BIN =3D ENV(WINSDK_PREFIX) DEFINE WINSDKx86_BIN =3D ENV(WINSDKx86_PREFIX) @@ -335,6 +336,9 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc # Required to build platforms or ACPI tables: # Intel(r) ACPI Compiler (iasl.exe) from # https://acpica.org/downloads +# Note: +# Building of XIP firmware images for ARM is n= ot currently supported (only applications). +# /FILEALIGN:4096 and other changes are needed= for ARM firmware builds. # DDK3790 -win32- Requires: # Microsoft Windows Server 2003 Driver Develop= ment Kit (Microsoft WINDDK) version 3790.1830 # Optional: @@ -4169,6 +4173,33 @@ NOOPT_VS2017_X64_NASM_FLAGS =3D -O0 -f win64 -g RELEASE_VS2017_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IG= NORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:= .pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI= _BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=3D.data NOOPT_VS2017_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OP= T:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pdata,D /Mac= hine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE= _DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG =20 +################# +# ARM definitions +################# +*_VS2017_ARM_CC_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_VFRPP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_SLINK_PATH =3D DEF(VS2017_BIN_ARM)\lib.exe +*_VS2017_ARM_DLINK_PATH =3D DEF(VS2017_BIN_ARM)\link.exe +*_VS2017_ARM_APP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_PP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_ASM_PATH =3D DEF(VS2017_BIN_ARM)\armasm.exe +*_VS2017_ARM_ASLCC_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_ASLPP_PATH =3D DEF(VS2017_BIN_ARM)\cl.exe +*_VS2017_ARM_ASLDLINK_PATH =3D DEF(VS2017_BIN_ARM)\link.exe + + *_VS2017_ARM_MAKE_FLAGS =3D /nologo + DEBUG_VS2017_ARM_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D = UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Gw /Oi- +RELEASE_VS2017_ARM_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D = UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gw /Oi- +NOOPT_VS2017_ARM_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32768 /D = UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Od /Oi- + + DEBUG_VS2017_ARM_ASM_FLAGS =3D /nologo /g +RELEASE_VS2017_ARM_ASM_FLAGS =3D /nologo +NOOPT_VS2017_ARM_ASM_FLAGS =3D /nologo + + DEBUG_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM= /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER = /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +RELEASE_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D= /MACHINE:ARM /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SE= RVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=3D.data +NOOPT_VS2017_ARM_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNORE:4001 /= OPT:REF /OPT:ICF=3D10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM= /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER = /SAFESEH:NO /BASE:0 /DRIVER /DEBUG + ################## # EBC definitions ################## --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel