From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340358149199.04110202330355; Wed, 22 Nov 2017 00:45:58 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1D853220D4BF2; Wed, 22 Nov 2017 00:41:41 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2EF8E2035689B for ; Wed, 22 Nov 2017 00:41:39 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:45:55 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:45:53 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479112" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:41 +0800 Message-Id: <20171122084548.6564-2-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 1/8] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dong , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" PcdCpuStackGuard is introduced to enable/disable Stack Guard feature. Its value is FALSE by default. Cc: Star Zeng Cc: Eric Dong Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- MdeModulePkg/MdeModulePkg.dec | 7 +++++++ MdeModulePkg/MdeModulePkg.uni | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 856d67aceb..b3831a21ad 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -949,6 +949,13 @@ # @Prompt The Heap Guard feature mask gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask|0x0|UINT8|0x3000= 1054 =20 + ## Indicates if UEFI Stack Guard will be enabled. + # If enabled, stack overflow in UEFI can be caught, preventing chaotic = consequences.

+ # TRUE - UEFI Stack Guard will be enabled.
+ # FALSE - UEFI Stack Guard will be disabled.
+ # @Prompt Enable UEFI Stack Guard. + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0x30001055 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## Dynamic type PCD can be registered callback function for Pcd setting = action. # PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of= callback function diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni index 588905a9a1..43dd5103be 100644 --- a/MdeModulePkg/MdeModulePkg.uni +++ b/MdeModulePkg/MdeModulePkg.uni @@ -1204,3 +1204,10 @@ = " 0 - The returned pool is adjacent to the botto= m guard page.
\n" = " 1 - The returned pool is adjacent to the top g= uard page.
" =20 +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdCpuStackGuard_PROMPT #langu= age en-US "Enable UEFI Stack Guard" + +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdCpuStackGuard_HELP #langu= age en-US "Indicates if UEFI Stack Guard will be enabled.\n" + = " If enabled, stack overflow in UEFI can be caught, preventing c= haotic consequences.

\n" + = " TRUE - UEFI Stack Guard will be enabled.
\n" + = " FALSE - UEFI Stack Guard will be disabled.
" + --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340360392762.7757389483892; Wed, 22 Nov 2017 00:46:00 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5AE93220D4BF6; Wed, 22 Nov 2017 00:41:43 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B79E421CF25D5 for ; Wed, 22 Nov 2017 00:41:40 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:45:56 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:45:55 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479129" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:42 +0800 Message-Id: <20171122084548.6564-3-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiewen Yao , Eric Dong , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" > v2: > Add prototype definition of InitializeCpuExceptionStackSwitchHandlers() A new API InitializeCpuExceptionStackSwitchHandlers() is introduced to supp= ort initializing exception handlers being able to switch stack. StackSwitchData= is arch dependent and required by IA32 processor to convey resources reserved = in advance. This is necessary because the CpuExceptionHandlerLib will be linked in different phases, in which there's no common way to reserve resources. EFI_STATUS EFIAPI InitializeCpuExceptionStackSwitchHandlers ( IN VOID *StackSwitchData OPTIONAL ); Cc: Star Zeng Cc: Eric Dong Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h | 18 +++++++++++++++= +++ 1 file changed, 18 insertions(+) diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeMod= ulePkg/Include/Library/CpuExceptionHandlerLib.h index 6cd8230127..68de4850e1 100644 --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h @@ -41,6 +41,24 @@ InitializeCpuExceptionHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ); =20 +/** + Setup separate stack for given exceptions. StackSwitchData is optional a= nd its + content depends one the specific arch of CPU. + + @param[in] StackSwitchData Pointer to data required for setuping up + stack switch. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionStackSwitchHandlers ( + IN VOID *StackSwitchData OPTIONAL + ); + /** Initializes all CPU interrupt/exceptions entries and provides the defaul= t interrupt/exception handlers. =20 --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340362749525.9514335031369; Wed, 22 Nov 2017 00:46:02 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 94DBE220D4BFC; Wed, 22 Nov 2017 00:41:43 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 49CF62035689B for ; Wed, 22 Nov 2017 00:41:42 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:45:58 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:45:57 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479137" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:43 +0800 Message-Id: <20171122084548.6564-4-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 3/8] MdePkg/BaseLib: Add stack switch related definitions for IA32 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Jiewen Yao , Liming Gao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" > v2: > Add new definitions required by stack switch in IA32 The new definitions include two structures IA32_TASK_STATE_SEGMENT IA32_TSS_DESCRIPTOR and one API VOID EFIAPI AsmWriteTr ( IN UINT16 Selector ); They're needed to setup task gate and interrupt stack table for stack switc= h. Cc: Michael D Kinney Cc: Liming Gao Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- MdePkg/Include/Library/BaseLib.h | 115 +++++++++++++++++++++++++++= ++++ MdePkg/Library/BaseLib/BaseLib.inf | 3 + MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++++++++++ MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++++++++++ 4 files changed, 191 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index d33c3b6b38..371109ad8f 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -6663,6 +6663,70 @@ typedef union { UINT64 Uint64; } IA32_IDT_GATE_DESCRIPTOR; =20 +#pragma pack (1) +// +// IA32 Task-State Segment Definition +// +typedef struct { + UINT16 PreviousTaskLink; + UINT16 Reserved_2; + UINT32 ESP0; + UINT16 SS0; + UINT16 Reserved_10; + UINT32 ESP1; + UINT16 SS1; + UINT16 Reserved_18; + UINT32 ESP2; + UINT16 SS2; + UINT16 Reserved_26; + UINT32 CR3; + UINT32 EIP; + UINT32 EFLAGS; + UINT32 EAX; + UINT32 ECX; + UINT32 EDX; + UINT32 EBX; + UINT32 ESP; + UINT32 EBP; + UINT32 ESI; + UINT32 EDI; + UINT16 ES; + UINT16 Reserved_74; + UINT16 CS; + UINT16 Reserved_78; + UINT16 SS; + UINT16 Reserved_82; + UINT16 DS; + UINT16 Reserved_86; + UINT16 FS; + UINT16 Reserved_90; + UINT16 GS; + UINT16 Reserved_94; + UINT16 LDTSegmentSelector; + UINT16 Reserved_98; + UINT16 T; + UINT16 IOMapBaseAddress; +} IA32_TASK_STATE_SEGMENT; + +typedef union { + struct { + UINT32 LimitLow:16; ///< Segment Limit 15..00 + UINT32 BaseLow:16; ///< Base Address 15..00 + UINT32 BaseMid:8; ///< Base Address 23..16 + UINT32 Type:4; ///< Type (1 0 B 1) + UINT32 Reserved_43:1; ///< 0 + UINT32 DPL:2; ///< Descriptor Privilege Level + UINT32 P:1; ///< Segment Present + UINT32 LimitHigh:4; ///< Segment Limit 19..16 + UINT32 AVL:1; ///< Available for use by system software + UINT32 Reserved_52:2; ///< 0 0 + UINT32 G:1; ///< Granularity + UINT32 BaseHigh:8; ///< Base Address 31..24 + } Bits; + UINT64 Uint64; +} IA32_TSS_DESCRIPTOR; +#pragma pack () + #endif =20 #if defined (MDE_CPU_X64) @@ -6685,6 +6749,46 @@ typedef union { } Uint128; =20 } IA32_IDT_GATE_DESCRIPTOR; =20 +#pragma pack (1) +// +// IA32 Task-State Segment Definition +// +typedef struct { + UINT32 Reserved_0; + UINT64 RSP0; + UINT64 RSP1; + UINT64 RSP2; + UINT64 Reserved_28; + UINT64 IST[7]; + UINT64 Reserved_92; + UINT16 Reserved_100; + UINT16 IOMapBaseAddress; +} IA32_TASK_STATE_SEGMENT; + +typedef union { + struct { + UINT32 LimitLow:16; ///< Segment Limit 15..00 + UINT32 BaseLow:16; ///< Base Address 15..00 + UINT32 BaseMidl:8; ///< Base Address 23..16 + UINT32 Type:4; ///< Type (1 0 B 1) + UINT32 Reserved_43:1; ///< 0 + UINT32 DPL:2; ///< Descriptor Privilege Level + UINT32 P:1; ///< Segment Present + UINT32 LimitHigh:4; ///< Segment Limit 19..16 + UINT32 AVL:1; ///< Available for use by system software + UINT32 Reserved_52:2; ///< 0 0 + UINT32 G:1; ///< Granularity + UINT32 BaseMidh:8; ///< Base Address 31..24 + UINT32 BaseHigh:32; ///< Base Address 63..32 + UINT32 Reserved_96:32; ///< Reserved + } Bits; + struct { + UINT64 Uint64; + UINT64 Uint64_1; + } Uint128; +} IA32_TSS_DESCRIPTOR; +#pragma pack () + #endif =20 /// @@ -8950,6 +9054,17 @@ AsmRdRand64 ( OUT UINT64 *Rand ); =20 +/** + Load given selector into TR register + + @param[in] Selector Task segment selector +**/ +VOID +EFIAPI +AsmWriteTr ( + IN UINT16 Selector + ); + #endif #endif =20 diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 320ac457ea..fbfb0063b7 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -67,6 +67,8 @@ BaseLibInternals.h =20 [Sources.Ia32] + Ia32/WriteTr.nasm + Ia32/Wbinvd.c | MSFT=20 Ia32/WriteMm7.c | MSFT=20 Ia32/WriteMm6.c | MSFT=20 @@ -447,6 +449,7 @@ X64/EnableCache.asm X64/DisableCache.nasm X64/DisableCache.asm + X64/WriteTr.nasm =20 X64/CpuBreakpoint.c | MSFT=20 X64/WriteMsr64.c | MSFT=20 diff --git a/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm b/MdePkg/Library/Base= Lib/Ia32/WriteTr.nasm new file mode 100644 index 0000000000..cde5a3a423 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm @@ -0,0 +1,36 @@ +;-------------------------------------------------------------------------= ----- ; +; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +; Module Name: +; +; WriteTr.nasm +; +; Abstract: +; +; Write TR register +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; AsmWriteTr ( +; UINT16 Selector +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmWriteTr) +ASM_PFX(AsmWriteTr): + mov eax, [esp+4] + ltr ax + ret + diff --git a/MdePkg/Library/BaseLib/X64/WriteTr.nasm b/MdePkg/Library/BaseL= ib/X64/WriteTr.nasm new file mode 100644 index 0000000000..3bf1500c36 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/WriteTr.nasm @@ -0,0 +1,37 @@ +;-------------------------------------------------------------------------= ----- ; +; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +; Module Name: +; +; WriteTr.nasm +; +; Abstract: +; +; Write TR register +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; AsmWriteTr ( +; UINT16 Selector +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmWriteTr) +ASM_PFX(AsmWriteTr): + mov eax, ecx + ltr ax + ret + --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340365786877.0700217862006; Wed, 22 Nov 2017 00:46:05 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D0AA3220D4C04; Wed, 22 Nov 2017 00:41:44 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01F5820359A90 for ; Wed, 22 Nov 2017 00:41:43 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:46:00 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:45:58 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479145" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:44 +0800 Message-Id: <20171122084548.6564-5-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 4/8] MdeModulePkg/DxeIpl: Enable paging for Stack Guard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiewen Yao , Eric Dong , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Stack guard feature makes use of paging mechanism to monitor if there's a stack overflow occurred during boot. This patch will check setting of PCD PcdCpuStackGuard. If it's TRUE, DxeIpl will setup page table and set the page at which the stack base locates to be NOT PRESENT. If stack is used up and memory access cross into the last page of it, #PF exception will be triggered. Cc: Star Zeng Cc: Eric Dong Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 ++- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 ++ MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 + MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++++++++++++++++++--= ---- 4 files changed, 46 insertions(+), 15 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index a1b8748432..ba1d9c6b05 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -49,7 +49,7 @@ [Sources.X64] X64/VirtualMemory.h X64/VirtualMemory.c - X64/DxeLoadFunc.c =20 + X64/DxeLoadFunc.c =20 [Sources.IPF] Ipf/DxeLoadFunc.c @@ -117,6 +117,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES @@ -132,7 +133,7 @@ # # [Hob] # MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # MEMORY_ALLOCAT= ION_MODULE for DxeCore -# MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # New Stack HoB = =20 +# MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # New Stack HoB # MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # Old Stack HOB # # [Hob.IPF] diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 5649265367..441096ad0f 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -235,6 +235,10 @@ ToBuildPageTable ( return TRUE; } =20 + if (PcdGetBool (PcdCpuStackGuard)) { + return TRUE; + } + if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) { return TRUE; } diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c b/MdeModulePkg/= Core/DxeIplPeim/X64/DxeLoadFunc.c index f613221b81..b75a4489bf 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c @@ -95,6 +95,7 @@ HandOffToDxeCore ( // for the DxeIpl and the DxeCore are both X64. // ASSERT (PcdGetBool (PcdSetNxForStack) =3D=3D FALSE); + ASSERT (PcdGetBool (PcdCpuStackGuard) =3D=3D FALSE); } =20 // diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 29b6205e88..a2466b7766 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -117,6 +117,39 @@ EnableExecuteDisableBit ( AsmWriteMsr64 (0xC0000080, MsrRegisters); } =20 +/** + The function will check if page table entry should be splitted to smaller + granularity. + + @retval TRUE Page table should be created. + @retval FALSE Page table should not be created. +**/ +BOOLEAN +ToSplitPageTable ( + IN EFI_PHYSICAL_ADDRESS Address, + IN UINTN Size, + IN EFI_PHYSICAL_ADDRESS StackBase, + IN UINTN StackSize + ) +{ + if (IsNullDetectionEnabled () && Address =3D=3D 0) { + return TRUE; + } + + if (PcdGetBool (PcdCpuStackGuard)) { + if (StackBase >=3D Address && StackBase < (Address + Size)) { + return TRUE; + } + } + + if (PcdGetBool (PcdSetNxForStack)) { + if ((Address < StackBase + StackSize) && ((Address + Size) > StackBase= )) { + return TRUE; + } + } + + return FALSE; +} /** Split 2M page to 4K. =20 @@ -160,7 +193,8 @@ Split2MPageTo4K ( PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | AddressEncMask; PageTableEntry->Bits.ReadWrite =3D 1; =20 - if (IsNullDetectionEnabled () && PhysicalAddress4K =3D=3D 0) { + if ((IsNullDetectionEnabled () && PhysicalAddress4K =3D=3D 0) || + (PcdGetBool (PcdCpuStackGuard) && PhysicalAddress4K =3D=3D StackBa= se)) { PageTableEntry->Bits.Present =3D 0; } else { PageTableEntry->Bits.Present =3D 1; @@ -214,10 +248,7 @@ Split1GPageTo2M ( =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { - if ((IsNullDetectionEnabled () && PhysicalAddress2M =3D=3D 0) - || (PcdGetBool (PcdSetNxForStack) - && (PhysicalAddress2M < StackBase + StackSize) - && ((PhysicalAddress2M + SIZE_2MB) > StackBase))) { + if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSiz= e)) { // // Need to split this 2M page that covers NULL or stack range. // @@ -359,10 +390,7 @@ CreateIdentityMappingPageTables ( PageDirectory1GEntry =3D (VOID *) PageDirectoryPointerEntry; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries = < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += =3D SIZE_1GB) { - if ((IsNullDetectionEnabled () && PageAddress =3D=3D 0) - || (PcdGetBool (PcdSetNxForStack) - && (PageAddress < StackBase + StackSize) - && ((PageAddress + SIZE_1GB) > StackBase))) { + if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)= ) { Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, S= tackBase, StackSize); } else { // @@ -391,10 +419,7 @@ CreateIdentityMappingPageTables ( PageDirectoryPointerEntry->Bits.Present =3D 1; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += =3D SIZE_2MB) { - if ((IsNullDetectionEnabled () && PageAddress =3D=3D 0) - || (PcdGetBool (PcdSetNxForStack) - && (PageAddress < StackBase + StackSize) - && ((PageAddress + SIZE_2MB) > StackBase))) { + if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSiz= e)) { // // Need to split this 2M page that covers NULL or stack range. // --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340368284761.265906554948; Wed, 22 Nov 2017 00:46:08 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 16195220D4BED; Wed, 22 Nov 2017 00:41:47 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 76A8720359A90 for ; Wed, 22 Nov 2017 00:41:45 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:46:01 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:46:00 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479154" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:45 +0800 Message-Id: <20171122084548.6564-6-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 5/8] UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiewen Yao , Laszlo Ersek , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" > v2: > Add two new PCDs to configure exception stack switch. Stack switch is required by Stack Guard feature. Following two PCDs are introduced to simplify the resource allocation for initializing stack switc= h. gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize PcdCpuStackSwitchExceptionList is used to specify which exception will have separate stack for its handler. For Stack Guard feature, #PF must be specified at least. PcdCpuKnownGoodStackSize is used to specify the size of good stack for an exception handler. Cpu driver or other drivers should use this PCD to reser= ve stack memory for exceptions specified above PCD. Cc: Eric Dong Cc: Laszlo Ersek Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- UefiCpuPkg/UefiCpuPkg.dec | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 3bd8740c98..b87e20fb38 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -144,6 +144,18 @@ # @Prompt Lock SMM Feature Control MSR. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x= 3213210B =20 +[PcdsFixedAtBuild] + ## List of exception vectors which need switching stack. + # This PCD will only take into effect if PcdCpuStackGuard is enabled. + # By default exception #DD(8), #PF(14) are supported. + # @Prompt Specify exception vectors which need switching stack. + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VO= ID*|0x30002000 + + ## Size of good stack for an exception. + # This PCD will only take into effect if PcdCpuStackGuard is enabled. + # @Prompt Specify size of good stack of exception which need switching s= tack. + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## This value is the CPU Local APIC base address, which aligns the addre= ss on a 4-KByte boundary. # @Prompt Configure base address of CPU Local APIC --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340370964343.021473348983; Wed, 22 Nov 2017 00:46:10 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5777B220D4C1E; Wed, 22 Nov 2017 00:41:49 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 251E8220D4C15 for ; Wed, 22 Nov 2017 00:41:47 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:46:03 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:46:01 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479178" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:46 +0800 Message-Id: <20171122084548.6564-7-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 6/8] UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiewen Yao , Laszlo Ersek , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" > v2: > Add code to save/restore GDTR, IDTR and TR for AP. In current implementation of CPU MP, AP is initialized with data copied from BSP. Stack switch required by Stack Guard feature needs different GDT, IDT table and task gates for each logic processor. This patch adds GDTR, IDTR a= nd TR into structure CPU_VOLATILE_REGISTERS and save/restore methods. This will make sure that any changes to GDT, IDT and task gate for an AP will be kept from overwritten by BSP settings. Cc: Eric Dong Cc: Laszlo Ersek Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 61b14c9843..0c2058a7b0 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -195,6 +195,10 @@ SaveVolatileRegisters ( VolatileRegisters->Dr6 =3D AsmReadDr6 (); VolatileRegisters->Dr7 =3D AsmReadDr7 (); } + + AsmReadGdtr (&VolatileRegisters->Gdtr); + AsmReadIdtr (&VolatileRegisters->Idtr); + VolatileRegisters->Tr =3D AsmReadTr (); } =20 /** @@ -211,6 +215,7 @@ RestoreVolatileRegisters ( ) { CPUID_VERSION_INFO_EDX VersionInfoEdx; + IA32_TSS_DESCRIPTOR *Tss; =20 AsmWriteCr0 (VolatileRegisters->Cr0); AsmWriteCr3 (VolatileRegisters->Cr3); @@ -231,6 +236,18 @@ RestoreVolatileRegisters ( AsmWriteDr7 (VolatileRegisters->Dr7); } } + + AsmWriteGdtr (&VolatileRegisters->Gdtr); + AsmWriteIdtr (&VolatileRegisters->Idtr); + if (VolatileRegisters->Tr !=3D 0 && + VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { + Tss =3D (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + + VolatileRegisters->Tr); + if (Tss->Bits.P =3D=3D 1) { + Tss->Bits.Type &=3D 0xD; // 1101 - Clear busy bit just in case + AsmWriteTr (VolatileRegisters->Tr); + } + } } =20 /** diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index d13d5c06f5..685e96cbac 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -102,6 +102,9 @@ typedef struct { UINTN Dr3; UINTN Dr6; UINTN Dr7; + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + UINT16 Tr; } CPU_VOLATILE_REGISTERS; =20 // --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340373569468.55487895231875; Wed, 22 Nov 2017 00:46:13 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 90524220B9003; Wed, 22 Nov 2017 00:41:51 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07977220D4C1E for ; Wed, 22 Nov 2017 00:41:49 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:46:05 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:46:03 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479189" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:47 +0800 Message-Id: <20171122084548.6564-8-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Jiewen Yao , Eric Dong , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" > v2: > a. Move common TSS structure and API definitions to BaseLib.h > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup stack > switch. This can avoid allocating memory for it in this library. > c. Add globals to reserve memory for stack switch initialized in early > phase of DXE core. > d. Remove the filter code used to exclude boot modes which doesn't sup= port > memory allocation because those memory can passed in by parameter n= ow. > e. Remove the nasm macro to define exception handler one by one and ad= d a > function to return the start address of each handler. If Stack Guard is enabled and there's really a stack overflow happened duri= ng boot, a Page Fault exception will be triggered. Because the stack is out of usage, the exception handler, which shares the stack with normal UEFI drive= r, cannot be executed and cannot dump the processor information. Without those information, it's very difficult for the BIOS developers loca= te the root cause of stack overflow. And without a workable stack, the develop= er cannot event use single step to debug the UEFI driver with JTAG debugger. In order to make sure the exception handler to execute normally after stack overflow. We need separate stacks for exception handlers in case of unusable stack. IA processor allows to switch to a new stack during handling interrupt and exception. But X64 and IA32 provides different ways to make it. X64 provides interrupt stack table (IST) to allow maximum 7 different exceptions to have new stack for its handler. IA32 doesn't have IST mechanism and can only use task gate to do it since task switch allows to load a new stack through its task-state segment (TSS). Cc: Star Zeng Cc: Eric Dong Cc: Jiewen Yao Cc: Michael Kinney Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++ .../DxeCpuExceptionHandlerLib.inf | 6 + .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++- .../Ia32/ArchExceptionHandler.c | 167 +++++++++ .../Ia32/ArchInterruptDefs.h | 8 + .../Ia32/ExceptionTssEntryAsm.nasm | 398 +++++++++++++++++= ++++ .../PeiCpuExceptionHandlerLib.inf | 1 + .../SecPeiCpuExceptionHandlerLib.inf | 1 + .../SmmCpuExceptionHandlerLib.inf | 1 + .../X64/ArchExceptionHandler.c | 133 +++++++ .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 + 11 files changed, 820 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/Exceptio= nTssEntryAsm.nasm diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 740a58828b..30334105d2 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -48,6 +48,32 @@ 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c= , 0x83 } \ } =20 +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \ + FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + +#define CPU_STACK_SWITCH_EXCEPTION_LIST \ + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList) + +#define CPU_KNOWN_GOOD_STACK_SIZE \ + FixedPcdGet32 (PcdCpuKnownGoodStackSize) + +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) + +#define IA32_GDT_TYPE_TSS 0x9 +#define IA32_GDT_ALIGNMENT 8 + +typedef struct { + UINTN StackTop; + UINTN StackSize; + UINT8 *Exceptions; + UINTN ExceptionNumber; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_SEGMENT_DESCRIPTOR *GdtTable; + UINTN GdtSize; + IA32_TSS_DESCRIPTOR *TssDesc; + IA32_TASK_STATE_SEGMENT *Tss; +} EXCEPTION_STACK_SWITCH_DATA; + // // Record exception handler information // @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker ( IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData ); =20 +/** + Setup separate stack for specific exceptions. + + @param[in] IdtTable IDT table base. +**/ +EFI_STATUS +EFIAPI +ArchSetupExcpetionStack ( + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData + ); + +/** + Return address map of exception handler template so that C code can gene= rate + exception tables. The template is only for exceptions using task gate in= stead + of interrupt gate. + + @param AddressMap Pointer to a buffer where the address map is returned. +**/ +VOID +EFIAPI +AsmGetTssTemplateMap ( + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap + ); + #endif =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index f4a8d01c80..58e55a8a2e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -30,6 +30,7 @@ [Sources.Ia32] Ia32/ExceptionHandlerAsm.asm Ia32/ExceptionHandlerAsm.nasm + Ia32/ExceptionTssEntryAsm.nasm Ia32/ExceptionHandlerAsm.S Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h @@ -47,6 +48,11 @@ PeiDxeSmmCpuException.c DxeException.c =20 +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index 31febec976..c0b2c615aa 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum =3D 0; =20 EXCEPTION_HANDLER_DATA mExceptionHandlerData; =20 +UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER * + CPU_KNOWN_GOOD_STACK_SIZE] =3D {0}; +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] =3D {0}; + /** Common exception handler. =20 @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL ) { + EFI_STATUS Status; + EXCEPTION_STACK_SWITCH_DATA StackSwitchData; + IA32_DESCRIPTOR Idtr; + IA32_DESCRIPTOR Gdtr; + mExceptionHandlerData.ReservedVectors =3D mReservedVectorsData; mExceptionHandlerData.ExternalInterruptHandler =3D mExternalInterruptHan= dlerTable; InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock); - return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHand= lerData); + Status =3D InitializeCpuExceptionHandlersWorker (VectorInfo, &mException= HandlerData); + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) { + AsmReadIdtr (&Idtr); + AsmReadGdtr (&Gdtr); + + StackSwitchData.StackTop =3D (UINTN)mNewStack; + StackSwitchData.StackSize =3D CPU_KNOWN_GOOD_STACK_SIZE; + StackSwitchData.Exceptions =3D CPU_STACK_SWITCH_EXCEPTION_LIST; + StackSwitchData.ExceptionNumber =3D CPU_STACK_SWITCH_EXCEPTION_NUMBER; + StackSwitchData.IdtTable =3D (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base; + StackSwitchData.GdtTable =3D (IA32_SEGMENT_DESCRIPTOR *)mNewGdt; + StackSwitchData.GdtSize =3D sizeof (mNewGdt); + StackSwitchData.TssDesc =3D (IA32_TSS_DESCRIPTOR *)(mNewGdt + Gdtr.Lim= it + 1); + StackSwitchData.Tss =3D (IA32_TASK_STATE_SEGMENT *)(mNewGdt + Gdtr.Lim= it + 1 + + CPU_TSS_DESC_SIZE); + Status =3D InitializeCpuExceptionStackSwitchHandlers ( + &StackSwitchData + ); + } + return Status; } =20 /** @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler ( { return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandle= r, &mExceptionHandlerData); } + +/** + Setup separate stack for given exceptions. This is required by + PcdCpuStackGuard feature. + + Note: For IA32 processor, StackSwitchData is a required parameter. + + @param[in] StackSwitchData Pointer to data required for setuping up + stack switch. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionStackSwitchHandlers ( + IN VOID *StackSwitchData OPTIONAL + ) +{ + return ArchSetupExcpetionStack (StackSwitchData); +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index f2c39eb193..0aaf794795 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -107,6 +107,173 @@ ArchRestoreExceptionContext ( SystemContext.SystemContextIa32->ExceptionData =3D ReservedVectors[Excep= tionType].ExceptionData; } =20 +/** + Setup separate stack for given exceptions. + + @param[in] StackSwitchData Pointer to data required for setuping = up + stack switch. + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content. + +**/ +EFI_STATUS +EFIAPI +ArchSetupExcpetionStack ( + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData + ) +{ + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_TSS_DESCRIPTOR *TssDesc; + IA32_TASK_STATE_SEGMENT *Tss; + UINTN StackTop; + UINTN Index; + UINTN Vector; + UINTN TssBase; + UINTN GdtSize; + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; + + if (StackSwitchData =3D=3D NULL || + StackSwitchData->StackTop =3D=3D 0 || + StackSwitchData->StackSize =3D=3D 0 || + StackSwitchData->Exceptions =3D=3D NULL || + StackSwitchData->ExceptionNumber =3D=3D 0 || + StackSwitchData->GdtTable =3D=3D NULL || + StackSwitchData->IdtTable =3D=3D NULL || + StackSwitchData->TssDesc =3D=3D NULL || + StackSwitchData->Tss =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // The caller is responsible for that the GDT table, no matter the exist= ing + // one or newly allocated, has enough space to hold descriptors for exce= ption + // task-state segments. + // + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { + return EFI_INVALID_PARAMETER; + } + + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable)= ) { + return EFI_INVALID_PARAMETER; + } + + if ((UINTN)StackSwitchData->TssDesc >=3D + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize))= { + return EFI_INVALID_PARAMETER; + } + + GdtSize =3D (UINTN)StackSwitchData->TssDesc - + (UINTN)(StackSwitchData->GdtTable) + + sizeof (IA32_TSS_DESCRIPTOR) * + (StackSwitchData->ExceptionNumber + 1); + if (GdtSize > StackSwitchData->GdtSize) { + return EFI_INVALID_PARAMETER; + } + + // + // Initialize new GDT table and/or IDT table, if any + // + AsmReadIdtr (&Idtr); + AsmReadGdtr (&Gdtr); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; + Gdtr.Limit =3D (UINT16)StackSwitchData->GdtSize - 1; + } + + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; + } + + // + // Fixup current task descriptor. Task-state segment for current task wi= ll + // be filled by processor during task switching. + // + TssDesc =3D StackSwitchData->TssDesc; + Tss =3D StackSwitchData->Tss; + + TssBase =3D (UINTN)Tss; + TssDesc->Bits.LimitLow =3D sizeof(IA32_TASK_STATE_SEGMENT) - 1; + TssDesc->Bits.BaseLow =3D (UINT16)TssBase; + TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); + TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; + TssDesc->Bits.P =3D 1; + TssDesc->Bits.LimitHigh =3D 0; + TssDesc->Bits.BaseHigh =3D (UINT8)(TssBase >> 24); + + // + // Fixup exception task descriptor and task-state segment + // + AsmGetTssTemplateMap (&TemplateMap); + StackTop =3D StackSwitchData->StackTop - CPU_STACK_ALIGNMENT; + StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->ExceptionNumber; ++Index) { + TssDesc +=3D 1; + Tss +=3D 1; + + // + // Fixup TSS descriptor + // + TssBase =3D (UINTN)Tss; + + TssDesc->Bits.LimitLow =3D sizeof(IA32_TASK_STATE_SEGMENT) - 1; + TssDesc->Bits.BaseLow =3D (UINT16)TssBase; + TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); + TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; + TssDesc->Bits.P =3D 1; + TssDesc->Bits.LimitHigh =3D 0; + TssDesc->Bits.BaseHigh =3D (UINT8)(TssBase >> 24); + + // + // Fixup TSS + // + Vector =3D StackSwitchData->Exceptions[Index]; + Tss->EIP =3D (UINT32)(TemplateMap.ExceptionStart + + Vector * TemplateMap.ExceptionStubHeaderSize); + Tss->EFLAGS =3D 0x2; + Tss->ESP =3D StackTop; + Tss->CR3 =3D AsmReadCr3 (); + Tss->ES =3D AsmReadEs (); + Tss->CS =3D AsmReadCs (); + Tss->SS =3D AsmReadSs (); + Tss->DS =3D AsmReadDs (); + Tss->FS =3D AsmReadFs (); + Tss->GS =3D AsmReadGs (); + + StackTop -=3D StackSwitchData->StackSize; + + // + // Update IDT to use Task Gate for given exception + // + IdtTable[Vector].Bits.OffsetLow =3D 0; + IdtTable[Vector].Bits.Selector =3D (UINT16)((UINTN)TssDesc - Gdtr.Ba= se); + IdtTable[Vector].Bits.Reserved_0 =3D 0; + IdtTable[Vector].Bits.GateType =3D IA32_IDT_GATE_TYPE_TASK; + IdtTable[Vector].Bits.OffsetHigh =3D 0; + } + + // + // Publish GDT + // + AsmWriteGdtr (&Gdtr); + + // + // Load current task + // + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base)); + + // + // Publish IDT + // + AsmWriteIdtr (&Idtr); + + return EFI_SUCCESS; +} + /** Display processor context. =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDe= fs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h index a8d3556a80..d9ded5977f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h @@ -41,4 +41,12 @@ typedef struct { UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; } RESERVED_VECTORS_DATA; =20 +#define CPU_TSS_DESC_SIZE \ + (sizeof (IA32_TSS_DESCRIPTOR) * \ + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1)) + +#define CPU_TSS_SIZE \ + (sizeof (IA32_TASK_STATE_SEGMENT) * \ + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1)) + #endif diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEnt= ryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEnt= ryAsm.nasm new file mode 100644 index 0000000000..62bcedea1a --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n= asm @@ -0,0 +1,398 @@ +;-------------------------------------------------------------------------= ----- ; +; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +; Module Name: +; +; ExceptionTssEntryAsm.Asm +; +; Abstract: +; +; IA32 CPU Exception Handler with Separate Stack +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + +; +; IA32 TSS Memory Layout Description +; +struc IA32_TSS + resw 1 + resw 1 + .ESP0: resd 1 + .SS0: resw 1 + resw 1 + .ESP1: resd 1 + .SS1: resw 1 + resw 1 + .ESP2: resd 1 + .SS2: resw 1 + resw 1 + ._CR3: resd 1 + .EIP: resd 1 + .EFLAGS: resd 1 + ._EAX: resd 1 + ._ECX: resd 1 + ._EDX: resd 1 + ._EBX: resd 1 + ._ESP: resd 1 + ._EBP: resd 1 + ._ESI: resd 1 + ._EDI: resd 1 + ._ES: resw 1 + resw 1 + ._CS: resw 1 + resw 1 + ._SS: resw 1 + resw 1 + ._DS: resw 1 + resw 1 + ._FS: resw 1 + resw 1 + ._GS: resw 1 + resw 1 + .LDT: resw 1 + resw 1 + resw 1 + resw 1 +endstruc + +; +; CommonExceptionHandler() +; +extern ASM_PFX(CommonExceptionHandler) + +SECTION .data + +SECTION .text + +ALIGN 8 + +; +; Exception handler stub table +; +AsmExceptionEntryBegin: +%assign Vector 0 +%rep 32 + +DoIret%[Vector]: + iretd +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]): + db 0x6a ; push #VectorNum + db %[Vector] + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) + call eax + mov esp, eax ; Restore stack top + jmp DoIret%[Vector] + +%assign Vector Vector+1 +%endrep +AsmExceptionEntryEnd: + +; +; Common part of exception handler +; +global ASM_PFX(CommonTaskSwtichEntryPoint) +ASM_PFX(CommonTaskSwtichEntryPoint): + ; + ; Stack: + ; +---------------------+ <-- EBP - 8 + ; + TSS Base + + ; +---------------------+ <-- EBP - 4 + ; + CPUID.EDX + + ; +---------------------+ <-- EBP + ; + EIP + + ; +---------------------+ <-- EBP + 4 + ; + Vector Number + + ; +---------------------+ <-- EBP + 8 + ; + Error Code + + ; +---------------------+ + ; + + mov ebp, esp ; Stack frame + +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported + mov eax, 1 + cpuid + push edx + +; Get TSS base of interrupted task through PreviousTaskLink field in +; current TSS base + sub esp, 8 + sgdt [esp + 2] + mov eax, [esp + 4] ; GDT base + add esp, 8 + + xor ebx, ebx + str bx ; Current TR + + mov ecx, [eax + ebx + 2] + shl ecx, 8 + mov cl, [eax + ebx + 7] + ror ecx, 8 ; ecx =3D Current TSS base + push ecx ; keep it in stack for later use + + movzx ebx, word [ecx] ; Previous Task Link + mov ecx, [eax + ebx + 2] + shl ecx, 8 + mov cl, [eax + ebx + 7] + ror ecx, 8 ; ecx =3D Previous TSS base + +; +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTE= XT_IA32 +; is 16-byte aligned +; + and esp, 0xfffffff0 + sub esp, 12 + +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax; + push dword [ecx + IA32_TSS._EAX] + push dword [ecx + IA32_TSS._ECX] + push dword [ecx + IA32_TSS._EDX] + push dword [ecx + IA32_TSS._EBX] + push dword [ecx + IA32_TSS._ESP] + push dword [ecx + IA32_TSS._EBP] + push dword [ecx + IA32_TSS._ESI] + push dword [ecx + IA32_TSS._EDI] + +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss; + movzx eax, word [ecx + IA32_TSS._SS] + push eax + movzx eax, word [ecx + IA32_TSS._CS] + push eax + movzx eax, word [ecx + IA32_TSS._DS] + push eax + movzx eax, word [ecx + IA32_TSS._ES] + push eax + movzx eax, word [ecx + IA32_TSS._FS] + push eax + movzx eax, word [ecx + IA32_TSS._GS] + push eax + +;; UINT32 Eip; + push dword [ecx + IA32_TSS.EIP] + +;; UINT32 Gdtr[2], Idtr[2]; + sub esp, 8 + sidt [esp] + mov eax, [esp + 2] + xchg eax, [esp] + and eax, 0xFFFF + mov [esp+4], eax + + sub esp, 8 + sgdt [esp] + mov eax, [esp + 2] + xchg eax, [esp] + and eax, 0xFFFF + mov [esp+4], eax + +;; UINT32 Ldtr, Tr; + mov eax, ebx ; ebx still keeps selector of interrupted task + push eax + movzx eax, word [ecx + IA32_TSS.LDT] + push eax + +;; UINT32 EFlags; + push dword [ecx + IA32_TSS.EFLAGS] + +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4; + mov eax, cr4 + push eax ; push cr4 firstly + + mov edx, [ebp - 4] ; cpuid.edx + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support + jz .1 + or eax, BIT9 ; Set CR4.OSFXSR +.1: + test edx, BIT2 ; Test for Debugging Extensions support + jz .2 + or eax, BIT3 ; Set CR4.DE +.2: + mov cr4, eax + + mov eax, cr3 + push eax + mov eax, cr2 + push eax + xor eax, eax + push eax + mov eax, cr0 + push eax + +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + mov eax, dr7 + push eax + mov eax, dr6 + push eax + mov eax, dr3 + push eax + mov eax, dr2 + push eax + mov eax, dr1 + push eax + mov eax, dr0 + push eax + +;; FX_SAVE_STATE_IA32 FxSaveState; +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM) +;; when executing fxsave/fxrstor instruction + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. + ; edx still contains result from CPUID above + jz .3 + clts + sub esp, 512 + mov edi, esp + db 0xf, 0xae, 0x7 ;fxsave [edi] +.3: + +;; UINT32 ExceptionData; + push dword [ebp + 8] + +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs= is clear + cld + +;; call into exception handler + mov esi, ecx ; Keep TSS base to avoid overwrite + mov eax, ASM_PFX(CommonExceptionHandler) + +;; Prepare parameter and call + mov edx, esp + push edx ; EFI_SYSTEM_CONTEXT + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number) + + ; + ; Call External Exception Handler + ; + call eax + add esp, 8 ; Restore stack before calling + mov ecx, esi ; Restore TSS base + +;; UINT32 ExceptionData; + add esp, 4 + +;; FX_SAVE_STATE_IA32 FxSaveState; + mov edx, [ebp - 4] ; cpuid.edx + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support + jz .4 + mov esi, esp + db 0xf, 0xae, 0xe ; fxrstor [esi] +.4: + add esp, 512 + +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; +;; Skip restoration of DRx registers to support debuggers +;; that set breakpoints in interrupt/exception context + add esp, 4 * 6 + +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4; + pop eax + mov cr0, eax + add esp, 4 ; not for Cr1 + pop eax + mov cr2, eax + pop eax + mov dword [ecx + IA32_TSS._CR3], eax + pop eax + mov cr4, eax + +;; UINT32 EFlags; + pop dword [ecx + IA32_TSS.EFLAGS] + mov ebx, dword [ecx + IA32_TSS.EFLAGS] + btr ebx, 9 ; Do 'cli' + mov dword [ecx + IA32_TSS.EFLAGS], ebx + +;; UINT32 Ldtr, Tr; +;; UINT32 Gdtr[2], Idtr[2]; +;; Best not let anyone mess with these particular registers... + add esp, 24 + +;; UINT32 Eip; + pop dword [ecx + IA32_TSS.EIP] + +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss; +;; NOTE - modified segment registers could hang the debugger... We +;; could attempt to insulate ourselves against this possibility, +;; but that poses risks as well. +;; + pop eax +o16 mov [ecx + IA32_TSS._GS], ax + pop eax +o16 mov [ecx + IA32_TSS._FS], ax + pop eax +o16 mov [ecx + IA32_TSS._ES], ax + pop eax +o16 mov [ecx + IA32_TSS._DS], ax + pop eax +o16 mov [ecx + IA32_TSS._CS], ax + pop eax +o16 mov [ecx + IA32_TSS._SS], ax + +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax; + pop dword [ecx + IA32_TSS._EDI] + pop dword [ecx + IA32_TSS._ESI] + add esp, 4 ; not for ebp + add esp, 4 ; not for esp + pop dword [ecx + IA32_TSS._EBX] + pop dword [ecx + IA32_TSS._EDX] + pop dword [ecx + IA32_TSS._ECX] + pop dword [ecx + IA32_TSS._EAX] + +; Set single step DB# to allow debugger to able to go back to the EIP +; where the exception is triggered. + +;; Create return context for iretd in stub function + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer + mov ebx, dword [ecx + IA32_TSS.EIP] + mov [eax - 0xc], ebx ; create EIP in old stack + movzx ebx, word [ecx + IA32_TSS._CS] + mov [eax - 0x8], ebx ; create CS in old stack + mov ebx, dword [ecx + IA32_TSS.EFLAGS] + bts ebx, 8 + mov [eax - 0x4], ebx ; create eflags in old st= ack + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer + sub eax, 0xc ; minus 12 byte + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer + +;; Replace the EIP of interrupted task with stub function + mov eax, ASM_PFX(SingleStepStubFunction) + mov dword [ecx + IA32_TSS.EIP], eax + + mov ecx, [ebp - 8] ; Get current TSS base + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top + mov esp, ebp + + ret + +global ASM_PFX(SingleStepStubFunction) +ASM_PFX(SingleStepStubFunction): +; +; we need clean TS bit in CR0 to execute +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions. +; + clts + iretd + +global ASM_PFX(AsmGetTssTemplateMap) +ASM_PFX(AsmGetTssTemplateMap): + push ebp ; C prolog + mov ebp, esp + pushad + + mov ebx, dword [ebp + 0x8] + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0) + mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin)= / 32 + mov dword [ebx + 0x8], 0 + + popad + pop ebp + ret + diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index 75443288a9..4c0d435136 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -30,6 +30,7 @@ [Sources.Ia32] Ia32/ExceptionHandlerAsm.asm Ia32/ExceptionHandlerAsm.nasm + Ia32/ExceptionTssEntryAsm.nasm Ia32/ExceptionHandlerAsm.S Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index d70a99c100..e5c03c16c9 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -30,6 +30,7 @@ [Sources.Ia32] Ia32/ExceptionHandlerAsm.asm Ia32/ExceptionHandlerAsm.nasm + Ia32/ExceptionTssEntryAsm.nasm Ia32/ExceptionHandlerAsm.S Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 634ffcb21d..56b875b7c8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -30,6 +30,7 @@ [Sources.Ia32] Ia32/ExceptionHandlerAsm.asm Ia32/ExceptionHandlerAsm.nasm + Ia32/ExceptionTssEntryAsm.nasm Ia32/ExceptionHandlerAsm.S Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index 65f0cff680..214aafcc13 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -112,6 +112,139 @@ ArchRestoreExceptionContext ( SystemContext.SystemContextX64->ExceptionData =3D ReservedVectors[Except= ionType].ExceptionData; } =20 +/** + Setup separate stack for given exceptions. + + @param[in] StackSwitchData Pointer to data required for setuping up + stack switch. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content. + +**/ +EFI_STATUS +EFIAPI +ArchSetupExcpetionStack ( + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData + ) +{ + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_TSS_DESCRIPTOR *TssDesc; + IA32_TASK_STATE_SEGMENT *Tss; + UINTN StackTop; + UINTN Index; + UINTN TssBase; + UINTN GdtSize; + + if (StackSwitchData =3D=3D NULL || + StackSwitchData->StackTop =3D=3D 0 || + StackSwitchData->StackSize =3D=3D 0 || + StackSwitchData->Exceptions =3D=3D NULL || + StackSwitchData->ExceptionNumber =3D=3D 0 || + StackSwitchData->GdtTable =3D=3D NULL || + StackSwitchData->IdtTable =3D=3D NULL || + StackSwitchData->TssDesc =3D=3D NULL || + StackSwitchData->Tss =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // The caller is responsible for that the GDT table, no matter the exist= ing + // one or newly allocated, has enough space to hold descriptors for exce= ption + // task-state segments. + // + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=3D 0= ) { + return EFI_INVALID_PARAMETER; + } + + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable)= ) { + return EFI_INVALID_PARAMETER; + } + + if ((UINTN)StackSwitchData->TssDesc >=3D + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize))= { + return EFI_INVALID_PARAMETER; + } + + GdtSize =3D (UINTN)StackSwitchData->TssDesc - + (UINTN)(StackSwitchData->GdtTable) + + sizeof (IA32_TSS_DESCRIPTOR); + if (GdtSize > StackSwitchData->GdtSize) { + return EFI_INVALID_PARAMETER; + } + + // + // Initialize new GDT table and/or IDT table, if any + // + AsmReadIdtr (&Idtr); + AsmReadGdtr (&Gdtr); + if ((UINTN)StackSwitchData->GdtTable !=3D Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN)StackSwitchData->GdtTable; + Gdtr.Limit =3D (UINT16)GdtSize - 1; + } + + if ((UINTN)StackSwitchData->IdtTable !=3D Idtr.Base) { + Idtr.Base =3D (UINTN)StackSwitchData->IdtTable; + } + + // + // Fixup current task descriptor. Task-state segment for current task wi= ll + // be filled by processor during task switching. + // + TssDesc =3D StackSwitchData->TssDesc; + Tss =3D StackSwitchData->Tss; + + TssBase =3D (UINTN)Tss; + TssDesc->Bits.LimitLow =3D sizeof(IA32_TASK_STATE_SEGMENT) - 1; + TssDesc->Bits.BaseLow =3D (UINT16)TssBase; + TssDesc->Bits.BaseMidl =3D (UINT8)(TssBase >> 16); + TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; + TssDesc->Bits.P =3D 1; + TssDesc->Bits.LimitHigh =3D 0; + TssDesc->Bits.BaseMidh =3D (UINT8)(TssBase >> 24); + TssDesc->Bits.BaseHigh =3D (UINT32)(TssBase >> 32); + + // + // Fixup exception task descriptor and task-state segment + // + StackTop =3D StackSwitchData->StackTop - CPU_STACK_ALIGNMENT; + StackTop =3D (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); + IdtTable =3D StackSwitchData->IdtTable; + for (Index =3D 0; Index < StackSwitchData->ExceptionNumber; ++Index) { + // + // Fixup IST + // + Tss->IST[Index] =3D StackTop; + StackTop -=3D StackSwitchData->StackSize; + + // + // Set the IST field to enable corresponding IST + // + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =3D (UINT= 8)(Index + 1); + } + + // + // Publish GDT + // + AsmWriteGdtr (&Gdtr); + + // + // Load current task + // + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base)); + + // + // Publish IDT + // + AsmWriteIdtr (&Idtr); + + return EFI_SUCCESS; +} + /** Display CPU information. =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDef= s.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h index 906480134a..c88be46286 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h @@ -43,4 +43,7 @@ typedef struct { UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; } RESERVED_VECTORS_DATA; =20 +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR) +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT) + #endif --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:33:06 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511340376029805.1574924130762; Wed, 22 Nov 2017 00:46:16 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE3CC220B9006; Wed, 22 Nov 2017 00:41:54 -0800 (PST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D4AC8220B9001 for ; Wed, 22 Nov 2017 00:41:53 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:46:09 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.71]) by orsmga005.jf.intel.com with ESMTP; 22 Nov 2017 00:46:05 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="176479205" From: Jian J Wang To: edk2-devel@lists.01.org Date: Wed, 22 Nov 2017 16:45:48 +0800 Message-Id: <20171122084548.6564-9-jian.j.wang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20171122084548.6564-1-jian.j.wang@intel.com> References: <20171122084548.6564-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Jiewen Yao , Laszlo Ersek , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" > v2: > Add code to reserve resources and initialize AP exception with stack > switch besides BSP, if PcdCpuStackGuard is enabled. In current MP implementation, BSP and AP shares the same exception configuration. Stack switch required by Stack Guard feature needs that BSP and AP have their own configuration. This patch adds code to ask BSP and AP to do exception handler initialization separately. Cc: Eric Dong Cc: Laszlo Ersek Cc: Jiewen Yao Cc: Michael Kinney Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + UefiCpuPkg/CpuDxe/CpuMp.c | 168 +++++++++++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/CpuDxe/CpuMp.h | 12 ++++ 3 files changed, 183 insertions(+) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 3e8d196739..02f86b774c 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -81,6 +81,9 @@ =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ##= CONSUMES =20 [Depex] TRUE diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c index b3c0178d07..6b2ceacb39 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.c +++ b/UefiCpuPkg/CpuDxe/CpuMp.c @@ -601,6 +601,169 @@ CollectBistDataFromHob ( } } =20 +/** + Get GDT register content. + + This function is mainly for AP purpose because AP may have different GDT + table than BSP. + +**/ +VOID +EFIAPI +GetGdtr ( + IN OUT VOID *Buffer + ) +{ + AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); +} + +/** + Initializes CPU exceptions handlers for the sake of stack switch require= ment. + + This function is a wrapper of InitializeCpuExceptionStackSwitchHandlers. + It's mainly for AP purpose because of EFI_AP_PROCEDURE API requirement. + +**/ +VOID +EFIAPI +InitializeExceptionStackSwitchHandlers ( + IN OUT VOID *Buffer + ) +{ + EXCEPTION_STACK_SWITCH_DATA *EssData; + IA32_DESCRIPTOR Idtr; + EFI_STATUS Status; + + EssData =3D Buffer; + // + // We don't plan to replace IDT table with a new one, and we don't assume + // the AP's IDT is the same as BSP's IDT either. + // + AsmReadIdtr (&Idtr); + EssData->IdtTable =3D (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base; + Status =3D InitializeCpuExceptionStackSwitchHandlers (EssData); + ASSERT_EFI_ERROR (Status); +} + +/** + Initializes MP exceptions handlers for the sake of stack switch requirem= ent. + + This function will allocate required resources for stack switch and pass + them through EXCEPTION_STACK_SWITCH_DATA to each logic processor. + +**/ +VOID +InitializeMpExceptionStackSwitchHandlers ( + VOID + ) +{ + UINTN Index; + UINTN Bsp; + UINTN ExceptionNumber; + UINTN NewGdtSize; + UINTN NewStackSize; + IA32_DESCRIPTOR Gdtr; + EXCEPTION_STACK_SWITCH_DATA EssData; + UINT8 *GdtBuffer; + UINT8 *StackTop; + + if (!PcdGetBool (PcdCpuStackGuard)) { + return; + } + + ExceptionNumber =3D FixedPcdGetSize (PcdCpuStackSwitchExceptionList); + NewStackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNum= ber; + + StackTop =3D AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors= ); + ASSERT (StackTop !=3D NULL); + StackTop +=3D NewStackSize * mNumberOfProcessors; + + EssData.Exceptions =3D FixedPcdGetPtr (PcdCpuStackSwitchExceptionList); + EssData.ExceptionNumber =3D ExceptionNumber; + EssData.StackSize =3D FixedPcdGet32 (PcdCpuKnownGoodStackSize); + + MpInitLibWhoAmI (&Bsp); + for (Index =3D 0; Index < mNumberOfProcessors; ++Index) { + // + // To support stack switch, we need to re-construct GDT but not IDT. + // + if (Index =3D=3D Bsp) { + GetGdtr (&Gdtr); + } else { + // + // AP might have different size of GDT from BSP. + // + MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL= ); + } + + // + // X64 needs only one TSS of current task working for all exceptions + // because of its IST feature. IA32 needs one TSS for each exception + // in addition to current task. Since AP is not supposed to allocate + // memory, we have to do it in BSP. To simplify the code, we allocate + // memory for IA32 case to cover both IA32 and X64 exception stack + // switch. + // + // Layout of memory to allocate for each processor: + // -------------------------------- + // | Alignment | (just in case) + // -------------------------------- + // | | + // | Original GDT | + // | | + // -------------------------------- + // | Current task descriptor | + // -------------------------------- + // | | + // | Exception task descriptors | X ExceptionNumber + // | | + // -------------------------------- + // | Current task-state segment | + // -------------------------------- + // | | + // | Exception task-state segment | X ExceptionNumber + // | | + // -------------------------------- + // + NewGdtSize =3D sizeof (IA32_TSS_DESCRIPTOR) + + (Gdtr.Limit + 1) + + sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1) + + sizeof (IA32_TASK_STATE_SEGMENT) * (ExceptionNumber + 1); + GdtBuffer =3D AllocateRuntimeZeroPool (NewGdtSize); + ASSERT (GdtBuffer !=3D NULL); + + EssData.GdtTable =3D ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIP= TOR)); + NewGdtSize -=3D ((UINT8 *)EssData.GdtTable - GdtBuffer); + EssData.GdtSize =3D NewGdtSize; + + EssData.TssDesc =3D (IA32_TSS_DESCRIPTOR *)((UINTN)EssData.GdtTable + + Gdtr.Limit + 1); + EssData.Tss =3D (IA32_TASK_STATE_SEGMENT *)((UINTN)EssData.GdtTable + + Gdtr.Limit + 1 + + sizeof (IA32_TSS_DESCRIPTOR)= * + (ExceptionNumber + 1)); + + EssData.StackTop =3D (UINTN)StackTop; + DEBUG ((DEBUG_INFO, "Exception stack top[%d]: 0x%lX\n", Index, + (UINT64)(UINTN)StackTop)); + + if (Index =3D=3D Bsp) { + InitializeExceptionStackSwitchHandlers (&EssData); + } else { + MpInitLibStartupThisAP ( + InitializeExceptionStackSwitchHandlers, + Index, + NULL, + 0, + (VOID *)&EssData, + NULL + ); + } + + StackTop -=3D NewStackSize; + } +} + /** Initialize Multi-processor support. =20 @@ -624,6 +787,11 @@ InitializeMpSupport ( mNumberOfProcessors =3D NumberOfProcessors; DEBUG ((DEBUG_INFO, "Detect CPU count: %d\n", mNumberOfProcessors)); =20 + // + // Initialize exception stack switch handlers for each logic processor. + // + InitializeMpExceptionStackSwitchHandlers (); + // // Update CPU healthy information from Guided HOB // diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h index d530149d7e..86d54a95e9 100644 --- a/UefiCpuPkg/CpuDxe/CpuMp.h +++ b/UefiCpuPkg/CpuDxe/CpuMp.h @@ -15,6 +15,18 @@ #ifndef _CPU_MP_H_ #define _CPU_MP_H_ =20 +typedef struct { + UINTN StackTop; + UINTN StackSize; + UINT8 *Exceptions; + UINTN ExceptionNumber; + IA32_IDT_GATE_DESCRIPTOR *IdtTable; + IA32_SEGMENT_DESCRIPTOR *GdtTable; + UINTN GdtSize; + IA32_TSS_DESCRIPTOR *TssDesc; + IA32_TASK_STATE_SEGMENT *Tss; +} EXCEPTION_STACK_SWITCH_DATA; + /** Initialize Multi-processor support. =20 --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel