From nobody Thu Apr 18 18:59:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507104761338402.5635048917828; Wed, 4 Oct 2017 01:12:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 93E4421F322B1; Wed, 4 Oct 2017 01:09:18 -0700 (PDT) Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9F410208F7903 for ; Wed, 4 Oct 2017 01:09:17 -0700 (PDT) Received: by mail-wm0-x232.google.com with SMTP id k4so19270665wmc.1 for ; Wed, 04 Oct 2017 01:12:38 -0700 (PDT) Received: from vanye.hemma.eciton.net (cpc92316-cmbg19-2-0-cust118.5-4.cable.virginm.net. [82.12.0.119]) by smtp.gmail.com with ESMTPSA id c24sm11161871wrg.92.2017.10.04.01.12.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Oct 2017 01:12:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::232; helo=mail-wm0-x232.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Gzpg/vjf5HI0LSVZsl9s0hyOby/v4JMOQ96bOKBf0kU=; b=FSsn6YrS+w/cJwzVKAVuHglj/SyuKgAgXeyxCSMACRvK8ZGMuFkLb23PnP6Xiby0+h VQx2747s/LXgPb6fZ2RWf5qvklhcGNvB7C+PGaxsxIo18UqypDFQoYxglehUoF+OwgR4 /cYTkoHPKChtXh1/U8eTkfbUWhJmZOObQjLxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Gzpg/vjf5HI0LSVZsl9s0hyOby/v4JMOQ96bOKBf0kU=; b=E49NEAi5Xm4u/Xmh6IDbrIhUtsxBXEY1Ku/ywwRuiZC4zPA5pxwujKEqnFxw44NCUP Nkl0Oi1FRC78cT68aC2s7XyP4jgj6iuIP0w3JJyk6xdKbWhbRaoLB0wd2N2aKBbztbBz EYZTHss04EBItZoyb+yoRZfQ1hnz7ujGoRXBvziDAUQxgzDeUxQSrYL7dWZr5dq4leWo eNE8HDEeObNASZHhmDe5gb9AVK0Vfypr+1Nw3O0tt1D4MF7gg0VZsuOqaBVWBg62m1hR stu++u5GlUaSSjsusckAE66H65Q7TClP4SqvRYHIoRUo7b3Lb8Somlc5L+P+ygz3xtV9 W19Q== X-Gm-Message-State: AMCzsaU7PWM5OUadvGtEHKjtswB4/wtvGMLb60E8QxWPjoA1B/QSfpLI yKEYlWfJHNHw++UPpHrVeC4cD6SbRCE= X-Google-Smtp-Source: AOwi7QDA5bsNvSH2YEWQzp4ACdkWEjkgGwLtynsiv/7eWjTKcqZ1BEmI1TiI6u4+gbHfZsiGB3spQA== X-Received: by 10.28.129.194 with SMTP id c185mr9575542wmd.49.1507104756107; Wed, 04 Oct 2017 01:12:36 -0700 (PDT) From: Leif Lindholm To: edk2-devel@lists.01.org Date: Wed, 4 Oct 2017 09:12:33 +0100 Message-Id: <20171004081233.5095-1-leif.lindholm@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH] Platform/Hisilicon: fix D02 driver indentation errors X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heyi Guo , ard.biesheuvel@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When building with a somewhat recent toolchain (GCC 6.3), the D02 platform fails due to (the implicit) -Werror=3Dmisleading-indentation. Cc: Heyi Guo Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c | 4 ++-- Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Silicon/Hisili= con/Drivers/SasV1Dxe/SasV1Dxe.c index d876565a7d..b18b56ddb2 100644 --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c +++ b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c @@ -497,8 +497,8 @@ STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLAT= FORM_SAS_PROTOCOL *plat) !(dma_rx_status & DMA_RX_STATUS_BUSY)) break; =20 - // Wait for status change in polling - NanoSecondDelay (100); + // Wait for status change in polling + NanoSecondDelay (100); } } =20 diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Si= licon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c index 3581b41c90..3739a36e64 100644 --- a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c @@ -570,7 +570,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT= 32 Port) if (pcs_local_status_checked) DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n")); =20 - count =3D 0; + count =3D 0; do { MicroSecondDelay(1000); count ++; @@ -583,7 +583,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT= 32 Port) if (hilink_status_checked) DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n")); =20 - return EFI_SUCCESS; + return EFI_SUCCESS; } =20 EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) @@ -616,7 +616,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, U= INT32 Port) if (pcs_local_status_checked) DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); =20 - count =3D 0; + count =3D 0; do { MicroSecondDelay(1000); RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HI= LINK_PCS_RESET_ST_REG, hilink_reset_status); @@ -627,7 +627,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, U= INT32 Port) if (hilink_status_checked) DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); =20 - return EFI_SUCCESS; + return EFI_SUCCESS; } =20 VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port) @@ -777,7 +777,7 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 Hos= tBridgeNum, UINT32 Port, if (clock_status_checked) DEBUG((EFI_D_ERROR, "clock operation failed!\n")); =20 - return EFI_SUCCESS; + return EFI_SUCCESS; } =20 VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 S= pd) --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel