From nobody Sun Apr 28 20:56:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1505964379047973.9124839698525; Wed, 20 Sep 2017 20:26:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B73FF21E2BE5F; Wed, 20 Sep 2017 20:23:09 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 08AE521D492E4 for ; Wed, 20 Sep 2017 20:23:08 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Sep 2017 20:26:14 -0700 Received: from zwei4-mobl1.ccr.corp.intel.com ([10.239.193.189]) by orsmga002.jf.intel.com with ESMTP; 20 Sep 2017 20:26:13 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,423,1500966000"; d="scan'208";a="137748070" From: zwei4 To: edk2-devel@lists.01.org Date: Thu, 21 Sep 2017 11:26:09 +0800 Message-Id: <20170921032609.17964-1-david.wei@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Calibrate PMIC IMON. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 --- .../PlatformPostMemPei/PlatformInit.c | 49 ++++++++++++++++++= ++++ .../PlatformSettings/PlatformSetupDxe/UnCore.vfi | 6 +-- .../BroxtonSiPkg/NorthCluster/Include/SaRegs.h | 8 +++- 3 files changed, 59 insertions(+), 4 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPo= stMemPei/PlatformInit.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettin= gs/PlatformPostMemPei/PlatformInit.c index bfed3bf1a..7d003e466 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPe= i/PlatformInit.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPostMemPe= i/PlatformInit.c @@ -311,6 +311,53 @@ BXTPolicyInit ( return EFI_SUCCESS; } =20 +VOID +ConfigurePmicIMON ( + VOID + ) +{ + UINTN PciD0F0RegBase =3D 0; + UINTN MchBar =3D 0; + UINT32 Data; + UINT16 StallCount; + UINT64 PkgPwrSKU; + + PciD0F0RegBase =3D MmPciAddress (0,SA_MC_BUS,SA_MC_DEV,SA_MC_FUN,0); + MchBar =3D MmioRead32 (PciD0F0RegBase + R_SA_MCHBAR_REG) &~BIT0; + PkgPwrSKU =3D AsmReadMsr64 (MSR_PACKAGE_POWER_SKU); + + StallCount =3D 0; + while (StallCount < 1000) { + Data =3D MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE);=20 + if ((Data & BIT31) =3D=3D BIT31) { + MicroSecondDelay (1); + } else { + break; + } + StallCount++; + } + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xfa0d04a4); + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000011d); + + StallCount =3D 0; + while (StallCount < 1000) { + Data =3D MmioRead32 (MchBar + R_BIOS_MAILBOX_INTERFACE); + if ((Data & BIT31) =3D=3D BIT31) { + MicroSecondDelay (1); + } else { + break; + } + StallCount++; + } + + if ((PkgPwrSKU & 0x07FFF) >=3D 0x0903){ + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xe8330466); + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000001d); + } else {=20 + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_DATA), 0xed3303b3); + MmioWrite32 ( (MchBar + R_BIOS_MAILBOX_INTERFACE), 0x8000001d); + } +} =20 /** Platform Init PEI module entry point @@ -363,6 +410,8 @@ PlatformInitEntryPoint ( } =20 PWM_Fan_Start (); + =20 + ConfigurePmicIMON(); =20 // // Initialize PlatformInfo HOB diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSe= tupDxe/UnCore.vfi b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/Pla= tformSetupDxe/UnCore.vfi index 32eea2005..f8b4b47ec 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= UnCore.vfi +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= UnCore.vfi @@ -1,7 +1,7 @@ // /** @file // UnCore Setup formset. // -// Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+// Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
// // This program and the accompanying materials // are licensed and made available under the terms and conditions of the = BSD License @@ -104,8 +104,8 @@ form formid =3D UNCORE_FORM_ID, oneof varid =3D Setup.EnableRenderStandby, prompt =3D STRING_TOKEN(STR_VIDEO_RS2_PROMPT), help =3D STRING_TOKEN(STR_VIDEO_RS2_HELP), - option text =3D STRING_TOKEN(STR_ENABLE), value =3D 1, flags =3D DEFAUL= T | MANUFACTURING | RESET_REQUIRED; - option text =3D STRING_TOKEN(STR_DISABLE), value =3D 0, flags =3D RESET= _REQUIRED; + option text =3D STRING_TOKEN(STR_ENABLE), value =3D 1, flags =3D RESET_= REQUIRED; + option text =3D STRING_TOKEN(STR_DISABLE), value =3D 0, flags =3D DEFAU= LT | MANUFACTURING | RESET_REQUIRED; endoneof; =20 oneof varid =3D Setup.GTTSize, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h = b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h index 5dd844092..e985e75c4 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h @@ -15,7 +15,7 @@ Registers / bits of new devices introduced in a SA generation will be ju= st named as "_SA_" without [generation_name] inserted. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -59,6 +59,12 @@ #define R_SA_MC_CAPID0_B 0xE8 #define R_SA_MCHBAR_REG 0x48 =20 +// +// IA-Punit Mailbox on MCH BAR=20 +// +#define R_BIOS_MAILBOX_DATA 0x7080 +#define R_BIOS_MAILBOX_INTERFACE 0x7084 + // // Silicon Steppings // --=20 2.14.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel