From nobody Sun May 5 05:31:51 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1505913779985557.2539909631046; Wed, 20 Sep 2017 06:22:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E15D221ECCB31; Wed, 20 Sep 2017 06:19:52 -0700 (PDT) Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 313E321ECCB13 for ; Wed, 20 Sep 2017 06:19:51 -0700 (PDT) Received: by mail-wr0-x22b.google.com with SMTP id a43so2161051wrc.0 for ; Wed, 20 Sep 2017 06:22:57 -0700 (PDT) Received: from vanye.hemma.eciton.net (cpc92316-cmbg19-2-0-cust118.5-4.cable.virginm.net. [82.12.0.119]) by smtp.gmail.com with ESMTPSA id 200sm1702827wmu.44.2017.09.20.06.22.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Sep 2017 06:22:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=keDACQGeXKsIebok8uAMz3zy3ICXJ7nSIYZsiYWCa0Y=; b=K3qXycAlBcEw864dcLWTuozW8PGOMRnXfUX3EygylTIu7Z+m1BlUMh6jZmqhvofwzV H5mxfzAJ0x1A6zCO6ybRXr32oEqLnnth9ilAVH5mEXkKY4g8Ndeg7YDj0eyQGTwVXiS7 3c7reo3I6l5jmqCXAeBgp57w5Bt0r+imc+jgk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=keDACQGeXKsIebok8uAMz3zy3ICXJ7nSIYZsiYWCa0Y=; b=eMjmBI1vRiI/ZMf8U4iQ2ZQe72nYhHDetotXANd2bGzjG9oGWKqF0xIxEhAF/b2Ee+ fJ7UNJSeMeQiXZDBl0gCd2UwHa7NL1Dwfzp/n4lFHjEGVH5Fsmk8KLO09zazf3SkGw5G mSrteDiFx5oRfc5s7FE3IFK/VV5ODOS3oW8YxtFFNc3iuAAmKqK8wAThVWqBN/iobUeU avh+4F8yRpN/UPzqMRUP1maEygP33AcoRY9z2QvjVykIVXxiLGrKE0bTRqNB9/miG10X hdbEmym70P1HF4w/PYNqwcPoxU8xfyZO9QwWcKX3LYUPH5dQY1pE6OZJ/I78lEVkBNQO /X5g== X-Gm-Message-State: AHPjjUhSXL9btQ+AESBJyrKL+UGzFGHdNteoE998+ccY7JSPjBJ10ukC MvbVpncojegqly8s0QTTR1leuBDfmKY= X-Google-Smtp-Source: AOwi7QDucVLQ0gSllvOz3oskSczhHXNORuXUjMzYWdFzYlv7Bo5Y5pdAD8lsaYoOyIGW1P3phDLeBA== X-Received: by 10.223.171.206 with SMTP id s72mr4530861wrc.27.1505913775116; Wed, 20 Sep 2017 06:22:55 -0700 (PDT) From: Leif Lindholm To: edk2-devel@lists.01.org Date: Wed, 20 Sep 2017 14:22:52 +0100 Message-Id: <20170920132252.11761-1-leif.lindholm@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH] MdePkg: add ARM/AARCH64 support to BaseCacheMaintenanceLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Liming Gao , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ARM platforms have been using a separately located library in ArmPkg for high-level cache maintenance calls. Resolve this anomaly by overwriting ArmCache.c with the contents of ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c, and add the ArmLib dependency for the affected architectures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm --- The intent is to delete the ArmPkg version once no upstream platforms are using it. MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c | 222 +++++------------= ---- .../BaseCacheMaintenanceLib.inf | 2 + 2 files changed, 55 insertions(+), 169 deletions(-) diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c b/MdePkg/Lib= rary/BaseCacheMaintenanceLib/ArmCache.c index 79c84a0982..0759e38cd4 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c @@ -1,67 +1,63 @@ /** @file - Cache Maintenance Functions. These functions vary by ARM architecture so= the MdePkg=20 - versions are null functions used to make sure things will compile.=20 =20 - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. + This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php. + http://opensource.org/licenses/bsd-license.php =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ - -// -// Include common header file for this module. -// #include +#include #include +#include =20 -/** - Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. - - Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. +STATIC +VOID +CacheRangeOperation ( + IN VOID *Start, + IN UINTN Length, + IN LINE_OPERATION LineOperation, + IN UINTN LineLength + ) +{ + UINTN ArmCacheLineAlignmentMask =3D LineLength - 1; + + // Align address (rounding down) + UINTN AlignedAddress =3D (UINTN)Start - ((UINTN)Start & ArmCacheLineAlig= nmentMask); + UINTN EndAddress =3D (UINTN)Start + Length; + + // Perform the line operation on an address in each cache line + while (AlignedAddress < EndAddress) { + LineOperation(AlignedAddress); + AlignedAddress +=3D LineLength; + } + ArmDataSynchronizationBarrier (); +} =20 -**/ VOID EFIAPI InvalidateInstructionCache ( VOID ) { - ASSERT(FALSE); + ASSERT (FALSE); } =20 -/** - Invalidates a range of instruction cache lines in the cache coherency do= main - of the calling CPU. - - Invalidates the instruction cache lines specified by Address and Length.= If - Address is not aligned on a cache line boundary, then entire instruction - cache line containing Address is invalidated. If Address + Length is not - aligned on a cache line boundary, then the entire instruction cache line - containing Address + Length -1 is invalidated. This function may choose = to - invalidate the entire instruction cache if that is more efficient than - invalidating the specified range. If Length is 0, then no instruction ca= che - lines are invalidated. Address is returned. - - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). - - @param Address The base address of the instruction cache lines to - invalidate. If the CPU is in a physical addressing mode,= then - Address is a physical address. If the CPU is in a virtual - addressing mode, then Address is a virtual address. - - @param Length The number of bytes to invalidate from the instruction c= ache. - - @return Address +VOID +EFIAPI +InvalidateDataCache ( + VOID + ) +{ + ASSERT (FALSE); +} =20 -**/ VOID * EFIAPI InvalidateInstructionCacheRange ( @@ -69,56 +65,26 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); - ASSERT(FALSE); - return Address; -} + CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA, + ArmDataCacheLineLength ()); + CacheRangeOperation (Address, Length, + ArmInvalidateInstructionCacheEntryToPoUByMVA, + ArmInstructionCacheLineLength ()); =20 -/** - Writes back and invalidates the entire data cache in cache coherency dom= ain - of the calling CPU. + ArmInstructionSynchronizationBarrier (); =20 - Writes Back and Invalidates the entire data cache in cache coherency dom= ain - of the calling CPU. This function guarantees that all dirty cache lines = are - written back to system memory, and also invalidates all the data cache l= ines - in the cache coherency domain of the calling CPU. + return Address; +} =20 -**/ VOID EFIAPI WriteBackInvalidateDataCache ( VOID ) { - ASSERT(FALSE); + ASSERT (FALSE); } =20 -/** - Writes back and invalidates a range of data cache lines in the cache - coherency domain of the calling CPU. - - Writes back and invalidates the data cache lines specified by Address and - Length. If Address is not aligned on a cache line boundary, then entire = data - cache line containing Address is written back and invalidated. If Addres= s + - Length is not aligned on a cache line boundary, then the entire data cac= he - line containing Address + Length -1 is written back and invalidated. This - function may choose to write back and invalidate the entire data cache if - that is more efficient than writing back and invalidating the specified - range. If Length is 0, then no data cache lines are written back and - invalidated. Address is returned. - - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). - - @param Address The base address of the data cache lines to write back a= nd - invalidate. If the CPU is in a physical addressing mode,= then - Address is a physical address. If the CPU is in a virtual - addressing mode, then Address is a virtual address. - @param Length The number of bytes to write back and invalidate from the - data cache. - - @return Address - -**/ VOID * EFIAPI WriteBackInvalidateDataCacheRange ( @@ -126,55 +92,20 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); - ASSERT(FALSE); + CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByM= VA, + ArmDataCacheLineLength ()); return Address; } =20 -/** - Writes back the entire data cache in cache coherency domain of the calli= ng - CPU. - - Writes back the entire data cache in cache coherency domain of the calli= ng - CPU. This function guarantees that all dirty cache lines are written bac= k to - system memory. This function may also invalidate all the data cache line= s in - the cache coherency domain of the calling CPU. - -**/ VOID EFIAPI WriteBackDataCache ( VOID ) { - ASSERT(FALSE); + ASSERT (FALSE); } =20 -/** - Writes back a range of data cache lines in the cache coherency domain of= the - calling CPU. - - Writes back the data cache lines specified by Address and Length. If Add= ress - is not aligned on a cache line boundary, then entire data cache line - containing Address is written back. If Address + Length is not aligned o= n a - cache line boundary, then the entire data cache line containing Address + - Length -1 is written back. This function may choose to write back the en= tire - data cache if that is more efficient than writing back the specified ran= ge. - If Length is 0, then no data cache lines are written back. This function= may - also invalidate all the data cache lines in the specified range of the c= ache - coherency domain of the calling CPU. Address is returned. - - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). - - @param Address The base address of the data cache lines to write back. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing - mode, then Address is a virtual address. - @param Length The number of bytes to write back from the data cache. - - @return Address - -**/ VOID * EFIAPI WriteBackDataCacheRange ( @@ -182,58 +113,11 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); - ASSERT(FALSE); + CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA, + ArmDataCacheLineLength ()); return Address; } =20 -/** - Invalidates the entire data cache in cache coherency domain of the calli= ng - CPU. - - Invalidates the entire data cache in cache coherency domain of the calli= ng - CPU. This function must be used with care because dirty cache lines are = not - written back to system memory. It is typically used for cache diagnostic= s. If - the CPU does not support invalidation of the entire data cache, then a w= rite - back and invalidate operation should be performed on the entire data cac= he. - -**/ -VOID -EFIAPI -InvalidateDataCache ( - VOID - ) -{ - ASSERT(FALSE); -} - -/** - Invalidates a range of data cache lines in the cache coherency domain of= the - calling CPU. - - Invalidates the data cache lines specified by Address and Length. If Add= ress - is not aligned on a cache line boundary, then entire data cache line - containing Address is invalidated. If Address + Length is not aligned on= a - cache line boundary, then the entire data cache line containing Address + - Length -1 is invalidated. This function must never invalidate any cache = lines - outside the specified range. If Length is 0, then no data cache lines are - invalidated. Address is returned. This function must be used with care - because dirty cache lines are not written back to system memory. It is - typically used for cache diagnostics. If the CPU does not support - invalidation of a data cache range, then a write back and invalidate - operation should be performed on the data cache range. - - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). - - @param Address The base address of the data cache lines to invalidate. = If - the CPU is in a physical addressing mode, then Address i= s a - physical address. If the CPU is in a virtual addressing = mode, - then Address is a virtual address. - @param Length The number of bytes to invalidate from the data cache. - - @return Address - -**/ VOID * EFIAPI InvalidateDataCacheRange ( @@ -241,7 +125,7 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); - ASSERT(FALSE); + CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA, + ArmDataCacheLineLength ()); return Address; } diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index d659161f33..7440a0062b 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -59,3 +59,5 @@ [LibraryClasses.Ipf] PalLib =20 +[LibraryClasses.ARM,LibraryClasses.AARCH64] + ArmLib --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel