From nobody Mon Apr 29 13:53:17 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1505848706757161.29826413867897; Tue, 19 Sep 2017 12:18:26 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D37B421E87976; Tue, 19 Sep 2017 12:15:20 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A58B521CEB108 for ; Tue, 19 Sep 2017 12:15:19 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2F01180468; Tue, 19 Sep 2017 19:18:24 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-37.rdu2.redhat.com [10.10.120.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 059305D6A4; Tue, 19 Sep 2017 19:18:21 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2F01180468 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=lersek@redhat.com From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 19 Sep 2017 21:18:13 +0200 Message-Id: <20170919191815.3004-2-lersek@redhat.com> In-Reply-To: <20170919191815.3004-1-lersek@redhat.com> References: <20170919191815.3004-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 19 Sep 2017 19:18:24 +0000 (UTC) Subject: [edk2] [PATCH 1/3] OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Aleksei Kovura , Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" * Introduce the PIIX4_PAM* and MCH_PAM* macros under "OvmfPkg/Include/IndustryStandard". These macros capture the PAM register offsets (in PCI config space) on the respective Memory Controller B/D/F, from the respective data sheets. * Under IndustryStandard, introduce the PMC_REGISTER_PIIX4() macro for PIIX4. (For Q35, we already have DRAMC_REGISTER_Q35().) In both cases, the B/D/F is 0/0/0. * Under CsmSupportLib, replace the "PAMRegOffset" field (UINT8) in the PAM_REGISTER_VALUE structure with "PAMRegPciLibAddress" (UINTN). The new field contains the return value of the PCI_LIB_ADDRESS() macro. * Under CsmSupportLib, replace the "mRegisterValues440" elements as follows: REG_PAMx_OFFSET_440, ReadEnableData, WriteEnableData --> PMC_REGISTER_PIIX4 (PIIX4_PAMx), ReadEnableData, WriteEnableData * Under CsmSupportLib, replace the "mRegisterValuesQ35" elements as follows: REG_PAMx_OFFSET_Q35, ReadEnableData, WriteEnableData --> DRAMC_REGISTER_Q35 (MCH_PAMx), ReadEnableData, WriteEnableData * Under CsmSupportLib, update the register address calculations as follows (for all of PciOr8(), PciAnd8() and PciRead8()): PCI_LIB_ADDRESS ( PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset ) --> mRegisterValues[Index].PAMRegPciLibAddress * Under CsmSupportLib, remove the PAM_PCI_* and REG_PAM*_OFFSET_* macros. Technically speaking, these changes could be split into three patches (IndustryStandard macro additions, CsmSupportLib code updates, CsmSupportLib macro removals). However, the patch is not big, and in this case it is actually helpful to present the code movement / refactoring in one step, for easier verification. Cc: Aleksei Kovura Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugs.launchpad.net/qemu/+bug/1715700 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Tested-by: Aleksei Kovura --- OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 22 +------ OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++ OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 8 +++ OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 62 ++++++++++---------- 4 files changed, 53 insertions(+), 52 deletions(-) diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupp= ortLib/LegacyRegion.h index f755a2a359e5..01d3109a7d7d 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h @@ -30,26 +30,6 @@ #include #include =20 -#define PAM_PCI_BUS 0 -#define PAM_PCI_DEV 0 -#define PAM_PCI_FUNC 0 - -#define REG_PAM0_OFFSET_440 0x59 // Programmable Attribute Map 0 -#define REG_PAM1_OFFSET_440 0x5a // Programmable Attribute Map 1 -#define REG_PAM2_OFFSET_440 0x5b // Programmable Attribute Map 2 -#define REG_PAM3_OFFSET_440 0x5c // Programmable Attribute Map 3 -#define REG_PAM4_OFFSET_440 0x5d // Programmable Attribute Map 4 -#define REG_PAM5_OFFSET_440 0x5e // Programmable Attribute Map 5 -#define REG_PAM6_OFFSET_440 0x5f // Programmable Attribute Map 6 - -#define REG_PAM0_OFFSET_Q35 0x90 // Programmable Attribute Map 0 -#define REG_PAM1_OFFSET_Q35 0x91 // Programmable Attribute Map 1 -#define REG_PAM2_OFFSET_Q35 0x92 // Programmable Attribute Map 2 -#define REG_PAM3_OFFSET_Q35 0x93 // Programmable Attribute Map 3 -#define REG_PAM4_OFFSET_Q35 0x94 // Programmable Attribute Map 4 -#define REG_PAM5_OFFSET_Q35 0x95 // Programmable Attribute Map 5 -#define REG_PAM6_OFFSET_Q35 0x96 // Programmable Attribute Map 6 - #define PAM_BASE_ADDRESS 0xc0000 #define PAM_LIMIT_ADDRESS BASE_1MB =20 @@ -67,7 +47,7 @@ typedef struct { // Provides a map of the PAM registers and bits used to set Read/Write acc= ess. // typedef struct { - UINT8 PAMRegOffset; + UINTN PAMRegPciLibAddress; UINT8 ReadEnableData; UINT8 WriteEnableData; } PAM_REGISTER_VALUE; diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Inclu= de/IndustryStandard/I440FxPiix4.h index baa4c063f16a..efe6e5c27834 100644 --- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h +++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h @@ -27,6 +27,19 @@ // #define INTEL_82441_DEVICE_ID 0x1237 =20 +// +// B/D/F/Type: 0/0/0/PCI +// +#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) + +#define PIIX4_PAM0 0x59 +#define PIIX4_PAM1 0x5A +#define PIIX4_PAM2 0x5B +#define PIIX4_PAM3 0x5C +#define PIIX4_PAM4 0x5D +#define PIIX4_PAM5 0x5E +#define PIIX4_PAM6 0x5F + // // B/D/F/Type: 0/1/3/PCI // diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Includ= e/IndustryStandard/Q35MchIch9.h index 68485bec71f7..193a262e5b54 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -47,6 +47,14 @@ #define MCH_PCIEXBAR_HIGH 0x64 #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 =20 +#define MCH_PAM0 0x90 +#define MCH_PAM1 0x91 +#define MCH_PAM2 0x92 +#define MCH_PAM3 0x93 +#define MCH_PAM4 0x94 +#define MCH_PAM5 0x95 +#define MCH_PAM6 0x96 + #define MCH_SMRAM 0x9D #define MCH_SMRAM_D_LCK BIT4 #define MCH_SMRAM_G_SMRAME BIT3 diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupp= ortLib/LegacyRegion.c index 8d5d2e58a994..c13d4bb88f47 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c @@ -52,35 +52,35 @@ STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] =3D= { }; =20 STATIC PAM_REGISTER_VALUE mRegisterValues440[] =3D { - {REG_PAM1_OFFSET_440, 0x01, 0x02}, - {REG_PAM1_OFFSET_440, 0x10, 0x20}, - {REG_PAM2_OFFSET_440, 0x01, 0x02}, - {REG_PAM2_OFFSET_440, 0x10, 0x20}, - {REG_PAM3_OFFSET_440, 0x01, 0x02}, - {REG_PAM3_OFFSET_440, 0x10, 0x20}, - {REG_PAM4_OFFSET_440, 0x01, 0x02}, - {REG_PAM4_OFFSET_440, 0x10, 0x20}, - {REG_PAM5_OFFSET_440, 0x01, 0x02}, - {REG_PAM5_OFFSET_440, 0x10, 0x20}, - {REG_PAM6_OFFSET_440, 0x01, 0x02}, - {REG_PAM6_OFFSET_440, 0x10, 0x20}, - {REG_PAM0_OFFSET_440, 0x10, 0x20} + {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20}, + {PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20} }; =20 STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] =3D { - {REG_PAM1_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM1_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM2_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM2_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM3_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM3_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM4_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM4_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM5_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM5_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM6_OFFSET_Q35, 0x01, 0x02}, - {REG_PAM6_OFFSET_Q35, 0x10, 0x20}, - {REG_PAM0_OFFSET_Q35, 0x10, 0x20} + {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02}, + {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20}, + {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20} }; =20 STATIC PAM_REGISTER_VALUE *mRegisterValues; @@ -145,12 +145,12 @@ LegacyRegionManipulationInternal ( if (ReadEnable !=3D NULL) { if (*ReadEnable) { PciOr8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegiste= rValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, mRegisterValues[Index].ReadEnableData ); } else { PciAnd8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegiste= rValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, (UINT8) (~mRegisterValues[Index].ReadEnableData) ); } @@ -158,12 +158,12 @@ LegacyRegionManipulationInternal ( if (WriteEnable !=3D NULL) { if (*WriteEnable) { PciOr8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegiste= rValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, mRegisterValues[Index].WriteEnableData ); } else { PciAnd8 ( - PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegiste= rValues[Index].PAMRegOffset), + mRegisterValues[Index].PAMRegPciLibAddress, (UINT8) (~mRegisterValues[Index].WriteEnableData) ); } @@ -204,7 +204,7 @@ LegacyRegionGetInfoInternal ( // *DescriptorCount =3D sizeof(mSectionArray) / sizeof (mSectionArray[0]); for (Index =3D 0; Index < *DescriptorCount; Index++) { - PamValue =3D PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_P= CI_FUNC, mRegisterValues[Index].PAMRegOffset)); + PamValue =3D PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress); mSectionArray[Index].ReadEnabled =3D FALSE; if ((PamValue & mRegisterValues[Index].ReadEnableData) !=3D 0) { mSectionArray[Index].ReadEnabled =3D TRUE; --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 13:53:17 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1505848710041142.49501658561815; Tue, 19 Sep 2017 12:18:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1C4D221E87985; Tue, 19 Sep 2017 12:15:24 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A96D621CEB108 for ; Tue, 19 Sep 2017 12:15:22 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 37AF5267C0; Tue, 19 Sep 2017 19:18:27 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-37.rdu2.redhat.com [10.10.120.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9F3EC5D6A6; Tue, 19 Sep 2017 19:18:25 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 37AF5267C0 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=lersek@redhat.com From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 19 Sep 2017 21:18:14 +0200 Message-Id: <20170919191815.3004-3-lersek@redhat.com> In-Reply-To: <20170919191815.3004-1-lersek@redhat.com> References: <20170919191815.3004-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 19 Sep 2017 19:18:27 +0000 (UTC) Subject: [edk2] [PATCH 2/3] OvmfPkg/QemuVideoDxe/VbeShim: rename Status to Segment0AllocationStatus X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Aleksei Kovura , Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This clarifies the purpose of the local variable in InstallVbeShim(). Cc: Aleksei Kovura Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugs.launchpad.net/qemu/+bug/1715700 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Tested-by: Aleksei Kovura --- OvmfPkg/QemuVideoDxe/VbeShim.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/OvmfPkg/QemuVideoDxe/VbeShim.c b/OvmfPkg/QemuVideoDxe/VbeShim.c index 4c4517e9da27..bc90e067266d 100644 --- a/OvmfPkg/QemuVideoDxe/VbeShim.c +++ b/OvmfPkg/QemuVideoDxe/VbeShim.c @@ -63,7 +63,7 @@ InstallVbeShim ( EFI_PHYSICAL_ADDRESS Segment0, SegmentC, SegmentF; UINTN Segment0Pages; IVT_ENTRY *Int0x10; - EFI_STATUS Status; + EFI_STATUS Segment0AllocationStatus; UINTN Pam1Address; UINT8 Pam1; UINTN SegmentCPages; @@ -87,10 +87,14 @@ InstallVbeShim ( // Segment0Pages =3D 1; Int0x10 =3D (IVT_ENTRY *)(UINTN)Segment0 + 0x10; - Status =3D gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, - Segment0Pages, &Segment0); + Segment0AllocationStatus =3D gBS->AllocatePages ( + AllocateAddress, + EfiBootServicesCode, + Segment0Pages, + &Segment0 + ); =20 - if (EFI_ERROR (Status)) { + if (EFI_ERROR (Segment0AllocationStatus)) { EFI_PHYSICAL_ADDRESS Handler; =20 // @@ -109,8 +113,12 @@ InstallVbeShim ( // Otherwise we'll overwrite the Int10h vector, even though we may not= own // the page at zero. // - DEBUG ((EFI_D_INFO, "%a: failed to allocate page at zero: %r\n", - __FUNCTION__, Status)); + DEBUG (( + DEBUG_INFO, + "%a: failed to allocate page at zero: %r\n", + __FUNCTION__, + Segment0AllocationStatus + )); } else { // // We managed to allocate the page at zero. SVN r14218 guarantees that= it --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 13:53:17 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1505848712728444.060713885739; Tue, 19 Sep 2017 12:18:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 579EB21E945ED; Tue, 19 Sep 2017 12:15:26 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0069621CEB108 for ; Tue, 19 Sep 2017 12:15:25 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 836CC272C0; Tue, 19 Sep 2017 19:18:29 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-37.rdu2.redhat.com [10.10.120.37]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8FB545D6A4; Tue, 19 Sep 2017 19:18:27 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 836CC272C0 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=lersek@redhat.com From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 19 Sep 2017 21:18:15 +0200 Message-Id: <20170919191815.3004-4-lersek@redhat.com> In-Reply-To: <20170919191815.3004-1-lersek@redhat.com> References: <20170919191815.3004-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 19 Sep 2017 19:18:29 +0000 (UTC) Subject: [edk2] [PATCH 3/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Aleksei Kovura , Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In commit db27e9f3d8f0 ("OvmfPkg/LegacyRegion: Support legacy region manipulation of Q35", 2016-03-15), Ray extended the OvmfPkg/Csm/CsmSupportLib PAM register manipulation to Q35. However, we missed that the same should be done to the QemuVideoDxe VBE Shim as well. The omission has caused no problems in practice on Q35, because QEMU has let us write to the ROM area, regardless of the PAM1 setting, all this time. This has now changed with recent QEMU commit 208fa0e43645 ("pc: make 'pc.rom' readonly when machine has PCI enabled", 2017-07-28). The QEMU commit exposes the OVMF bug when Windows 7 is started on Q35, using QEMU 2.10 -- the VBE Shim is no longer put in place and Windows 7 cannot find it. To remedy this, assign the "Pam1Address" local variable a PciLib address that matches the board type (i440fx vs. q35). Regarding the PcdLib dependency: QemuVideoDxe already uses PcdLib, both directly (see "PcdDriverSupportedEfiVersion") and indirectly (e.g. via the DxePciLibI440FxQ35 PciLib instance). Add PcdLib to [LibraryClasses] for completeness. Cc: Aleksei Kovura Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugs.launchpad.net/qemu/+bug/1715700 Reported-by: Aleksei Kovura Special-thanks-to: Gerd Hoffmann Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Tested-by: Aleksei Kovura --- OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf | 3 ++- OvmfPkg/QemuVideoDxe/VbeShim.c | 27 +++++++++++++++++++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf b/OvmfPkg/QemuVideoDxe/Q= emuVideoDxe.inf index 7c7d429bca27..577e07b0a8bf 100644 --- a/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf +++ b/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf @@ -60,6 +60,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + PcdLib PciLib PrintLib TimerLib @@ -75,4 +76,4 @@ [Protocols] =20 [Pcd] gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion - + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId diff --git a/OvmfPkg/QemuVideoDxe/VbeShim.c b/OvmfPkg/QemuVideoDxe/VbeShim.c index bc90e067266d..e45a08e8873f 100644 --- a/OvmfPkg/QemuVideoDxe/VbeShim.c +++ b/OvmfPkg/QemuVideoDxe/VbeShim.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #include "Qemu.h" #include "VbeShim.h" @@ -64,6 +65,7 @@ InstallVbeShim ( UINTN Segment0Pages; IVT_ENTRY *Int0x10; EFI_STATUS Segment0AllocationStatus; + UINT16 HostBridgeDevId; UINTN Pam1Address; UINT8 Pam1; UINTN SegmentCPages; @@ -131,7 +133,30 @@ InstallVbeShim ( // // Put the shim in place first. // - Pam1Address =3D PCI_LIB_ADDRESS (0, 0, 0, 0x5A); + // Start by determining the address of the PAM1 register. + // + HostBridgeDevId =3D PcdGet16 (PcdOvmfHostBridgePciDevId); + switch (HostBridgeDevId) { + case INTEL_82441_DEVICE_ID: + Pam1Address =3D PMC_REGISTER_PIIX4 (PIIX4_PAM1); + break; + case INTEL_Q35_MCH_DEVICE_ID: + Pam1Address =3D DRAMC_REGISTER_Q35 (MCH_PAM1); + break; + default: + DEBUG (( + DEBUG_ERROR, + "%a: unknown host bridge device ID: 0x%04x\n", + __FUNCTION__, + HostBridgeDevId + )); + ASSERT (FALSE); + + if (!EFI_ERROR (Segment0AllocationStatus)) { + gBS->FreePages (Segment0, Segment0Pages); + } + return; + } // // low nibble covers 0xC0000 to 0xC3FFF // high nibble covers 0xC4000 to 0xC7FFF --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel