Changeset
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc                                                      |  528 +++++++
Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf                                                      |  361 +++++
Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl                                                        |  292 ++++
Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h                                                               |   58 +
Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf                                                             |   58 +
Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl                                                                   |  168 +++
Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc                                                                  |   88 ++
Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc                                                                  |   98 ++
Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc                                                                  |  164 +++
Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc                                                                  |  152 ++
Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc                                                                  |   63 +
Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc                                                                  |  127 ++
Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi                                                             |  517 +++++++
Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts                                                     |   21 +
Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf                                                     |   28 +
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec                                                       |   31 +
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf                                                       |   78 ++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h                                                         |  242 ++++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c                                                |  136 ++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c                                                       | 1313 ++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h                                                       |  305 ++++
Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c                                                    |  845 ++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c                                                     | 1000 ++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec                                                   |   47 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h                                                     |   88 ++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf                                                   |   69 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h                   |  736 ++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h            |   45 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h               |   24 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c              |   88 ++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h              |   52 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c          | 1391 +++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h |  111 ++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c               | 1454 ++++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h                  |  210 +++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c                      | 1385 +++++++++++++++++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h             |   38 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h                       |  219 +++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h            |  222 +++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h                |  368 +++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h                                   |   25 +
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h                                         |  265 ++++
Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c                                    |  176 +++
Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c                                 |  588 ++++++++
Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf                               |   50 +
Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h                                                          |   65 +
Silicon/Socionext/Synquacer/Include/Platform/Pcie.h                                                               |   63 +
Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c                                      |   60 +
Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf                                 |   38 +
Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S                                        |   93 ++
Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S                                            |   93 ++
Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c                                                      |  124 ++
Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf                                                 |   39 +
Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c                         |  150 ++
Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf                       |   52 +
Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c                         |  223 +++
Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf                       |   50 +
Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c              |  383 ++++++
Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c                                        | 1396 +++++++++++++++++++
Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf                             |   35 +
Silicon/Socionext/Synquacer/Synquacer.dec                                                                         |   22 +
61 files changed, 17210 insertions(+)
create mode 100644 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
create mode 100644 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
create mode 100644 Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi
create mode 100644 Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts
create mode 100644 Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
create mode 100644 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
create mode 100644 Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
create mode 100644 Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
create mode 100644 Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c
create mode 100644 Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
create mode 100644 Silicon/Socionext/Synquacer/Synquacer.dec
Git apply log
Switched to a new branch '20170908182315.9591-1-ard.biesheuvel@linaro.org'
Applying: Silicon/Synquacer: add package with platform headers
Applying: Silicon/Synquacer: add MemoryInitPeiLib implementation
Applying: Platform: add support for Socionext Synquacer eval board
Applying: Silicon/Synquacer: implement PciSegmentLib to support dual RCs
Applying: Silicon/Synquacer: implement PciHostBridgeLib support
Applying: Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL
Applying: Platform/SynquacerEvalBoard: add PCI support
Applying: Silicon/Socionext: add driver for NETSEC network controller
Applying: Platform/SynquacerEvalBoard: add NETSEC driver
Applying: Silicon/Synquacer: add ACPI support
Applying: Silicon/Synquacer: add device tree support for eval board
Applying: Silicon/Synquacer: add NorFlashPlatformLib implementation
Applying: Silicon/Socionext: add driver for SPI NOR flash
Applying: Platform/Synquacer: incorporate NOR flash and variable drivers
To https://github.com/patchew-project/edk2
 * [new tag]               patchew/20170908182315.9591-1-ard.biesheuvel@linaro.org -> patchew/20170908182315.9591-1-ard.biesheuvel@linaro.org
[edk2] [PATCH edk2-platforms 00/14] add support for Socionext Synquacer EVB
Posted by Ard Biesheuvel, 2 weeks ago
This adds support for the Socionext Synquacer SC2A11 evaluation board.

It implements support for the core peripherals (CPU, GIC, serial), and
for the two PCIe RCs present on this board. (Note that the board requires
PCI slot CN2 to be populated or it will not boot).

Both ACPI and DT hardware descriptions are provided. In ACPI mode, Debian
stretch can be booted and installed on PCIe based peripherals, and
requires a PCIe based network card that already has upstream support.

The DT description contains references to drivers that are not upstream
yet, and will be merged into Linux v4.15 at the earliest. No other OS
support is currently planned (as far as I am aware)

The non-volatile EFI variable store is backed by the SPI NOR flash,
which is therefore not exposed to the OS. Note that it occupies the
'devtree' partition, which must be wiped before use.

A driver for the NETSEC network interface is included, which means
network boot is supported as well. (Note that this driver deviates
in coding style. This code is based on the platform independent
driver provided by Socionext, and making cosmetic changes to it
will only make it more difficult to track upstream changes)

Note that this firmware requires a version of the CM3 firmware that is
compatible with the PCIe window configuration as can be found in the file
Silicon/Socionext/Synquacer/Include/Platform/Pcie.h (patch #1)

Ard Biesheuvel (14):
  Silicon/Synquacer: add package with platform headers
  Silicon/Synquacer: add MemoryInitPeiLib implementation
  Platform: add support for Socionext Synquacer eval board
  Silicon/Synquacer: implement PciSegmentLib to support dual RCs
  Silicon/Synquacer: implement PciHostBridgeLib support
  Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL
  Platform/SynquacerEvalBoard: add PCI support
  Silicon/Socionext: add driver for NETSEC network controller
  Platform/SynquacerEvalBoard: add NETSEC driver
  Silicon/Synquacer: add ACPI support
  Silicon/Synquacer: add device tree support for eval board
  Silicon/Synquacer: add NorFlashPlatformLib implementation
  Silicon/Socionext: add driver for SPI NOR flash
  Platform/Synquacer: incorporate NOR flash and variable drivers

 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc                                                      |  528 +++++++
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf                                                      |  361 +++++
 Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl                                                        |  292 ++++
 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h                                                               |   58 +
 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf                                                             |   58 +
 Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl                                                                   |  168 +++
 Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc                                                                  |   88 ++
 Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc                                                                  |   98 ++
 Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc                                                                  |  164 +++
 Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc                                                                  |  152 ++
 Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc                                                                  |   63 +
 Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc                                                                  |  127 ++
 Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi                                                             |  517 +++++++
 Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts                                                     |   21 +
 Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf                                                     |   28 +
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec                                                       |   31 +
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf                                                       |   78 ++
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h                                                         |  242 ++++
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c                                                |  136 ++
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c                                                       | 1313 ++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h                                                       |  305 ++++
 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c                                                    |  845 ++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c                                                     | 1000 ++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec                                                   |   47 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h                                                     |   88 ++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf                                                   |   69 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h                   |  736 ++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h            |   45 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h               |   24 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c              |   88 ++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h              |   52 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c          | 1391 +++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h |  111 ++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c               | 1454 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h                  |  210 +++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c                      | 1385 +++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h             |   38 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h                       |  219 +++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h            |  222 +++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h                |  368 +++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h                                   |   25 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h                                         |  265 ++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c                                    |  176 +++
 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c                                 |  588 ++++++++
 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf                               |   50 +
 Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h                                                          |   65 +
 Silicon/Socionext/Synquacer/Include/Platform/Pcie.h                                                               |   63 +
 Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c                                      |   60 +
 Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf                                 |   38 +
 Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S                                        |   93 ++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S                                            |   93 ++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c                                                      |  124 ++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf                                                 |   39 +
 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c                         |  150 ++
 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf                       |   52 +
 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c                         |  223 +++
 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf                       |   50 +
 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c              |  383 ++++++
 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c                                        | 1396 +++++++++++++++++++
 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf                             |   35 +
 Silicon/Socionext/Synquacer/Synquacer.dec                                                                         |   22 +
 61 files changed, 17210 insertions(+)
 create mode 100644 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
 create mode 100644 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc
 create mode 100644 Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc
 create mode 100644 Silicon/Socionext/Synquacer/DeviceTree/Synquacer.dtsi
 create mode 100644 Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.dts
 create mode 100644 Silicon/Socionext/Synquacer/DeviceTree/SynquacerEvalBoard.inf
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.dec
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Dxe.inf
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/Fip006Reg.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashDxe.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
 create mode 100644 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
 create mode 100644 Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
 create mode 100644 Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
 create mode 100644 Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacer.c
 create mode 100644 Silicon/Socionext/Synquacer/Library/NorFlashSynquacerLib/NorFlashSynquacerLib.inf
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
 create mode 100644 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
 create mode 100644 Silicon/Socionext/Synquacer/Synquacer.dec

-- 
2.11.0

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[edk2] [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers
Posted by Ard Biesheuvel, 2 weeks ago
Add a package .DEC description for Synquacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h | 65 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/Include/Platform/Pcie.h      | 63 +++++++++++++++++++
 Silicon/Socionext/Synquacer/Synquacer.dec                | 22 +++++++
 3 files changed, 150 insertions(+)

diff --git a/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
new file mode 100644
index 000000000000..1b5393c32f1d
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
@@ -0,0 +1,65 @@
+/** @file
+  PCI memory configuration for Synquacer
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
+#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
+
+// Memory mapped SPI NOR
+#define SYNQUACER_SPI_NOR_BASE          0x08000000
+#define SYNQUACER_SPI_NOR_SIZE          SIZE_128MB
+
+// On-Chip non-secure ROM
+#define SYNQUACER_NON_SECURE_ROM_BASE   0x1F000000
+#define SYNQUACER_NON_SECURE_ROM_SZ     SIZE_512KB
+
+// On-Chip Peripherals
+#define SYNQUACER_PERIPHERALS_BASE      0x20000000
+#define SYNQUACER_PERIPHERALS_SZ        0x0E000000
+
+// On-Chip non-secure SRAM
+#define SYNQUACER_NON_SECURE_SRAM_BASE  0x2E000000
+#define SYNQUACER_NON_SECURE_SRAM_SZ    SIZE_32KB
+
+// GIC-500
+#define SYNQUACER_GIC500_DIST_BASE      FixedPcdGet64 (PcdGicDistributorBase)
+#define SYNQUACER_GIC500_DIST_SIZE      SIZE_256KB
+#define SYNQUACER_GIC500_RDIST_BASE     FixedPcdGet64 (PcdGicRedistributorsBase)
+#define SYNQUACER_GIC500_RDIST_SIZE     SIZE_8MB
+
+// eMMC(SDH30)
+#define SYNQUACER_EMMC_BASE             0x52300000
+#define SYNQUACER_EMMC_BASE_SZ          SIZE_4KB
+
+#define SYNQUACER_EEPROM_BASE           0x10000000
+#define SYNQUACER_EEPROM_BASE_SZ        SIZE_64KB
+
+// NETSEC
+#define SYNQUACER_NETSEC_BASE           0x522D0000
+#define SYNQUACER_NETSEC_BASE_SZ        SIZE_64KB
+
+#define SYNQUACER_SYSTEM_MEMORY_1_BASE  0x80000000
+#define SYNQUACER_SYSTEM_MEMORY_1_SZ    (SIZE_2GB - SIZE_16MB)
+
+#define SYNQUACER_SYSTEM_MEMORY_2_BASE  0x0880000000ULL
+#define SYNQUACER_SYSTEM_MEMORY_2_SZ    (SIZE_32GB - SIZE_2GB)
+
+#define SYNQUACER_SYSTEM_MEMORY_3_BASE  0x8800000000ULL
+#define SYNQUACER_SYSTEM_MEMORY_3_SZ    SIZE_32GB
+
+// PCI
+#define SYNQUACER_PCIE_BASE             0x58200000
+#define SYNQUACER_PCIE_SIZE             0x00200000
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
new file mode 100644
index 000000000000..f7bdc13ad915
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
@@ -0,0 +1,63 @@
+/** @file
+  PCI memory configuration for Synquacer
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_PCI_H_
+#define _SYNQUACER_PLATFORM_PCI_H_
+
+#define SYNQUACER_PCI_SEG0_CONFIG_BASE      0x60000000
+#define SYNQUACER_PCI_SEG0_CONFIG_SIZE      0x07f00000
+#define SYNQUACER_PCI_SEG0_DBI_BASE         0x583d0000
+#define SYNQUACER_PCI_SEG0_EXS_BASE         0x58390000
+
+#define SYNQUACER_PCI_SEG0_BUSNUM_MIN       0x0
+#define SYNQUACER_PCI_SEG0_BUSNUM_MAX       0x7e
+
+#define SYNQUACER_PCI_SEG0_PORTIO_MIN       0x0
+#define SYNQUACER_PCI_SEG0_PORTIO_MAX       0xffff
+#define SYNQUACER_PCI_SEG0_PORTIO_SIZE      0x10000
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE   0x67f00000
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE   SYNQUACER_PCI_SEG0_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000
+#define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff
+#define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000
+
+#define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000
+#define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff
+#define SYNQUACER_PCI_SEG0_MMIO64_SIZE      0x100000000
+
+#define SYNQUACER_PCI_SEG1_CONFIG_BASE      0x70000000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE      0x07f00000
+#define SYNQUACER_PCI_SEG1_DBI_BASE         0x583c0000
+#define SYNQUACER_PCI_SEG1_EXS_BASE         0x58380000
+
+#define SYNQUACER_PCI_SEG1_BUSNUM_MIN       0x0
+#define SYNQUACER_PCI_SEG1_BUSNUM_MAX       0x7e
+
+#define SYNQUACER_PCI_SEG1_PORTIO_MIN       0x10000
+#define SYNQUACER_PCI_SEG1_PORTIO_MAX       0x1ffff
+#define SYNQUACER_PCI_SEG1_PORTIO_SIZE      0x10000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE   0x77f00000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE   SYNQUACER_PCI_SEG1_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000
+#define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff
+#define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000
+
+#define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000
+#define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff
+#define SYNQUACER_PCI_SEG1_MMIO64_SIZE      0x100000000
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Synquacer.dec b/Silicon/Socionext/Synquacer/Synquacer.dec
new file mode 100644
index 000000000000..955a056a8d59
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Synquacer.dec
@@ -0,0 +1,22 @@
+#
+#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = Synquacer
+  PACKAGE_GUID                   = 9c782fd2-7db1-438d-b51c-2155cee2c5cc
+  PACKAGE_VERSION                = 0.1
+
+[Includes]
+  Include
+
+
-- 
2.11.0

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Re: [edk2] [PATCH edk2-platforms 01/14] Silicon/Synquacer: add package with platform headers
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:02PM +0100, Ard Biesheuvel wrote:
> Add a package .DEC description for Synquacer with an [Includes]
> section, and add header files containing descriptions of the
> platform's memory map and PCIe configuration. No code yet.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h | 65 ++++++++++++++++++++
>  Silicon/Socionext/Synquacer/Include/Platform/Pcie.h      | 63 +++++++++++++++++++
>  Silicon/Socionext/Synquacer/Synquacer.dec                | 22 +++++++

I'll start with the bikeshedding (questions for consideration):
- SynQuacer is written that (<-) way in all public information I can
  find.
- Does SynQuacer refer to the SC2A11, or is SC2A11 the first member of
  a SynQuacer family of products?

>  3 files changed, 150 insertions(+)
> 
> diff --git a/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
> new file mode 100644
> index 000000000000..1b5393c32f1d
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Include/Platform/MemoryMap.h
> @@ -0,0 +1,65 @@
> +/** @file
> +  PCI memory configuration for Synquacer

Not just PCI?

> +
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> +  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
> +#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
> +
> +// Memory mapped SPI NOR
> +#define SYNQUACER_SPI_NOR_BASE          0x08000000
> +#define SYNQUACER_SPI_NOR_SIZE          SIZE_128MB
> +
> +// On-Chip non-secure ROM
> +#define SYNQUACER_NON_SECURE_ROM_BASE   0x1F000000
> +#define SYNQUACER_NON_SECURE_ROM_SZ     SIZE_512KB
> +
> +// On-Chip Peripherals
> +#define SYNQUACER_PERIPHERALS_BASE      0x20000000
> +#define SYNQUACER_PERIPHERALS_SZ        0x0E000000
> +
> +// On-Chip non-secure SRAM
> +#define SYNQUACER_NON_SECURE_SRAM_BASE  0x2E000000
> +#define SYNQUACER_NON_SECURE_SRAM_SZ    SIZE_32KB
> +
> +// GIC-500
> +#define SYNQUACER_GIC500_DIST_BASE      FixedPcdGet64 (PcdGicDistributorBase)
> +#define SYNQUACER_GIC500_DIST_SIZE      SIZE_256KB
> +#define SYNQUACER_GIC500_RDIST_BASE     FixedPcdGet64 (PcdGicRedistributorsBase)
> +#define SYNQUACER_GIC500_RDIST_SIZE     SIZE_8MB
> +
> +// eMMC(SDH30)
> +#define SYNQUACER_EMMC_BASE             0x52300000
> +#define SYNQUACER_EMMC_BASE_SZ          SIZE_4KB
> +
> +#define SYNQUACER_EEPROM_BASE           0x10000000
> +#define SYNQUACER_EEPROM_BASE_SZ        SIZE_64KB
> +
> +// NETSEC
> +#define SYNQUACER_NETSEC_BASE           0x522D0000
> +#define SYNQUACER_NETSEC_BASE_SZ        SIZE_64KB
> +
> +#define SYNQUACER_SYSTEM_MEMORY_1_BASE  0x80000000
> +#define SYNQUACER_SYSTEM_MEMORY_1_SZ    (SIZE_2GB - SIZE_16MB)
> +
> +#define SYNQUACER_SYSTEM_MEMORY_2_BASE  0x0880000000ULL
> +#define SYNQUACER_SYSTEM_MEMORY_2_SZ    (SIZE_32GB - SIZE_2GB)
> +
> +#define SYNQUACER_SYSTEM_MEMORY_3_BASE  0x8800000000ULL
> +#define SYNQUACER_SYSTEM_MEMORY_3_SZ    SIZE_32GB
> +
> +// PCI
> +#define SYNQUACER_PCIE_BASE             0x58200000
> +#define SYNQUACER_PCIE_SIZE             0x00200000
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
> new file mode 100644
> index 000000000000..f7bdc13ad915
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Include/Platform/Pcie.h
> @@ -0,0 +1,63 @@
> +/** @file
> +  PCI memory configuration for Synquacer

Not just memory configuration.

> +
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> +  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef _SYNQUACER_PLATFORM_PCI_H_
> +#define _SYNQUACER_PLATFORM_PCI_H_
> +
> +#define SYNQUACER_PCI_SEG0_CONFIG_BASE      0x60000000
> +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE      0x07f00000
> +#define SYNQUACER_PCI_SEG0_DBI_BASE         0x583d0000
> +#define SYNQUACER_PCI_SEG0_EXS_BASE         0x58390000
> +
> +#define SYNQUACER_PCI_SEG0_BUSNUM_MIN       0x0
> +#define SYNQUACER_PCI_SEG0_BUSNUM_MAX       0x7e
> +
> +#define SYNQUACER_PCI_SEG0_PORTIO_MIN       0x0
> +#define SYNQUACER_PCI_SEG0_PORTIO_MAX       0xffff
> +#define SYNQUACER_PCI_SEG0_PORTIO_SIZE      0x10000
> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE   0x67f00000
> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE   SYNQUACER_PCI_SEG0_PORTIO_SIZE
> +
> +#define SYNQUACER_PCI_SEG0_MMIO32_MIN       0x68000000
> +#define SYNQUACER_PCI_SEG0_MMIO32_MAX       0x6fffffff
> +#define SYNQUACER_PCI_SEG0_MMIO32_SIZE      0x08000000
> +
> +#define SYNQUACER_PCI_SEG0_MMIO64_MIN       0x3e00000000
> +#define SYNQUACER_PCI_SEG0_MMIO64_MAX       0x3effffffff
> +#define SYNQUACER_PCI_SEG0_MMIO64_SIZE      0x100000000
> +
> +#define SYNQUACER_PCI_SEG1_CONFIG_BASE      0x70000000
> +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE      0x07f00000
> +#define SYNQUACER_PCI_SEG1_DBI_BASE         0x583c0000
> +#define SYNQUACER_PCI_SEG1_EXS_BASE         0x58380000
> +
> +#define SYNQUACER_PCI_SEG1_BUSNUM_MIN       0x0
> +#define SYNQUACER_PCI_SEG1_BUSNUM_MAX       0x7e
> +
> +#define SYNQUACER_PCI_SEG1_PORTIO_MIN       0x10000
> +#define SYNQUACER_PCI_SEG1_PORTIO_MAX       0x1ffff
> +#define SYNQUACER_PCI_SEG1_PORTIO_SIZE      0x10000
> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE   0x77f00000
> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE   SYNQUACER_PCI_SEG1_PORTIO_SIZE
> +
> +#define SYNQUACER_PCI_SEG1_MMIO32_MIN       0x78000000
> +#define SYNQUACER_PCI_SEG1_MMIO32_MAX       0x7fffffff
> +#define SYNQUACER_PCI_SEG1_MMIO32_SIZE      0x08000000
> +
> +#define SYNQUACER_PCI_SEG1_MMIO64_MIN       0x3f00000000
> +#define SYNQUACER_PCI_SEG1_MMIO64_MAX       0x3fffffffff
> +#define SYNQUACER_PCI_SEG1_MMIO64_SIZE      0x100000000
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Synquacer.dec b/Silicon/Socionext/Synquacer/Synquacer.dec
> new file mode 100644
> index 000000000000..955a056a8d59
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Synquacer.dec
> @@ -0,0 +1,22 @@
> +#
> +#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> +  DEC_SPECIFICATION              = 0x00010005

I think we're at 0x0001001a (1.26) now?

> +  PACKAGE_NAME                   = Synquacer
> +  PACKAGE_GUID                   = 9c782fd2-7db1-438d-b51c-2155cee2c5cc
> +  PACKAGE_VERSION                = 0.1
> +
> +[Includes]
> +  Include
> +
> +

Drop trailing blanks?

/
    Leif

> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation
Posted by Ard Biesheuvel, 2 weeks ago
Replace the common MemoryInitPeiLib implementation with one that does
not remove the primary FV from the memory map. This is a waste of
memory and TLB entries, given that the OS can no longer use a 1 GB
block mapping to map this memory.

Since we have our own implementation now, there is no point in using
ArmPlatformLib's GetVirtualMemoryMap() implementation, and we can
simply declare and map the regions directly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c   | 140 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf |  50 +++++++
 2 files changed, 190 insertions(+)

diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
new file mode 100644
index 000000000000..1d25d63f1b6c
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
@@ -0,0 +1,140 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmLib.h>
+#include <Library/ArmMmuLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+
+#include <Platform/MemoryMap.h>
+#include <Platform/Pcie.h>
+
+#define ARM_MEMORY_REGION(Base, Size) \
+  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK }
+
+#define ARM_DEVICE_REGION(Base, Size) \
+  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
+
+VOID
+BuildMemoryTypeInformationHob (
+  VOID
+  );
+
+STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
+  // DDR - 2 GB
+  ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_1_BASE,
+                     SYNQUACER_SYSTEM_MEMORY_1_SZ),
+
+  // DDR - 30 GB
+  ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_2_BASE,
+                     SYNQUACER_SYSTEM_MEMORY_2_SZ),
+
+  // DDR - 32 GB
+//  ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_3_BASE,
+//                     SYNQUACER_SYSTEM_MEMORY_3_SZ),
+
+  // Synquacer OnChip non-secure ROM
+  ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_ROM_BASE,
+                     SYNQUACER_NON_SECURE_ROM_SZ),
+
+  // Synquacer OnChip peripherals
+  ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
+                     SYNQUACER_PERIPHERALS_SZ),
+
+  // Synquacer OnChip non-secure SRAM
+  ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_SRAM_BASE,
+                     SYNQUACER_NON_SECURE_SRAM_SZ),
+
+  // Synquacer GIC-500
+  ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE),
+  ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE),
+
+  // Synquacer eMMC(SDH30)
+  ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ),
+
+  // Synquacer EEPROM
+  ARM_DEVICE_REGION (SYNQUACER_EEPROM_BASE, SYNQUACER_EEPROM_BASE_SZ),
+
+  // Synquacer NETSEC
+  ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ),
+
+  // PCIe control registers
+  ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE),
+
+  // PCIe config space
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE,
+                     SYNQUACER_PCI_SEG0_CONFIG_SIZE),
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE,
+                     SYNQUACER_PCI_SEG1_CONFIG_SIZE),
+
+  // PCIe I/O space
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,
+                     SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE),
+  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
+                     SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
+
+  { }
+};
+
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+  IN EFI_PHYSICAL_ADDRESS       UefiMemoryBase,
+  IN UINT64                     UefiMemorySize
+  )
+{
+  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
+  RETURN_STATUS                 Status;
+
+  ResourceAttributes =
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+      EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    ResourceAttributes,
+    SYNQUACER_SYSTEM_MEMORY_1_BASE,
+    SYNQUACER_SYSTEM_MEMORY_1_SZ);
+
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_SYSTEM_MEMORY,
+    ResourceAttributes,
+    SYNQUACER_SYSTEM_MEMORY_2_BASE,
+    SYNQUACER_SYSTEM_MEMORY_2_SZ);
+
+//  BuildResourceDescriptorHob (
+//    EFI_RESOURCE_SYSTEM_MEMORY,
+//    ResourceAttributes,
+//    SYNQUACER_SYSTEM_MEMORY_3_BASE,
+//    SYNQUACER_SYSTEM_MEMORY_3_SZ);
+
+  Status = ArmConfigureMmu (mVirtualMemoryTable, NULL, NULL);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+    // Optional feature that helps prevent EFI memory map fragmentation.
+    BuildMemoryTypeInformationHob ();
+  }
+  return EFI_SUCCESS;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
new file mode 100644
index 000000000000..5f45c30a5e92
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+#  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SynquacerMemoryInitPeiLib
+  FILE_GUID                      = c69d3ce7-098c-4fcd-afb4-15fb05a39308
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = MemoryInitPeiLib|SEC PEIM
+
+[Sources]
+  SynquacerMemoryInitPeiLib.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmMmuLib
+  DebugLib
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-- 
2.11.0

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Re: [edk2] [PATCH edk2-platforms 02/14] Silicon/Synquacer: add MemoryInitPeiLib implementation
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:03PM +0100, Ard Biesheuvel wrote:
> Replace the common MemoryInitPeiLib implementation with one that does
> not remove the primary FV from the memory map. This is a waste of
> memory and TLB entries, given that the OS can no longer use a 1 GB
> block mapping to map this memory.
> 
> Since we have our own implementation now, there is no point in using
> ArmPlatformLib's GetVirtualMemoryMap() implementation, and we can
> simply declare and map the regions directly.

Is there any reason we could not extend this to a better core
implementation, kept in ArmPkg?
(No, that does not need to happen now.)

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c   | 140 ++++++++++++++++++++
>  Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf |  50 +++++++
>  2 files changed, 190 insertions(+)
> 
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> new file mode 100644
> index 000000000000..1d25d63f1b6c
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.c
> @@ -0,0 +1,140 @@
> +/** @file
> +*
> +*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +*  Copyright (c) 2017, Linaro, Ltd. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmMmuLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +
> +#include <Platform/MemoryMap.h>
> +#include <Platform/Pcie.h>
> +
> +#define ARM_MEMORY_REGION(Base, Size) \
> +  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK }
> +
> +#define ARM_DEVICE_REGION(Base, Size) \
> +  { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> +  VOID
> +  );
> +
> +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
> +  // DDR - 2 GB
> +  ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_1_BASE,
> +                     SYNQUACER_SYSTEM_MEMORY_1_SZ),
> +
> +  // DDR - 30 GB
> +  ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_2_BASE,
> +                     SYNQUACER_SYSTEM_MEMORY_2_SZ),
> +
> +  // DDR - 32 GB
> +//  ARM_MEMORY_REGION (SYNQUACER_SYSTEM_MEMORY_3_BASE,
> +//                     SYNQUACER_SYSTEM_MEMORY_3_SZ),

Could these be kept behind a #define (or FixedPcd) until no longer
needed?

> +
> +  // Synquacer OnChip non-secure ROM
> +  ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_ROM_BASE,
> +                     SYNQUACER_NON_SECURE_ROM_SZ),
> +
> +  // Synquacer OnChip peripherals
> +  ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
> +                     SYNQUACER_PERIPHERALS_SZ),
> +
> +  // Synquacer OnChip non-secure SRAM
> +  ARM_MEMORY_REGION (SYNQUACER_NON_SECURE_SRAM_BASE,
> +                     SYNQUACER_NON_SECURE_SRAM_SZ),
> +
> +  // Synquacer GIC-500
> +  ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE),
> +  ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE),
> +
> +  // Synquacer eMMC(SDH30)
> +  ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ),
> +
> +  // Synquacer EEPROM
> +  ARM_DEVICE_REGION (SYNQUACER_EEPROM_BASE, SYNQUACER_EEPROM_BASE_SZ),
> +
> +  // Synquacer NETSEC
> +  ARM_DEVICE_REGION (SYNQUACER_NETSEC_BASE, SYNQUACER_NETSEC_BASE_SZ),
> +
> +  // PCIe control registers
> +  ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE),
> +
> +  // PCIe config space
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE,
> +                     SYNQUACER_PCI_SEG0_CONFIG_SIZE),
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE,
> +                     SYNQUACER_PCI_SEG1_CONFIG_SIZE),
> +
> +  // PCIe I/O space
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,
> +                     SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE),
> +  ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,
> +                     SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE),
> +
> +  { }
> +};
> +
> +EFI_STATUS
> +EFIAPI
> +MemoryPeim (
> +  IN EFI_PHYSICAL_ADDRESS       UefiMemoryBase,
> +  IN UINT64                     UefiMemorySize
> +  )
> +{
> +  EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
> +  RETURN_STATUS                 Status;
> +
> +  ResourceAttributes =
> +      EFI_RESOURCE_ATTRIBUTE_PRESENT |
> +      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> +      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> +      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> +      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> +      EFI_RESOURCE_ATTRIBUTE_TESTED;
> +
> +  BuildResourceDescriptorHob (
> +    EFI_RESOURCE_SYSTEM_MEMORY,
> +    ResourceAttributes,
> +    SYNQUACER_SYSTEM_MEMORY_1_BASE,
> +    SYNQUACER_SYSTEM_MEMORY_1_SZ);
> +
> +  BuildResourceDescriptorHob (
> +    EFI_RESOURCE_SYSTEM_MEMORY,
> +    ResourceAttributes,
> +    SYNQUACER_SYSTEM_MEMORY_2_BASE,
> +    SYNQUACER_SYSTEM_MEMORY_2_SZ);
> +
> +//  BuildResourceDescriptorHob (
> +//    EFI_RESOURCE_SYSTEM_MEMORY,
> +//    ResourceAttributes,
> +//    SYNQUACER_SYSTEM_MEMORY_3_BASE,
> +//    SYNQUACER_SYSTEM_MEMORY_3_SZ);

Same #define / FixedPcd?

/
    Leif

> +
> +  Status = ArmConfigureMmu (mVirtualMemoryTable, NULL, NULL);
> +  ASSERT_EFI_ERROR (Status);
> +  if (EFI_ERROR (Status)) {
> +    return Status;
> +  }
> +
> +  if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
> +    // Optional feature that helps prevent EFI memory map fragmentation.
> +    BuildMemoryTypeInformationHob ();
> +  }
> +  return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> new file mode 100644
> index 000000000000..5f45c30a5e92
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> @@ -0,0 +1,50 @@
> +#/** @file
> +#
> +#  Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
> +#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010019
> +  BASE_NAME                      = SynquacerMemoryInitPeiLib
> +  FILE_GUID                      = c69d3ce7-098c-4fcd-afb4-15fb05a39308
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = MemoryInitPeiLib|SEC PEIM
> +
> +[Sources]
> +  SynquacerMemoryInitPeiLib.c
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  ArmMmuLib
> +  DebugLib
> +
> +[FeaturePcd]
> +  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdGicDistributorBase
> +  gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board
Posted by Ard Biesheuvel, 2 weeks ago
This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
code provided by Socionext. It can boot into the UiApp menu screen
or the UEFI Shell, but lacks support for any peripherals.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc               | 394 ++++++++++++++++++++
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf               | 276 ++++++++++++++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S |  93 +++++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S     |  93 +++++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c               | 124 ++++++
 Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf          |  39 ++
 6 files changed, 1019 insertions(+)

diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
new file mode 100644
index 000000000000..2a9a0037dcda
--- /dev/null
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -0,0 +1,394 @@
+#
+#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = SynquacerEvalBoard
+  PLATFORM_GUID                  = a8180daa-fb8b-11e5-ab24-9fc3167c073d
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64|ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+
+[BuildOptions]
+  RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
+
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+[LibraryClasses.common]
+  ArmPlatformLib|Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
+  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+
+  # Networking Requirements
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+  # ARM Architectural Libraries
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  # BDS Libraries
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+
+  #
+  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+  # This library provides the instrinsic functions generate by a given compiler.
+  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+  #
+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+  # Add support for GCC stack protector
+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.SEC]
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+  MemoryInitPeiLib|Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
+  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+  # UiApp dependencies
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+  ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag]
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+[PcdsFixedAtBuild.common]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro"
+
+  # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
+  # Ashbrook 12-Cluster profile
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|2
+  gArmPlatformTokenSpaceGuid.PcdClusterCount|12
+  gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+  ## PL011 - Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+  gArmPlatformTokenSpaceGuid.PL011UartInteger|0
+  gArmPlatformTokenSpaceGuid.PL011UartFractional|0
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|62500000
+
+  #
+  # ARM Generic Interrupt Controller
+  #
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30400000
+
+  #
+  # Generic watchdog
+  #
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
+
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+  # DEBUG_ASSERT_ENABLED       0x01
+  # DEBUG_PRINT_ENABLED        0x02
+  # DEBUG_CODE_ENABLED         0x04
+  # CLEAR_MEMORY_ENABLED       0x08
+  # ASSERT_BREAKPOINT_ENABLED  0x10
+  # ASSERT_DEADLOOP_ENABLED    0x20
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x3f
+!endif
+
+  #  DEBUG_INIT      0x00000001  // Initialization
+  #  DEBUG_WARN      0x00000002  // Warnings
+  #  DEBUG_LOAD      0x00000004  // Load events
+  #  DEBUG_FS        0x00000008  // EFI File system
+  #  DEBUG_POOL      0x00000010  // Alloc & Free (pool)
+  #  DEBUG_PAGE      0x00000020  // Alloc & Free (page)
+  #  DEBUG_INFO      0x00000040  // Informational debug messages
+  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE/SMM Dispatchers
+  #  DEBUG_VARIABLE  0x00000100  // Variable
+  #  DEBUG_BM        0x00000400  // Boot Manager
+  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
+  #  DEBUG_NET       0x00004000  // SNP Driver
+  #  DEBUG_UNDI      0x00010000  // UNDI Driver
+  #  DEBUG_LOADFILE  0x00020000  // LoadFile
+  #  DEBUG_EVENT     0x00080000  // Event messages
+  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
+  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
+  #  DEBUG_VERBOSE   0x00400000  // Detailed debug messages that may
+  #                              // significantly impact boot performance
+  #  DEBUG_ERROR     0x80000000  // Error
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+
+  #
+  # Optional feature to help prevent EFI memory map fragments
+  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+  # Values are in EFI Pages (4K). DXE Core will make sure that
+  # at least this much of each type of memory can be allocated
+  # from a single memory range. This way you only end up with
+  # maximum of two fragements for each type in the memory map
+  # (the memory used, and the free memory that was prereserved
+  # but not used).
+  #
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|2000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+  # use the TTY terminal type
+  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+  # GUID of the UI app
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  #
+  # Enable strict image permissions for all images. (This applies
+  # only to images that were built with >= 4 KB section alignment.)
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
+
+  #
+  # Enable NX memory protection for all non-code regions, including OEM and OS
+  # reserved ones, with the exception of LoaderData regions, of which OS loaders
+  # (i.e., GRUB) may assume that its contents are executable.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
+
+  #
+  # Enable the non-executable DXE stack. (This gets set up by DxeIpl)
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
+
+[PcdsDynamicHii]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+  #
+  # PEI Phase modules
+  #
+  ArmPlatformPkg/PrePi/PeiUniCore.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+    <LibraryClasses>
+      ## TODO
+      RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
+  }
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+  }
+
+  #
+  # Generic BDS
+  #
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
new file mode 100644
index 000000000000..6c00e16b169e
--- /dev/null
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -0,0 +1,276 @@
+#
+#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2017, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.BL33_AP_UEFI]
+BaseAddress   = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00001000
+NumBlocks     = 0xF0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x000F0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid         = 89cc2ab6-b847-475f-93e2-819603c3d15a
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 8         # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+  #
+  # UEFI applications
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Generic BDS
+  #
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 8
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+#  FILE DRIVER = $(NAMED_GUID) {
+#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+#    COMPRESS PI_STD {
+#      GUIDED {
+#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+#        UI       STRING="$(MODULE_NAME)" Optional
+#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+#      }
+#    }
+#  }
+#
+############################################################################
+
+#
+# These SEC rules are used for ArmPlatformPkg/PrePi module.
+# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
+# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
+#
+[Rule.ARM.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.AARCH64.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+# A shim specific rule is required to ensure the alignment is 4K.
+# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
+[Rule.ARM.SEC.SHIM]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID) {
+    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI     STRING ="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
+      UI        STRING="$(MODULE_NAME)" Optional
+    }
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI           STRING="$(MODULE_NAME)" Optional
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    UI     STRING ="$(MODULE_NAME)" Optional
+    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
new file mode 100644
index 000000000000..7edae77067d0
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
@@ -0,0 +1,93 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+
+PrimaryCoreMpid:
+  .word    0x0
+
+//
+// First platform specific function to be called in the PEI phase
+//
+// This function is actually the first function called by the PrePi
+// or PrePeiCore modules. It allows to retrieve arguments passed to
+// the UEFI firmware through the CPU registers.
+//
+ASM_PFX(ArmPlatformPeiBootAction):
+  // The trusted firmware passes the primary CPU MPID through x0 register.
+  // Save it in a variable.
+  adr  x1, PrimaryCoreMpid
+  str  w0, [x1]
+  ret
+
+//
+// Return the core position from the value of its MpId register
+//
+// This function returns the core position from the position 0 in the processor.
+// This function might be called from assembler before any stack is set.
+//
+// @return   Return the core position
+//
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+  and   x1, x0, #ARM_CORE_MASK
+  and   x0, x0, #ARM_CLUSTER_MASK
+  add   x0, x1, x0, LSR #7
+  ret
+
+//
+// Return the MpId of the primary core
+//
+// This function returns the MpId of the primary core.
+// This function might be called from assembler before any stack is set.
+//
+// @return   Return the MpId of the primary core
+//
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+  ldr   w0, PrimaryCoreMpid
+  ret
+
+//
+// Return a non-zero value if the callee is the primary core
+//
+// This function returns a non-zero value if the callee is the primary core.
+// The primary core is the core responsible to initialize the hardware and run UEFI.
+// This function might be called from assembler before any stack is set.
+//
+//  @return   Return a non-zero value if the callee is the primary core.
+//
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+  mov   w0, #1
+  ret
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
new file mode 100644
index 000000000000..b37b461b77a5
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
@@ -0,0 +1,93 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+
+PrimaryCoreMpid:
+  .word    0x0
+
+//
+// First platform specific function to be called in the PEI phase
+//
+// This function is actually the first function called by the PrePi
+// or PrePeiCore modules. It allows to retrieve arguments passed to
+// the UEFI firmware through the CPU registers.
+//
+ASM_PFX(ArmPlatformPeiBootAction):
+  // The trusted firmware passes the primary CPU MPID through r0 register.
+  // Save it in a variable.
+  adr  r1, PrimaryCoreMpid
+  str  r0, [r1]
+  bx   lr
+
+//
+// Return the core position from the value of its MpId register
+//
+// This function returns the core position from the position 0 in the processor.
+// This function might be called from assembler before any stack is set.
+//
+// @return   Return the core position
+//
+//UINTN
+//ArmPlatformGetCorePosition (
+//  IN UINTN MpId
+//  );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+  and   r1, r0, #ARM_CORE_MASK
+  and   r0, r0, #ARM_CLUSTER_MASK
+  add   r0, r1, r0, LSR #7
+  bx    lr
+
+//
+// Return the MpId of the primary core
+//
+// This function returns the MpId of the primary core.
+// This function might be called from assembler before any stack is set.
+//
+// @return   Return the MpId of the primary core
+//
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+//  VOID
+//  );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+  ldr   r0, PrimaryCoreMpid
+  bx    lr
+
+//
+// Return a non-zero value if the callee is the primary core
+//
+// This function returns a non-zero value if the callee is the primary core.
+// The primary core is the core responsible to initialize the hardware and run UEFI.
+// This function might be called from assembler before any stack is set.
+//
+//  @return   Return a non-zero value if the callee is the primary core.
+//
+//UINTN
+//ArmPlatformIsPrimaryCore (
+//  IN UINTN MpId
+//  );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+  mov   r0, #1
+  bx    lr
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
new file mode 100644
index 000000000000..014db60add8e
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
@@ -0,0 +1,124 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+STATIC ARM_CORE_INFO mSynquacerInfoTable[] = {
+  { 0x0, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 0
+  { 0x0, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 1
+  { 0x1, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 0
+  { 0x1, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 1
+  { 0x2, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 0
+  { 0x2, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 1
+  { 0x3, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 0
+  { 0x3, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 1
+  { 0x4, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 0
+  { 0x4, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 1
+  { 0x5, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 0
+  { 0x5, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 1
+  { 0x6, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 0
+  { 0x6, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 1
+  { 0x7, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 0
+  { 0x7, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 1
+  { 0x8, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 0
+  { 0x8, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 1
+  { 0x9, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 0
+  { 0x9, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 1
+  { 0xa, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 0
+  { 0xa, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 1
+  { 0xb, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 0
+  { 0xb, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 1
+};
+
+/**
+  Return the current Boot Mode
+
+  This function returns the boot reason on the platform
+
+  @return   Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+  Initialize controllers that must setup in the normal world
+
+  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+  in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+  IN  UINTN                     MpId
+  )
+{
+  return RETURN_SUCCESS;
+}
+
+/**
+  Initialize the system (or sometimes called permanent) memory
+
+  This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+  VOID
+  )
+{
+}
+
+STATIC
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+  OUT UINTN                   *CoreCount,
+  OUT ARM_CORE_INFO           **ArmCoreTable
+  )
+{
+  *CoreCount    = ARRAY_SIZE (mSynquacerInfoTable);
+  *ArmCoreTable = mSynquacerInfoTable;
+
+  return EFI_SUCCESS;
+}
+
+STATIC ARM_MP_CORE_INFO_PPI       mMpCoreInfoPpi = {
+  PrePeiCoreGetMpCoreInfo
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR     mPlatformPpiTable[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gArmMpCoreInfoPpiGuid,
+    &mMpCoreInfoPpi
+  }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+  OUT UINTN                   *PpiListSize,
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
+  )
+{
+  *PpiListSize = sizeof mPlatformPpiTable;
+  *PpiList = mPlatformPpiTable;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
new file mode 100644
index 000000000000..63c3c8d35e21
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
@@ -0,0 +1,39 @@
+#
+#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SynquacerLib
+  FILE_GUID                      = 8301a0ab-dd8d-476d-8170-1e34b51490d3
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = ArmPlatformLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+
+[Sources.common]
+  Synquacer.c
+
+[Sources.AARCH64]
+  AArch64/SynquacerHelper.S | GCC
+
+[Sources.ARM]
+  Arm/SynquacerHelper.S     | GCC
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
-- 
2.11.0

_______________________________________________
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Re: [edk2] [PATCH edk2-platforms 03/14] Platform: add support for Socionext Synquacer eval board
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:04PM +0100, Ard Biesheuvel wrote:
> This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
> code provided by Socionext. It can boot into the UiApp menu screen
> or the UEFI Shell, but lacks support for any peripherals.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc               | 394 ++++++++++++++++++++
>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf               | 276 ++++++++++++++
>  Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S |  93 +++++
>  Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S     |  93 +++++

Oh - is the platform usable in AArch32 as well? Neat.

>  Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c               | 124 ++++++
>  Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf          |  39 ++
>  6 files changed, 1019 insertions(+)
> 
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> new file mode 100644
> index 000000000000..2a9a0037dcda
> --- /dev/null
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -0,0 +1,394 @@
> +#
> +#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +#  Copyright (c) 2017, Linaro Limited. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> +  PLATFORM_NAME                  = SynquacerEvalBoard
> +  PLATFORM_GUID                  = a8180daa-fb8b-11e5-ab24-9fc3167c073d
> +  PLATFORM_VERSION               = 0.1
> +  DSC_SPECIFICATION              = 0x00010005

Bump the version a bit.

> +  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
> +  SUPPORTED_ARCHITECTURES        = AARCH64|ARM
> +  BUILD_TARGETS                  = DEBUG|RELEASE
> +  SKUID_IDENTIFIER               = DEFAULT
> +  FLASH_DEFINITION               = Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +
> +[BuildOptions]
> +  RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
> +
> +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
> +  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> +  GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
> +  GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +[LibraryClasses.common]
> +  ArmPlatformLib|Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
> +  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
> +  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> +
> +  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> +  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> +
> +!if $(TARGET) == RELEASE
> +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!else
> +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> +!endif
> +  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> +
> +  BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
> +
> +  # Networking Requirements
> +  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> +  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> +  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> +  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> +
> +  # ARM Architectural Libraries
> +  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> +  DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> +  CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> +  ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> +  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> +  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> +  ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> +  ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> +  ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> +  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> +  ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> +
> +  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> +  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> +  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> +  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> +  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> +  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> +  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> +  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> +  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> +  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> +  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> +  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> +  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> +  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> +  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> +  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> +  ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
> +  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> +  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> +  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> +  # BDS Libraries
> +  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> +  PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> +  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +
> +  PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
> +  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> +  DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
> +  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> +  PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
> +
> +  #
> +  # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> +  # This library provides the instrinsic functions generate by a given compiler.
> +  # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.

This is actually under [.common], though.

> +  #
> +  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> +  # Add support for GCC stack protector
> +  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> +
> +[LibraryClasses.common.SEC]
> +  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +  PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> +  ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> +  LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> +  MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> +  HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> +  PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> +  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> +  PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> +  MemoryInitPeiLib|Silicon/Socionext/Synquacer/Library/SynquacerMemoryInitPeiLib/SynquacerMemoryInitPeiLib.inf
> +  ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> +  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> +  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> +  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> +  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> +  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> +  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> +  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> +  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> +  # UiApp dependencies
> +  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> +  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> +  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +  ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> +  ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> +  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> +  HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> +  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> +  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +  ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag]
> +  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> +
> +[PcdsFixedAtBuild.common]
> +  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro"
> +
> +  # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
> +  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> +  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
> +  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> +
> +  # Ashbrook 12-Cluster profile

I know what that means, but may make more sense to others as
     # 12x 2-core processor clusters.

> +  gArmPlatformTokenSpaceGuid.PcdCoreCount|2
> +  gArmPlatformTokenSpaceGuid.PcdClusterCount|12
> +  gArmTokenSpaceGuid.PcdVFPEnabled|1

For internal use only on ARM?

> +
> +  ## PL011 - Serial Terminal
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2a400000
> +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> +  gArmPlatformTokenSpaceGuid.PL011UartInteger|0
> +  gArmPlatformTokenSpaceGuid.PL011UartFractional|0
> +  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|62500000
> +
> +  #
> +  # ARM Generic Interrupt Controller
> +  #
> +  gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
> +  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30400000
> +
> +  #
> +  # Generic watchdog
> +  #
> +  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
> +  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
> +
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> +  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> +  gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> +  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> +
> +  # DEBUG_ASSERT_ENABLED       0x01
> +  # DEBUG_PRINT_ENABLED        0x02
> +  # DEBUG_CODE_ENABLED         0x04
> +  # CLEAR_MEMORY_ENABLED       0x08
> +  # ASSERT_BREAKPOINT_ENABLED  0x10
> +  # ASSERT_DEADLOOP_ENABLED    0x20
> +!if $(TARGET) == RELEASE
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
> +!else
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x3f
> +!endif
> +
> +  #  DEBUG_INIT      0x00000001  // Initialization
> +  #  DEBUG_WARN      0x00000002  // Warnings
> +  #  DEBUG_LOAD      0x00000004  // Load events
> +  #  DEBUG_FS        0x00000008  // EFI File system
> +  #  DEBUG_POOL      0x00000010  // Alloc & Free (pool)
> +  #  DEBUG_PAGE      0x00000020  // Alloc & Free (page)
> +  #  DEBUG_INFO      0x00000040  // Informational debug messages
> +  #  DEBUG_DISPATCH  0x00000080  // PEI/DXE/SMM Dispatchers
> +  #  DEBUG_VARIABLE  0x00000100  // Variable
> +  #  DEBUG_BM        0x00000400  // Boot Manager
> +  #  DEBUG_BLKIO     0x00001000  // BlkIo Driver
> +  #  DEBUG_NET       0x00004000  // SNP Driver
> +  #  DEBUG_UNDI      0x00010000  // UNDI Driver
> +  #  DEBUG_LOADFILE  0x00020000  // LoadFile
> +  #  DEBUG_EVENT     0x00080000  // Event messages
> +  #  DEBUG_GCD       0x00100000  // Global Coherency Database changes
> +  #  DEBUG_CACHE     0x00200000  // Memory range cachability changes
> +  #  DEBUG_VERBOSE   0x00400000  // Detailed debug messages that may
> +  #                              // significantly impact boot performance
> +  #  DEBUG_ERROR     0x80000000  // Error
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
> +
> +  #
> +  # Optional feature to help prevent EFI memory map fragments
> +  # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> +  # Values are in EFI Pages (4K). DXE Core will make sure that
> +  # at least this much of each type of memory can be allocated
> +  # from a single memory range. This way you only end up with
> +  # maximum of two fragements for each type in the memory map
> +  # (the memory used, and the free memory that was prereserved
> +  # but not used).
> +  #
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|2000
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
> +  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0

Are these actually used by your reimplemented MemoryInitPeiLib?

> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> +
> +  # use the TTY terminal type
> +  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
> +  # GUID of the UI app
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> +
> +  #
> +  # Enable strict image permissions for all images. (This applies
> +  # only to images that were built with >= 4 KB section alignment.)
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
> +
> +  #
> +  # Enable NX memory protection for all non-code regions, including OEM and OS
> +  # reserved ones, with the exception of LoaderData regions, of which OS loaders
> +  # (i.e., GRUB) may assume that its contents are executable.
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1
> +
> +  #
> +  # Enable the non-executable DXE stack. (This gets set up by DxeIpl)
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
> +
> +[PcdsDynamicHii]
> +  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> +  #
> +  # PEI Phase modules
> +  #
> +  ArmPlatformPkg/PrePi/PeiUniCore.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  }
> +
> +  #
> +  # DXE
> +  #
> +  MdeModulePkg/Core/Dxe/DxeMain.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> +  }
> +
> +  #
> +  # Architectural Protocols
> +  #
> +  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> +  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
> +    <LibraryClasses>
> +      ## TODO
> +      RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
> +  }
> +  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +  ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> +  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +
> +  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> +  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +
> +  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> +  }
> +
> +  #
> +  # UEFI application (Shell Embedded Boot Loader)
> +  #
> +  ShellPkg/Application/Shell/Shell.inf {
> +    <LibraryClasses>
> +      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> +      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf

Actually, could you leave out the TFTP command?

> +      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> +      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> +      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> +      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +
> +    <PcdsFixedAtBuild>
> +      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> +      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +  }
> +
> +  #
> +  # Generic BDS
> +  #
> +  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
> +  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  MdeModulePkg/Application/UiApp/UiApp.inf {
> +    <LibraryClasses>
> +      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> +      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> +      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> +  }
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> new file mode 100644
> index 000000000000..6c00e16b169e
> --- /dev/null
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -0,0 +1,276 @@
> +#
> +#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +#  Copyright (c) 2017, Linaro Limited. All rights reserved.
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into  the Flash Device Image.  Each FD section
> +# defines one flash "device" image.  A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash"  image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.BL33_AP_UEFI]
> +BaseAddress   = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
> +Size          = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +
> +# This one is tricky, it must be: BlockSize * NumBlocks = Size
> +BlockSize     = 0x00001000
> +NumBlocks     = 0xF0
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +
> +0x00000000|0x000F0000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file.  This section also defines order the components and modules are positioned
> +# within the image.  The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid         = 89cc2ab6-b847-475f-93e2-819603c3d15a
> +BlockSize          = 0x40
> +NumBlocks          = 0         # This FV gets compressed so make it just big enough
> +FvAlignment        = 8         # FV alignment and FV attributes setting.
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +  INF MdeModulePkg/Core/Dxe/DxeMain.inf
> +
> +  #
> +  # PI DXE Drivers producing Architectural Protocols (EFI Services)
> +  #
> +  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> +  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +  INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +  INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> +  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> +
> +  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> +  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> +  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> +  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> +
> +  #
> +  # UEFI applications
> +  #
> +  INF ShellPkg/Application/Shell/Shell.inf
> +
> +  #
> +  # Generic BDS
> +  #
> +  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> +  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> +  INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
> +  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +  INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment        = 8
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +  INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> +  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> +      SECTION FV_IMAGE = FVMAIN
> +    }
> +  }
> +
> +
> +################################################################################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the default
> +# rules for the different module type. User can add the customized rules to define the
> +# content of the FFS file.
> +#
> +################################################################################
> +
> +
> +############################################################################
> +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section   #
> +############################################################################
> +#
> +#[Rule.Common.DXE_DRIVER]
> +#  FILE DRIVER = $(NAMED_GUID) {
> +#    DXE_DEPEX    DXE_DEPEX               Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +#    COMPRESS PI_STD {
> +#      GUIDED {
> +#        PE32     PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
> +#        UI       STRING="$(MODULE_NAME)" Optional
> +#        VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +#      }
> +#    }
> +#  }
> +#
> +############################################################################
> +
> +#
> +# These SEC rules are used for ArmPlatformPkg/PrePi module.
> +# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the
> +# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint
> +#
> +[Rule.ARM.SEC]
> +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> +    TE  TE    Align = 32                $(INF_OUTPUT)/$(MODULE_NAME).efi
> +  }
> +
> +[Rule.AARCH64.SEC]
> +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> +    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
> +  }
> +
> +# A shim specific rule is required to ensure the alignment is 4K.
> +# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)
> +[Rule.ARM.SEC.SHIM]
> +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> +    TE  TE    Align = 4K                $(INF_OUTPUT)/$(MODULE_NAME).efi
> +  }
> +
> +[Rule.Common.PEI_CORE]
> +  FILE PEI_CORE = $(NAMED_GUID) {
> +    TE     TE                           $(INF_OUTPUT)/$(MODULE_NAME).efi
> +    UI     STRING ="$(MODULE_NAME)" Optional
> +  }
> +
> +[Rule.Common.PEIM]
> +  FILE PEIM = $(NAMED_GUID) {
> +     PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
> +     TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
> +     UI       STRING="$(MODULE_NAME)" Optional
> +  }
> +
> +[Rule.Common.PEIM.TIANOCOMPRESSED]
> +  FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> +    PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
> +    GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> +      PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
> +      UI        STRING="$(MODULE_NAME)" Optional
> +    }
> +  }
> +
> +[Rule.Common.DXE_CORE]
> +  FILE DXE_CORE = $(NAMED_GUID) {
> +    PE32     PE32                       $(INF_OUTPUT)/$(MODULE_NAME).efi
> +    UI       STRING="$(MODULE_NAME)" Optional
> +  }
> +
> +[Rule.Common.UEFI_DRIVER]
> +  FILE DRIVER = $(NAMED_GUID) {
> +    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
> +    UI           STRING="$(MODULE_NAME)" Optional
> +  }
> +
> +[Rule.Common.DXE_DRIVER]
> +  FILE DRIVER = $(NAMED_GUID) {
> +    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
> +    UI           STRING="$(MODULE_NAME)" Optional
> +  }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> +  FILE DRIVER = $(NAMED_GUID) {
> +    DXE_DEPEX    DXE_DEPEX              Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +    PE32         PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
> +    UI           STRING="$(MODULE_NAME)" Optional
> +  }
> +
> +[Rule.Common.UEFI_APPLICATION]
> +  FILE APPLICATION = $(NAMED_GUID) {
> +    UI     STRING ="$(MODULE_NAME)" Optional
> +    PE32   PE32                         $(INF_OUTPUT)/$(MODULE_NAME).efi
> +  }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> +  FILE DRIVER = $(NAMED_GUID) {
> +    DXE_DEPEX DXE_DEPEX Optional      |.depex
> +    PE32      PE32                    |.efi
> +    UI        STRING="$(MODULE_NAME)" Optional
> +    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +  }
> +
> +[Rule.Common.UEFI_APPLICATION.BINARY]
> +  FILE APPLICATION = $(NAMED_GUID) {
> +    PE32      PE32                    |.efi
> +    UI        STRING="$(MODULE_NAME)" Optional
> +    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +  }
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
> new file mode 100644
> index 000000000000..7edae77067d0
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/AArch64/SynquacerHelper.S
> @@ -0,0 +1,93 @@
> +/** @file
> +*
> +*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> +
> +PrimaryCoreMpid:
> +  .word    0x0
> +
> +//
> +// First platform specific function to be called in the PEI phase
> +//
> +// This function is actually the first function called by the PrePi
> +// or PrePeiCore modules. It allows to retrieve arguments passed to
> +// the UEFI firmware through the CPU registers.
> +//
> +ASM_PFX(ArmPlatformPeiBootAction):
> +  // The trusted firmware passes the primary CPU MPID through x0 register.
> +  // Save it in a variable.
> +  adr  x1, PrimaryCoreMpid
> +  str  w0, [x1]
> +  ret
> +
> +//
> +// Return the core position from the value of its MpId register
> +//
> +// This function returns the core position from the position 0 in the processor.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return   Return the core position
> +//
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +//  IN UINTN MpId
> +//  );
> +// With this function: CorePos = (ClusterId * 2) + CoreId
> +ASM_PFX(ArmPlatformGetCorePosition):
> +  and   x1, x0, #ARM_CORE_MASK
> +  and   x0, x0, #ARM_CLUSTER_MASK
> +  add   x0, x1, x0, LSR #7
> +  ret
> +
> +//
> +// Return the MpId of the primary core
> +//
> +// This function returns the MpId of the primary core.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return   Return the MpId of the primary core
> +//
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +//  VOID
> +//  );
> +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> +  ldr   w0, PrimaryCoreMpid
> +  ret
> +
> +//
> +// Return a non-zero value if the callee is the primary core
> +//
> +// This function returns a non-zero value if the callee is the primary core.
> +// The primary core is the core responsible to initialize the hardware and run UEFI.
> +// This function might be called from assembler before any stack is set.
> +//
> +//  @return   Return a non-zero value if the callee is the primary core.
> +//
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +//  IN UINTN MpId
> +//  );
> +ASM_PFX(ArmPlatformIsPrimaryCore):
> +  mov   w0, #1
> +  ret
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
> new file mode 100644
> index 000000000000..b37b461b77a5
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Arm/SynquacerHelper.S
> @@ -0,0 +1,93 @@
> +/** @file
> +*
> +*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> +
> +PrimaryCoreMpid:
> +  .word    0x0
> +
> +//
> +// First platform specific function to be called in the PEI phase
> +//
> +// This function is actually the first function called by the PrePi
> +// or PrePeiCore modules. It allows to retrieve arguments passed to
> +// the UEFI firmware through the CPU registers.
> +//
> +ASM_PFX(ArmPlatformPeiBootAction):
> +  // The trusted firmware passes the primary CPU MPID through r0 register.
> +  // Save it in a variable.
> +  adr  r1, PrimaryCoreMpid
> +  str  r0, [r1]
> +  bx   lr
> +
> +//
> +// Return the core position from the value of its MpId register
> +//
> +// This function returns the core position from the position 0 in the processor.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return   Return the core position
> +//
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +//  IN UINTN MpId
> +//  );
> +// With this function: CorePos = (ClusterId * 2) + CoreId
> +ASM_PFX(ArmPlatformGetCorePosition):
> +  and   r1, r0, #ARM_CORE_MASK
> +  and   r0, r0, #ARM_CLUSTER_MASK
> +  add   r0, r1, r0, LSR #7
> +  bx    lr
> +
> +//
> +// Return the MpId of the primary core
> +//
> +// This function returns the MpId of the primary core.
> +// This function might be called from assembler before any stack is set.
> +//
> +// @return   Return the MpId of the primary core
> +//
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +//  VOID
> +//  );
> +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> +  ldr   r0, PrimaryCoreMpid
> +  bx    lr
> +
> +//
> +// Return a non-zero value if the callee is the primary core
> +//
> +// This function returns a non-zero value if the callee is the primary core.
> +// The primary core is the core responsible to initialize the hardware and run UEFI.
> +// This function might be called from assembler before any stack is set.
> +//
> +//  @return   Return a non-zero value if the callee is the primary core.
> +//
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +//  IN UINTN MpId
> +//  );
> +ASM_PFX(ArmPlatformIsPrimaryCore):
> +  mov   r0, #1
> +  bx    lr
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
> new file mode 100644
> index 000000000000..014db60add8e
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/Synquacer.c
> @@ -0,0 +1,124 @@
> +/** @file
> +*
> +*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +*
> +*  This program and the accompanying materials
> +*  are licensed and made available under the terms and conditions of the BSD License
> +*  which accompanies this distribution.  The full text of the license may be found at
> +*  http://opensource.org/licenses/bsd-license.php
> +*
> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +STATIC ARM_CORE_INFO mSynquacerInfoTable[] = {
> +  { 0x0, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 0
> +  { 0x0, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 0, Core 1
> +  { 0x1, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 0
> +  { 0x1, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 1, Core 1
> +  { 0x2, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 0
> +  { 0x2, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 2, Core 1
> +  { 0x3, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 0
> +  { 0x3, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 3, Core 1
> +  { 0x4, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 0
> +  { 0x4, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 4, Core 1
> +  { 0x5, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 0
> +  { 0x5, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 5, Core 1
> +  { 0x6, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 0
> +  { 0x6, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 6, Core 1
> +  { 0x7, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 0
> +  { 0x7, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 7, Core 1
> +  { 0x8, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 0
> +  { 0x8, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 8, Core 1
> +  { 0x9, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 0
> +  { 0x9, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 9, Core 1
> +  { 0xa, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 0
> +  { 0xa, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 10, Core 1
> +  { 0xb, 0x0, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 0
> +  { 0xb, 0x1, 0x0, 0x0, 0x0, (UINT64)0xFFFFFFFF }, // Cluster 11, Core 1
> +};
> +
> +/**
> +  Return the current Boot Mode
> +
> +  This function returns the boot reason on the platform
> +
> +  @return   Return the current Boot Mode of the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> +  VOID
> +  )
> +{
> +  return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> +  Initialize controllers that must setup in the normal world
> +
> +  This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
> +  in the PEI phase.
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformInitialize (
> +  IN  UINTN                     MpId
> +  )
> +{
> +  return RETURN_SUCCESS;
> +}
> +
> +/**
> +  Initialize the system (or sometimes called permanent) memory
> +
> +  This memory is generally represented by the DRAM.
> +
> +**/
> +VOID
> +ArmPlatformInitializeSystemMemory (
> +  VOID
> +  )
> +{
> +}
> +
> +STATIC
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> +  OUT UINTN                   *CoreCount,
> +  OUT ARM_CORE_INFO           **ArmCoreTable
> +  )
> +{
> +  *CoreCount    = ARRAY_SIZE (mSynquacerInfoTable);
> +  *ArmCoreTable = mSynquacerInfoTable;
> +
> +  return EFI_SUCCESS;
> +}
> +
> +STATIC ARM_MP_CORE_INFO_PPI       mMpCoreInfoPpi = {
> +  PrePeiCoreGetMpCoreInfo
> +};
> +
> +STATIC EFI_PEI_PPI_DESCRIPTOR     mPlatformPpiTable[] = {
> +  {
> +    EFI_PEI_PPI_DESCRIPTOR_PPI,
> +    &gArmMpCoreInfoPpiGuid,
> +    &mMpCoreInfoPpi
> +  }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> +  OUT UINTN                   *PpiListSize,
> +  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
> +  )
> +{
> +  *PpiListSize = sizeof mPlatformPpiTable;
> +  *PpiList = mPlatformPpiTable;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
> new file mode 100644
> index 000000000000..63c3c8d35e21
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerLib/SynquacerLib.inf
> @@ -0,0 +1,39 @@
> +#
> +#  Copyright (c) 2013-2014, ARM Limited. All rights reserved.

So, there are a bunch of files in a row here all with the same
ARM-only Copyright statement - is this all accurate?

/
    Leif

> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010019
> +  BASE_NAME                      = SynquacerLib
> +  FILE_GUID                      = 8301a0ab-dd8d-476d-8170-1e34b51490d3
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = ArmPlatformLib
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> +  BaseLib
> +
> +[Sources.common]
> +  Synquacer.c
> +
> +[Sources.AARCH64]
> +  AArch64/SynquacerHelper.S | GCC
> +
> +[Sources.ARM]
> +  Arm/SynquacerHelper.S     | GCC
> +
> +[Ppis]
> +  gArmMpCoreInfoPpiGuid
> -- 
> 2.11.0
> 
_______________________________________________
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[edk2] [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs
Posted by Ard Biesheuvel, 2 weeks ago
Having two distinct root complexes is not supported by the standard
set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
of the latter specifically for this platform (and forget about the
others).

This also allows us to implement the Synopsys Designware PCIe specific
workaround for PCI config space accesses to devices 1 and up on bus 0.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c            | 1396 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf |   35 +
 2 files changed, 1431 insertions(+)

diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
new file mode 100644
index 000000000000..a9b57883b6cf
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1396 @@
+/** @file
+  PCI Segment Library for Synquacer SoC with multiple RCs
+
+  Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials are
+  licensed and made available under the terms and conditions of
+  the BSD License which accompanies this distribution.  The full
+  text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+#include <Platform/Pcie.h>
+
+typedef enum {
+  PciCfgWidthUint8      = 0,
+  PciCfgWidthUint16,
+  PciCfgWidthUint32,
+  PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+  Assert the validity of a PCI Segment address.
+  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+  @param  A The address to validate.
+  @param  M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+  ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+  IN  UINT64      Address
+  )
+{
+  switch ((UINT16)(Address >> 32)) {
+  case 0:
+    return SYNQUACER_PCI_SEG0_CONFIG_BASE;
+  case 1:
+    return SYNQUACER_PCI_SEG1_CONFIG_BASE;
+  default:
+    ASSERT (FALSE);
+  }
+
+  return 0;
+}
+
+/**
+  Internal worker function to read a PCI configuration register.
+
+  @param  Address The address that encodes the PCI Bus, Device, Function and
+                  Register.
+  @param  Width   The width of data to read
+
+  @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+  IN  UINT64                      Address,
+  IN  PCI_CFG_WIDTH               Width
+  )
+{
+  UINT64    Base;
+
+  Base = PciSegmentLibGetConfigBase (Address);
+
+  // ignore devices > 0 on bus 0
+  if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
+    return 0xffffffff;
+  }
+
+  switch (Width) {
+  case PciCfgWidthUint8:
+    return MmioRead8 (Base + (UINT32)Address);
+  case PciCfgWidthUint16:
+    return MmioRead16 (Base + (UINT32)Address);
+  case PciCfgWidthUint32:
+    return MmioRead32 (Base + (UINT32)Address);
+  default:
+    ASSERT (FALSE);
+  }
+
+  return 0;
+}
+
+/**
+  Internal worker function to writes a PCI configuration register.
+
+  @param  Address The address that encodes the PCI Bus, Device, Function and
+                  Register.
+  @param  Width   The width of data to write
+  @param  Data    The value to write.
+
+  @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+  IN  UINT64                      Address,
+  IN  PCI_CFG_WIDTH               Width,
+  IN  UINT32                      Data
+  )
+{
+  UINT64    Base;
+
+  Base = PciSegmentLibGetConfigBase (Address);
+
+  // ignore devices > 0 on bus 0
+  if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
+    return Data;
+  }
+
+  switch (Width) {
+  case PciCfgWidthUint8:
+    MmioWrite8 (Base + (UINT32)Address, Data);
+    break;
+  case PciCfgWidthUint16:
+    MmioWrite16 (Base + (UINT32)Address, Data);
+    break;
+  case PciCfgWidthUint32:
+    MmioWrite32 (Base + (UINT32)Address, Data);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+
+  return Data;
+}
+
+/**
+  Register a PCI device so PCI configuration registers may be accessed after
+  SetVirtualAddressMap().
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address The address that encodes the PCI Bus, Device, Function and
+                  Register.
+
+  @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
+                                   after ExitBootServices().
+  @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
+                                   at runtime could not be mapped.
+  @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
+                                   complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+  IN UINTN  Address
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+  return RETURN_UNSUPPORTED;
+}
+
+/**
+  Reads an 8-bit PCI configuration register.
+
+  Reads and returns the 8-bit PCI configuration register specified by Address.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
+                    and Register.
+
+  @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+  IN UINT64                    Address
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+  return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+  Writes an 8-bit PCI configuration register.
+
+  Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address     The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  Value       The value to write.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+  IN UINT64                    Address,
+  IN UINT8                     Value
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+  return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+  Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+  Reads the 8-bit PCI configuration register specified by Address,
+  performs a bitwise OR between the read result and the value specified by OrData,
+  and writes the result to the 8-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+  IN UINT64                    Address,
+  IN UINT8                     OrData
+  )
+{
+  return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+  Reads the 8-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  and writes the result to the 8-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+  IN UINT64                    Address,
+  IN UINT8                     AndData
+  )
+{
+  return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+  followed a  bitwise OR with another 8-bit value.
+
+  Reads the 8-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+  and writes the result to the 8-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData    The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+  IN UINT64                    Address,
+  IN UINT8                     AndData,
+  IN UINT8                     OrData
+  )
+{
+  return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
+}
+
+/**
+  Reads a bit field of a PCI configuration register.
+
+  Reads the bit field in an 8-bit PCI configuration register. The bit field is
+  specified by the StartBit and the EndBit. The value of the bit field is
+  returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to read.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+
+  @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit
+  )
+{
+  return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+  Writes a bit field to a PCI configuration register.
+
+  Writes Value to the bit field of the PCI configuration register. The bit
+  field is specified by the StartBit and the EndBit. All other bits in the
+  destination PCI configuration register are preserved. The new value of the
+  8-bit register is returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  Value     The new value of the bit field.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     Value
+  )
+{
+  return PciSegmentWrite8 (
+           Address,
+           BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
+           );
+}
+
+/**
+  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+  writes the result back to the bit field in the 8-bit port.
+
+  Reads the 8-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 8-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized. Extra left bits in OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     OrData
+  )
+{
+  return PciSegmentWrite8 (
+           Address,
+           BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
+           );
+}
+
+/**
+  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+  AND, and writes the result back to the bit field in the 8-bit register.
+
+  Reads the 8-bit PCI configuration register specified by Address, performs a
+  bitwise AND between the read result and the value specified by AndData, and
+  writes the result to the 8-bit PCI configuration register specified by
+  Address. The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are
+  serialized. Extra left bits in AndData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     AndData
+  )
+{
+  return PciSegmentWrite8 (
+           Address,
+           BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
+           );
+}
+
+/**
+  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+  bitwise OR, and writes the result back to the bit field in the
+  8-bit port.
+
+  Reads the 8-bit PCI configuration register specified by Address, performs a
+  bitwise AND followed by a bitwise OR between the read result and
+  the value specified by AndData, and writes the result to the 8-bit PCI
+  configuration register specified by Address. The value written to the PCI
+  configuration register is returned. This function must guarantee that all PCI
+  read and write operations are serialized. Extra left bits in both AndData and
+  OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the result of the AND operation.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     AndData,
+  IN UINT8                     OrData
+  )
+{
+  return PciSegmentWrite8 (
+           Address,
+           BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
+           );
+}
+
+/**
+  Reads a 16-bit PCI configuration register.
+
+  Reads and returns the 16-bit PCI configuration register specified by Address.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+  @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+  IN UINT64                    Address
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+  return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+  Writes a 16-bit PCI configuration register.
+
+  Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address     The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  Value       The value to write.
+
+  @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+  IN UINT64                    Address,
+  IN UINT16                    Value
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+  return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+  Performs a bitwise OR of a 16-bit PCI configuration register with
+  a 16-bit value.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 16-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address The address that encodes the PCI Segment, Bus, Device, Function and
+                  Register.
+  @param  OrData  The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+  IN UINT64                    Address,
+  IN UINT16                    OrData
+  )
+{
+  return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+  Reads the 16-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  and writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+  IN UINT64                    Address,
+  IN UINT16                    AndData
+  )
+{
+  return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+  followed a  bitwise OR with another 16-bit value.
+
+  Reads the 16-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+  and writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+  IN UINT64                    Address,
+  IN UINT16                    AndData,
+  IN UINT16                    OrData
+  )
+{
+  return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+}
+
+/**
+  Reads a bit field of a PCI configuration register.
+
+  Reads the bit field in a 16-bit PCI configuration register. The bit field is
+  specified by the StartBit and the EndBit. The value of the bit field is
+  returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to read.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+
+  @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit
+  )
+{
+  return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+  Writes a bit field to a PCI configuration register.
+
+  Writes Value to the bit field of the PCI configuration register. The bit
+  field is specified by the StartBit and the EndBit. All other bits in the
+  destination PCI configuration register are preserved. The new value of the
+  16-bit register is returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  Value     The new value of the bit field.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    Value
+  )
+{
+  return PciSegmentWrite16 (
+           Address,
+           BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
+           );
+}
+
+/**
+  Reads the 16-bit PCI configuration register specified by Address,
+  performs a bitwise OR between the read result and the value specified by OrData,
+  and writes the result to the 16-bit PCI configuration register specified by Address.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    OrData
+  )
+{
+  return PciSegmentWrite16 (
+           Address,
+           BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
+           );
+}
+
+/**
+  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+  and writes the result back to the bit field in the 16-bit port.
+
+  Reads the 16-bit PCI configuration register specified by Address,
+  performs a bitwise OR between the read result and the value specified by OrData,
+  and writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+  Extra left bits in OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    The ordinal of the least significant bit in a byte is bit 0.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    The ordinal of the most significant bit in a byte is bit 7.
+  @param  AndData   The value to AND with the read value from the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    AndData
+  )
+{
+  return PciSegmentWrite16 (
+           Address,
+           BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
+           );
+}
+
+/**
+  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+  bitwise OR, and writes the result back to the bit field in the
+  16-bit port.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise AND followed by a bitwise OR between the read result and
+  the value specified by AndData, and writes the result to the 16-bit PCI
+  configuration register specified by Address. The value written to the PCI
+  configuration register is returned. This function must guarantee that all PCI
+  read and write operations are serialized. Extra left bits in both AndData and
+  OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the result of the AND operation.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    AndData,
+  IN UINT16                    OrData
+  )
+{
+  return PciSegmentWrite16 (
+           Address,
+           BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
+           );
+}
+
+/**
+  Reads a 32-bit PCI configuration register.
+
+  Reads and returns the 32-bit PCI configuration register specified by Address.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
+                    and Register.
+
+  @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+  IN UINT64                    Address
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+  return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+  Writes a 32-bit PCI configuration register.
+
+  Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address     The address that encodes the PCI Segment, Bus, Device,
+                      Function, and Register.
+  @param  Value       The value to write.
+
+  @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+  IN UINT64                    Address,
+  IN UINT32                    Value
+  )
+{
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+  return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+  Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+  Reads the 32-bit PCI configuration register specified by Address,
+  performs a bitwise OR between the read result and the value specified by OrData,
+  and writes the result to the 32-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+  IN UINT64                    Address,
+  IN UINT32                    OrData
+  )
+{
+  return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+  Reads the 32-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  and writes the result to the 32-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
+                    and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+  IN UINT64                    Address,
+  IN UINT32                    AndData
+  )
+{
+  return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+  followed a  bitwise OR with another 32-bit value.
+
+  Reads the 32-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+  and writes the result to the 32-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
+                    and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+  IN UINT64                    Address,
+  IN UINT32                    AndData,
+  IN UINT32                    OrData
+  )
+{
+  return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+  Reads a bit field of a PCI configuration register.
+
+  Reads the bit field in a 32-bit PCI configuration register. The bit field is
+  specified by the StartBit and the EndBit. The value of the bit field is
+  returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to read.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+
+  @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit
+  )
+{
+  return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+  Writes a bit field to a PCI configuration register.
+
+  Writes Value to the bit field of the PCI configuration register. The bit
+  field is specified by the StartBit and the EndBit. All other bits in the
+  destination PCI configuration register are preserved. The new value of the
+  32-bit register is returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  Value     The new value of the bit field.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    Value
+  )
+{
+  return PciSegmentWrite32 (
+           Address,
+           BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
+           );
+}
+
+/**
+  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+  writes the result back to the bit field in the 32-bit port.
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 32-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized. Extra left bits in OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    OrData
+  )
+{
+  return PciSegmentWrite32 (
+           Address,
+           BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
+           );
+}
+
+/**
+  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+  AND, and writes the result back to the bit field in the 32-bit register.
+
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+  AND between the read result and the value specified by AndData, and writes the result
+  to the 32-bit PCI configuration register specified by Address. The value written to
+  the PCI configuration register is returned.  This function must guarantee that all PCI
+  read and write operations are serialized.  Extra left bits in AndData are stripped.
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    AndData
+  )
+{
+  return PciSegmentWrite32 (
+           Address,
+           BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
+           );
+}
+
+/**
+  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+  bitwise OR, and writes the result back to the bit field in the
+  32-bit port.
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a
+  bitwise AND followed by a bitwise OR between the read result and
+  the value specified by AndData, and writes the result to the 32-bit PCI
+  configuration register specified by Address. The value written to the PCI
+  configuration register is returned. This function must guarantee that all PCI
+  read and write operations are serialized. Extra left bits in both AndData and
+  OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   The PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the result of the AND operation.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    AndData,
+  IN UINT32                    OrData
+  )
+{
+  return PciSegmentWrite32 (
+           Address,
+           BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
+           );
+}
+
+/**
+  Reads a range of PCI configuration registers into a caller supplied buffer.
+
+  Reads the range of PCI configuration registers specified by StartAddress and
+  Size into the buffer specified by Buffer. This function only allows the PCI
+  configuration registers from a single PCI function to be read. Size is
+  returned. When possible 32-bit PCI configuration read cycles are used to read
+  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+  and 16-bit PCI configuration read cycles may be used at the beginning and the
+  end of the range.
+
+  If any reserved bits in StartAddress are set, then ASSERT().
+  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+  If Size > 0 and Buffer is NULL, then ASSERT().
+
+  @param  StartAddress  The starting address that encodes the PCI Segment, Bus,
+                        Device, Function and Register.
+  @param  Size          The size in bytes of the transfer.
+  @param  Buffer        The pointer to a buffer receiving the data read.
+
+  @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+  IN  UINT64                   StartAddress,
+  IN  UINTN                    Size,
+  OUT VOID                     *Buffer
+  )
+{
+  UINTN                             ReturnValue;
+
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+  if (Size == 0) {
+    return Size;
+  }
+
+  ASSERT (Buffer != NULL);
+
+  //
+  // Save Size for return
+  //
+  ReturnValue = Size;
+
+  if ((StartAddress & BIT0) != 0) {
+    //
+    // Read a byte if StartAddress is byte aligned
+    //
+    *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+    StartAddress += sizeof (UINT8);
+    Size -= sizeof (UINT8);
+    Buffer = (UINT8*)Buffer + 1;
+  }
+
+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+    //
+    // Read a word if StartAddress is word aligned
+    //
+    WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+    StartAddress += sizeof (UINT16);
+    Size -= sizeof (UINT16);
+    Buffer = (UINT16*)Buffer + 1;
+  }
+
+  while (Size >= sizeof (UINT32)) {
+    //
+    // Read as many double words as possible
+    //
+    WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+    StartAddress += sizeof (UINT32);
+    Size -= sizeof (UINT32);
+    Buffer = (UINT32*)Buffer + 1;
+  }
+
+  if (Size >= sizeof (UINT16)) {
+    //
+    // Read the last remaining word if exist
+    //
+    WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+    StartAddress += sizeof (UINT16);
+    Size -= sizeof (UINT16);
+    Buffer = (UINT16*)Buffer + 1;
+  }
+
+  if (Size >= sizeof (UINT8)) {
+    //
+    // Read the last remaining byte if exist
+    //
+    *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+  }
+
+  return ReturnValue;
+}
+
+
+/**
+  Copies the data in a caller supplied buffer to a specified range of PCI
+  configuration space.
+
+  Writes the range of PCI configuration registers specified by StartAddress and
+  Size from the buffer specified by Buffer. This function only allows the PCI
+  configuration registers from a single PCI function to be written. Size is
+  returned. When possible 32-bit PCI configuration write cycles are used to
+  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+  8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+  and the end of the range.
+
+  If any reserved bits in StartAddress are set, then ASSERT().
+  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+  If Size > 0 and Buffer is NULL, then ASSERT().
+
+  @param  StartAddress  The starting address that encodes the PCI Segment, Bus,
+                        Device, Function and Register.
+  @param  Size          The size in bytes of the transfer.
+  @param  Buffer        The pointer to a buffer containing the data to write.
+
+  @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+  IN UINT64                    StartAddress,
+  IN UINTN                     Size,
+  IN VOID                      *Buffer
+  )
+{
+  UINTN                             ReturnValue;
+
+  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+  if (Size == 0) {
+    return 0;
+  }
+
+  ASSERT (Buffer != NULL);
+
+  //
+  // Save Size for return
+  //
+  ReturnValue = Size;
+
+  if ((StartAddress & BIT0) != 0) {
+    //
+    // Write a byte if StartAddress is byte aligned
+    //
+    PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+    StartAddress += sizeof (UINT8);
+    Size -= sizeof (UINT8);
+    Buffer = (UINT8*)Buffer + 1;
+  }
+
+  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+    //
+    // Write a word if StartAddress is word aligned
+    //
+    PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+    StartAddress += sizeof (UINT16);
+    Size -= sizeof (UINT16);
+    Buffer = (UINT16*)Buffer + 1;
+  }
+
+  while (Size >= sizeof (UINT32)) {
+    //
+    // Write as many double words as possible
+    //
+    PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+    StartAddress += sizeof (UINT32);
+    Size -= sizeof (UINT32);
+    Buffer = (UINT32*)Buffer + 1;
+  }
+
+  if (Size >= sizeof (UINT16)) {
+    //
+    // Write the last remaining word if exist
+    //
+    PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+    StartAddress += sizeof (UINT16);
+    Size -= sizeof (UINT16);
+    Buffer = (UINT16*)Buffer + 1;
+  }
+
+  if (Size >= sizeof (UINT8)) {
+    //
+    // Write the last remaining byte if exist
+    //
+    PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+  }
+
+  return ReturnValue;
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
new file mode 100644
index 000000000000..e5f3ac494b32
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCI Segment Library for Synquacer SoC with multiple RCs
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SynquacerPciSegmentLib
+  FILE_GUID                      = 1299f005-a30b-47d3-9003-24a91f100840
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PciSegmentLib
+
+[Sources]
+  PciSegmentLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
-- 
2.11.0

_______________________________________________
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edk2-devel@lists.01.org
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Re: [edk2] [PATCH edk2-platforms 04/14] Silicon/Synquacer: implement PciSegmentLib to support dual RCs
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:05PM +0100, Ard Biesheuvel wrote:
> Having two distinct root complexes is not supported by the standard
> set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
> of the latter specifically for this platform (and forget about the
> others).
> 
> This also allows us to implement the Synopsys Designware PCIe specific
> workaround for PCI config space accesses to devices 1 and up on bus 0.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c            | 1396 ++++++++++++++++++++
>  Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf |   35 +
>  2 files changed, 1431 insertions(+)
> 
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 000000000000..a9b57883b6cf
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,1396 @@
> +/** @file
> +  PCI Segment Library for Synquacer SoC with multiple RCs
> +
> +  Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>

This does not look unmodified to me.

(I don't really have any comments on the below.)

/
    Leif

> +  This program and the accompanying materials are
> +  licensed and made available under the terms and conditions of
> +  the BSD License which accompanies this distribution.  The full
> +  text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +
> +#include <Library/PciSegmentLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +
> +#include <Platform/Pcie.h>
> +
> +typedef enum {
> +  PciCfgWidthUint8      = 0,
> +  PciCfgWidthUint16,
> +  PciCfgWidthUint32,
> +  PciCfgWidthMax
> +} PCI_CFG_WIDTH;
> +
> +/**
> +  Assert the validity of a PCI Segment address.
> +  A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
> +
> +  @param  A The address to validate.
> +  @param  M Additional bits to assert to be zero.
> +
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> +  ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> +
> +STATIC
> +UINT64
> +PciSegmentLibGetConfigBase (
> +  IN  UINT64      Address
> +  )
> +{
> +  switch ((UINT16)(Address >> 32)) {
> +  case 0:
> +    return SYNQUACER_PCI_SEG0_CONFIG_BASE;
> +  case 1:
> +    return SYNQUACER_PCI_SEG1_CONFIG_BASE;
> +  default:
> +    ASSERT (FALSE);
> +  }
> +
> +  return 0;
> +}
> +
> +/**
> +  Internal worker function to read a PCI configuration register.
> +
> +  @param  Address The address that encodes the PCI Bus, Device, Function and
> +                  Register.
> +  @param  Width   The width of data to read
> +
> +  @return The value read from the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> +  IN  UINT64                      Address,
> +  IN  PCI_CFG_WIDTH               Width
> +  )
> +{
> +  UINT64    Base;
> +
> +  Base = PciSegmentLibGetConfigBase (Address);
> +
> +  // ignore devices > 0 on bus 0
> +  if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
> +    return 0xffffffff;
> +  }
> +
> +  switch (Width) {
> +  case PciCfgWidthUint8:
> +    return MmioRead8 (Base + (UINT32)Address);
> +  case PciCfgWidthUint16:
> +    return MmioRead16 (Base + (UINT32)Address);
> +  case PciCfgWidthUint32:
> +    return MmioRead32 (Base + (UINT32)Address);
> +  default:
> +    ASSERT (FALSE);
> +  }
> +
> +  return 0;
> +}
> +
> +/**
> +  Internal worker function to writes a PCI configuration register.
> +
> +  @param  Address The address that encodes the PCI Bus, Device, Function and
> +                  Register.
> +  @param  Width   The width of data to write
> +  @param  Data    The value to write.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> +  IN  UINT64                      Address,
> +  IN  PCI_CFG_WIDTH               Width,
> +  IN  UINT32                      Data
> +  )
> +{
> +  UINT64    Base;
> +
> +  Base = PciSegmentLibGetConfigBase (Address);
> +
> +  // ignore devices > 0 on bus 0
> +  if ((Address & 0xff00000) == 0 && (Address & 0xf800) != 0) {
> +    return Data;
> +  }
> +
> +  switch (Width) {
> +  case PciCfgWidthUint8:
> +    MmioWrite8 (Base + (UINT32)Address, Data);
> +    break;
> +  case PciCfgWidthUint16:
> +    MmioWrite16 (Base + (UINT32)Address, Data);
> +    break;
> +  case PciCfgWidthUint32:
> +    MmioWrite32 (Base + (UINT32)Address, Data);
> +    break;
> +  default:
> +    ASSERT (FALSE);
> +  }
> +
> +  return Data;
> +}
> +
> +/**
> +  Register a PCI device so PCI configuration registers may be accessed after
> +  SetVirtualAddressMap().
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +
> +  @param  Address The address that encodes the PCI Bus, Device, Function and
> +                  Register.
> +
> +  @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
> +  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
> +                                   after ExitBootServices().
> +  @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
> +                                   at runtime could not be mapped.
> +  @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
> +                                   complete the registration.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PciSegmentRegisterForRuntimeAccess (
> +  IN UINTN  Address
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +  return RETURN_UNSUPPORTED;
> +}
> +
> +/**
> +  Reads an 8-bit PCI configuration register.
> +
> +  Reads and returns the 8-bit PCI configuration register specified by Address.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
> +                    and Register.
> +
> +  @return The 8-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> +  IN UINT64                    Address
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> +  return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> +}
> +
> +/**
> +  Writes an 8-bit PCI configuration register.
> +
> +  Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
> +  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +
> +  @param  Address     The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  Value       The value to write.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> +  IN UINT64                    Address,
> +  IN UINT8                     Value
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> +  return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
> +}
> +
> +/**
> +  Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
> +
> +  Reads the 8-bit PCI configuration register specified by Address,
> +  performs a bitwise OR between the read result and the value specified by OrData,
> +  and writes the result to the 8-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentOr8 (
> +  IN UINT64                    Address,
> +  IN UINT8                     OrData
> +  )
> +{
> +  return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
> +}
> +
> +/**
> +  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
> +
> +  Reads the 8-bit PCI configuration register specified by Address,
> +  performs a bitwise AND between the read result and the value specified by AndData,
> +  and writes the result to the 8-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +  If any reserved bits in Address are set, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAnd8 (
> +  IN UINT64                    Address,
> +  IN UINT8                     AndData
> +  )
> +{
> +  return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
> +}
> +
> +/**
> +  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
> +  followed a  bitwise OR with another 8-bit value.
> +
> +  Reads the 8-bit PCI configuration register specified by Address,
> +  performs a bitwise AND between the read result and the value specified by AndData,
> +  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> +  and writes the result to the 8-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  AndData    The value to AND with the PCI configuration register.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentAndThenOr8 (
> +  IN UINT64                    Address,
> +  IN UINT8                     AndData,
> +  IN UINT8                     OrData
> +  )
> +{
> +  return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
> +}
> +
> +/**
> +  Reads a bit field of a PCI configuration register.
> +
> +  Reads the bit field in an 8-bit PCI configuration register. The bit field is
> +  specified by the StartBit and the EndBit. The value of the bit field is
> +  returned.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 7, then ASSERT().
> +  If EndBit is greater than 7, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to read.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..7.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..7.
> +
> +  @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldRead8 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit
> +  )
> +{
> +  return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
> +}
> +
> +/**
> +  Writes a bit field to a PCI configuration register.
> +
> +  Writes Value to the bit field of the PCI configuration register. The bit
> +  field is specified by the StartBit and the EndBit. All other bits in the
> +  destination PCI configuration register are preserved. The new value of the
> +  8-bit register is returned.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 7, then ASSERT().
> +  If EndBit is greater than 7, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..7.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..7.
> +  @param  Value     The new value of the bit field.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldWrite8 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT8                     Value
> +  )
> +{
> +  return PciSegmentWrite8 (
> +           Address,
> +           BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> +  writes the result back to the bit field in the 8-bit port.
> +
> +  Reads the 8-bit PCI configuration register specified by Address, performs a
> +  bitwise OR between the read result and the value specified by
> +  OrData, and writes the result to the 8-bit PCI configuration register
> +  specified by Address. The value written to the PCI configuration register is
> +  returned. This function must guarantee that all PCI read and write operations
> +  are serialized. Extra left bits in OrData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 7, then ASSERT().
> +  If EndBit is greater than 7, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..7.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..7.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldOr8 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT8                     OrData
> +  )
> +{
> +  return PciSegmentWrite8 (
> +           Address,
> +           BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> +  AND, and writes the result back to the bit field in the 8-bit register.
> +
> +  Reads the 8-bit PCI configuration register specified by Address, performs a
> +  bitwise AND between the read result and the value specified by AndData, and
> +  writes the result to the 8-bit PCI configuration register specified by
> +  Address. The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are
> +  serialized. Extra left bits in AndData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 7, then ASSERT().
> +  If EndBit is greater than 7, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..7.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..7.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAnd8 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT8                     AndData
> +  )
> +{
> +  return PciSegmentWrite8 (
> +           Address,
> +           BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> +  bitwise OR, and writes the result back to the bit field in the
> +  8-bit port.
> +
> +  Reads the 8-bit PCI configuration register specified by Address, performs a
> +  bitwise AND followed by a bitwise OR between the read result and
> +  the value specified by AndData, and writes the result to the 8-bit PCI
> +  configuration register specified by Address. The value written to the PCI
> +  configuration register is returned. This function must guarantee that all PCI
> +  read and write operations are serialized. Extra left bits in both AndData and
> +  OrData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 7, then ASSERT().
> +  If EndBit is greater than 7, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..7.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..7.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +  @param  OrData    The value to OR with the result of the AND operation.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentBitFieldAndThenOr8 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT8                     AndData,
> +  IN UINT8                     OrData
> +  )
> +{
> +  return PciSegmentWrite8 (
> +           Address,
> +           BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
> +           );
> +}
> +
> +/**
> +  Reads a 16-bit PCI configuration register.
> +
> +  Reads and returns the 16-bit PCI configuration register specified by Address.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> +  @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> +  IN UINT64                    Address
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> +  return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
> +}
> +
> +/**
> +  Writes a 16-bit PCI configuration register.
> +
> +  Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
> +  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address     The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  Value       The value to write.
> +
> +  @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> +  IN UINT64                    Address,
> +  IN UINT16                    Value
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> +  return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> +  Performs a bitwise OR of a 16-bit PCI configuration register with
> +  a 16-bit value.
> +
> +  Reads the 16-bit PCI configuration register specified by Address, performs a
> +  bitwise OR between the read result and the value specified by
> +  OrData, and writes the result to the 16-bit PCI configuration register
> +  specified by Address. The value written to the PCI configuration register is
> +  returned. This function must guarantee that all PCI read and write operations
> +  are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address The address that encodes the PCI Segment, Bus, Device, Function and
> +                  Register.
> +  @param  OrData  The value to OR with the PCI configuration register.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentOr16 (
> +  IN UINT64                    Address,
> +  IN UINT16                    OrData
> +  )
> +{
> +  return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
> +}
> +
> +/**
> +  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
> +
> +  Reads the 16-bit PCI configuration register specified by Address,
> +  performs a bitwise AND between the read result and the value specified by AndData,
> +  and writes the result to the 16-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAnd16 (
> +  IN UINT64                    Address,
> +  IN UINT16                    AndData
> +  )
> +{
> +  return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
> +}
> +
> +/**
> +  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
> +  followed a  bitwise OR with another 16-bit value.
> +
> +  Reads the 16-bit PCI configuration register specified by Address,
> +  performs a bitwise AND between the read result and the value specified by AndData,
> +  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> +  and writes the result to the 16-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentAndThenOr16 (
> +  IN UINT64                    Address,
> +  IN UINT16                    AndData,
> +  IN UINT16                    OrData
> +  )
> +{
> +  return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
> +}
> +
> +/**
> +  Reads a bit field of a PCI configuration register.
> +
> +  Reads the bit field in a 16-bit PCI configuration register. The bit field is
> +  specified by the StartBit and the EndBit. The value of the bit field is
> +  returned.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +  If StartBit is greater than 15, then ASSERT().
> +  If EndBit is greater than 15, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to read.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..15.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..15.
> +
> +  @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldRead16 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit
> +  )
> +{
> +  return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
> +}
> +
> +/**
> +  Writes a bit field to a PCI configuration register.
> +
> +  Writes Value to the bit field of the PCI configuration register. The bit
> +  field is specified by the StartBit and the EndBit. All other bits in the
> +  destination PCI configuration register are preserved. The new value of the
> +  16-bit register is returned.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +  If StartBit is greater than 15, then ASSERT().
> +  If EndBit is greater than 15, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..15.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..15.
> +  @param  Value     The new value of the bit field.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldWrite16 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT16                    Value
> +  )
> +{
> +  return PciSegmentWrite16 (
> +           Address,
> +           BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
> +           );
> +}
> +
> +/**
> +  Reads the 16-bit PCI configuration register specified by Address,
> +  performs a bitwise OR between the read result and the value specified by OrData,
> +  and writes the result to the 16-bit PCI configuration register specified by Address.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +  If StartBit is greater than 15, then ASSERT().
> +  If EndBit is greater than 15, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..15.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..15.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldOr16 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT16                    OrData
> +  )
> +{
> +  return PciSegmentWrite16 (
> +           Address,
> +           BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
> +  and writes the result back to the bit field in the 16-bit port.
> +
> +  Reads the 16-bit PCI configuration register specified by Address,
> +  performs a bitwise OR between the read result and the value specified by OrData,
> +  and writes the result to the 16-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +  Extra left bits in OrData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 16-bit boundary, then ASSERT().
> +  If StartBit is greater than 7, then ASSERT().
> +  If EndBit is greater than 7, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    The ordinal of the least significant bit in a byte is bit 0.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    The ordinal of the most significant bit in a byte is bit 7.
> +  @param  AndData   The value to AND with the read value from the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAnd16 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT16                    AndData
> +  )
> +{
> +  return PciSegmentWrite16 (
> +           Address,
> +           BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> +  bitwise OR, and writes the result back to the bit field in the
> +  16-bit port.
> +
> +  Reads the 16-bit PCI configuration register specified by Address, performs a
> +  bitwise AND followed by a bitwise OR between the read result and
> +  the value specified by AndData, and writes the result to the 16-bit PCI
> +  configuration register specified by Address. The value written to the PCI
> +  configuration register is returned. This function must guarantee that all PCI
> +  read and write operations are serialized. Extra left bits in both AndData and
> +  OrData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 15, then ASSERT().
> +  If EndBit is greater than 15, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..15.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..15.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +  @param  OrData    The value to OR with the result of the AND operation.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentBitFieldAndThenOr16 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT16                    AndData,
> +  IN UINT16                    OrData
> +  )
> +{
> +  return PciSegmentWrite16 (
> +           Address,
> +           BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
> +           );
> +}
> +
> +/**
> +  Reads a 32-bit PCI configuration register.
> +
> +  Reads and returns the 32-bit PCI configuration register specified by Address.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
> +                    and Register.
> +
> +  @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> +  IN UINT64                    Address
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> +  return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> +  Writes a 32-bit PCI configuration register.
> +
> +  Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
> +  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address     The address that encodes the PCI Segment, Bus, Device,
> +                      Function, and Register.
> +  @param  Value       The value to write.
> +
> +  @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> +  IN UINT64                    Address,
> +  IN UINT32                    Value
> +  )
> +{
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> +  return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> +  Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
> +
> +  Reads the 32-bit PCI configuration register specified by Address,
> +  performs a bitwise OR between the read result and the value specified by OrData,
> +  and writes the result to the 32-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentOr32 (
> +  IN UINT64                    Address,
> +  IN UINT32                    OrData
> +  )
> +{
> +  return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
> +}
> +
> +/**
> +  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
> +
> +  Reads the 32-bit PCI configuration register specified by Address,
> +  performs a bitwise AND between the read result and the value specified by AndData,
> +  and writes the result to the 32-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
> +                    and Register.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAnd32 (
> +  IN UINT64                    Address,
> +  IN UINT32                    AndData
> +  )
> +{
> +  return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
> +}
> +
> +/**
> +  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
> +  followed a  bitwise OR with another 32-bit value.
> +
> +  Reads the 32-bit PCI configuration register specified by Address,
> +  performs a bitwise AND between the read result and the value specified by AndData,
> +  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
> +  and writes the result to the 32-bit PCI configuration register specified by Address.
> +  The value written to the PCI configuration register is returned.
> +  This function must guarantee that all PCI read and write operations are serialized.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> +  @param  Address   The address that encodes the PCI Segment, Bus, Device, Function,
> +                    and Register.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentAndThenOr32 (
> +  IN UINT64                    Address,
> +  IN UINT32                    AndData,
> +  IN UINT32                    OrData
> +  )
> +{
> +  return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
> +}
> +
> +/**
> +  Reads a bit field of a PCI configuration register.
> +
> +  Reads the bit field in a 32-bit PCI configuration register. The bit field is
> +  specified by the StartBit and the EndBit. The value of the bit field is
> +  returned.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +  If StartBit is greater than 31, then ASSERT().
> +  If EndBit is greater than 31, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to read.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..31.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..31.
> +
> +  @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldRead32 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit
> +  )
> +{
> +  return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
> +}
> +
> +/**
> +  Writes a bit field to a PCI configuration register.
> +
> +  Writes Value to the bit field of the PCI configuration register. The bit
> +  field is specified by the StartBit and the EndBit. All other bits in the
> +  destination PCI configuration register are preserved. The new value of the
> +  32-bit register is returned.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +  If StartBit is greater than 31, then ASSERT().
> +  If EndBit is greater than 31, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..31.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..31.
> +  @param  Value     The new value of the bit field.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldWrite32 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT32                    Value
> +  )
> +{
> +  return PciSegmentWrite32 (
> +           Address,
> +           BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> +  writes the result back to the bit field in the 32-bit port.
> +
> +  Reads the 32-bit PCI configuration register specified by Address, performs a
> +  bitwise OR between the read result and the value specified by
> +  OrData, and writes the result to the 32-bit PCI configuration register
> +  specified by Address. The value written to the PCI configuration register is
> +  returned. This function must guarantee that all PCI read and write operations
> +  are serialized. Extra left bits in OrData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 31, then ASSERT().
> +  If EndBit is greater than 31, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..31.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..31.
> +  @param  OrData    The value to OR with the PCI configuration register.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldOr32 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT32                    OrData
> +  )
> +{
> +  return PciSegmentWrite32 (
> +           Address,
> +           BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> +  AND, and writes the result back to the bit field in the 32-bit register.
> +
> +
> +  Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
> +  AND between the read result and the value specified by AndData, and writes the result
> +  to the 32-bit PCI configuration register specified by Address. The value written to
> +  the PCI configuration register is returned.  This function must guarantee that all PCI
> +  read and write operations are serialized.  Extra left bits in AndData are stripped.
> +  If any reserved bits in Address are set, then ASSERT().
> +  If Address is not aligned on a 32-bit boundary, then ASSERT().
> +  If StartBit is greater than 31, then ASSERT().
> +  If EndBit is greater than 31, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..31.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..31.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAnd32 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT32                    AndData
> +  )
> +{
> +  return PciSegmentWrite32 (
> +           Address,
> +           BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
> +           );
> +}
> +
> +/**
> +  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> +  bitwise OR, and writes the result back to the bit field in the
> +  32-bit port.
> +
> +  Reads the 32-bit PCI configuration register specified by Address, performs a
> +  bitwise AND followed by a bitwise OR between the read result and
> +  the value specified by AndData, and writes the result to the 32-bit PCI
> +  configuration register specified by Address. The value written to the PCI
> +  configuration register is returned. This function must guarantee that all PCI
> +  read and write operations are serialized. Extra left bits in both AndData and
> +  OrData are stripped.
> +
> +  If any reserved bits in Address are set, then ASSERT().
> +  If StartBit is greater than 31, then ASSERT().
> +  If EndBit is greater than 31, then ASSERT().
> +  If EndBit is less than StartBit, then ASSERT().
> +  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
> +
> +  @param  Address   The PCI configuration register to write.
> +  @param  StartBit  The ordinal of the least significant bit in the bit field.
> +                    Range 0..31.
> +  @param  EndBit    The ordinal of the most significant bit in the bit field.
> +                    Range 0..31.
> +  @param  AndData   The value to AND with the PCI configuration register.
> +  @param  OrData    The value to OR with the result of the AND operation.
> +
> +  @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentBitFieldAndThenOr32 (
> +  IN UINT64                    Address,
> +  IN UINTN                     StartBit,
> +  IN UINTN                     EndBit,
> +  IN UINT32                    AndData,
> +  IN UINT32                    OrData
> +  )
> +{
> +  return PciSegmentWrite32 (
> +           Address,
> +           BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
> +           );
> +}
> +
> +/**
> +  Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> +  Reads the range of PCI configuration registers specified by StartAddress and
> +  Size into the buffer specified by Buffer. This function only allows the PCI
> +  configuration registers from a single PCI function to be read. Size is
> +  returned. When possible 32-bit PCI configuration read cycles are used to read
> +  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> +  and 16-bit PCI configuration read cycles may be used at the beginning and the
> +  end of the range.
> +
> +  If any reserved bits in StartAddress are set, then ASSERT().
> +  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> +  If Size > 0 and Buffer is NULL, then ASSERT().
> +
> +  @param  StartAddress  The starting address that encodes the PCI Segment, Bus,
> +                        Device, Function and Register.
> +  @param  Size          The size in bytes of the transfer.
> +  @param  Buffer        The pointer to a buffer receiving the data read.
> +
> +  @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> +  IN  UINT64                   StartAddress,
> +  IN  UINTN                    Size,
> +  OUT VOID                     *Buffer
> +  )
> +{
> +  UINTN                             ReturnValue;
> +
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> +  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> +
> +  if (Size == 0) {
> +    return Size;
> +  }
> +
> +  ASSERT (Buffer != NULL);
> +
> +  //
> +  // Save Size for return
> +  //
> +  ReturnValue = Size;
> +
> +  if ((StartAddress & BIT0) != 0) {
> +    //
> +    // Read a byte if StartAddress is byte aligned
> +    //
> +    *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> +    StartAddress += sizeof (UINT8);
> +    Size -= sizeof (UINT8);
> +    Buffer = (UINT8*)Buffer + 1;
> +  }
> +
> +  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> +    //
> +    // Read a word if StartAddress is word aligned
> +    //
> +    WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> +    StartAddress += sizeof (UINT16);
> +    Size -= sizeof (UINT16);
> +    Buffer = (UINT16*)Buffer + 1;
> +  }
> +
> +  while (Size >= sizeof (UINT32)) {
> +    //
> +    // Read as many double words as possible
> +    //
> +    WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> +    StartAddress += sizeof (UINT32);
> +    Size -= sizeof (UINT32);
> +    Buffer = (UINT32*)Buffer + 1;
> +  }
> +
> +  if (Size >= sizeof (UINT16)) {
> +    //
> +    // Read the last remaining word if exist
> +    //
> +    WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> +    StartAddress += sizeof (UINT16);
> +    Size -= sizeof (UINT16);
> +    Buffer = (UINT16*)Buffer + 1;
> +  }
> +
> +  if (Size >= sizeof (UINT8)) {
> +    //
> +    // Read the last remaining byte if exist
> +    //
> +    *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> +  }
> +
> +  return ReturnValue;
> +}
> +
> +
> +/**
> +  Copies the data in a caller supplied buffer to a specified range of PCI
> +  configuration space.
> +
> +  Writes the range of PCI configuration registers specified by StartAddress and
> +  Size from the buffer specified by Buffer. This function only allows the PCI
> +  configuration registers from a single PCI function to be written. Size is
> +  returned. When possible 32-bit PCI configuration write cycles are used to
> +  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> +  8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> +  and the end of the range.
> +
> +  If any reserved bits in StartAddress are set, then ASSERT().
> +  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> +  If Size > 0 and Buffer is NULL, then ASSERT().
> +
> +  @param  StartAddress  The starting address that encodes the PCI Segment, Bus,
> +                        Device, Function and Register.
> +  @param  Size          The size in bytes of the transfer.
> +  @param  Buffer        The pointer to a buffer containing the data to write.
> +
> +  @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> +  IN UINT64                    StartAddress,
> +  IN UINTN                     Size,
> +  IN VOID                      *Buffer
> +  )
> +{
> +  UINTN                             ReturnValue;
> +
> +  ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> +  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
> +
> +  if (Size == 0) {
> +    return 0;
> +  }
> +
> +  ASSERT (Buffer != NULL);
> +
> +  //
> +  // Save Size for return
> +  //
> +  ReturnValue = Size;
> +
> +  if ((StartAddress & BIT0) != 0) {
> +    //
> +    // Write a byte if StartAddress is byte aligned
> +    //
> +    PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> +    StartAddress += sizeof (UINT8);
> +    Size -= sizeof (UINT8);
> +    Buffer = (UINT8*)Buffer + 1;
> +  }
> +
> +  if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> +    //
> +    // Write a word if StartAddress is word aligned
> +    //
> +    PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> +    StartAddress += sizeof (UINT16);
> +    Size -= sizeof (UINT16);
> +    Buffer = (UINT16*)Buffer + 1;
> +  }
> +
> +  while (Size >= sizeof (UINT32)) {
> +    //
> +    // Write as many double words as possible
> +    //
> +    PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> +    StartAddress += sizeof (UINT32);
> +    Size -= sizeof (UINT32);
> +    Buffer = (UINT32*)Buffer + 1;
> +  }
> +
> +  if (Size >= sizeof (UINT16)) {
> +    //
> +    // Write the last remaining word if exist
> +    //
> +    PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> +    StartAddress += sizeof (UINT16);
> +    Size -= sizeof (UINT16);
> +    Buffer = (UINT16*)Buffer + 1;
> +  }
> +
> +  if (Size >= sizeof (UINT8)) {
> +    //
> +    // Write the last remaining byte if exist
> +    //
> +    PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> +  }
> +
> +  return ReturnValue;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
> new file mode 100644
> index 000000000000..e5f3ac494b32
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
> @@ -0,0 +1,35 @@
> +## @file
> +# PCI Segment Library for Synquacer SoC with multiple RCs
> +#
> +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution. The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php.
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010019
> +  BASE_NAME                      = SynquacerPciSegmentLib
> +  FILE_GUID                      = 1299f005-a30b-47d3-9003-24a91f100840
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = PciSegmentLib
> +
> +[Sources]
> +  PciSegmentLib.c
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  IoLib
> -- 
> 2.11.0
> 
_______________________________________________
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[edk2] [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support
Posted by Ard Biesheuvel, 2 weeks ago
Implement the glue library that exposes the PCIe root complexes to
the generic PCI host bridge driver. Since that driver is the first
one to access the PCI config space, put the low level init code for
the RCs into this library's constructor.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c            | 223 ++++++++++++
 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf          |  50 +++
 Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c | 383 ++++++++++++++++++++
 3 files changed, 656 insertions(+)

diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
new file mode 100644
index 000000000000..10ddaac3b924
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
@@ -0,0 +1,223 @@
+/** @file
+  PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Platform/Pcie.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#pragma pack(1)
+typedef struct {
+  ACPI_HID_DEVICE_PATH     AcpiDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+  {
+    {
+      {
+        ACPI_DEVICE_PATH,
+        ACPI_DP,
+        {
+          (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+          (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+        }
+      },
+      EISA_PNP_ID(0x0A08), // PCI Express
+      0
+    },
+
+    {
+      END_DEVICE_PATH_TYPE,
+      END_ENTIRE_DEVICE_PATH_SUBTYPE,
+      {
+        END_DEVICE_PATH_LENGTH,
+        0
+      }
+    }
+  },
+  {
+    {
+      {
+        ACPI_DEVICE_PATH,
+        ACPI_DP,
+        {
+          (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+          (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+        }
+      },
+      EISA_PNP_ID(0x0A08), // PCI Express
+      1
+    },
+
+    {
+      END_DEVICE_PATH_TYPE,
+      END_ENTIRE_DEVICE_PATH_SUBTYPE,
+      {
+        END_DEVICE_PATH_LENGTH,
+        0
+      }
+    }
+  }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+  L"Mem", L"I/O", L"Bus"
+};
+
+STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = {
+  {
+    0,                                      // Segment
+    0,                                      // Supports
+    0,                                      // Attributes
+    TRUE,                                   // DmaAbove4G
+    FALSE,                                  // NoExtendedConfigSpace
+    FALSE,                                  // ResourceAssigned
+    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,       // AllocationAttributes
+    { SYNQUACER_PCI_SEG0_BUSNUM_MIN,
+      SYNQUACER_PCI_SEG0_BUSNUM_MAX },      // Bus
+    { SYNQUACER_PCI_SEG0_PORTIO_MIN,
+      SYNQUACER_PCI_SEG0_PORTIO_MAX },      // Io
+    { SYNQUACER_PCI_SEG0_MMIO32_MIN,
+      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem
+    { SYNQUACER_PCI_SEG0_MMIO64_MIN,
+      SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G
+    { MAX_UINT64, 0x0 },                    // PMem
+    { MAX_UINT64, 0x0 },                    // PMemAbove4G
+    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
+  }, {
+    1,                                      // Segment
+    0,                                      // Supports
+    0,                                      // Attributes
+    TRUE,                                   // DmaAbove4G
+    FALSE,                                  // NoExtendedConfigSpace
+    FALSE,                                  // ResourceAssigned
+    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
+    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,       // AllocationAttributes
+    { SYNQUACER_PCI_SEG1_BUSNUM_MIN,
+      SYNQUACER_PCI_SEG1_BUSNUM_MAX },      // Bus
+    { SYNQUACER_PCI_SEG1_PORTIO_MIN,
+      SYNQUACER_PCI_SEG1_PORTIO_MAX },      // Io
+    { SYNQUACER_PCI_SEG1_MMIO32_MIN,
+      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem
+    { SYNQUACER_PCI_SEG1_MMIO64_MIN,
+      SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G
+    { MAX_UINT64, 0x0 },                    // PMem
+    { MAX_UINT64, 0x0 },                    // PMemAbove4G
+    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+  }
+};
+
+/**
+  Return all the root bridge instances in an array.
+
+  @param Count  Return the count of root bridge instances.
+
+  @return All the root bridge instances in an array.
+          The array should be passed into PciHostBridgeFreeRootBridges()
+          when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+  OUT UINTN     *Count
+  )
+{
+  *Count = ARRAY_SIZE (mPciRootBridges);
+
+  return mPciRootBridges;
+}
+
+/**
+  Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+  @param Bridges The root bridge instances array.
+  @param Count   The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+  PCI_ROOT_BRIDGE *Bridges,
+  UINTN           Count
+  )
+{
+}
+
+/**
+  Inform the platform that the resource conflict happens.
+
+  @param HostBridgeHandle Handle of the Host Bridge.
+  @param Configuration    Pointer to PCI I/O and PCI memory resource
+                          descriptors. The Configuration contains the resources
+                          for all the root bridges. The resource for each root
+                          bridge is terminated with END descriptor and an
+                          additional END is appended indicating the end of the
+                          entire resources. The resource descriptor field
+                          values follow the description in
+                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+                          .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+  EFI_HANDLE                        HostBridgeHandle,
+  VOID                              *Configuration
+  )
+{
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+  UINTN                             RootBridgeIndex;
+  DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+  RootBridgeIndex = 0;
+  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+    DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+      ASSERT (Descriptor->ResType <
+              (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+               sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+               )
+              );
+      DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+              Descriptor->AddrLen, Descriptor->AddrRangeMax
+              ));
+      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+        DEBUG ((DEBUG_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",
+                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+                ((Descriptor->SpecificFlag &
+                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+                  ) != 0) ? L" (Prefetchable)" : L""
+                ));
+      }
+    }
+    //
+    // Skip the END descriptor for root bridge
+    //
+    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+                   );
+  }
+}
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
new file mode 100644
index 000000000000..cfa9b2fc1c07
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
@@ -0,0 +1,50 @@
+## @file
+#  PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
+#
+#  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials are licensed and made available
+#  under the terms and conditions of the BSD License which accompanies this
+#  distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+#  IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = SynquacerPciHostBridgeLib
+  FILE_GUID                      = fdc92446-65bc-4f86-b4a0-014a2119a732
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PciHostBridgeLib|DXE_DRIVER
+  CONSTRUCTOR                    = SynquacerPciHostBridgeLibConstructor
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  SynquacerPciHostBridgeLib.c
+  SynquacerPciHostBridgeLibConstructor.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+  ArmLib
+  DebugLib
+  DevicePathLib
+  MemoryAllocationLib
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdPciIoTranslation
diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
new file mode 100644
index 000000000000..b3acca32070f
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
@@ -0,0 +1,383 @@
+/** @file
+  PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
+
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Platform/Pcie.h>
+
+#define IATU_VIEWPORT_OFF                                   0x900
+#define IATU_VIEWPORT_INBOUND                               BIT31
+#define IATU_VIEWPORT_OUTBOUND                              0
+#define IATU_VIEWPORT_REGION_INDEX(Idx)                     ((Idx) & 7)
+
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0                   0x904
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM          0x0
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO           0x2
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0         0x4
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1         0x5
+
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0                   0x908
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN         BIT31
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE    BIT28
+
+#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0                   0x90C
+#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0                 0x910
+#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0                      0x914
+#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0                 0x918
+#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0               0x91C
+
+#define CORE_CONTROL       0x000
+#define   APP_LTSSM_ENABLE    BIT4
+#define   DEVICE_TYPE         (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define AXI_CLK_STOP       0x004
+#define   DBI_ACLK_STOP       BIT8
+#define   SLV_ACLK_STOP       BIT4
+#define   MSTR_ACLK_STOP      BIT0
+#define   DBI_CSYSREQ_REG     BIT9
+#define   SLV_CSYSREQ_REG     BIT5
+#define   MSTR_CSYSREQ_REG    BIT1
+
+#define RESET_CONTROL_1    0x00C
+#define   PERST_N_O_REG       BIT5
+#define   PERST_N_I_REG       BIT4
+#define   BUTTON_RST_N_REG    BIT1
+#define   PWUP_RST_N_REG      BIT0
+
+#define RESET_CONTROL_2    0x010
+
+#define RESET_SELECT_1     0x014
+#define   SQU_RST_SEL         BIT29
+#define   PHY_RST_SEL         BIT28
+#define   PWR_RST_SEL         BIT24
+#define   STI_RST_SEL         BIT20
+#define   N_STI_RST_SEL       BIT16
+#define   CORE_RST_SEL        BIT12
+#define   PERST_SEL           BIT4
+#define   BUTTON_RST_SEL      BIT1
+#define   PWUP_RST_SEL        BIT0
+
+#define RESET_SELECT_2     0x018
+#define   DBI_ARST_SEL        BIT8
+#define   SLV_ARST_SEL        BIT4
+#define   MSTR_ARST_SEL       BIT0
+
+#define EM_CONTROL 0x030
+#define   PRE_DET_STT_REG     BIT4
+
+#define EM_SELECT 0x034
+#define   PRE_DET_STT_SEL     BIT4
+
+#define PM_CONTROL_2       0x050
+#define   SYS_AUX_PWR_DET     BIT8
+
+#define PHY_CONFIG_COM_6   0x114
+#define   PIPE_PORT_SEL       (BIT1 | BIT0)
+
+#define LINK_MONITOR       0x210
+#define   SMLH_LINK_UP        BIT0
+
+#define LINK_CAPABILITIES_REG 0x07C
+#define   PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4)
+#define   PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0)
+
+#define LINK_CONTROL_LINK_STATUS_REG 0x080
+#define   PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20)
+#define   PCIE_CAP_LINK_SPEED      (BIT19 | BIT18 | BIT17 | BIT16)
+
+#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
+#define   BASE_CLASS_CODE             0xFF000000
+#define     BASE_CLASS_CODE_VALUE       0x06
+#define   SUBCLASS_CODE               0x00FF0000
+#define     SUBCLASS_CODE_VALUE         0x04
+#define   PROGRAM_INTERFACE           0x0000FF00
+#define     PROGRAM_INTERFACE_VALUE     0x00
+
+#define MISC_CONTROL_1_OFF 0x8BC
+#define   DBI_RO_WR_EN       BIT0
+
+STATIC
+VOID
+ConfigureWindow (
+  IN  EFI_PHYSICAL_ADDRESS    DbiBase,
+  IN  UINTN                   Index,
+  IN  UINT64                  CpuBase,
+  IN  UINT64                  PciBase,
+  IN  UINT64                  Size,
+  IN  UINTN                   Type,
+  IN  UINTN                   EnableFlags
+  )
+{
+  ArmDataMemoryBarrier ();
+
+  MmioWrite32 (DbiBase + IATU_VIEWPORT_OFF,
+               IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index));
+
+  ArmDataMemoryBarrier ();
+
+  MmioWrite32 (DbiBase + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
+               (UINT32)(CpuBase & 0xFFFFFFFF));
+  MmioWrite32 (DbiBase + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
+               (UINT32)(CpuBase >> 32));
+  MmioWrite32 (DbiBase + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
+               (UINT32)(CpuBase + Size - 1));
+  MmioWrite32 (DbiBase + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
+               (UINT32)(PciBase & 0xFFFFFFFF));
+  MmioWrite32 (DbiBase + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
+               (UINT32)(PciBase >> 32));
+  MmioWrite32 (DbiBase + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
+               Type);
+  MmioWrite32 (DbiBase + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
+               IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags);
+}
+
+STATIC
+VOID
+SnPcieSetData (
+  EFI_PHYSICAL_ADDRESS  Base,
+  UINT32                Offset,
+  UINT32                Mask,
+  UINT32                In
+  )
+{
+  UINT32 Data;
+  UINT32 Shift;
+
+  Shift = 1;
+  if (In) {
+    while (!(Mask & Shift))
+      Shift <<= 1;
+    Data = (MmioRead32 (Base + Offset) & ~Mask) | (In * Shift);
+  } else {
+    Data = MmioRead32 (Base + Offset) & ~Mask;
+  }
+
+  MmioWrite32 (Base + Offset, Data);
+}
+
+STATIC
+UINT32
+SnPcieReadData (
+  EFI_PHYSICAL_ADDRESS  Base,
+  UINT32                Offset,
+  UINT32                Mask
+  )
+{
+  UINT32 Shift;
+
+  Shift = 0;
+  while (!(Mask & 1)) {
+    Mask >>= 1;
+    Shift++;
+  }
+
+  return (MmioRead32 (Base + Offset) >> Shift) & Mask;
+}
+
+STATIC
+VOID
+SnDbiRoWrEn (
+  IN  EFI_PHYSICAL_ADDRESS    DbiBase,
+  IN  INTN                    MaxLinkWidth,
+  IN  INTN                    MaxLinkSpeed
+  )
+{
+  SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
+
+  SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_WIDTH, MaxLinkWidth);
+  SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_SPEED, MaxLinkSpeed);
+
+  SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
+  SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
+  SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
+
+  SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
+}
+
+STATIC
+VOID
+PciInitController (
+  IN  EFI_PHYSICAL_ADDRESS    ExsBase,
+  IN  EFI_PHYSICAL_ADDRESS    DbiBase,
+  IN  EFI_PHYSICAL_ADDRESS    ConfigBase,
+  IN  CONST PCI_ROOT_BRIDGE   *RootBridge
+  )
+{
+  SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0);
+  SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 0);
+  SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 1);
+
+  // 1: Assert all PHY / LINK resets
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , PERST_SEL     , 0);
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG , 0);
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG , 0);
+
+  // Device Reset(PERST#) is effective afrer Set device_type (RC)
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , PWUP_RST_SEL  , 0);
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , BUTTON_RST_SEL  , 0);
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , PWR_RST_SEL     , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_2 , MSTR_ARST_SEL   , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_2 , SLV_ARST_SEL    , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_2 , DBI_ARST_SEL    , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , CORE_RST_SEL    , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , STI_RST_SEL     , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , N_STI_RST_SEL   , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , SQU_RST_SEL     , 1);
+  SnPcieSetData (ExsBase, RESET_SELECT_1 , PHY_RST_SEL     , 1);
+
+  // 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup.
+  SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
+
+  // 3: Set device_type (RC)
+  SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4);
+
+  // 4: Set Bifurcation  1=disable  4=able
+  // 5: Supply Reference (It has executed)
+  // 6: Wait for 10usec (Reference Clocks is stable)
+  // 7 De assert PERST# */
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG, 1);
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG, 1);
+
+  // 8 Assert SYS_AUX_PWR_DET
+  SnPcieSetData(ExsBase, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
+
+  // 9 Supply following clocks
+  SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
+  SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
+  SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
+  SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
+  SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
+  SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
+
+  // 10 De assert PHY reset
+  // 11 De assert LINK's PMC reset
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
+  SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
+  // 12 PHY auto
+  // 13 Wrapper auto
+  // 14-17 PHY auto
+  // 18 Wrapper auto
+  // 19 Update registers through DBI AXI Slave interface
+  SnDbiRoWrEn (DbiBase, 4 /* lanes */, /* Gen */ 2);
+
+  //
+  // ECAM shift mode uses bits [27:12] of the untranslated address as
+  // B/D/F identifiers. This only works as expected if the base of the
+  // region is aligned to 256 MB, or the effective bus numbers will be
+  // out of sync with the bus base and limit values we chose.
+  //
+  ASSERT ((ConfigBase % SIZE_256MB) == RootBridge->Bus.Base * SIZE_1MB);
+
+  MmioOr32 (DbiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE |
+                                          EFI_PCI_COMMAND_MEMORY_SPACE |
+                                          EFI_PCI_COMMAND_BUS_MASTER);
+
+  // Region 0: MMIO32 range
+  ConfigureWindow (DbiBase, 0,
+    RootBridge->Mem.Base,
+    RootBridge->Mem.Base,
+    RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
+    0);
+
+  // Region 1: Type 0 config space
+  ConfigureWindow (DbiBase, 1,
+    ConfigBase + RootBridge->Bus.Base * SIZE_1MB,
+    0x0,
+    SIZE_64KB,
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
+    IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+  // Region 2: Type 1 config space
+  ConfigureWindow (DbiBase, 2,
+    ConfigBase + RootBridge->Bus.Base * SIZE_1MB + SIZE_64KB,
+    0x0,
+    (RootBridge->Bus.Limit - RootBridge->Bus.Base + 1) * SIZE_1MB - SIZE_64KB,
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
+    IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
+
+  // Region 3: port I/O range
+  ConfigureWindow (DbiBase, 3,
+    FixedPcdGet32 (PcdPciIoTranslation) + RootBridge->Io.Base,
+    RootBridge->Io.Base,
+    RootBridge->Io.Limit - RootBridge->Io.Base + 1,
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
+    0);
+
+  // Region 4: MMIO64 range
+  ConfigureWindow (DbiBase, 4,
+    RootBridge->MemAbove4G.Base,
+    RootBridge->MemAbove4G.Base,
+    RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1,
+    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
+    0);
+
+  // enable link
+  if (SnPcieReadData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) {
+    SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
+  }
+}
+
+STATIC CONST struct {
+  EFI_PHYSICAL_ADDRESS      DbiBase;
+  EFI_PHYSICAL_ADDRESS      ExsBase;
+  EFI_PHYSICAL_ADDRESS      ConfigBase;
+} mBaseAddresses [] = {
+  {
+    SYNQUACER_PCI_SEG0_DBI_BASE,
+    SYNQUACER_PCI_SEG0_EXS_BASE,
+    SYNQUACER_PCI_SEG0_CONFIG_BASE
+  },
+  {
+    SYNQUACER_PCI_SEG1_DBI_BASE,
+    SYNQUACER_PCI_SEG1_EXS_BASE,
+    SYNQUACER_PCI_SEG1_CONFIG_BASE
+  },
+};
+
+
+EFI_STATUS
+EFIAPI
+SynquacerPciHostBridgeLibConstructor (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  PCI_ROOT_BRIDGE     *RootBridges;
+  UINTN               Count;
+  UINTN               Idx;
+
+  RootBridges = PciHostBridgeGetRootBridges (&Count);
+  ASSERT (Count == ARRAY_SIZE(mBaseAddresses));
+  if (Count != ARRAY_SIZE(mBaseAddresses)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  for (Idx = 0; Idx < Count; Idx++) {
+    PciInitController (mBaseAddresses[Idx].ExsBase,
+                       mBaseAddresses[Idx].DbiBase,
+                       mBaseAddresses[Idx].ConfigBase,
+                       &RootBridges[Idx]);
+  }
+
+  return EFI_SUCCESS;
+}
+
-- 
2.11.0

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Re: [edk2] [PATCH edk2-platforms 05/14] Silicon/Synquacer: implement PciHostBridgeLib support
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:06PM +0100, Ard Biesheuvel wrote:
> Implement the glue library that exposes the PCIe root complexes to
> the generic PCI host bridge driver. Since that driver is the first
> one to access the PCI config space, put the low level init code for
> the RCs into this library's constructor.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c            | 223 ++++++++++++
>  Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf          |  50 +++
>  Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c | 383 ++++++++++++++++++++
>  3 files changed, 656 insertions(+)
> 
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
> new file mode 100644
> index 000000000000..10ddaac3b924
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.c
> @@ -0,0 +1,223 @@
> +/** @file
> +  PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
> +
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> +  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Platform/Pcie.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>

The above is well enough sorted that I'd let it slip, but it isn't
flawless.

> +
> +#pragma pack(1)
> +typedef struct {
> +  ACPI_HID_DEVICE_PATH     AcpiDevicePath;
> +  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> +  {
> +    {
> +      {
> +        ACPI_DEVICE_PATH,
> +        ACPI_DP,
> +        {
> +          (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> +          (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)

Shift the spaces after (UINT8) to after sizeof?

> +        }
> +      },
> +      EISA_PNP_ID(0x0A08), // PCI Express

Space before (?

Why don't we have that 0x0a08 in a central header?

> +      0
> +    },
> +
> +    {
> +      END_DEVICE_PATH_TYPE,
> +      END_ENTIRE_DEVICE_PATH_SUBTYPE,
> +      {
> +        END_DEVICE_PATH_LENGTH,
> +        0
> +      }
> +    }
> +  },
> +  {
> +    {
> +      {
> +        ACPI_DEVICE_PATH,
> +        ACPI_DP,
> +        {
> +          (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> +          (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)

Shift the spaces after (UINT8) to after sizeof?

> +        }
> +      },
> +      EISA_PNP_ID(0x0A08), // PCI Express

Same as above.

> +      1
> +    },
> +
> +    {
> +      END_DEVICE_PATH_TYPE,
> +      END_ENTIRE_DEVICE_PATH_SUBTYPE,
> +      {
> +        END_DEVICE_PATH_LENGTH,
> +        0
> +      }
> +    }
> +  }
> +};
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> +  L"Mem", L"I/O", L"Bus"
> +};
> +
> +STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = {
> +  {
> +    0,                                      // Segment
> +    0,                                      // Supports
> +    0,                                      // Attributes
> +    TRUE,                                   // DmaAbove4G
> +    FALSE,                                  // NoExtendedConfigSpace
> +    FALSE,                                  // ResourceAssigned
> +    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
> +    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,       // AllocationAttributes
> +    { SYNQUACER_PCI_SEG0_BUSNUM_MIN,
> +      SYNQUACER_PCI_SEG0_BUSNUM_MAX },      // Bus
> +    { SYNQUACER_PCI_SEG0_PORTIO_MIN,
> +      SYNQUACER_PCI_SEG0_PORTIO_MAX },      // Io
> +    { SYNQUACER_PCI_SEG0_MMIO32_MIN,
> +      SYNQUACER_PCI_SEG0_MMIO32_MAX },      // Mem
> +    { SYNQUACER_PCI_SEG0_MMIO64_MIN,
> +      SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G
> +    { MAX_UINT64, 0x0 },                    // PMem
> +    { MAX_UINT64, 0x0 },                    // PMemAbove4G
> +    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> +  }, {
> +    1,                                      // Segment
> +    0,                                      // Supports
> +    0,                                      // Attributes
> +    TRUE,                                   // DmaAbove4G
> +    FALSE,                                  // NoExtendedConfigSpace
> +    FALSE,                                  // ResourceAssigned
> +    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
> +    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,       // AllocationAttributes
> +    { SYNQUACER_PCI_SEG1_BUSNUM_MIN,
> +      SYNQUACER_PCI_SEG1_BUSNUM_MAX },      // Bus
> +    { SYNQUACER_PCI_SEG1_PORTIO_MIN,
> +      SYNQUACER_PCI_SEG1_PORTIO_MAX },      // Io
> +    { SYNQUACER_PCI_SEG1_MMIO32_MIN,
> +      SYNQUACER_PCI_SEG1_MMIO32_MAX },      // Mem
> +    { SYNQUACER_PCI_SEG1_MMIO64_MIN,
> +      SYNQUACER_PCI_SEG1_MMIO64_MAX },      // MemAbove4G
> +    { MAX_UINT64, 0x0 },                    // PMem
> +    { MAX_UINT64, 0x0 },                    // PMemAbove4G
> +    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> +  }
> +};
> +
> +/**
> +  Return all the root bridge instances in an array.
> +
> +  @param Count  Return the count of root bridge instances.
> +
> +  @return All the root bridge instances in an array.
> +          The array should be passed into PciHostBridgeFreeRootBridges()
> +          when it's not used.
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> +  OUT UINTN     *Count
> +  )
> +{
> +  *Count = ARRAY_SIZE (mPciRootBridges);
> +
> +  return mPciRootBridges;
> +}
> +
> +/**
> +  Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> +  @param Bridges The root bridge instances array.
> +  @param Count   The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> +  PCI_ROOT_BRIDGE *Bridges,
> +  UINTN           Count
> +  )
> +{
> +}
> +
> +/**
> +  Inform the platform that the resource conflict happens.
> +
> +  @param HostBridgeHandle Handle of the Host Bridge.
> +  @param Configuration    Pointer to PCI I/O and PCI memory resource
> +                          descriptors. The Configuration contains the resources
> +                          for all the root bridges. The resource for each root
> +                          bridge is terminated with END descriptor and an
> +                          additional END is appended indicating the end of the
> +                          entire resources. The resource descriptor field
> +                          values follow the description in
> +                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> +                          .SubmitResources().
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> +  EFI_HANDLE                        HostBridgeHandle,
> +  VOID                              *Configuration
> +  )
> +{
> +  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> +  UINTN                             RootBridgeIndex;
> +  DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> +  RootBridgeIndex = 0;
> +  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> +  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> +    DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> +    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> +      ASSERT (Descriptor->ResType <
> +              (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
> +               sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
> +               )
> +              );

Replace with ARRAY_SIZE?

> +      DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> +              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> +              Descriptor->AddrLen, Descriptor->AddrRangeMax
> +              ));
> +      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> +        DEBUG ((DEBUG_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",
> +                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> +                ((Descriptor->SpecificFlag &
> +                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> +                  ) != 0) ? L" (Prefetchable)" : L""
> +                ));
> +      }
> +    }
> +    //
> +    // Skip the END descriptor for root bridge
> +    //
> +    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> +    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> +                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> +                   );
> +  }
> +}
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
> new file mode 100644
> index 000000000000..cfa9b2fc1c07
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
> @@ -0,0 +1,50 @@
> +## @file
> +#  PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
> +#
> +#  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +#  This program and the accompanying materials are licensed and made available
> +#  under the terms and conditions of the BSD License which accompanies this
> +#  distribution. The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +#  IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010019
> +  BASE_NAME                      = SynquacerPciHostBridgeLib
> +  FILE_GUID                      = fdc92446-65bc-4f86-b4a0-014a2119a732
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = PciHostBridgeLib|DXE_DRIVER
> +  CONSTRUCTOR                    = SynquacerPciHostBridgeLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the build
> +# tools.
> +#
> +#  VALID_ARCHITECTURES           = AARCH64

Do we only have AArch64 support for this specific component?

> +#
> +
> +[Sources]
> +  SynquacerPciHostBridgeLib.c
> +  SynquacerPciHostBridgeLibConstructor.c
> +
> +[Packages]
> +  ArmPkg/ArmPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> +  ArmLib
> +  DebugLib
> +  DevicePathLib
> +  MemoryAllocationLib
> +
> +[FixedPcd]
> +  gArmTokenSpaceGuid.PcdPciIoTranslation
> diff --git a/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
> new file mode 100644
> index 000000000000..b3acca32070f
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLibConstructor.c
> @@ -0,0 +1,383 @@
> +/** @file
> +  PCI Host Bridge Library instance for Socionext Synquacer ARM SOC
> +
> +  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials are licensed and made available
> +  under the terms and conditions of the BSD License which accompanies this
> +  distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php.
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> +  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/ArmLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Platform/Pcie.h>
> +
> +#define IATU_VIEWPORT_OFF                                   0x900
> +#define IATU_VIEWPORT_INBOUND                               BIT31
> +#define IATU_VIEWPORT_OUTBOUND                              0
> +#define IATU_VIEWPORT_REGION_INDEX(Idx)                     ((Idx) & 7)
> +
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0                   0x904
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM          0x0
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO           0x2
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0         0x4
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1         0x5
> +
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0                   0x908
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN         BIT31
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE    BIT28
> +
> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0                   0x90C
> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0                 0x910
> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0                      0x914
> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0                 0x918
> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0               0x91C
> +
> +#define CORE_CONTROL       0x000
> +#define   APP_LTSSM_ENABLE    BIT4
> +#define   DEVICE_TYPE         (BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define AXI_CLK_STOP       0x004
> +#define   DBI_ACLK_STOP       BIT8
> +#define   SLV_ACLK_STOP       BIT4
> +#define   MSTR_ACLK_STOP      BIT0
> +#define   DBI_CSYSREQ_REG     BIT9
> +#define   SLV_CSYSREQ_REG     BIT5
> +#define   MSTR_CSYSREQ_REG    BIT1
> +
> +#define RESET_CONTROL_1    0x00C
> +#define   PERST_N_O_REG       BIT5
> +#define   PERST_N_I_REG       BIT4
> +#define   BUTTON_RST_N_REG    BIT1
> +#define   PWUP_RST_N_REG      BIT0
> +
> +#define RESET_CONTROL_2    0x010
> +
> +#define RESET_SELECT_1     0x014
> +#define   SQU_RST_SEL         BIT29
> +#define   PHY_RST_SEL         BIT28
> +#define   PWR_RST_SEL         BIT24
> +#define   STI_RST_SEL         BIT20
> +#define   N_STI_RST_SEL       BIT16
> +#define   CORE_RST_SEL        BIT12
> +#define   PERST_SEL           BIT4
> +#define   BUTTON_RST_SEL      BIT1
> +#define   PWUP_RST_SEL        BIT0
> +
> +#define RESET_SELECT_2     0x018
> +#define   DBI_ARST_SEL        BIT8
> +#define   SLV_ARST_SEL        BIT4
> +#define   MSTR_ARST_SEL       BIT0
> +
> +#define EM_CONTROL 0x030
> +#define   PRE_DET_STT_REG     BIT4
> +
> +#define EM_SELECT 0x034
> +#define   PRE_DET_STT_SEL     BIT4
> +
> +#define PM_CONTROL_2       0x050
> +#define   SYS_AUX_PWR_DET     BIT8
> +
> +#define PHY_CONFIG_COM_6   0x114
> +#define   PIPE_PORT_SEL       (BIT1 | BIT0)
> +
> +#define LINK_MONITOR       0x210
> +#define   SMLH_LINK_UP        BIT0
> +
> +#define LINK_CAPABILITIES_REG 0x07C
> +#define   PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4)
> +#define   PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define LINK_CONTROL_LINK_STATUS_REG 0x080
> +#define   PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20)
> +#define   PCIE_CAP_LINK_SPEED      (BIT19 | BIT18 | BIT17 | BIT16)
> +
> +#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
> +#define   BASE_CLASS_CODE             0xFF000000
> +#define     BASE_CLASS_CODE_VALUE       0x06
> +#define   SUBCLASS_CODE               0x00FF0000
> +#define     SUBCLASS_CODE_VALUE         0x04
> +#define   PROGRAM_INTERFACE           0x0000FF00
> +#define     PROGRAM_INTERFACE_VALUE     0x00
> +
> +#define MISC_CONTROL_1_OFF 0x8BC
> +#define   DBI_RO_WR_EN       BIT0
> +
> +STATIC
> +VOID
> +ConfigureWindow (
> +  IN  EFI_PHYSICAL_ADDRESS    DbiBase,
> +  IN  UINTN                   Index,
> +  IN  UINT64                  CpuBase,
> +  IN  UINT64                  PciBase,
> +  IN  UINT64                  Size,
> +  IN  UINTN                   Type,
> +  IN  UINTN                   EnableFlags
> +  )
> +{
> +  ArmDataMemoryBarrier ();
> +
> +  MmioWrite32 (DbiBase + IATU_VIEWPORT_OFF,
> +               IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index));
> +
> +  ArmDataMemoryBarrier ();
> +
> +  MmioWrite32 (DbiBase + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> +               (UINT32)(CpuBase & 0xFFFFFFFF));
> +  MmioWrite32 (DbiBase + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> +               (UINT32)(CpuBase >> 32));
> +  MmioWrite32 (DbiBase + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> +               (UINT32)(CpuBase + Size - 1));
> +  MmioWrite32 (DbiBase + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> +               (UINT32)(PciBase & 0xFFFFFFFF));
> +  MmioWrite32 (DbiBase + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> +               (UINT32)(PciBase >> 32));
> +  MmioWrite32 (DbiBase + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> +               Type);
> +  MmioWrite32 (DbiBase + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> +               IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags);

No barrier needed here?

> +}
> +
> +STATIC
> +VOID
> +SnPcieSetData (
> +  EFI_PHYSICAL_ADDRESS  Base,
> +  UINT32                Offset,
> +  UINT32                Mask,
> +  UINT32                In
> +  )
> +{
> +  UINT32 Data;
> +  UINT32 Shift;
> +
> +  Shift = 1;
> +  if (In) {
> +    while (!(Mask & Shift))

                               {

> +      Shift <<= 1;

       }

/
    Leif

> +    Data = (MmioRead32 (Base + Offset) & ~Mask) | (In * Shift);
> +  } else {
> +    Data = MmioRead32 (Base + Offset) & ~Mask;
> +  }
> +
> +  MmioWrite32 (Base + Offset, Data);
> +}
> +
> +STATIC
> +UINT32
> +SnPcieReadData (
> +  EFI_PHYSICAL_ADDRESS  Base,
> +  UINT32                Offset,
> +  UINT32                Mask
> +  )
> +{
> +  UINT32 Shift;
> +
> +  Shift = 0;
> +  while (!(Mask & 1)) {
> +    Mask >>= 1;
> +    Shift++;
> +  }
> +
> +  return (MmioRead32 (Base + Offset) >> Shift) & Mask;
> +}
> +
> +STATIC
> +VOID
> +SnDbiRoWrEn (
> +  IN  EFI_PHYSICAL_ADDRESS    DbiBase,
> +  IN  INTN                    MaxLinkWidth,
> +  IN  INTN                    MaxLinkSpeed
> +  )
> +{
> +  SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
> +
> +  SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_WIDTH, MaxLinkWidth);
> +  SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_SPEED, MaxLinkSpeed);
> +
> +  SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
> +  SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
> +  SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
> +
> +  SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
> +}
> +
> +STATIC
> +VOID
> +PciInitController (
> +  IN  EFI_PHYSICAL_ADDRESS    ExsBase,
> +  IN  EFI_PHYSICAL_ADDRESS    DbiBase,
> +  IN  EFI_PHYSICAL_ADDRESS    ConfigBase,
> +  IN  CONST PCI_ROOT_BRIDGE   *RootBridge
> +  )
> +{
> +  SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0);
> +  SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 0);
> +  SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 1);
> +
> +  // 1: Assert all PHY / LINK resets
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , PERST_SEL     , 0);
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG , 0);
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG , 0);
> +
> +  // Device Reset(PERST#) is effective afrer Set device_type (RC)
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , PWUP_RST_SEL  , 0);
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , BUTTON_RST_SEL  , 0);
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , PWR_RST_SEL     , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_2 , MSTR_ARST_SEL   , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_2 , SLV_ARST_SEL    , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_2 , DBI_ARST_SEL    , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , CORE_RST_SEL    , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , STI_RST_SEL     , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , N_STI_RST_SEL   , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , SQU_RST_SEL     , 1);
> +  SnPcieSetData (ExsBase, RESET_SELECT_1 , PHY_RST_SEL     , 1);
> +
> +  // 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup.
> +  SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
> +
> +  // 3: Set device_type (RC)
> +  SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4);
> +
> +  // 4: Set Bifurcation  1=disable  4=able
> +  // 5: Supply Reference (It has executed)
> +  // 6: Wait for 10usec (Reference Clocks is stable)
> +  // 7 De assert PERST# */
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG, 1);
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG, 1);
> +
> +  // 8 Assert SYS_AUX_PWR_DET
> +  SnPcieSetData(ExsBase, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
> +
> +  // 9 Supply following clocks
> +  SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
> +  SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
> +  SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
> +  SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
> +  SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
> +  SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
> +
> +  // 10 De assert PHY reset
> +  // 11 De assert LINK's PMC reset
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
> +  SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
> +  // 12 PHY auto
> +  // 13 Wrapper auto
> +  // 14-17 PHY auto
> +  // 18 Wrapper auto
> +  // 19 Update registers through DBI AXI Slave interface
> +  SnDbiRoWrEn (DbiBase, 4 /* lanes */, /* Gen */ 2);
> +
> +  //
> +  // ECAM shift mode uses bits [27:12] of the untranslated address as
> +  // B/D/F identifiers. This only works as expected if the base of the
> +  // region is aligned to 256 MB, or the effective bus numbers will be
> +  // out of sync with the bus base and limit values we chose.
> +  //
> +  ASSERT ((ConfigBase % SIZE_256MB) == RootBridge->Bus.Base * SIZE_1MB);
> +
> +  MmioOr32 (DbiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE |
> +                                          EFI_PCI_COMMAND_MEMORY_SPACE |
> +                                          EFI_PCI_COMMAND_BUS_MASTER);
> +
> +  // Region 0: MMIO32 range
> +  ConfigureWindow (DbiBase, 0,
> +    RootBridge->Mem.Base,
> +    RootBridge->Mem.Base,
> +    RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
> +    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> +    0);
> +
> +  // Region 1: Type 0 config space
> +  ConfigureWindow (DbiBase, 1,
> +    ConfigBase + RootBridge->Bus.Base * SIZE_1MB,
> +    0x0,
> +    SIZE_64KB,
> +    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> +    IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
> +
> +  // Region 2: Type 1 config space
> +  ConfigureWindow (DbiBase, 2,
> +    ConfigBase + RootBridge->Bus.Base * SIZE_1MB + SIZE_64KB,
> +    0x0,
> +    (RootBridge->Bus.Limit - RootBridge->Bus.Base + 1) * SIZE_1MB - SIZE_64KB,
> +    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> +    IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
> +
> +  // Region 3: port I/O range
> +  ConfigureWindow (DbiBase, 3,
> +    FixedPcdGet32 (PcdPciIoTranslation) + RootBridge->Io.Base,
> +    RootBridge->Io.Base,
> +    RootBridge->Io.Limit - RootBridge->Io.Base + 1,
> +    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> +    0);
> +
> +  // Region 4: MMIO64 range
> +  ConfigureWindow (DbiBase, 4,
> +    RootBridge->MemAbove4G.Base,
> +    RootBridge->MemAbove4G.Base,
> +    RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1,
> +    IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> +    0);
> +
> +  // enable link
> +  if (SnPcieReadData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) {
> +    SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
> +  }
> +}
> +
> +STATIC CONST struct {
> +  EFI_PHYSICAL_ADDRESS      DbiBase;
> +  EFI_PHYSICAL_ADDRESS      ExsBase;
> +  EFI_PHYSICAL_ADDRESS      ConfigBase;
> +} mBaseAddresses [] = {
> +  {
> +    SYNQUACER_PCI_SEG0_DBI_BASE,
> +    SYNQUACER_PCI_SEG0_EXS_BASE,
> +    SYNQUACER_PCI_SEG0_CONFIG_BASE
> +  },
> +  {
> +    SYNQUACER_PCI_SEG1_DBI_BASE,
> +    SYNQUACER_PCI_SEG1_EXS_BASE,
> +    SYNQUACER_PCI_SEG1_CONFIG_BASE
> +  },
> +};
> +
> +
> +EFI_STATUS
> +EFIAPI
> +SynquacerPciHostBridgeLibConstructor (
> +  IN EFI_HANDLE       ImageHandle,
> +  IN EFI_SYSTEM_TABLE *SystemTable
> +  )
> +{
> +  PCI_ROOT_BRIDGE     *RootBridges;
> +  UINTN               Count;
> +  UINTN               Idx;
> +
> +  RootBridges = PciHostBridgeGetRootBridges (&Count);
> +  ASSERT (Count == ARRAY_SIZE(mBaseAddresses));
> +  if (Count != ARRAY_SIZE(mBaseAddresses)) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  for (Idx = 0; Idx < Count; Idx++) {
> +    PciInitController (mBaseAddresses[Idx].ExsBase,
> +                       mBaseAddresses[Idx].DbiBase,
> +                       mBaseAddresses[Idx].ConfigBase,
> +                       &RootBridges[Idx]);
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> +
> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL
Posted by Ard Biesheuvel, 2 weeks ago
The Synquacer SOC has two separate PCIe RCs, which means there is
no single value for the translation offset between I/O port accesses
and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
that takes the two disjoint I/O windows into account.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c   | 588 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf |  50 ++
 2 files changed, 638 insertions(+)

diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
new file mode 100644
index 000000000000..8591a251aea3
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
@@ -0,0 +1,588 @@
+/** @file
+  Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Platform/Pcie.h>
+#include <Protocol/CpuIo2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_IO_PORT_ADDRESS   SYNQUACER_PCI_SEG1_PORTIO_MAX
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE  mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  0, // EfiCpuIoWidthFifoUint8
+  0, // EfiCpuIoWidthFifoUint16
+  0, // EfiCpuIoWidthFifoUint32
+  0, // EfiCpuIoWidthFifoUint64
+  1, // EfiCpuIoWidthFillUint8
+  2, // EfiCpuIoWidthFillUint16
+  4, // EfiCpuIoWidthFillUint32
+  8  // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  1, // EfiCpuIoWidthFifoUint8
+  2, // EfiCpuIoWidthFifoUint16
+  4, // EfiCpuIoWidthFifoUint32
+  8, // EfiCpuIoWidthFifoUint64
+  0, // EfiCpuIoWidthFillUint8
+  0, // EfiCpuIoWidthFillUint16
+  0, // EfiCpuIoWidthFillUint32
+  0  // EfiCpuIoWidthFillUint64
+};
+
+/**
+  Check parameters to a CPU I/O 2 Protocol service request.
+
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port operation.
+  @param[in] Width          Signifies the width of the I/O or Memory operation.
+  @param[in] Address        The base address of the I/O operation.
+  @param[in] Count          The number of I/O operations to perform. The number of
+                            bytes moved is Width size * Count, starting at Address.
+  @param[in] Buffer         For read operations, the destination buffer to store the results.
+                            For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The parameters for this request pass the checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+  IN BOOLEAN                    MmioOperation,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                     Address,
+  IN UINTN                      Count,
+  IN VOID                       *Buffer
+  )
+{
+  UINT64  MaxCount;
+  UINT64  Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Count as 1
+  //
+  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+    Count = 1;
+  }
+
+  //
+  // Check to see if Width is in the valid range for I/O Port operations
+  //
+  Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Address is aligned
+  //
+  if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+    ASSERT (FALSE);
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Check to see if any address associated with this transfer exceeds the maximum
+  // allowed address.  The maximum address implied by the parameters passed in is
+  // Address + Size * Count.  If the following condition is met, then the transfer
+  // is not supported.
+  //
+  //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+  //
+  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+  // can also be the maximum integer value supported by the CPU, this range
+  // check must be adjusted to avoid all oveflow conditions.
+  //
+  // The following form of the range check is equivalent but assumes that
+  // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+  //
+  Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+  if (Count == 0) {
+    if (Address > Limit) {
+      ASSERT (FALSE);
+      return EFI_UNSUPPORTED;
+    }
+  } else {
+    MaxCount = RShiftU64 (Limit, Width);
+    if (MaxCount < (Count - 1)) {
+      ASSERT (FALSE);
+      return EFI_UNSUPPORTED;
+    }
+    if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+      ASSERT (FALSE);
+      return EFI_UNSUPPORTED;
+    }
+  }
+
+  //
+  // Check to see if Buffer is aligned
+  //
+  if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width])  - 1))) != 0) {
+    ASSERT (FALSE);
+    return EFI_UNSUPPORTED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Reads memory-mapped registers.
+
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+  each of the Count operations that is performed.
+
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times on the same Address.
+
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times from the first element of Buffer.
+
+  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+  @param[in]  Width    Signifies the width of the I/O or Memory operation.
+  @param[in]  Address  The base address of the I/O operation.
+  @param[in]  Count    The number of I/O operations to perform. The number of
+                       bytes moved is Width size * Count, starting at Address.
+  @param[out] Buffer   For read operations, the destination buffer to store the results.
+                       For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the PI system.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+  IN  EFI_CPU_IO2_PROTOCOL       *This,
+  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                     Address,
+  IN  UINTN                      Count,
+  OUT VOID                       *Buffer
+  )
+{
+  EFI_STATUS                 Status;
+  UINT8                      InStride;
+  UINT8                      OutStride;
+  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                      *Uint8Buffer;
+
+  Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Select loop based on the width of the transfer
+  //
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (OperationWidth == EfiCpuIoWidthUint8) {
+      *Uint8Buffer = MmioRead8 ((UINTN)Address);
+    } else if (OperationWidth == EfiCpuIoWidthUint16) {
+      *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+    } else if (OperationWidth == EfiCpuIoWidthUint32) {
+      *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+    } else if (OperationWidth == EfiCpuIoWidthUint64) {
+      *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Writes memory-mapped registers.
+
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+  each of the Count operations that is performed.
+
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times on the same Address.
+
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times from the first element of Buffer.
+
+  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+  @param[in]  Width    Signifies the width of the I/O or Memory operation.
+  @param[in]  Address  The base address of the I/O operation.
+  @param[in]  Count    The number of I/O operations to perform. The number of
+                       bytes moved is Width size * Count, starting at Address.
+  @param[in]  Buffer   For read operations, the destination buffer to store the results.
+                       For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the PI system.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+  IN EFI_CPU_IO2_PROTOCOL       *This,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                     Address,
+  IN UINTN                      Count,
+  IN VOID                       *Buffer
+  )
+{
+  EFI_STATUS                 Status;
+  UINT8                      InStride;
+  UINT8                      OutStride;
+  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                      *Uint8Buffer;
+
+  Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  //
+  // Select loop based on the width of the transfer
+  //
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (OperationWidth == EfiCpuIoWidthUint8) {
+      MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+    } else if (OperationWidth == EfiCpuIoWidthUint16) {
+      MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+    } else if (OperationWidth == EfiCpuIoWidthUint32) {
+      MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+    } else if (OperationWidth == EfiCpuIoWidthUint64) {
+      MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+    }
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Reads I/O registers.
+
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+  each of the Count operations that is performed.
+
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times on the same Address.
+
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times from the first element of Buffer.
+
+  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+  @param[in]  Width    Signifies the width of the I/O or Memory operation.
+  @param[in]  Address  The base address of the I/O operation.
+  @param[in]  Count    The number of I/O operations to perform. The number of
+                       bytes moved is Width size * Count, starting at Address.
+  @param[out] Buffer   For read operations, the destination buffer to store the results.
+                       For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the PI system.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+  IN  EFI_CPU_IO2_PROTOCOL       *This,
+  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN  UINT64                     Address,
+  IN  UINTN                      Count,
+  OUT VOID                       *Buffer
+  )
+{
+  EFI_STATUS                 Status;
+  UINT8                      InStride;
+  UINT8                      OutStride;
+  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                      *Uint8Buffer;
+
+  Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  switch (Address) {
+  case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:
+    Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
+    break;
+  case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
+    Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
+    break;
+  default:
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Select loop based on the width of the transfer
+  //
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (OperationWidth == EfiCpuIoWidthUint8) {
+      *Uint8Buffer = MmioRead8 ((UINTN)Address);
+    } else if (OperationWidth == EfiCpuIoWidthUint16) {
+      *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+    } else if (OperationWidth == EfiCpuIoWidthUint32) {
+      *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Write I/O registers.
+
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+  each of the Count operations that is performed.
+
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times on the same Address.
+
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+  incremented for each of the Count operations that is performed. The read or
+  write operation is performed Count times from the first element of Buffer.
+
+  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+  @param[in]  Width    Signifies the width of the I/O or Memory operation.
+  @param[in]  Address  The base address of the I/O operation.
+  @param[in]  Count    The number of I/O operations to perform. The number of
+                       bytes moved is Width size * Count, starting at Address.
+  @param[in]  Buffer   For read operations, the destination buffer to store the results.
+                       For write operations, the source buffer from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the PI system.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
+                                 and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+  IN EFI_CPU_IO2_PROTOCOL       *This,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64                     Address,
+  IN UINTN                      Count,
+  IN VOID                       *Buffer
+  )
+{
+  EFI_STATUS                 Status;
+  UINT8                      InStride;
+  UINT8                      OutStride;
+  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
+  UINT8                      *Uint8Buffer;
+
+  //
+  // Make sure the parameters are valid
+  //
+  Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  switch (Address) {
+  case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:
+    Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
+    break;
+  case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
+    Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
+    break;
+  default:
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Select loop based on the width of the transfer
+  //
+  InStride = mInStride[Width];
+  OutStride = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+  for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+    if (OperationWidth == EfiCpuIoWidthUint8) {
+      MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+    } else if (OperationWidth == EfiCpuIoWidthUint16) {
+      MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+    } else if (OperationWidth == EfiCpuIoWidthUint32) {
+      MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+  {
+    CpuMemoryServiceRead,
+    CpuMemoryServiceWrite
+  },
+  {
+    CpuIoServiceRead,
+    CpuIoServiceWrite
+  }
+};
+
+
+/**
+  The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.
+  @param[in] SystemTable    A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+  @retval other             Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+SynquacerPciCpuIo2Initialize (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EFI_STATUS Status;
+
+  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &mHandle,
+                  &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
new file mode 100644
index 000000000000..8b56561f029d
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
@@ -0,0 +1,50 @@
+## @file
+#  Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SynquacerPciCpuIo2Dxe
+  FILE_GUID                      = cee8beea-507a-49f4-a3d7-d1100a2008cc
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = SynquacerPciCpuIo2Initialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = ARM AARCH64
+#
+
+[Sources]
+  SynquacerPciCpuIo2Dxe.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  Silicon/Socionext/Synquacer/Synquacer.dec
+
+[LibraryClasses]
+  UefiDriverEntryPoint
+  BaseLib
+  DebugLib
+  IoLib
+  PcdLib
+  UefiBootServicesTableLib
+
+[Protocols]
+  gEfiCpuIo2ProtocolGuid                         ## PRODUCES
+
+[Depex]
+  TRUE
-- 
2.11.0

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edk2-devel@lists.01.org
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Re: [edk2] [PATCH edk2-platforms 06/14] Silicon/Synquacer: implement EFI_CPU_IO2_PROTOCOL
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:07PM +0100, Ard Biesheuvel wrote:
> The Synquacer SOC has two separate PCIe RCs, which means there is
> no single value for the translation offset between I/O port accesses
> and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
> that takes the two disjoint I/O windows into account.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c   | 588 ++++++++++++++++++++
>  Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf |  50 ++
>  2 files changed, 638 insertions(+)
> 
> diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
> new file mode 100644
> index 000000000000..8591a251aea3
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.c
> @@ -0,0 +1,588 @@
> +/** @file
> +  Produces the CPU I/O 2 Protocol.
> +
> +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
> +
> +This program and the accompanying materials
> +are licensed and made available under the terms and conditions of the BSD License
> +which accompanies this distribution.  The full text of the license may be found at
> +http://opensource.org/licenses/bsd-license.php
> +
> +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Platform/Pcie.h>
> +#include <Protocol/CpuIo2.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#define MAX_IO_PORT_ADDRESS   SYNQUACER_PCI_SEG1_PORTIO_MAX
> +
> +//
> +// Handle for the CPU I/O 2 Protocol
> +//
> +STATIC EFI_HANDLE  mHandle = NULL;
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mInStride[] = {
> +  1, // EfiCpuIoWidthUint8
> +  2, // EfiCpuIoWidthUint16
> +  4, // EfiCpuIoWidthUint32
> +  8, // EfiCpuIoWidthUint64
> +  0, // EfiCpuIoWidthFifoUint8
> +  0, // EfiCpuIoWidthFifoUint16
> +  0, // EfiCpuIoWidthFifoUint32
> +  0, // EfiCpuIoWidthFifoUint64
> +  1, // EfiCpuIoWidthFillUint8
> +  2, // EfiCpuIoWidthFillUint16
> +  4, // EfiCpuIoWidthFillUint32
> +  8  // EfiCpuIoWidthFillUint64
> +};
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mOutStride[] = {
> +  1, // EfiCpuIoWidthUint8
> +  2, // EfiCpuIoWidthUint16
> +  4, // EfiCpuIoWidthUint32
> +  8, // EfiCpuIoWidthUint64
> +  1, // EfiCpuIoWidthFifoUint8
> +  2, // EfiCpuIoWidthFifoUint16
> +  4, // EfiCpuIoWidthFifoUint32
> +  8, // EfiCpuIoWidthFifoUint64
> +  0, // EfiCpuIoWidthFillUint8
> +  0, // EfiCpuIoWidthFillUint16
> +  0, // EfiCpuIoWidthFillUint32
> +  0  // EfiCpuIoWidthFillUint64
> +};
> +
> +/**
> +  Check parameters to a CPU I/O 2 Protocol service request.
> +
> +  The I/O operations are carried out exactly as requested. The caller is responsible
> +  for satisfying any alignment and I/O width restrictions that a PI System on a
> +  platform might require. For example on some platforms, width requests of
> +  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> +  be handled by the driver.
> +
> +  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port operation.
> +  @param[in] Width          Signifies the width of the I/O or Memory operation.
> +  @param[in] Address        The base address of the I/O operation.
> +  @param[in] Count          The number of I/O operations to perform. The number of
> +                            bytes moved is Width size * Count, starting at Address.
> +  @param[in] Buffer         For read operations, the destination buffer to store the results.
> +                            For write operations, the source buffer from which to write data.
> +
> +  @retval EFI_SUCCESS            The parameters for this request pass the checks.
> +  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
> +  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
> +  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
> +  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
> +                                 and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CpuIoCheckParameter (
> +  IN BOOLEAN                    MmioOperation,
> +  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
> +  IN UINT64                     Address,
> +  IN UINTN                      Count,
> +  IN VOID                       *Buffer
> +  )
> +{
> +  UINT64  MaxCount;
> +  UINT64  Limit;
> +
> +  //
> +  // Check to see if Buffer is NULL
> +  //
> +  if (Buffer == NULL) {
> +    ASSERT (FALSE);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  //
> +  // Check to see if Width is in the valid range
> +  //
> +  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
> +    ASSERT (FALSE);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  //
> +  // For FIFO type, the target address won't increase during the access,
> +  // so treat Count as 1
> +  //
> +  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
> +    Count = 1;
> +  }
> +
> +  //
> +  // Check to see if Width is in the valid range for I/O Port operations
> +  //
> +  Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);

No space before (Width?

> +  if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
> +    ASSERT (FALSE);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  //
> +  // Check to see if Address is aligned
> +  //
> +  if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
> +    ASSERT (FALSE);
> +    return EFI_UNSUPPORTED;
> +  }
> +
> +  //
> +  // Check to see if any address associated with this transfer exceeds the maximum
> +  // allowed address.  The maximum address implied by the parameters passed in is
> +  // Address + Size * Count.  If the following condition is met, then the transfer
> +  // is not supported.
> +  //
> +  //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
> +  //
> +  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
> +  // can also be the maximum integer value supported by the CPU, this range
> +  // check must be adjusted to avoid all oveflow conditions.
> +  //
> +  // The following form of the range check is equivalent but assumes that
> +  // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
> +  //
> +  Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
> +  if (Count == 0) {
> +    if (Address > Limit) {
> +      ASSERT (FALSE);
> +      return EFI_UNSUPPORTED;
> +    }
> +  } else {
> +    MaxCount = RShiftU64 (Limit, Width);
> +    if (MaxCount < (Count - 1)) {
> +      ASSERT (FALSE);
> +      return EFI_UNSUPPORTED;
> +    }
> +    if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
> +      ASSERT (FALSE);
> +      return EFI_UNSUPPORTED;
> +    }
> +  }
> +
> +  //
> +  // Check to see if Buffer is aligned
> +  //
> +  if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width])  - 1))) != 0) {
> +    ASSERT (FALSE);
> +    return EFI_UNSUPPORTED;
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Reads memory-mapped registers.
> +
> +  The I/O operations are carried out exactly as requested. The caller is responsible
> +  for satisfying any alignment and I/O width restrictions that a PI System on a
> +  platform might require. For example on some platforms, width requests of
> +  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> +  be handled by the driver.
> +
> +  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> +  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> +  each of the Count operations that is performed.
> +
> +  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> +  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times on the same Address.
> +
> +  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> +  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times from the first element of Buffer.
> +
> +  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> +  @param[in]  Width    Signifies the width of the I/O or Memory operation.
> +  @param[in]  Address  The base address of the I/O operation.
> +  @param[in]  Count    The number of I/O operations to perform. The number of
> +                       bytes moved is Width size * Count, starting at Address.
> +  @param[out] Buffer   For read operations, the destination buffer to store the results.
> +                       For write operations, the source buffer from which to write data.
> +
> +  @retval EFI_SUCCESS            The data was read from or written to the PI system.
> +  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
> +  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
> +  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
> +  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
> +                                 and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceRead (
> +  IN  EFI_CPU_IO2_PROTOCOL       *This,
> +  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,
> +  IN  UINT64                     Address,
> +  IN  UINTN                      Count,
> +  OUT VOID                       *Buffer
> +  )
> +{
> +  EFI_STATUS                 Status;
> +  UINT8                      InStride;
> +  UINT8                      OutStride;
> +  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
> +  UINT8                      *Uint8Buffer;

I know this is arguably just a question of preference (and taken from
the template), but why not VOID * and BufferPointer (or something)?
Casts to UINT8 * tingle my spidey sense.

> +
> +  Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> +  if (EFI_ERROR (Status)) {
> +    return Status;
> +  }
> +
> +  //
> +  // Select loop based on the width of the transfer
> +  //
> +  InStride = mInStride[Width];
> +  OutStride = mOutStride[Width];
> +  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> +  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> +    if (OperationWidth == EfiCpuIoWidthUint8) {
> +      *Uint8Buffer = MmioRead8 ((UINTN)Address);

Obviously a *((UINT8 *) would be needed.

> +    } else if (OperationWidth == EfiCpuIoWidthUint16) {
> +      *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> +    } else if (OperationWidth == EfiCpuIoWidthUint32) {
> +      *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> +    } else if (OperationWidth == EfiCpuIoWidthUint64) {
> +      *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
> +    }
> +  }
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Writes memory-mapped registers.
> +
> +  The I/O operations are carried out exactly as requested. The caller is responsible
> +  for satisfying any alignment and I/O width restrictions that a PI System on a
> +  platform might require. For example on some platforms, width requests of
> +  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> +  be handled by the driver.
> +
> +  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> +  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> +  each of the Count operations that is performed.
> +
> +  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> +  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times on the same Address.
> +
> +  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> +  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times from the first element of Buffer.
> +
> +  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> +  @param[in]  Width    Signifies the width of the I/O or Memory operation.
> +  @param[in]  Address  The base address of the I/O operation.
> +  @param[in]  Count    The number of I/O operations to perform. The number of
> +                       bytes moved is Width size * Count, starting at Address.
> +  @param[in]  Buffer   For read operations, the destination buffer to store the results.
> +                       For write operations, the source buffer from which to write data.
> +
> +  @retval EFI_SUCCESS            The data was read from or written to the PI system.
> +  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
> +  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
> +  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
> +  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
> +                                 and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceWrite (
> +  IN EFI_CPU_IO2_PROTOCOL       *This,
> +  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
> +  IN UINT64                     Address,
> +  IN UINTN                      Count,
> +  IN VOID                       *Buffer
> +  )
> +{
> +  EFI_STATUS                 Status;
> +  UINT8                      InStride;
> +  UINT8                      OutStride;
> +  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
> +  UINT8                      *Uint8Buffer;

Same comment.

> +
> +  Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> +  if (EFI_ERROR (Status)) {
> +    return Status;
> +  }
> +
> +  //
> +  // Select loop based on the width of the transfer
> +  //
> +  InStride = mInStride[Width];
> +  OutStride = mOutStride[Width];
> +  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> +  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> +    if (OperationWidth == EfiCpuIoWidthUint8) {
> +      MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> +    } else if (OperationWidth == EfiCpuIoWidthUint16) {
> +      MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> +    } else if (OperationWidth == EfiCpuIoWidthUint32) {
> +      MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> +    } else if (OperationWidth == EfiCpuIoWidthUint64) {
> +      MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
> +    }
> +  }
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Reads I/O registers.
> +
> +  The I/O operations are carried out exactly as requested. The caller is responsible
> +  for satisfying any alignment and I/O width restrictions that a PI System on a
> +  platform might require. For example on some platforms, width requests of
> +  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> +  be handled by the driver.
> +
> +  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> +  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> +  each of the Count operations that is performed.
> +
> +  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> +  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times on the same Address.
> +
> +  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> +  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times from the first element of Buffer.
> +
> +  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> +  @param[in]  Width    Signifies the width of the I/O or Memory operation.
> +  @param[in]  Address  The base address of the I/O operation.
> +  @param[in]  Count    The number of I/O operations to perform. The number of
> +                       bytes moved is Width size * Count, starting at Address.
> +  @param[out] Buffer   For read operations, the destination buffer to store the results.
> +                       For write operations, the source buffer from which to write data.
> +
> +  @retval EFI_SUCCESS            The data was read from or written to the PI system.
> +  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
> +  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
> +  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
> +  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
> +                                 and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceRead (
> +  IN  EFI_CPU_IO2_PROTOCOL       *This,
> +  IN  EFI_CPU_IO_PROTOCOL_WIDTH  Width,
> +  IN  UINT64                     Address,
> +  IN  UINTN                      Count,
> +  OUT VOID                       *Buffer
> +  )
> +{
> +  EFI_STATUS                 Status;
> +  UINT8                      InStride;
> +  UINT8                      OutStride;
> +  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
> +  UINT8                      *Uint8Buffer;

Same comment.

> +
> +  Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
> +  if (EFI_ERROR (Status)) {
> +    return Status;
> +  }
> +
> +  switch (Address) {
> +  case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:

Is the '...' extension permitted?
This wouldn't look horrifically worse as an if ... else if .. else,
and it would be portable.

> +    Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
> +    break;
> +  case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
> +    Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
> +    break;
> +  default:
> +    ASSERT (FALSE);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  //
> +  // Select loop based on the width of the transfer
> +  //
> +  InStride = mInStride[Width];
> +  OutStride = mOutStride[Width];
> +  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);

Drop space before (Width?

> +
> +  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> +    if (OperationWidth == EfiCpuIoWidthUint8) {
> +      *Uint8Buffer = MmioRead8 ((UINTN)Address);
> +    } else if (OperationWidth == EfiCpuIoWidthUint16) {
> +      *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> +    } else if (OperationWidth == EfiCpuIoWidthUint32) {
> +      *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> +    }
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Write I/O registers.
> +
> +  The I/O operations are carried out exactly as requested. The caller is responsible
> +  for satisfying any alignment and I/O width restrictions that a PI System on a
> +  platform might require. For example on some platforms, width requests of
> +  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
> +  be handled by the driver.
> +
> +  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> +  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> +  each of the Count operations that is performed.
> +
> +  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> +  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times on the same Address.
> +
> +  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> +  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> +  incremented for each of the Count operations that is performed. The read or
> +  write operation is performed Count times from the first element of Buffer.
> +
> +  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> +  @param[in]  Width    Signifies the width of the I/O or Memory operation.
> +  @param[in]  Address  The base address of the I/O operation.
> +  @param[in]  Count    The number of I/O operations to perform. The number of
> +                       bytes moved is Width size * Count, starting at Address.
> +  @param[in]  Buffer   For read operations, the destination buffer to store the results.
> +                       For write operations, the source buffer from which to write data.
> +
> +  @retval EFI_SUCCESS            The data was read from or written to the PI system.
> +  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
> +  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
> +  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
> +  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
> +                                 and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceWrite (
> +  IN EFI_CPU_IO2_PROTOCOL       *This,
> +  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
> +  IN UINT64                     Address,
> +  IN UINTN                      Count,
> +  IN VOID                       *Buffer
> +  )
> +{
> +  EFI_STATUS                 Status;
> +  UINT8                      InStride;
> +  UINT8                      OutStride;
> +  EFI_CPU_IO_PROTOCOL_WIDTH  OperationWidth;
> +  UINT8                      *Uint8Buffer;

Same comment?

> +
> +  //
> +  // Make sure the parameters are valid
> +  //
> +  Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
> +  if (EFI_ERROR (Status)) {
> +    return Status;
> +  }
> +
> +  switch (Address) {
> +  case SYNQUACER_PCI_SEG0_PORTIO_MIN ... SYNQUACER_PCI_SEG0_PORTIO_MAX:

Same comment.

> +    Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE;
> +    break;
> +  case SYNQUACER_PCI_SEG1_PORTIO_MIN ... SYNQUACER_PCI_SEG1_PORTIO_MAX:
> +    Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE;
> +    break;
> +  default:
> +    ASSERT (FALSE);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  //
> +  // Select loop based on the width of the transfer
> +  //
> +  InStride = mInStride[Width];
> +  OutStride = mOutStride[Width];
> +  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);

Drop space before (Width?

> +
> +  for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> +    if (OperationWidth == EfiCpuIoWidthUint8) {
> +      MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> +    } else if (OperationWidth == EfiCpuIoWidthUint16) {
> +      MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> +    } else if (OperationWidth == EfiCpuIoWidthUint32) {
> +      MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> +    }
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> +
> +//
> +// CPU I/O 2 Protocol instance
> +//
> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
> +  {
> +    CpuMemoryServiceRead,
> +    CpuMemoryServiceWrite
> +  },
> +  {
> +    CpuIoServiceRead,
> +    CpuIoServiceWrite
> +  }
> +};
> +
> +
> +/**
> +  The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
> +
> +  @param[in] ImageHandle    The firmware allocated handle for the EFI image.
> +  @param[in] SystemTable    A pointer to the EFI System Table.
> +
> +  @retval EFI_SUCCESS       The entry point is executed successfully.
> +  @retval other             Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SynquacerPciCpuIo2Initialize (
> +  IN EFI_HANDLE        ImageHandle,
> +  IN EFI_SYSTEM_TABLE  *SystemTable
> +  )
> +{
> +  EFI_STATUS Status;
> +
> +  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
> +  Status = gBS->InstallMultipleProtocolInterfaces (
> +                  &mHandle,
> +                  &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
> +                  NULL
> +                  );
> +  ASSERT_EFI_ERROR (Status);
> +
> +  return Status;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> new file mode 100644
> index 000000000000..8b56561f029d
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> @@ -0,0 +1,50 @@
> +## @file
> +#  Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
> +#
> +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution.  The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010005

Bump.

> +  BASE_NAME                      = SynquacerPciCpuIo2Dxe
> +  FILE_GUID                      = cee8beea-507a-49f4-a3d7-d1100a2008cc
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 1.0
> +  ENTRY_POINT                    = SynquacerPciCpuIo2Initialize
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +#  VALID_ARCHITECTURES           = ARM AARCH64
> +#
> +
> +[Sources]
> +  SynquacerPciCpuIo2Dxe.c
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  Silicon/Socionext/Synquacer/Synquacer.dec
> +
> +[LibraryClasses]
> +  UefiDriverEntryPoint
> +  BaseLib
> +  DebugLib
> +  IoLib
> +  PcdLib
> +  UefiBootServicesTableLib

Sort, please?

/
   Leif

> +
> +[Protocols]
> +  gEfiCpuIo2ProtocolGuid                         ## PRODUCES
> +
> +[Depex]
> +  TRUE
> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support
Posted by Ard Biesheuvel, 2 weeks ago
Wire up the various drivers and libraries for the SynquacerEvalBoard
platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
and the various bus, partition and file system drivers that we need
to make use of PCIe devices.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 49 ++++++++++++++++++++
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 38 +++++++++++++++
 2 files changed, 87 insertions(+)

diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index 2a9a0037dcda..aea39b46d91b 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -100,6 +100,7 @@
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
   SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
 
   # BDS Libraries
   UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -148,6 +149,12 @@
   SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
 
+  #
+  # PCI
+  #
+  PciSegmentLib|Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
+  PciHostBridgeLib|Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
+
 [LibraryClasses.common.UEFI_APPLICATION]
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
@@ -184,6 +191,7 @@
   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
 
   # Ashbrook 12-Cluster profile
   gArmPlatformTokenSpaceGuid.PcdCoreCount|2
@@ -392,3 +400,44 @@
       NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
       NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
   }
+
+  #
+  # PCI
+  #
+  Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+  }
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  #
+  # USB
+  #
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # RNG
+  #
+  Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index 6c00e16b169e..befad354918e 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -128,6 +128,44 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
   INF MdeModulePkg/Application/UiApp/UiApp.inf
 
+  #
+  # PCI
+  #
+  INF Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
+  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+  #
+  # USB
+  #
+  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF FatPkg/EnhancedFatDxe/Fat.inf
+
+  #
+  # RNG
+  #
+  INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
+
 [FV.FVMAIN_COMPACT]
 FvAlignment        = 8
 ERASE_POLARITY     = 1
-- 
2.11.0

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Re: [edk2] [PATCH edk2-platforms 07/14] Platform/SynquacerEvalBoard: add PCI support
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:08PM +0100, Ard Biesheuvel wrote:
> Wire up the various drivers and libraries for the SynquacerEvalBoard
> platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
> and the various bus, partition and file system drivers that we need
> to make use of PCIe devices.

If you're folding ChaosKey driver in here (as you are) it deserves a
mention in the commit message.

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 49 ++++++++++++++++++++
>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 38 +++++++++++++++
>  2 files changed, 87 insertions(+)
> 
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index 2a9a0037dcda..aea39b46d91b 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -100,6 +100,7 @@
>    DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>    SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
>    UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>  
>    # BDS Libraries
>    UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> @@ -148,6 +149,12 @@
>    SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
>    PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
>  
> +  #
> +  # PCI
> +  #
> +  PciSegmentLib|Silicon/Socionext/Synquacer/Library/SynquacerPciSegmentLib/SynquacerPciSegmentLib.inf
> +  PciHostBridgeLib|Silicon/Socionext/Synquacer/Library/SynquacerPciHostBridgeLib/SynquacerPciHostBridgeLib.inf
> +
>  [LibraryClasses.common.UEFI_APPLICATION]
>    PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
>    HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> @@ -184,6 +191,7 @@
>    gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
>    gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
>    gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> +  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
>  
>    # Ashbrook 12-Cluster profile
>    gArmPlatformTokenSpaceGuid.PcdCoreCount|2
> @@ -392,3 +400,44 @@
>        NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
>        NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
>    }
> +
> +  #
> +  # PCI
> +  #
> +  Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> +  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> +    <PcdsFixedAtBuild>
> +        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> +  }
> +  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> +  #
> +  # AHCI Support
> +  #
> +  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +  #
> +  # USB
> +  #
> +  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf

Is there a good reason for leaving out Uhci/Ehci?

/
    Leif

> +
> +  #
> +  # FAT filesystem + GPT/MBR partitioning
> +  #
> +  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +  FatPkg/EnhancedFatDxe/Fat.inf
> +
> +  #
> +  # RNG
> +  #
> +  Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index 6c00e16b169e..befad354918e 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -128,6 +128,44 @@ READ_LOCK_STATUS   = TRUE
>    INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
>    INF MdeModulePkg/Application/UiApp/UiApp.inf
>  
> +  #
> +  # PCI
> +  #
> +  INF Silicon/Socionext/Synquacer/Drivers/SynquacerPciCpuIo2dxe/SynquacerPciCpuIo2Dxe.inf
> +  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> +  #
> +  # AHCI Support
> +  #
> +  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +  #
> +  # USB
> +  #
> +  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> +  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> +  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> +
> +  #
> +  # FAT filesystem + GPT/MBR partitioning
> +  #
> +  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> +  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> +  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +  INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> +  #
> +  # RNG
> +  #
> +  INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> +
>  [FV.FVMAIN_COMPACT]
>  FvAlignment        = 8
>  ERASE_POLARITY     = 1
> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller
Posted by Ard Biesheuvel, 2 weeks ago
This adds the NetSecDxe driver provided by Socionext, but reworked
extensively to improve compliance with the SimpleNetworkProtocol API,
and to avoid uncached allocations for streaming DMA.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c                                                     | 1000 ++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec                                                   |   47 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h                                                     |   88 ++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf                                                   |   69 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h                   |  736 ++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h            |   45 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h               |   24 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c              |   88 ++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h              |   52 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c          | 1391 +++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h |  111 ++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c               | 1454 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h                  |  210 +++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c                      | 1385 +++++++++++++++++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h             |   38 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h                       |  219 +++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h            |  222 +++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h                |  368 +++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h                                   |   25 +
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h                                         |  265 ++++
 Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c                                    |  176 +++
 21 files changed, 8013 insertions(+)

diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
new file mode 100644
index 000000000000..7c3f12362f14
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
@@ -0,0 +1,1000 @@
+/** @file
+
+  Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/NetLib.h>
+
+#include "NetsecDxe.h"
+#include "netsec_for_uefi/pfdep.h"
+
+EFI_CPU_ARCH_PROTOCOL      *mCpu;
+
+STATIC NETSEC_DEVICE_PATH NetsecPathTemplate =  {
+  {
+    {
+      MESSAGING_DEVICE_PATH,
+      MSG_MAC_ADDR_DP,
+      {
+        (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)),
+        (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH) >> 8)
+      }
+    },
+    {
+      {
+        0
+      }
+    },
+    0
+  },
+  {
+    END_DEVICE_PATH_TYPE,
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    {
+      sizeof(EFI_DEVICE_PATH_PROTOCOL), 0
+    }
+  }
+};
+
+STATIC
+VOID
+GetCurrentMacAddress(
+  OUT UINT8   *Mac)
+{
+  Mac[0] = MmioRead8(MAC_ADDRESS + 3);
+  Mac[1] = MmioRead8(MAC_ADDRESS + 2);
+  Mac[2] = MmioRead8(MAC_ADDRESS + 1);
+  Mac[3] = MmioRead8(MAC_ADDRESS + 0);
+  Mac[4] = MmioRead8(MAC_ADDRESS + 7);
+  Mac[5] = MmioRead8(MAC_ADDRESS + 6);
+}
+
+/*
+ *  Probe()
+ */
+STATIC
+EFI_STATUS
+Probe (
+  IN  EFI_HANDLE          Handle,
+  IN  NETSEC_DRIVER       *LanDriver
+  )
+{
+  ogma_param_t  Param;
+  ogma_err_t    ogma_err;
+  UINT64        dmac_hm_cmd_base, dmac_mh_cmd_base, core_cmd_base;
+  UINT32        dmac_hm_cmd_size, dmac_mh_cmd_size, core_cmd_size;
+
+  SetMem (&Param, sizeof(Param), 0);
+
+  Param.use_gmac_flag = OGMA_TRUE;
+
+  Param.use_jumbo_pkt_flag = PcdGet8 (PcdJumboPacket);
+
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag = OGMA_TRUE;
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].little_endian_flag = OGMA_TRUE;
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].tmr_mode_flag = OGMA_FALSE;
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].entry_num = PcdGet16 (PcdEncTxDescNum);
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag = OGMA_TRUE;
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].little_endian_flag = OGMA_TRUE;
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].tmr_mode_flag = OGMA_FALSE;
+  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].entry_num = PcdGet16 (PcdDecRxDescNum);
+
+  // phy-interface
+  Param.gmac_config.phy_interface = OGMA_PHY_INTERFACE_RGMII;
+
+  // Read and save the Permanent MAC Address
+  GetCurrentMacAddress (LanDriver->SnpMode.PermanentAddress.Addr);
+
+  LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
+  DEBUG ((DEBUG_NET | DEBUG_INFO,
+    "Netsec: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
+    LanDriver->SnpMode.PermanentAddress.Addr[0],
+    LanDriver->SnpMode.PermanentAddress.Addr[1],
+    LanDriver->SnpMode.PermanentAddress.Addr[2],
+    LanDriver->SnpMode.PermanentAddress.Addr[3],
+    LanDriver->SnpMode.PermanentAddress.Addr[4],
+    LanDriver->SnpMode.PermanentAddress.Addr[5]));
+
+  // Get hm microcode's physical addresses
+  dmac_hm_cmd_base = MmioRead32 (HM_ME_ADDRESS_H);
+  dmac_hm_cmd_base <<= 32;
+  dmac_hm_cmd_base |= MmioRead32 (HM_ME_ADDRESS_L);
+  dmac_hm_cmd_size = MmioRead32 (HM_ME_SIZE);
+
+  // Get mh microcode's physical addresses
+  dmac_mh_cmd_base = MmioRead32 (MH_ME_ADDRESS_H);
+  dmac_mh_cmd_base <<= 32;
+  dmac_mh_cmd_base |= MmioRead32 (MH_ME_ADDRESS_L);
+  dmac_mh_cmd_size = MmioRead32 (MH_ME_SIZE);
+
+  // Get core microcode's physical addresses
+  core_cmd_base = MmioRead32 (PACKET_ME_ADDRESS);
+  core_cmd_size = MmioRead32 (PACKET_ME_SIZE);
+
+  ogma_err = ogma_init ((VOID *)((UINTN)PcdGet32(PcdNetsecDxeBaseAddress)),
+                        Handle, &Param,
+                        (VOID *)dmac_hm_cmd_base, dmac_hm_cmd_size,
+                        (VOID *)dmac_mh_cmd_base, dmac_mh_cmd_size,
+                        (VOID *)core_cmd_base, core_cmd_size,
+                        &LanDriver->Handle);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR, "NETSEC: ogma_init() failed with error code %d\n",
+      ogma_err));
+    return EFI_DEVICE_ERROR;
+  }
+
+  ogma_enable_top_irq (LanDriver->Handle,
+                       OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX);
+
+  return EFI_SUCCESS;
+}
+
+/*
+ *  UEFI Stop() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpStop (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL    *Snp
+  )
+{
+  EFI_TPL       SavedTpl;
+  EFI_STATUS    Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // Check state of the driver
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkStarted:
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Change the state
+  Snp->Mode->State = EfiSimpleNetworkStopped;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+ *  UEFI Initialize() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpInitialize (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
+  IN  UINTN                         RxBufferSize  OPTIONAL,
+  IN  UINTN                         TxBufferSize  OPTIONAL
+  )
+{
+  NETSEC_DRIVER           *LanDriver;
+  EFI_TPL                 SavedTpl;
+  EFI_STATUS              Status;
+
+  ogma_phy_link_status_t  phy_link_status;
+  ogma_err_t              ogma_err;
+  ogma_gmac_mode_t        ogma_gmac_mode;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // Check that driver was started but not initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkStarted:
+    break;
+  case EfiSimpleNetworkInitialized:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver already initialized\n"));
+    ReturnUnlock (EFI_SUCCESS);
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // ##### open
+  ogma_err = ogma_clean_rx_desc_ring (LanDriver->Handle,
+                                      OGMA_DESC_RING_ID_NRM_RX);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_clean_rx_desc_ring() failed with error code %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+                                      OGMA_DESC_RING_ID_NRM_TX);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_clean_tx_desc_ring() failed with error code %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_clear_desc_ring_irq_status (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
+                                   OGMA_CH_IRQ_REG_EMPTY);
+
+  // ##### open_sub
+  ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
+      OGMA_DESC_RING_ID_NRM_RX,
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_err = ogma_set_irq_coalesce_param(LanDriver->Handle,
+                                         OGMA_DESC_RING_ID_NRM_RX,
+                                         RXINT_PKTCNT,
+                                         OGMA_FALSE,
+                                         RXINT_TMR_CNT_US);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_set_irq_coalesce_param() failed with error code %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
+      OGMA_DESC_RING_ID_NRM_TX,
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
+                              OGMA_CH_IRQ_REG_EMPTY);
+
+  // ##### configure_mac
+  ogma_err = ogma_stop_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_stop_gmac() failed with error status %d\n",
+      ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_err = ogma_get_phy_link_status(LanDriver->Handle, PcdGet8(PcdPhyDevAddr), &phy_link_status);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_get_phy_link_status() failed error code %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  SetMem (&ogma_gmac_mode, sizeof(ogma_gmac_mode_t), 0);
+  ogma_gmac_mode.link_speed = phy_link_status.link_speed;
+  ogma_gmac_mode.half_duplex_flag = (ogma_bool)phy_link_status.half_duplex_flag;
+  if ((!phy_link_status.half_duplex_flag) && PcdGet8(PcdFlowCtrl)) {
+    ogma_gmac_mode.flow_ctrl_enable_flag      = (ogma_bool)PcdGet8(PcdFlowCtrl);
+    ogma_gmac_mode.flow_ctrl_start_threshold  = (ogma_uint16)PcdGet16(PcdFlowCtrlStartThreshold);
+    ogma_gmac_mode.flow_ctrl_stop_threshold   = (ogma_uint16)PcdGet16(PcdFlowCtrlStopThreshold);
+    ogma_gmac_mode.pause_time                 = (ogma_uint16)PcdGet16(PcdPauseTime);
+  }
+
+  ogma_err = ogma_set_gmac_mode(LanDriver->Handle, &ogma_gmac_mode);
+  if(ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_set_gmac() failed with error status %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_err = ogma_start_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+  if(ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_start_gmac() failed with error status %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Declare the driver as initialized
+  Snp->Mode->State = EfiSimpleNetworkInitialized;
+  Status = EFI_SUCCESS;
+
+  DEBUG ((DEBUG_INFO | DEBUG_LOAD, "NETSEC: Driver started\n"));
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+ *  UEFI Shutdown () function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpShutdown (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL    *Snp
+  )
+{
+  NETSEC_DRIVER     *LanDriver;
+  EFI_TPL           SavedTpl;
+  EFI_STATUS        Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // First check that driver has already been initialized
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver in stopped state\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
+
+  ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
+  ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+
+  Snp->Mode->State = EfiSimpleNetworkStarted;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+STATIC
+VOID
+EFIAPI
+NotifyExitBoot (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  EFI_SIMPLE_NETWORK_PROTOCOL     *Snp;
+  EFI_STATUS                      Status;
+
+  Snp = Context;
+
+  if (Snp->Mode != EfiSimpleNetworkStopped) {
+    Status = SnpShutdown (Snp);
+    if (!EFI_ERROR (Status)) {
+      SnpStop (Snp);
+    }
+  }
+  gBS->CloseEvent (Event);
+}
+
+/*
+ *  UEFI Start() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpStart (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL    *Snp
+  )
+{
+  EFI_SIMPLE_NETWORK_MODE   *Mode;
+  EFI_TPL                   SavedTpl;
+  EFI_STATUS                Status;
+  NETSEC_DRIVER             *LanDriver;
+
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Check Snp instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+  Mode = Snp->Mode;
+
+  // Check state of the driver
+  switch (Mode->State) {
+  case EfiSimpleNetworkStopped:
+    break;
+  case EfiSimpleNetworkStarted:
+  case EfiSimpleNetworkInitialized:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver already started\n"));
+    ReturnUnlock (EFI_ALREADY_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, NETSEC_TPL,
+                  NotifyExitBoot, Snp, &LanDriver->ExitBootEvent);
+  ASSERT_EFI_ERROR (Status);
+
+  // Change state
+  Mode->State = EfiSimpleNetworkStarted;
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+
+}
+
+/*
+ *  UEFI ReceiveFilters() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpReceiveFilters (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL     *Snp,
+  IN  UINT32                          Enable,
+  IN  UINT32                          Disable,
+  IN  BOOLEAN                         Reset,
+  IN  UINTN                           NumMfilter  OPTIONAL,
+  IN  EFI_MAC_ADDRESS                 *Mfilter    OPTIONAL
+  )
+{
+  EFI_TPL             SavedTpl;
+  EFI_STATUS          Status;
+
+  // Check Snp Instance
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // First check that driver has already been initialized
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n", (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+ *  UEFI GetStatus () function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpGetStatus (
+  IN      EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
+      OUT UINT32                        *IrqStat  OPTIONAL,
+      OUT VOID                          **TxBuff  OPTIONAL
+  )
+{
+  NETSEC_DRIVER             *LanDriver;
+  EFI_TPL                   SavedTpl;
+  EFI_STATUS                Status;
+  pfdep_pkt_handle_t        pkt_handle;
+  LIST_ENTRY                *Link;
+
+  ogma_phy_link_status_t  phy_link_status;
+  ogma_err_t              ogma_err;
+
+  // Check preliminaries
+  if (Snp == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  // Update the media status
+  ogma_err = ogma_get_phy_link_status (LanDriver->Handle,
+                                       PcdGet8(PcdPhyDevAddr),
+                                       &phy_link_status);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_get_phy_link_status failed with error code: %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  Snp->Mode->MediaPresent = phy_link_status.up_flag;
+
+  ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+                                      OGMA_DESC_RING_ID_NRM_TX);
+
+  if (TxBuff != NULL) {
+    *TxBuff = NULL;
+    //
+    // Find a buffer in the list that has been released
+    //
+    for (Link = GetFirstNode (&LanDriver->TxBufferList);
+         !IsNull (&LanDriver->TxBufferList, Link);
+         Link = GetNextNode (&LanDriver->TxBufferList, Link)) {
+
+      pkt_handle = BASE_CR (Link, PACKET_HANDLE, Link);
+      if (pkt_handle->Released) {
+        *TxBuff = pkt_handle->Buffer;
+        RemoveEntryList (Link);
+        FreePool (pkt_handle);
+        break;
+      }
+    }
+  }
+
+  if (IrqStat != 0) {
+    *IrqStat = 0;
+  }
+
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+ *  UEFI Transmit() function
+ */
+STATIC
+EFI_STATUS
+EFIAPI
+SnpTransmit (
+  IN  EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
+  IN  UINTN                         HdrSize,
+  IN  UINTN                         BufSize,
+  IN  VOID                          *BufAddr,
+  IN  EFI_MAC_ADDRESS               *SrcAddr    OPTIONAL,
+  IN  EFI_MAC_ADDRESS               *DstAddr    OPTIONAL,
+  IN  UINT16                        *Protocol   OPTIONAL
+  )
+{
+  NETSEC_DRIVER             *LanDriver;
+  EFI_TPL                   SavedTpl;
+  EFI_STATUS                Status;
+
+  ogma_tx_pkt_ctrl_t  tx_pkt_ctrl;
+  ogma_frag_info_t    scat_info;
+  ogma_uint16         tx_avail_num;
+  ogma_err_t          ogma_err;
+  UINT16              Proto;
+  pfdep_pkt_handle_t  pkt_handle;
+
+  // Check preliminaries
+  if ((Snp == NULL) || (BufAddr == NULL)) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n", Snp, BufAddr));
+    return EFI_DEVICE_ERROR;
+  }
+
+  pkt_handle = AllocateZeroPool (sizeof *pkt_handle);
+  if (pkt_handle == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  pkt_handle->Buffer = BufAddr;
+  pkt_handle->RecycleForTx = TRUE;
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  ogma_err = ogma_clear_desc_ring_irq_status (LanDriver->Handle,
+                                              OGMA_DESC_RING_ID_NRM_TX,
+                                              OGMA_CH_IRQ_REG_EMPTY);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_clear_desc_ring_irq_status failed with error code: %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
+                                      OGMA_DESC_RING_ID_NRM_TX);
+  if (ogma_err != OGMA_ERR_OK) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_clean_tx_desc_ring failed with error code: %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Ensure header is correct size if non-zero
+  if (HdrSize) {
+    if (HdrSize != Snp->Mode->MediaHeaderSize) {
+      DEBUG ((DEBUG_ERROR, "NETSEC: SnpTransmit(): Invalid HdrSize %d\n",
+        HdrSize));
+      ReturnUnlock (EFI_INVALID_PARAMETER);
+    }
+
+    if ((DstAddr == NULL) || (Protocol == NULL)) {
+      DEBUG ((DEBUG_ERROR,
+        "NETSEC: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
+        DstAddr, Protocol));
+      ReturnUnlock (EFI_INVALID_PARAMETER);
+    }
+
+    // Copy destination address
+    CopyMem (BufAddr, (VOID *)DstAddr, NET_ETHER_ADDR_LEN);
+    // Copy source address
+    CopyMem (BufAddr + NET_ETHER_ADDR_LEN, (VOID *)SrcAddr, NET_ETHER_ADDR_LEN);
+    // Copy protocol
+    Proto = HTONS(*Protocol);
+    CopyMem (BufAddr + (NET_ETHER_ADDR_LEN * 2), (VOID *)&Proto, sizeof(UINT16));
+  }
+
+  Status = DmaMap (MapOperationBusMasterRead, BufAddr, &BufSize,
+             &scat_info.phys_addr, &pkt_handle->Mapping);
+  if (EFI_ERROR (Status)) {
+    goto ExitUnlock;
+  }
+
+  scat_info.addr        = BufAddr;
+  scat_info.len         = BufSize;
+
+  SetMem (&tx_pkt_ctrl, sizeof (ogma_tx_pkt_ctrl_t), 0);
+
+  tx_pkt_ctrl.pass_through_flag     = OGMA_TRUE;
+  tx_pkt_ctrl.target_desc_ring_id   = OGMA_DESC_RING_ID_GMAC;
+
+  // check empty slot
+  do {
+    tx_avail_num = ogma_get_tx_avail_num (LanDriver->Handle,
+                                          OGMA_DESC_RING_ID_NRM_TX);
+  } while (tx_avail_num < SCAT_NUM);
+
+  // send
+  ogma_err = ogma_set_tx_pkt_data (LanDriver->Handle,
+                                   OGMA_DESC_RING_ID_NRM_TX,
+                                   &tx_pkt_ctrl,
+                                   SCAT_NUM,
+                                   &scat_info,
+                                   pkt_handle);
+
+  if (ogma_err != OGMA_ERR_OK) {
+    DmaUnmap (pkt_handle->Mapping);
+    FreePool (pkt_handle);
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC: ogma_set_tx_pkt_data failed with error code: %d\n",
+      (INT32)ogma_err));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  //
+  // Queue the descriptor so we can release the buffer once it has been
+  // consumed by the hardware.
+  //
+  InsertTailList (&LanDriver->TxBufferList, &pkt_handle->Link);
+
+  gBS->RestoreTPL (SavedTpl);
+  return EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  FreePool (pkt_handle);
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+ *  UEFI Receive() function
+ */
+EFI_STATUS
+EFIAPI
+SnpReceive (
+  IN      EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
+      OUT UINTN                         *HdrSize    OPTIONAL,
+  IN  OUT UINTN                         *BuffSize,
+      OUT VOID                          *Data,
+      OUT EFI_MAC_ADDRESS               *SrcAddr    OPTIONAL,
+      OUT EFI_MAC_ADDRESS               *DstAddr    OPTIONAL,
+      OUT UINT16                        *Protocol   OPTIONAL
+  )
+{
+  EFI_TPL             SavedTpl;
+  EFI_STATUS          Status;
+  NETSEC_DRIVER       *LanDriver;
+
+  ogma_err_t          ogma_err;
+  ogma_rx_pkt_info_t  rx_pkt_info;
+  ogma_frag_info_t    rx_data;
+  ogma_uint16         len;
+  pfdep_pkt_handle_t  pkt_handle;
+
+  // Check preliminaries
+  if ((Snp == NULL) || (Data == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  // Serialize access to data and registers
+  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
+
+  // Check that driver was started and initialised
+  switch (Snp->Mode->State) {
+  case EfiSimpleNetworkInitialized:
+    break;
+  case EfiSimpleNetworkStarted:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  case EfiSimpleNetworkStopped:
+    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
+    ReturnUnlock (EFI_NOT_STARTED);
+  default:
+    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
+      (UINTN)Snp->Mode->State));
+    ReturnUnlock (EFI_DEVICE_ERROR);
+  }
+
+  // Find the LanDriver structure
+  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
+
+  if (ogma_get_rx_num (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX) > 0) {
+
+    ogma_err = ogma_get_rx_pkt_data(LanDriver->Handle,
+                                    OGMA_DESC_RING_ID_NRM_RX,
+                                    &rx_pkt_info, &rx_data, &len, &pkt_handle);
+    if (ogma_err != OGMA_ERR_OK) {
+      DEBUG ((DEBUG_ERROR,
+        "NETSEC: ogma_get_rx_pkt_data failed with error code: %d\n",
+        (INT32)ogma_err));
+      ReturnUnlock (EFI_DEVICE_ERROR);
+    }
+
+    DmaUnmap (pkt_handle->Mapping);
+    pkt_handle->Mapping = NULL;
+
+    CopyMem (Data, (VOID*)rx_data.addr, len);
+    *BuffSize = len;
+
+    pfdep_free_pkt_buf (LanDriver->Handle, rx_data.len, rx_data.addr,
+      rx_data.phys_addr, PFDEP_TRUE, pkt_handle);
+  } else {
+    // not received any packets
+    ReturnUnlock (EFI_NOT_READY);
+  }
+
+  if (HdrSize != NULL) {
+    *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
+  }
+
+  ogma_clear_desc_ring_irq_status (LanDriver->Handle,
+                                   OGMA_DESC_RING_ID_NRM_TX,
+                                   OGMA_CH_IRQ_REG_EMPTY);
+
+  ogma_clean_tx_desc_ring(LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
+
+  ogma_enable_top_irq (LanDriver->Handle,
+                       OGMA_TOP_IRQ_REG_NRM_TX | OGMA_TOP_IRQ_REG_NRM_RX);
+
+  Status = EFI_SUCCESS;
+
+  // Restore TPL and return
+ExitUnlock:
+  gBS->RestoreTPL (SavedTpl);
+  return Status;
+}
+
+/*
+ *  Entry point for the Netxec driver
+ */
+EFI_STATUS
+NetsecDxeEntry (
+  IN  EFI_HANDLE        Handle,
+  IN  EFI_SYSTEM_TABLE  *SystemTable)
+{
+  EFI_STATUS                  Status;
+  NETSEC_DRIVER               *LanDriver;
+  EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
+  EFI_SIMPLE_NETWORK_MODE     *SnpMode;
+  NETSEC_DEVICE_PATH          *NetsecPath;
+
+  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
+  ASSERT_EFI_ERROR(Status);
+
+  // Allocate Resources
+  LanDriver = AllocateZeroPool (sizeof(NETSEC_DRIVER));
+  NetsecPath = AllocateCopyPool (sizeof(NETSEC_DEVICE_PATH),
+                                 &NetsecPathTemplate);
+
+  // Initialize pointers
+  Snp = &(LanDriver->Snp);
+  SnpMode = &(LanDriver->SnpMode);
+  Snp->Mode = SnpMode;
+
+  // Set the signature of the LAN Driver structure
+  LanDriver->Signature = NETSEC_SIGNATURE;
+
+  // Probe the device
+  Status = Probe (Handle, LanDriver);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "NETSEC:NetsecDxeEntry(): Probe failed with status %d\n", Status));
+    return Status;
+  }
+
+  // Assign fields and func pointers
+  Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
+  Snp->WaitForPacket = NULL;
+  Snp->Initialize = SnpInitialize;
+  Snp->Start = SnpStart;
+  Snp->Stop = SnpStop;
+  Snp->Reset = NULL;
+  Snp->Shutdown = SnpShutdown;
+  Snp->ReceiveFilters = SnpReceiveFilters;
+  Snp->StationAddress = NULL;
+  Snp->Statistics = NULL;
+  Snp->MCastIpToMac = NULL;
+  Snp->NvData = NULL;
+  Snp->GetStatus = SnpGetStatus;
+  Snp->Transmit = SnpTransmit;
+  Snp->Receive = SnpReceive;
+
+  // Fill in simple network mode structure
+  SnpMode->State = EfiSimpleNetworkStopped;
+  SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN;    // HW address is 6 bytes
+  SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD);  // Size of an Ethernet header
+  SnpMode->MaxPacketSize = EFI_PAGE_SIZE;         // Ethernet Frame (with VLAN tag +4 bytes)
+
+  // Supported receive filters
+  SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+                               EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+                               EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
+                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
+                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
+
+  // Initially-enabled receive filters
+  SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
+                                  EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
+                                  EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
+
+  // Netsec has 64bit hash table. We can filter an infinite MACs, but
+  // higher-level software must filter out any hash collisions.
+  SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
+  SnpMode->MCastFilterCount = 0;
+  ZeroMem (&SnpMode->MCastFilter,
+           MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
+
+  // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
+  SnpMode->IfType = NET_IFTYPE_ETHERNET;
+
+  // Mac address is changeable
+  SnpMode->MacAddressChangeable = TRUE;
+
+  // We can only transmit one packet at a time
+  SnpMode->MultipleTxSupported = FALSE;
+
+  // MediaPresent checks for cable connection and partner link
+  SnpMode->MediaPresentSupported = TRUE;
+  SnpMode->MediaPresent = FALSE;
+
+  //  Set broadcast address
+  SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
+
+  // Assign fields for device path
+  NetsecPath->Netsec.MacAddress = SnpMode->PermanentAddress;
+  NetsecPath->Netsec.IfType = SnpMode->IfType;
+
+  InitializeListHead (&LanDriver->TxBufferList);
+
+  // Initialise the protocol
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &LanDriver->ControllerHandle,
+                  &gEfiSimpleNetworkProtocolGuid, Snp,
+                  &gEfiDevicePathProtocolGuid, NetsecPath,
+                  NULL);
+
+  // Say what the status of loading the protocol structure is
+  if (EFI_ERROR(Status)) {
+    ogma_terminate (LanDriver->Handle);
+    FreePool (LanDriver);
+  }
+
+  return Status;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
new file mode 100644
index 000000000000..7537d1059b28
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
@@ -0,0 +1,47 @@
+## @file
+#
+#  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION              = 0x00010005
+  PACKAGE_NAME                   = OpenPlatformDriversNetNetsecDxePkg
+  PACKAGE_GUID                   = bd8ddfdd-2e8d-4081-8117-99405df3ffc8
+  PACKAGE_VERSION                = 0.1
+
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+#                   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Guids.common]
+  gNetsecDxeTokenSpaceGuid = { 0x47d6c028, 0x2413, 0x416d,  { 0xa8, 0xef, 0xe4, 0x5c, 0x58, 0x83, 0x5e, 0x49 }}
+
+[PcdsFixedAtBuild.common]
+  # Netsec Ethernet Driver PCDs
+  gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x0|UINT32|0x00000000
+  gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x0|UINT32|0x00000001
+  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|0x0|UINT16|0x00000002
+  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|0x0|UINT16|0x00000003
+  gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0x0|UINT8|0x00000004
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0x0|UINT8|0x00000005
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|0x0|UINT16|0x00000006
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|0x0|UINT16|0x00000007
+  gNetsecDxeTokenSpaceGuid.PcdPauseTime|0x0|UINT16|0x00000008
+  gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|0x0|UINT8|0x00000009
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
new file mode 100644
index 000000000000..f0acdc1448d7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
@@ -0,0 +1,88 @@
+/** @file
+
+  Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NETSEC_DXE_H_
+#define __NETSEC_DXE_H_
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+
+// Synchronization TPLs
+#define NETSEC_TPL        TPL_CALLBACK
+
+/*--------------- Simple Network Driver entry point functions ----------------*/
+
+// Refer to the Simple Network Protocol section (21.1)
+// in the UEFI 2.3.1 Specification for documentation.
+
+#define ReturnUnlock(s)   do { Status = (s); goto ExitUnlock; } while (0)
+
+/*------------------------------------------------------------------------------
+  NETSEC Information Structure
+------------------------------------------------------------------------------*/
+
+typedef struct {
+  // Driver signature
+  UINT32                            Signature;
+  EFI_HANDLE                        ControllerHandle;
+
+  // EFI SNP protocol instances
+  EFI_SIMPLE_NETWORK_PROTOCOL       Snp;
+  EFI_SIMPLE_NETWORK_MODE           SnpMode;
+
+  // EFI Snp statistics instance
+  EFI_NETWORK_STATISTICS            Stats;
+
+  // ogma handle
+  ogma_handle_t                     Handle;
+
+  // List of submitted TX buffers
+  LIST_ENTRY                        TxBufferList;
+
+  EFI_EVENT                         ExitBootEvent;
+} NETSEC_DRIVER;
+
+#define NETSEC_SIGNATURE            SIGNATURE_32('n', 't', 's', 'c')
+#define INSTANCE_FROM_SNP_THIS(a)   CR(a, NETSEC_DRIVER, Snp, NETSEC_SIGNATURE)
+
+typedef struct {
+  MAC_ADDR_DEVICE_PATH              Netsec;
+  EFI_DEVICE_PATH_PROTOCOL          End;
+} NETSEC_DEVICE_PATH;
+
+/*------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------*/
+
+#define EEPROM_BASE                 ((UINT32)PcdGet32(PcdEepRomBase))
+
+#define MAC_ADDRESS                 (0x00 + EEPROM_BASE)
+
+#define HM_ME_ADDRESS_H             (0x08 + EEPROM_BASE)
+#define HM_ME_ADDRESS_L             (0x0C + EEPROM_BASE)
+#define HM_ME_SIZE                  (0x10 + EEPROM_BASE)
+
+#define MH_ME_ADDRESS_H             (0x14 + EEPROM_BASE)
+#define MH_ME_ADDRESS_L             (0x18 + EEPROM_BASE)
+#define MH_ME_SIZE                  (0x1C + EEPROM_BASE)
+
+#define PACKET_ME_ADDRESS           (0x20 + EEPROM_BASE)
+#define PACKET_ME_SIZE              (0x24 + EEPROM_BASE)
+
+#define SCAT_NUM                    1
+
+#define RXINT_TMR_CNT_US            0
+#define RXINT_PKTCNT                1
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
new file mode 100644
index 000000000000..42de56d89c30
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
@@ -0,0 +1,69 @@
+## @file
+#
+# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = NetsecDxe
+  FILE_GUID                      = a4eed3af-9837-46b3-9275-c71cb47071f9
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 0.1
+  ENTRY_POINT                    = NetsecDxeEntry
+
+[Sources]
+  NetsecDxe.c
+
+  netsec_for_uefi/pfdep_uefi.c
+  netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
+  netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
+  netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
+  netsec_for_uefi/netsec_sdk/src/ogma_misc.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  NetworkPkg/NetworkPkg.dec
+  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DevicePathLib
+  DmaLib
+  IoLib
+  NetLib
+  SynchronizationLib
+  TimerLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Protocols]
+  gEfiSimpleNetworkProtocolGuid
+  gEfiDevicePathProtocolGuid
+
+[FixedPcd]
+  gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress
+  gNetsecDxeTokenSpaceGuid.PcdEepRomBase
+  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum
+  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum
+  gNetsecDxeTokenSpaceGuid.PcdJumboPacket
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold
+  gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr
+  gNetsecDxeTokenSpaceGuid.PcdPauseTime
+
+[Depex]
+  gEfiCpuArchProtocolGuid
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
new file mode 100644
index 000000000000..336325109e33
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
@@ -0,0 +1,736 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_API_H
+#define OGMA_API_H
+
+#include "ogma_version.h"
+#include "netsec_for_uefi/ogma_config.h"
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "netsec_for_uefi/pfdep.h"
+/**
+ * Check configuration macro settings.
+ */
+#ifdef OGMA_CONFIG_CLK_HZ
+#if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) )
+#error "OGMA_CONFIG_CLK_HZ is not appropriate."
+#endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */
+#else /* ! OGMA_CONFIG_CLK_HZ */
+#error "OGMA_CONFIG_CLK_HZ is not given."
+#endif /* OGMA_CONFIG_CLK_HZ */
+
+#ifndef OGMA_CONFIG_GMAC_CLK_HZ
+#define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ
+#endif
+
+/**
+ * Number of hardware limits
+ */
+
+
+/**
+ * Number of Common Descriptor ring id
+ */
+#define OGMA_DESC_RING_ID_NRM_TX 0
+#define OGMA_DESC_RING_ID_NRM_RX 1
+
+#define OGMA_DESC_RING_ID_GMAC   15
+#define OGMA_DESC_RING_ID_MAX    1
+
+/**
+ * Numbre of TCP Segmentation length limits
+ */
+#define OGMA_TCP_SEG_LEN_MAX 1460
+#define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960
+
+/**
+ * Number of ER check result for received packet
+ */
+#define OGMA_RX_ER_RESULT_NG       0x1
+#define OGMA_RX_ER_RESULT_OK       0x0
+
+/**
+ * Number of checksum calculation result for received packet
+ */
+#define OGMA_RX_CKSUM_RESULT_OK       0x1
+#define OGMA_RX_CKSUM_RESULT_NG       0x2
+#define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0
+
+/**
+ * Number of ErrorCode for received packet
+ */
+#define OGMA_RX_ERRCODE_HEADER_INCOMLETE_ERR   0x2
+#define OGMA_RX_ERRCODE_IP_HEADER_ERR          0x1
+#define OGMA_RX_ERRCODE_NONE                   0x0
+
+/**
+ * Number of top interrupt enable register bit field
+ */
+#define OGMA_TOP_IRQ_REG_ME_START        (1UL << 20)
+#define OGMA_TOP_IRQ_REG_MAC             (1UL << 19)
+#define OGMA_TOP_IRQ_REG_PKT             (1UL << 18)
+#define OGMA_TOP_IRQ_REG_BOOTCODE_TX     (1UL <<  5)
+#define OGMA_TOP_IRQ_REG_NRM_RX          (1UL <<  1)
+#define OGMA_TOP_IRQ_REG_NRM_TX          (1UL <<  0)
+
+
+/**
+ *  Number of top channel enable register bit field
+ */
+#define OGMA_CH_IRQ_REG_EMPTY   (1UL << 17)
+#define OGMA_CH_IRQ_REG_ERR     (1UL << 16)
+#define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15)
+#define OGMA_CH_IRQ_REG_TIMEUP  (1UL << 14)
+#define OGMA_CH_IRQ_REG_RCV     (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP)
+
+/**
+ *  Number of top channel enable register bit field for F_NETSEC_C
+ */
+#define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15)
+#define OGMA_CH_IRQ_REG_SND     (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP)
+
+
+/**
+ *  Number of packet interrupt enable register bit field
+ */
+#define OGMA_PKT_IRQ_MAC_ER            (1UL << 5)
+#define OGMA_PKT_IRQ_JUMBO_ER          (1UL << 4)
+#define OGMA_PKT_IRQ_CHKSUM_ER         (1UL << 3)
+#define OGMA_PKT_IRQ_HD_INCOMPLETE     (1UL << 2)
+#define OGMA_PKT_IRQ_HD_ER             (1UL << 1)
+#define OGMA_PKT_IRQ_DRP_NO_MATCH      (1UL << 0)
+
+
+/**
+ *  Number of mac irq enable register bit field
+ */
+#define OGMA_MAC_IRQ_INT_PMT (1UL << 31)
+#define OGMA_MAC_IRQ_INT_SBD (1UL << 30)
+#define OGMA_MAC_IRQ_INT_LPI (1UL << 29)
+#define OGMA_MAC_IRQ_INT_MAC_TX_RX_INFO_INT (1UL << 27)
+#define OGMA_MAC_IRQ_INT_LPI_TX_ENTRY (1UL << 26)
+#define OGMA_MAC_IRQ_INT_LPI_RX_ENTRY (1UL << 25)
+#define OGMA_MAC_IRQ_INT_LPI_TX_EXIT (1UL << 24)
+#define OGMA_MAC_IRQ_INT_LPI_RX_EXIT (1UL << 23)
+
+
+/**
+ *  Number of SR IER register bit field
+ */
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GLPII (1U << 30)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TTI   (1U << 29)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GPI   (1U << 28)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GMI   (1U << 27)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_GLI   (1U << 26)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_NIS   (1U << 16)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_AIS   (1U << 15)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ERI   (1U << 14)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_FBI   (1U << 13)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ETI   (1U << 10)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RWT   (1U << 9)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RPS   (1U << 8)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RU    (1U << 7)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_RI    (1U << 6)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_UNF   (1U << 5)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_OVF   (1U << 4)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TJT   (1U << 3)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TU    (1U << 2)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TPS   (1U << 1)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_TI    (1U << 0)
+#define OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_RU  | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_RI  | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_TU  | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+                                          OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+#define OGMA_GMAC_INT_SBD_IRQ_SR_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_GLPII | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_TTI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_GPI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_GMI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_GLI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_NIS   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_AIS   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_ERI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_FBI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_ETI   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_RWT   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_RPS   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_RU    | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_RI    | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_UNF   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_OVF   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_TJT   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_TU    | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_TPS   | \
+                                       OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+#define OGMA_GMAC_INT_SBD_IRQ_IER_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_RU  | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_RI  | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_TU  | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
+                                        OGMA_GMAC_INT_SBD_IRQ_SR_TI)
+
+/**
+ *  Number of ISR IMR register bit field
+ */
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_LPII (1U << 10)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_TSI  (1U << 9)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_COI  (1U << 7)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_TI   (1U << 6)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_RI   (1U << 5)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_MI   (1U << 4)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_PI   (1U << 3)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_RGI  (1U << 0)
+#define OGMA_GMAC_INT_SBD_IRQ_ISR_ALL ( OGMA_GMAC_INT_SBD_IRQ_ISR_LPII | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_TSI  | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_COI  | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_TI   | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_RI   | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_MI   | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_PI   | \
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_RGI)
+
+/**
+ *  Number of LPICSR register bit field
+ */
+#define OGMA_GMAC_LPICSR_REG_LPITXA (1U << 19)
+#define OGMA_GMAC_LPICSR_REG_PLSEN  (1U << 18)
+#define OGMA_GMAC_LPICSR_REG_PLS    (1U << 17)
+#define OGMA_GMAC_LPICSR_REG_LPIEN  (1U << 16)
+#define OGMA_GMAC_LPICSR_REG_RLPIST (1U << 9)
+#define OGMA_GMAC_LPICSR_REG_TLPIST (1U << 8)
+#define OGMA_GMAC_LPICSR_REG_RLPIEX (1U << 3)
+#define OGMA_GMAC_LPICSR_REG_RLPIEN (1U << 2)
+#define OGMA_GMAC_LPICSR_REG_TLPIEX (1U << 1)
+#define OGMA_GMAC_LPICSR_REG_TLPIEN (1U << 0)
+
+/**
+ *  Number of RGSR register bit field
+ */
+#define OGMA_GMAC_RGSR_REG_LS  (1U << 3)
+#define OGMA_GMAC_RGSR_REG_LSP (1U << 1)
+#define OGMA_GMAC_RGSR_REG_LM  (1U << 0)
+
+/**
+ * Number of various limits
+ */
+#define OGMA_DESC_ENTRY_NUM_MIN        2
+#define OGMA_DESC_ENTRY_NUM_MAX        2047
+#define OGMA_INT_PKTCNT_MAX            2047
+#define OGMA_L4_MIN_LEN_MAX            64
+
+/**
+ * Number of ogma phy interface setting
+ */
+#define OGMA_PHY_INTERFACE_GMII  0
+#define OGMA_PHY_INTERFACE_RGMII 1
+#define OGMA_PHY_INTERFACE_RMII  4
+
+/**
+ * Number of ogma link speed setting
+ */
+#define OGMA_PHY_LINK_SPEED_1G          0
+#define OGMA_PHY_LINK_SPEED_100M        1U
+#define OGMA_PHY_LINK_SPEED_10M         2U
+#define OGMA_PHY_LINK_SPEED_100M_OR_10M 3U
+
+/**
+ * Number of flow control limits
+ */
+#define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 95
+#define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX  95
+#define OGMA_FLOW_CTRL_PAUSE_TIME_MIN      5
+
+enum ogma_err_e{
+    OGMA_ERR_OK = 0,
+    OGMA_ERR_PARAM,
+    OGMA_ERR_ALLOC,
+    OGMA_ERR_BUSY,
+    OGMA_ERR_RANGE,
+    OGMA_ERR_DATA,
+    OGMA_ERR_NOTAVAIL,
+    OGMA_ERR_INTERRUPT,
+    OGMA_ERR_AGAIN,
+    OGMA_ERR_INVALID,
+};
+
+typedef void *ogma_handle_t;
+typedef struct ogma_param_s ogma_param_t;
+typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t;
+typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t;
+typedef enum ogma_err_e ogma_err_t;
+typedef ogma_uint8 ogma_desc_ring_id_t;
+typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t;
+typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t;
+typedef struct ogma_frag_info_s ogma_frag_info_t;
+typedef struct ogma_gmac_config_s ogma_gmac_config_t;
+typedef struct ogma_gmac_mode_s ogma_gmac_mode_t;
+
+struct ogma_gmac_config_s{
+    ogma_uint8 phy_interface;
+};
+
+struct ogma_pkt_ctrl_param_s{
+    ogma_uint log_chksum_er_flag:1;
+    ogma_uint log_hd_imcomplete_flag:1;
+    ogma_uint log_hd_er_flag:1;
+    ogma_uint drp_no_match_flag:1;
+};
+
+struct ogma_desc_ring_param_s{
+    ogma_uint valid_flag:1;
+    ogma_uint little_endian_flag:1;
+    ogma_uint tmr_mode_flag:1;
+    ogma_uint16 entry_num;
+};
+
+struct ogma_param_s{
+
+    ogma_uint use_gmac_flag:1;
+    ogma_uint use_jumbo_pkt_flag:1;
+    ogma_pkt_ctrl_param_t pkt_ctrl_param;
+    ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1];
+    ogma_gmac_config_t gmac_config;
+    ogma_uint8 mac_addr[6];
+};
+
+struct ogma_tx_pkt_ctrl_s{
+    ogma_uint pass_through_flag:1;
+    ogma_uint cksum_offload_flag:1;
+    ogma_uint tcp_seg_offload_flag:1;
+    ogma_desc_ring_id_t target_desc_ring_id;
+    ogma_uint16 tcp_seg_len;
+};
+
+struct ogma_rx_pkt_info_s{
+    ogma_uint fragmented_flag:1;
+    ogma_uint err_flag:1;
+    ogma_uint rx_cksum_result:2;
+    ogma_uint8 err_code;
+};
+
+struct ogma_frag_info_s{
+    pfdep_phys_addr_t phys_addr;
+    void *addr;
+    ogma_uint32 len;
+};
+
+struct ogma_gmac_mode_s{
+    ogma_uint half_duplex_flag:1;
+    ogma_uint flow_ctrl_enable_flag:1;
+    ogma_uint8 link_speed;
+    ogma_uint16 flow_ctrl_start_threshold;
+    ogma_uint16 flow_ctrl_stop_threshold;
+    ogma_uint16 pause_time;
+};
+
+#ifdef OGMA_CONFIG_REC_STAT
+typedef struct ogma_stat_info_s {
+    ogma_uint16 current_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
+    ogma_uint16 max_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
+} ogma_stat_info_t;
+#endif /* OGMA_CONFIG_REC_STAT */
+
+typedef struct ogma_gmac_int_sbd_regs_s{
+    ogma_uint32 base;
+    ogma_uint32 extended;
+} ogma_gmac_int_sbd_regs_t;
+
+typedef struct ogma_phy_link_status_s{
+    ogma_uint up_flag:1;
+    ogma_uint auto_nego_enable_flag:1;
+    ogma_uint auto_nego_complete_flag:1;
+    ogma_uint half_duplex_flag:1;
+    ogma_uint latched_link_down_flag:1;
+    ogma_uint lpi_capable_flag:1;
+    ogma_uint8 link_speed;
+} ogma_phy_link_status_t;
+
+/**************************
+***************************
+***************************/
+
+ogma_err_t ogma_init (
+    void *base_addr,
+    pfdep_dev_handle_t dev_handle,
+    const ogma_param_t *param_p,
+    const void *dma_hm_mc_addr,
+    ogma_uint32 dma_hm_mc_len,
+    const void *dma_mh_mc_addr,
+    ogma_uint32 dma_mh_mc_len,
+    const void *pktc_mc_addr,
+    ogma_uint32 pktc_mc_len,
+    ogma_handle_t *ogma_handle_p
+    );
+
+void ogma_terminate (
+    ogma_handle_t ogma_handle
+    );
+
+ogma_err_t ogma_start_gmac (
+    ogma_handle_t ogma_handle,
+    ogma_bool rx_flag,
+    ogma_bool tx_flag
+    );
+
+ogma_err_t ogma_stop_gmac (
+    ogma_handle_t ogma_handle,
+    ogma_bool rx_flag,
+    ogma_bool tx_flag
+    );
+
+ogma_err_t ogma_set_gmac_mode (
+    ogma_handle_t ogma_handle,
+    const ogma_gmac_mode_t *gmac_mode_p
+    );
+
+void ogma_set_phy_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr,
+    ogma_uint16 value
+    );
+
+ogma_uint16 ogma_get_phy_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr
+    );
+
+ogma_err_t ogma_get_gmac_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool *valid_flag_p,
+    ogma_gmac_mode_t *gmac_mode_p,
+    ogma_bool *rx_running_flag_p,
+    ogma_bool *tx_running_flag_p
+    );
+
+ogma_uint32 ogma_get_top_irq_enable (
+    ogma_handle_t ogma_handle
+    );
+
+ogma_uint32 ogma_get_top_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    );
+
+#define ogma_get_top_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_top_irq_status(ogma_handle,mask_flag)
+
+ogma_err_t ogma_clear_top_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    );
+
+ogma_uint32 ogma_get_desc_ring_irq_enable (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_uint32 ogma_get_desc_ring_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_bool mask_flag
+    );
+
+#define ogma_get_desc_ring_irq_status_non_clear(ogma_handle,ring_id,mask_flag) \
+ogma_get_desc_ring_irq_status(ogma_handle,ring_id,mask_flag)
+
+
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint32 value
+    );
+
+ogma_uint32 ogma_get_pkt_irq_enable (
+    ogma_handle_t ogma_handle
+    );
+
+ogma_uint32 ogma_get_pkt_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    );
+
+#define ogma_get_pkt_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_pkt_irq_status(ogma_handle,mask_flag)
+
+
+ogma_err_t ogma_clear_pkt_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    );
+
+/* ogma_desc_ring_access.c */
+ogma_err_t ogma_start_desc_ring (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_err_t ogma_stop_desc_ring (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_uint16 ogma_get_rx_num (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_uint16 ogma_get_tx_avail_num (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_err_t ogma_clean_tx_desc_ring(
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_err_t ogma_clean_rx_desc_ring(
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    );
+
+ogma_err_t ogma_set_tx_pkt_data (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+    ogma_uint8 scat_num,
+    const ogma_frag_info_t *scat_info_p,
+    pfdep_pkt_handle_t pkt_handle
+    );
+
+ogma_err_t ogma_get_rx_pkt_data (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_rx_pkt_info_t *rx_pkt_info_p,
+    ogma_frag_info_t *frag_info_p,
+    ogma_uint16 *len_p,
+    pfdep_pkt_handle_t *pkt_handle_p
+    );
+
+ogma_err_t ogma_enable_top_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    );
+
+ogma_err_t ogma_disable_top_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    );
+
+ogma_err_t ogma_enable_desc_ring_irq (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint32 irq_factor
+    );
+
+ogma_err_t ogma_disable_desc_ring_irq (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint32 irq_factor
+    );
+
+ogma_err_t ogma_enable_pkt_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    );
+
+ogma_err_t ogma_disable_pkt_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    );
+
+ogma_uint32 ogma_get_hw_ver (
+    ogma_handle_t ogma_handle
+    );
+
+ogma_uint32 ogma_get_mcr_ver (
+    ogma_handle_t ogma_handle
+    );
+
+/**
+ * Set up IRQ coalesce parameters.
+ *
+ * [Note]
+ *  - This is a tentative implementation.
+ *    Not tested enough. Use with care.
+ *
+ *  - Call this function after every invocation of ogma_start_desc_ring()
+ *    because ogma_start_desc_ring() resets IRQ coalesce settings.
+ *
+ */
+ogma_err_t ogma_set_irq_coalesce_param (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint16 int_pktcnt,
+    ogma_bool int_tmr_unit_ms_flag,
+    ogma_uint16 int_tmr_cnt
+    );
+
+ogma_uint32 ogma_get_mac_irq_enable (
+    ogma_handle_t ogma_handle
+    );
+
+
+ogma_uint32 ogma_get_mac_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    );
+
+#define ogma_get_mac_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_mac_irq_status(ogma_handle,mask_flag)
+
+
+ogma_err_t ogma_clear_mac_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    );
+
+ogma_err_t ogma_enable_mac_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    );
+
+ogma_err_t ogma_disable_mac_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    );
+
+#ifdef OGMA_CONFIG_REC_STAT
+/**
+ * Get statistics information.
+ */
+ogma_err_t ogma_get_stat_info (
+    ogma_handle_t ogma_handle,
+    ogma_stat_info_t *stat_info_p,
+    ogma_bool clear_flag
+    );
+#endif /* OGMA_CONFIG_REC_STAT */
+
+ogma_err_t ogma_set_gmac_lpictrl_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    );
+
+ogma_err_t ogma_get_gmac_lpictrl_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 *value_p
+    );
+
+ogma_err_t ogma_set_gmac_lpitimer_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint16 ls_timer_ms,
+    ogma_uint16 tw_timer_ms
+    );
+
+ogma_err_t ogma_get_gmac_lpitimer_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint16 *ls_timer_ms_p,
+    ogma_uint16 *tw_timer_ms_p
+    );
+
+void ogma_set_phy_mmd_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr,
+    ogma_uint16 value
+    );
+
+ogma_uint16 ogma_get_phy_mmd_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr
+    );
+
+ogma_err_t ogma_get_phy_link_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_phy_link_status_t *phy_link_status_p
+    );
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
+    ogma_handle_t ogma_handle
+    );
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    );
+
+#define ogma_get_gmac_int_sbd_irq_status_non_clear(ogma_handle,mask_flag) \
+ogma_get_gmac_int_sbd_irq_status(ogma_handle,mask_flag)
+
+ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_gmac_int_sbd_regs_t int_sbd_regs
+    );
+
+ogma_err_t ogma_enable_gmac_int_sbd_irq (
+    ogma_handle_t ogma_handle,
+    ogma_gmac_int_sbd_regs_t int_sbd_regs
+    );
+
+ogma_err_t ogma_disable_gmac_int_sbd_irq (
+    ogma_handle_t ogma_handle,
+    ogma_gmac_int_sbd_regs_t int_sbd_regs
+    );
+
+ogma_err_t ogma_get_gmac_rgmii_status_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 *value_p
+    );
+
+#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
+ogma_err_t ogma_read_gmac_stat (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 *value_p,
+    ogma_bool reset_flag
+    );
+#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
+
+ogma_err_t ogma_reset_gmac_stat (
+    ogma_handle_t ogma_handle
+    );
+
+/**************************
+***************************
+***************************/
+
+#endif /* OGMA_API_H*/
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
new file mode 100644
index 000000000000..7c39b7c9cdd7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
@@ -0,0 +1,45 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_BASIC_TYPE_H
+#define OGMA_BASIC_TYPE_H
+#include "netsec_for_uefi/pfdep.h"
+
+/**
+ *
+ */
+#define OGMA_TRUE  PFDEP_TRUE
+#define OGMA_FALSE PFDEP_FALSE
+
+/**
+ * OGMA SDK BASIC DATA TYPE
+ */
+typedef pfdep_int8 ogma_int8;
+typedef pfdep_uint8 ogma_uint8;
+typedef pfdep_int16 ogma_int16;
+typedef pfdep_uint16 ogma_uint16;
+typedef pfdep_int32 ogma_int32;
+typedef pfdep_uint32 ogma_uint32;
+typedef int ogma_int;
+typedef unsigned int ogma_uint;
+typedef pfdep_bool ogma_bool;
+typedef pfdep_char ogma_char;
+
+#ifdef PFDEP_INT64_AVAILABLE
+typedef signed long long ogma_int64;
+typedef unsigned long long ogma_uint64;
+#endif /* PFDEP_INT64_AVAILABLE*/
+
+#endif /* OGMA_BASIC_TYPE_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
new file mode 100644
index 000000000000..61335b96db77
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
@@ -0,0 +1,24 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_VERSION_H
+#define OGMA_VERSION_H
+
+#define OGMA_VER_NETSEC   (0x00050050UL)
+
+#define OGMA_INVALID_VER             0x0
+#define OGMA_VER_MAJOR_NUM(x) (x&0xffff0000UL)
+
+#endif /* OGMA_VERSION_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
new file mode 100644
index 000000000000..7b399beaedb2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
@@ -0,0 +1,88 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+void ogma_set_mac_reg (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 addr,
+    ogma_uint32 value)
+{
+
+    ogma_uint32 cmd;
+
+    ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+    /*
+     * Argument check is omitted because this function is
+     * of private use only.
+     */
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_MAC_DATA,
+                    value);
+
+    cmd = addr | OGMA_GMAC_CMD_ST_WRITE;
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_MAC_CMD,
+                    cmd);
+
+    /*
+     * Waits until BUSY bit is cleared.
+     */
+    while ( ( ogma_read_reg( ctrl_p,
+                             OGMA_REG_ADDR_MAC_CMD)
+              & OGMA_GMAC_CMD_ST_BUSY)
+            != 0) {
+        ;
+    }
+}
+
+ogma_uint32 ogma_get_mac_reg (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 addr)
+{
+    ogma_uint32 cmd;
+
+    ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+    /*
+     * Argument check is omitted because this function is
+     * of private use only.
+     */
+
+    cmd = addr | OGMA_GMAC_CMD_ST_READ;
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_MAC_CMD,
+                    cmd);
+
+    /*
+     * Waits until BUSY bit is cleared.
+     */
+    while ( ( ogma_read_reg( ctrl_p,
+                             OGMA_REG_ADDR_MAC_CMD)
+              & OGMA_GMAC_CMD_ST_BUSY)
+            != 0) {
+        ;
+    }
+    return ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DATA);
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
new file mode 100644
index 000000000000..a81b9249f4a2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
@@ -0,0 +1,52 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_BASIC_ACCESS_H
+#define OGMA_BASIC_ACCESS_H
+
+#include "ogma_internal.h"
+
+static __inline void ogma_write_reg (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 reg_addr,
+    ogma_uint32 value
+    )
+{
+
+    pfdep_iomem_write( (void *) ( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
+                                  ( reg_addr << 2) ),
+                       value);
+}
+
+static __inline ogma_uint32 ogma_read_reg (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 reg_addr
+    )
+{
+
+    return ( ogma_uint32)pfdep_iomem_read( (void *)( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
+                                                     ( reg_addr << 2) ) );
+}
+
+void ogma_set_mac_reg (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 addr,
+    ogma_uint32 value);
+
+ogma_uint32 ogma_get_mac_reg (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 addr);
+
+#endif/* OGMA_BASIC_ACCESS_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
new file mode 100644
index 000000000000..a38aff3ce4a5
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
@@ -0,0 +1,1391 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+#include "ogma_desc_ring_access_internal.h"
+
+
+const ogma_uint32 ogma_desc_start_reg_addr_upper[OGMA_DESC_RING_ID_MAX+1] = {
+    OGMA_REG_ADDR_NRM_TX_DESC_START_UP,
+    OGMA_REG_ADDR_NRM_RX_DESC_START_UP,
+};
+
+const ogma_uint32 ogma_desc_start_reg_addr_lower[OGMA_DESC_RING_ID_MAX+1] = {
+    OGMA_REG_ADDR_NRM_TX_DESC_START_LW,
+    OGMA_REG_ADDR_NRM_RX_DESC_START_LW,
+};
+
+const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+    OGMA_REG_ADDR_NRM_TX_INTEN,
+    OGMA_REG_ADDR_NRM_RX_INTEN,
+};
+
+const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+    OGMA_REG_ADDR_NRM_TX_INTEN_SET,
+    OGMA_REG_ADDR_NRM_RX_INTEN_SET,
+};
+
+const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+    OGMA_REG_ADDR_NRM_TX_INTEN_CLR,
+    OGMA_REG_ADDR_NRM_RX_INTEN_CLR,
+};
+
+static const ogma_uint32 int_tmr_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+    OGMA_REG_ADDR_NRM_TX_TXINT_TMR,
+    OGMA_REG_ADDR_NRM_RX_RXINT_TMR,
+};
+
+static const ogma_uint32 rx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+    0,
+    OGMA_REG_ADDR_NRM_RX_PKTCNT,
+};
+
+static const ogma_uint32 tx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+    OGMA_REG_ADDR_NRM_TX_PKTCNT,
+    0,
+
+};
+
+static const ogma_uint32 int_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+    OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT,
+    OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT,
+};
+
+static const ogma_uint32 tx_done_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
+    OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT,
+    0,
+};
+
+
+STATIC void ogma_set_tx_desc_entry (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+    ogma_bool first_flag,
+    ogma_bool last_flag,
+    ogma_bool trs_flag,
+    const ogma_frag_info_t *frag_info_p,
+    pfdep_pkt_handle_t pkt_handle);
+
+STATIC void ogma_set_rx_desc_entry (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    const ogma_frag_info_t *frag_info_p,
+    pfdep_pkt_handle_t pkt_handle);
+
+STATIC void ogma_get_rx_desc_entry (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    ogma_rx_pkt_info_t *rx_pkt_info_p,
+    ogma_frag_info_t *frag_info_p,
+    ogma_uint16 *len_p,
+    pfdep_pkt_handle_t *pkt_handle_p);
+
+STATIC void ogma_clean_tx_desc_ring_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    );
+
+STATIC void ogma_clean_rx_desc_ring_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    );
+
+STATIC void ogma_inc_desc_head_idx (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 increment);
+
+STATIC void ogma_inc_desc_tail_idx (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 increment);
+
+STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
+    ogma_ctrl_t *ctrl_p,
+    const ogma_desc_ring_t *desc_ring_p
+    );
+
+STATIC ogma_uint16 ogma_get_tx_done_num_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    );
+
+static __inline void ogma_desc_ring_cpy_to_mem(
+        void *dst_p,
+        void *src_p,
+        ogma_uint32 len)
+{
+    pfdep_memcpy(dst_p,src_p,len);
+}
+
+static __inline void ogma_desc_ring_cpy_from_mem(
+        void *dst_p,
+        void *src_p,
+        ogma_uint32 len)
+{
+    pfdep_memcpy(dst_p,src_p,len);
+}
+
+static __inline void ogma_desc_ring_memclr(
+        void *dst_p,
+        ogma_uint32 len)
+{
+    pfdep_memset(dst_p,0,len);
+}
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_alloc_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_desc_ring_t *desc_ring_p = &ctrl_p->desc_ring[ring_id];
+    ogma_desc_ring_param_t *desc_ring_param_p = &ctrl_p->desc_ring[ring_id].param;
+    pfdep_err_t pfdep_err;
+
+    if ( ( ctrl_p->param.desc_ring_param[ring_id].valid_flag) &&
+         ( ( ctrl_p->param.desc_ring_param[ring_id].entry_num <
+             OGMA_DESC_ENTRY_NUM_MIN) ||
+           ( ctrl_p->param.desc_ring_param[ring_id].entry_num >
+             OGMA_DESC_ENTRY_NUM_MAX) ) ) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_alloc_desc_ring.\n"
+                     "Please set entry_num between %d and %d.\n",
+                     OGMA_DESC_ENTRY_NUM_MIN, OGMA_DESC_ENTRY_NUM_MAX);
+        return OGMA_ERR_PARAM;
+    }
+
+    desc_ring_p->ring_id = ring_id;
+
+    pfdep_memcpy( desc_ring_param_p,
+                  &ctrl_p->param.desc_ring_param[ring_id],
+                  sizeof( ogma_desc_ring_param_t) );
+
+    if ( !desc_ring_param_p->valid_flag) {
+
+        desc_ring_p->desc_ring_phys_addr = ctrl_p->dummy_desc_entry_phys_addr;
+
+        ogma_write_reg( ctrl_p,
+                        ogma_desc_start_reg_addr_upper[ring_id],
+                        (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
+        ogma_write_reg( ctrl_p,
+                        ogma_desc_start_reg_addr_lower[ring_id],
+                        (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
+
+        return OGMA_ERR_OK;
+    }
+
+    switch ( ring_id) {
+    case OGMA_DESC_RING_ID_NRM_TX:
+        desc_ring_p->tx_desc_ring_flag = OGMA_TRUE;
+        desc_ring_p->desc_entry_len = sizeof( ogma_tx_desc_entry_t);
+        break;
+
+    case OGMA_DESC_RING_ID_NRM_RX:
+        desc_ring_p->rx_desc_ring_flag = OGMA_TRUE;
+        desc_ring_p->desc_entry_len = sizeof( ogma_rx_desc_entry_t);
+        break;
+
+    default:
+        pfdep_assert(0);
+    }
+
+    if ( ( pfdep_err = pfdep_init_hard_lock ( &desc_ring_p->inten_reg_hard_lock) )
+         != PFDEP_ERR_OK) {
+        pfdep_memset( desc_ring_param_p,
+                      0,
+                      sizeof( ogma_desc_ring_param_t) );
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_alloc_desc_ring.\n"
+                     "Failed to inten_reg_hard_lock's initialization.\n");
+        return OGMA_ERR_ALLOC;
+    }
+
+    if ( ( pfdep_err = pfdep_init_soft_lock ( &desc_ring_p->soft_lock) )
+         != PFDEP_ERR_OK) {
+        pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
+        pfdep_memset( desc_ring_param_p,
+                      0,
+                      sizeof( ogma_desc_ring_param_t) );
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_alloc_desc_ring.\n"
+                     "Failed to soft_lock's initialization.\n");
+        return OGMA_ERR_ALLOC;
+    }
+
+    if ( ( pfdep_err = pfdep_dma_malloc (
+               ( pfdep_dev_handle_t) ctrl_p->dev_handle,
+               ( pfdep_uint32) desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num,
+               ( void **) &desc_ring_p->desc_ring_cpu_addr,
+               ( pfdep_phys_addr_t *) &desc_ring_p->desc_ring_phys_addr) )
+         != PFDEP_ERR_OK) {
+        ogma_err = OGMA_ERR_ALLOC;
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_alloc_desc_ring.\n"
+                     "Failed to desc_ring entry memory allocation.\n");
+        goto err;
+    }
+
+    ogma_desc_ring_memclr(
+        desc_ring_p->desc_ring_cpu_addr,
+        ( ogma_uint32)desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num);
+
+    ogma_write_reg( ctrl_p,
+                    ogma_desc_start_reg_addr_upper[ring_id],
+                    (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
+    ogma_write_reg( ctrl_p,
+                    ogma_desc_start_reg_addr_lower[ring_id],
+                    (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
+
+    if ( ( desc_ring_p->frag_info_p =
+           pfdep_malloc( sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num) )
+         == NULL) {
+        ogma_err = OGMA_ERR_ALLOC;
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_alloc_desc_ring.\n"
+                     "Failed to fragment infomation memory allocation.\n");
+        goto err;
+    }
+
+    pfdep_memset(
+        desc_ring_p->frag_info_p,
+        0,
+        sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num);
+
+    if ( ( desc_ring_p->priv_data_p =
+           pfdep_malloc( sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num) )
+         == NULL) {
+        ogma_err = OGMA_ERR_ALLOC;
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_alloc_desc_ring.\n"
+                     "Failed to private data memory allocation.\n");
+        goto err;
+    }
+
+    pfdep_memset(
+        desc_ring_p->priv_data_p,
+        0,
+        sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num);
+
+    return OGMA_ERR_OK;
+
+err:
+    ogma_free_desc_ring( ctrl_p, desc_ring_p);
+    return ogma_err;
+}
+
+void ogma_free_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    )
+{
+
+    if ( !desc_ring_p->param.valid_flag) {
+        return ;
+    }
+    if ( ogma_is_pkt_desc_ring ( desc_ring_p) ) {
+        if ( ( desc_ring_p->desc_ring_cpu_addr != NULL) &&
+             ( desc_ring_p->frag_info_p != NULL) &&
+             ( desc_ring_p->priv_data_p != NULL) ) {
+            ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
+        }
+    }
+    if ( desc_ring_p->desc_ring_cpu_addr != NULL) {
+        pfdep_dma_free( ctrl_p->dev_handle,
+                        ( ogma_uint32)desc_ring_p->desc_entry_len *
+                        desc_ring_p->param.entry_num,
+                        desc_ring_p->desc_ring_cpu_addr,
+                        desc_ring_p->desc_ring_phys_addr);
+    }
+
+    if ( desc_ring_p->frag_info_p != NULL) {
+        pfdep_free(desc_ring_p->frag_info_p);
+    }
+
+    if ( desc_ring_p->priv_data_p != NULL) {
+        pfdep_free( desc_ring_p->priv_data_p);
+    }
+
+    pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
+
+    pfdep_uninit_soft_lock ( &desc_ring_p->soft_lock);
+
+    pfdep_memset( desc_ring_p, 0, sizeof( ogma_desc_ring_t) );
+}
+
+ogma_err_t ogma_setup_rx_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    )
+{
+    ogma_uint16 idx;
+    ogma_frag_info_t frag_info= {0,0,0};
+
+    pfdep_err_t pfdep_err;
+    pfdep_pkt_handle_t tmp_pkt_handle;
+
+    frag_info.len = ctrl_p->rx_pkt_buf_len;
+
+    for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
+        if ( ( pfdep_err = pfdep_alloc_pkt_buf (
+                   ( pfdep_dev_handle_t)ctrl_p->dev_handle,
+                   ( ogma_uint16)frag_info.len,
+                   ( void **)&frag_info.addr,
+                   ( pfdep_phys_addr_t *)&frag_info.phys_addr,
+                   ( pfdep_pkt_handle_t *)&tmp_pkt_handle) )
+             != PFDEP_ERR_OK) {
+            ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "An error occurred at ogma_setup_rx_desc_ring.\n"
+                         "Failed to rx packet memory allocation.\n");
+            return OGMA_ERR_ALLOC;
+        }
+        ogma_set_rx_desc_entry( ctrl_p,
+                                desc_ring_p,
+                                idx,
+                                &frag_info,
+                                tmp_pkt_handle);
+    }
+    return OGMA_ERR_OK;
+}
+
+void ogma_uninit_pkt_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    )
+{
+    ogma_uint16 idx;
+    ogma_uint32 tmp;
+    ogma_bool last_flag;
+
+    for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
+        if ( desc_ring_p->frag_info_p[idx].addr == NULL ) {
+            continue;
+        }
+
+        tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
+
+        last_flag = ( ( ( tmp >> 8) & 0x1) != 0);
+
+        pfdep_free_pkt_buf (
+            ctrl_p->dev_handle,
+            desc_ring_p->frag_info_p[idx].len,
+            desc_ring_p->frag_info_p[idx].addr,
+            desc_ring_p->frag_info_p[idx].phys_addr,
+            last_flag,
+            desc_ring_p->priv_data_p[idx].pkt_handle);
+    }
+
+    /* clear frag_info_p */
+    pfdep_memset( desc_ring_p->frag_info_p,
+                  0,
+                  sizeof( ogma_frag_info_t) * desc_ring_p->param.entry_num);
+
+    /* clear pkt_handle_p */
+    pfdep_memset( desc_ring_p->priv_data_p,
+                  0,
+                  sizeof( ogma_desc_entry_priv_t) * desc_ring_p->param.entry_num);
+
+    /* clear desc ring entry*/
+    ogma_desc_ring_memclr ( desc_ring_p->desc_ring_cpu_addr,
+                            ( ogma_uint32)desc_ring_p->desc_entry_len *
+                            desc_ring_p->param.entry_num);
+}
+
+STATIC void ogma_set_tx_desc_entry (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+    ogma_bool first_flag,
+    ogma_bool last_flag,
+    ogma_bool trs_flag,
+    const ogma_frag_info_t *frag_info_p,
+    pfdep_pkt_handle_t pkt_handle
+    )
+{
+    ogma_tx_desc_entry_t tx_desc_entry;
+    ogma_uint32 attr, i, *debug_desc_entry_p;
+
+    ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
+
+    pfdep_memset( &tx_desc_entry, 0, sizeof( ogma_tx_desc_entry_t) );
+
+    attr = ( 1UL << OGMA_TX_PKT_DESC_RING_OWN_FIELD) |
+        ( desc_ring_p->ring_id << OGMA_TX_PKT_DESC_RING_DRID_FIELD) |
+        ( tx_pkt_ctrl_p->pass_through_flag <<
+          OGMA_TX_PKT_DESC_RING_PT_FIELD) |
+        ( tx_pkt_ctrl_p->target_desc_ring_id <<
+          OGMA_TX_PKT_DESC_RING_TDRID_FIELD) |
+        ( first_flag << OGMA_TX_PKT_DESC_RING_FS_FIELD) |
+        ( last_flag << OGMA_TX_PKT_DESC_RING_LS_FIELD) |
+        ( tx_pkt_ctrl_p->cksum_offload_flag <<
+          OGMA_TX_PKT_DESC_RING_CO_FIELD) |
+        ( tx_pkt_ctrl_p->tcp_seg_offload_flag <<
+          OGMA_TX_PKT_DESC_RING_SO_FIELD) |
+        ( trs_flag << OGMA_TX_PKT_DESC_RING_TRS_FIELD);
+
+    if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
+        attr |= ( 0x1U << OGMA_TX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+    }
+
+    tx_desc_entry.attr = attr;
+
+    tx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
+
+    tx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
+
+    tx_desc_entry.buf_len_info =
+        ( tx_pkt_ctrl_p->tcp_seg_len << 16) | frag_info_p->len;
+
+    ogma_desc_ring_cpy_to_mem( ( (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+                               desc_ring_p->desc_entry_len * idx) ),
+                               ( void *)&tx_desc_entry,
+                               desc_ring_p->desc_entry_len);
+
+    debug_desc_entry_p = ( ogma_uint32 *)&tx_desc_entry;
+
+    for ( i = 0; i < ( sizeof( ogma_tx_desc_entry_t) >> 2); i++) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                     "%08x\n", debug_desc_entry_p[i]);
+    }
+
+    desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
+    desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
+    desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
+    desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
+
+}
+
+STATIC void ogma_set_rx_desc_entry (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    const ogma_frag_info_t *frag_info_p,
+    pfdep_pkt_handle_t pkt_handle
+    )
+{
+    ogma_rx_desc_entry_t rx_desc_entry;
+
+    ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
+
+    pfdep_memset( &rx_desc_entry, 0, sizeof ( ogma_rx_desc_entry_t) );
+
+    rx_desc_entry.attr = ( 1UL << OGMA_RX_PKT_DESC_RING_OWN_FIELD) |
+        ( 1UL << OGMA_RX_PKT_DESC_RING_FS_FIELD) |
+        ( 1UL << OGMA_RX_PKT_DESC_RING_LS_FIELD) ; /* OWN = FS = LS = 1 */
+
+    rx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
+
+    rx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
+
+    rx_desc_entry.buf_len_info = frag_info_p->len;
+
+    if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
+        rx_desc_entry.attr |= ( 0x1U << OGMA_RX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
+    }
+
+    ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+                               desc_ring_p->desc_entry_len * idx + 4) ),
+                               ( void *) ( ( pfdep_cpu_addr_t)&rx_desc_entry + 4),
+                               ( ogma_uint32)( desc_ring_p->desc_entry_len - 4U) );
+
+    pfdep_write_mem_barrier();
+
+    ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+                               desc_ring_p->desc_entry_len * idx) ),
+                               ( void *)&rx_desc_entry,
+                               4);
+
+    desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
+    desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
+    desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
+    desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
+}
+
+STATIC void ogma_get_rx_desc_entry (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    ogma_rx_pkt_info_t *rx_pkt_info_p,
+    ogma_frag_info_t *frag_info_p,
+    ogma_uint16 *len_p,
+    pfdep_pkt_handle_t *pkt_handle_p)
+{
+    ogma_uint32 *debug_desc_entry_p;
+    ogma_rx_desc_entry_t rx_desc_entry;
+
+    ogma_check_desc_own_sanity( ctrl_p, desc_ring_p, idx, 0);
+
+    pfdep_memset( &rx_desc_entry, 0, sizeof( ogma_rx_desc_entry_t) );
+    pfdep_memset( rx_pkt_info_p, 0, sizeof( ogma_rx_pkt_info_t) );
+
+    ogma_desc_ring_cpy_from_mem( &rx_desc_entry,
+                                 (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+                                 desc_ring_p->desc_entry_len * idx),
+                                 desc_ring_p->desc_entry_len);
+
+    debug_desc_entry_p = (ogma_uint32 *)&rx_desc_entry;
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "%08x\n", *debug_desc_entry_p);
+
+    *len_p = rx_desc_entry.buf_len_info >> 16;
+
+    rx_pkt_info_p->fragmented_flag =
+        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_FR_FIELD) & 0x1; /* FR*/
+
+    rx_pkt_info_p->err_flag =
+        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ER_FIELD) & 0x1; /* ER */
+
+    rx_pkt_info_p->rx_cksum_result =
+        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_CO_FIELD) & 0x3; /* CO */
+
+    rx_pkt_info_p->err_code =
+        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD) &
+        OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK; /* Error Code */
+
+    pfdep_memcpy( frag_info_p,
+                  &desc_ring_p->frag_info_p[idx],
+                  sizeof(ogma_frag_info_t) );
+
+    *pkt_handle_p = desc_ring_p->priv_data_p[idx].pkt_handle;
+}
+
+#ifdef OGMA_CONFIG_REC_STAT
+STATIC __inline ogma_uint16 ogma_calc_busy_entry_num (
+    ogma_uint16 head_idx,
+    ogma_uint16 tail_idx,
+    ogma_uint16 entry_num,
+    ogma_bool full_flag
+    )
+{
+
+    ogma_int16 busy_entry_num;
+
+    if (full_flag) {
+        busy_entry_num = entry_num;
+    } else if (head_idx >= tail_idx) {
+        busy_entry_num = head_idx - tail_idx;
+    } else {
+        busy_entry_num = entry_num + head_idx - tail_idx;
+    }
+
+    return busy_entry_num;
+
+}
+#endif /* OGMA_CONFIG_REC_STAT */
+
+STATIC void ogma_clean_tx_desc_ring_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    )
+{
+
+    ogma_uint32 tmp;
+
+    ogma_get_tx_done_num_sub( ctrl_p, desc_ring_p);
+
+    while( ( (desc_ring_p->tail_idx != desc_ring_p->head_idx) ||
+             desc_ring_p->full_flag) && ( desc_ring_p->tx_done_num != 0) ) {
+
+        tmp = ogma_get_desc_ring_attr(desc_ring_p,
+                                      desc_ring_p->tail_idx);
+
+        pfdep_free_pkt_buf (
+            ctrl_p->dev_handle,
+            desc_ring_p->frag_info_p[desc_ring_p->tail_idx].len,
+            desc_ring_p->frag_info_p[desc_ring_p->tail_idx].addr,
+            desc_ring_p->frag_info_p[desc_ring_p->tail_idx].phys_addr,
+            ( ( ( tmp >> OGMA_TX_PKT_DESC_RING_LS_FIELD) & 0x1) != 0),
+            desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+
+        pfdep_memset( &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+                      0,
+                      sizeof( ogma_frag_info_t) );
+
+        ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+
+        if ( ( tmp & ( 1UL << OGMA_TX_PKT_DESC_RING_LS_FIELD) ) != 0) {
+
+            pfdep_assert( desc_ring_p->tx_done_num != 0);
+
+            desc_ring_p->tx_done_num--;
+
+        }
+    }
+
+}
+
+STATIC void ogma_clean_rx_desc_ring_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    )
+{
+
+    while( desc_ring_p->full_flag ||
+           ( desc_ring_p->tail_idx != desc_ring_p->head_idx) ) {
+
+        ogma_set_rx_desc_entry(
+            ctrl_p,
+            desc_ring_p,
+            desc_ring_p->tail_idx,
+            &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+            desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+
+        --desc_ring_p->rx_num;
+        ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+    }
+
+    pfdep_assert( desc_ring_p->rx_num == 0);/* error check*/
+
+}
+
+STATIC void ogma_inc_desc_head_idx (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 increment)
+{
+    ogma_uint32 sum;
+
+    if ( ( desc_ring_p->tail_idx > desc_ring_p->head_idx) ||
+         desc_ring_p->full_flag) {
+        pfdep_assert( increment <=
+                      ( desc_ring_p->tail_idx -
+                       desc_ring_p->head_idx));
+    } else {
+        pfdep_assert( increment <=
+                      ( desc_ring_p->param.entry_num +
+                        desc_ring_p->tail_idx -
+                        desc_ring_p->head_idx) );
+    }
+
+    sum = (ogma_uint32) desc_ring_p->head_idx + increment;
+
+    if ( sum >= desc_ring_p->param.entry_num) {
+        sum -= desc_ring_p->param.entry_num;
+    }
+
+    desc_ring_p->head_idx = ( ogma_uint16)sum;
+
+    if ( desc_ring_p->head_idx == desc_ring_p->tail_idx) {
+        desc_ring_p->full_flag = OGMA_TRUE;
+    }
+
+}
+
+STATIC void ogma_inc_desc_tail_idx (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 increment)
+{
+    ogma_uint32 sum;
+
+    if ( ( desc_ring_p->head_idx >= desc_ring_p->tail_idx) &&
+         ( !desc_ring_p->full_flag) ) {
+        pfdep_assert( increment <=
+                      ( desc_ring_p->head_idx -
+                        desc_ring_p->tail_idx) );
+    } else {
+        pfdep_assert( increment <=
+                      ( desc_ring_p->param.entry_num +
+                        desc_ring_p->head_idx -
+                        desc_ring_p->tail_idx) );
+    }
+
+    sum = (ogma_uint32) desc_ring_p->tail_idx + increment;
+
+    if ( sum >= desc_ring_p->param.entry_num) {
+        sum -= desc_ring_p->param.entry_num;
+    }
+
+    desc_ring_p->tail_idx = ( ogma_uint16)sum;
+
+    desc_ring_p->full_flag = OGMA_FALSE;
+}
+
+
+STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
+    ogma_ctrl_t *ctrl_p,
+    const ogma_desc_ring_t *desc_ring_p
+    )
+{
+    ogma_uint16 tx_avail_num;
+
+    if ( desc_ring_p->full_flag) {
+
+        tx_avail_num = 0;
+
+    } else if ( desc_ring_p->tail_idx > desc_ring_p->head_idx) {
+
+        tx_avail_num = desc_ring_p->tail_idx - desc_ring_p->head_idx;
+
+    } else {
+
+        tx_avail_num =
+            desc_ring_p->param.entry_num +
+            desc_ring_p->tail_idx -
+            desc_ring_p->head_idx;
+    }
+
+    return tx_avail_num;
+}
+
+STATIC ogma_uint16 ogma_get_tx_done_num_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    )
+{
+    ogma_uint32 value;
+
+    value = ogma_read_reg ( ctrl_p,
+                            tx_done_pkt_cnt_reg_addr[desc_ring_p->ring_id] );
+
+    desc_ring_p->tx_done_num += value;
+
+    return desc_ring_p->tx_done_num;
+}
+
+
+ogma_err_t ogma_start_desc_ring (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+    pfdep_err_t pfdep_err;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    if ( desc_ring_p->running_flag) {
+        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                                 &soft_lock_ctx);
+        return OGMA_ERR_BUSY;
+    }
+
+    if ( desc_ring_p->rx_desc_ring_flag) {
+
+        ogma_write_reg ( ctrl_p,
+                         desc_ring_irq_inten_set_reg_addr[ring_id],
+                         OGMA_CH_IRQ_REG_RCV);
+
+        ogma_write_reg ( ctrl_p,
+                         int_pkt_cnt_reg_addr[ring_id],
+                         1);
+    }
+
+    if ( desc_ring_p->tx_desc_ring_flag) {
+
+
+        value = OGMA_CH_IRQ_REG_EMPTY;
+
+
+        ogma_write_reg ( ctrl_p,
+                         desc_ring_irq_inten_set_reg_addr[ring_id],
+                         value);
+
+        ogma_write_reg ( ctrl_p,
+                         int_pkt_cnt_reg_addr[ring_id],
+                         1);
+
+    }
+
+    desc_ring_p->running_flag = OGMA_TRUE;
+
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+
+    return ogma_err;
+}
+
+
+ogma_err_t ogma_stop_desc_ring (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+    pfdep_err_t pfdep_err;
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id] ) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    if ( !desc_ring_p->running_flag) {
+        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                                 &soft_lock_ctx);
+        return OGMA_ERR_INVALID;
+    }
+
+    value = ( OGMA_CH_IRQ_REG_RCV |
+              OGMA_CH_IRQ_REG_EMPTY |
+              OGMA_CH_IRQ_REG_SND);
+
+    ogma_write_reg ( ctrl_p,
+                     desc_ring_irq_inten_clr_reg_addr[ring_id],
+                     value);
+
+    desc_ring_p->running_flag = OGMA_FALSE;
+
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+
+    return OGMA_ERR_OK;
+}
+
+ogma_uint16 ogma_get_rx_num (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+
+    ogma_uint32 result;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p = NULL;
+    ogma_desc_ring_id_t tmp_ring_id;
+
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+    pfdep_err_t pfdep_err;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_rx_num.\n"
+                     "Please set valid argument.\n");
+        return 0;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_rx_num.\n"
+                     "Please set valid argument.\n");
+        return 0;
+    }
+
+    tmp_ring_id = ring_id;
+
+    if (! ctrl_p->desc_ring[tmp_ring_id].rx_desc_ring_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_rx_num.\n"
+                     "Please select rx packet desc ring or bulk desc ring.\n");
+        return 0;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+               &desc_ring_p->soft_lock,
+               &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_rx_num.\n"
+                     "Failed to get soft lock.\n");
+        return 0;
+    }
+
+    result = ogma_read_reg( ctrl_p, rx_pkt_cnt_reg_addr[tmp_ring_id]);
+
+    desc_ring_p->rx_num += result;
+
+    if ( desc_ring_p->rx_desc_ring_flag && ( result != 0) ) {
+        ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, ( ogma_uint16)result);
+    }
+
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+
+    return desc_ring_p->rx_num;
+}
+
+
+ogma_uint16 ogma_get_tx_avail_num (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+
+    ogma_uint16 result;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_id_t tmp_ring_id;
+    ogma_desc_ring_t *desc_ring_p = NULL;
+
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+    pfdep_err_t pfdep_err;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ||
+         ( !ctrl_p->desc_ring[ring_id].param.valid_flag) ) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_tx_avail_num.\n"
+                     "Please select valid argument.\n");
+        return 0;
+    }
+
+    tmp_ring_id = ring_id;
+
+    if (! ctrl_p->desc_ring[tmp_ring_id].tx_desc_ring_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_tx_avail_num.\n"
+                     "Please select tx packet desc ring or bulk desc ring.\n");
+        return 0;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_tx_avail_num.\n"
+                     "Failed to get soft lock.\n");
+        return 0;
+    }
+
+    if ( !desc_ring_p->running_flag) {
+        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                                 &soft_lock_ctx);
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_tx_avail_num.\n"
+                     "Please select running desc ring.\n");
+        return 0;
+    }
+
+    result = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
+
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+    return result;
+}
+
+ogma_err_t ogma_clean_tx_desc_ring (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+
+    pfdep_err_t pfdep_err;
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
+        return OGMA_ERR_PARAM;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    ogma_clean_tx_desc_ring_sub(ctrl_p, desc_ring_p);
+
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+    return OGMA_ERR_OK;
+
+
+}
+
+ogma_err_t ogma_clean_rx_desc_ring (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+
+    pfdep_err_t pfdep_err;
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
+        return OGMA_ERR_PARAM;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    ogma_clean_rx_desc_ring_sub(ctrl_p, desc_ring_p);
+
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+    return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_tx_pkt_data (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
+    ogma_uint8 scat_num,
+    const ogma_frag_info_t *scat_info_p,
+    pfdep_pkt_handle_t pkt_handle
+    )
+{
+    ogma_uint i;
+    ogma_uint16 tx_avail_num;
+    ogma_uint32 sum_len = 0;
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+
+    pfdep_err_t pfdep_err;
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
+
+    if ( ( ctrl_p == NULL) ||
+         ( tx_pkt_ctrl_p == NULL) ||
+         ( scat_info_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
+        return OGMA_ERR_PARAM;
+    }
+
+    {
+        if ( !ctrl_p->param.use_gmac_flag ||
+             ( tx_pkt_ctrl_p->target_desc_ring_id != OGMA_DESC_RING_ID_GMAC) ) {
+            return OGMA_ERR_DATA;
+        }
+    }
+
+
+    if ( tx_pkt_ctrl_p->tcp_seg_offload_flag &&
+         ( !tx_pkt_ctrl_p->cksum_offload_flag) ) {
+        return OGMA_ERR_DATA;
+    }
+
+    if ( tx_pkt_ctrl_p->tcp_seg_offload_flag) {
+
+        if ( tx_pkt_ctrl_p->tcp_seg_len == 0) {
+            return OGMA_ERR_DATA;
+        }
+
+        if ( ctrl_p->param.use_jumbo_pkt_flag) {
+            if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_JUMBO_SEG_LEN_MAX) {
+                return OGMA_ERR_DATA;
+            }
+        } else {
+            if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_SEG_LEN_MAX) {
+                return OGMA_ERR_DATA;
+            }
+        }
+
+    } else {
+        if ( tx_pkt_ctrl_p->tcp_seg_len != 0) {
+            return OGMA_ERR_DATA;
+        }
+    }
+
+
+    if ( scat_num == 0) {
+        return OGMA_ERR_RANGE;
+    }
+
+    for ( i = 0; i < scat_num; i++) {
+        if ( ( scat_info_p[i].len == 0) ||
+             ( scat_info_p[i].len > 0xffffU) ) {
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "An error occurred at ogma_set_tx_pkt_data.\n"
+                         "Pleas check scat_info_p[%u].len.\n",
+                         i);
+            return OGMA_ERR_DATA;
+        }
+        sum_len += scat_info_p[i].len;
+    }
+
+    if ( !tx_pkt_ctrl_p->tcp_seg_offload_flag) {
+
+        if ( ctrl_p->param.use_jumbo_pkt_flag) {
+            if ( sum_len > OGMA_MAX_TX_JUMBO_PKT_LEN) {
+                return OGMA_ERR_DATA;
+            }
+        } else {
+            if ( sum_len > OGMA_MAX_TX_PKT_LEN) {
+                return OGMA_ERR_DATA;
+            }
+        }
+
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    if ( !desc_ring_p->running_flag) {
+        ogma_err = OGMA_ERR_NOTAVAIL;
+        goto end;
+    }
+
+    tx_avail_num = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
+
+    if ( scat_num > tx_avail_num ) {
+        ogma_err = OGMA_ERR_BUSY;
+        goto end;
+    }
+
+    for ( i = 0; i < scat_num; i++) {
+
+
+        ogma_set_tx_desc_entry(
+            ctrl_p,
+            desc_ring_p,
+            desc_ring_p->head_idx,
+            tx_pkt_ctrl_p,
+            ( i == 0),
+            ( i == ( scat_num - 1U) ),
+            OGMA_TRUE,
+            &scat_info_p[i],
+            pkt_handle);
+        ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, 1);
+    }
+
+    pfdep_write_mem_barrier();
+
+    ogma_write_reg( ctrl_p,
+                    tx_pkt_cnt_reg_addr[ring_id],
+                    (ogma_uint32)1);
+
+end:
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+
+    return ogma_err;
+}
+
+ogma_err_t ogma_get_rx_pkt_data (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_rx_pkt_info_t *rx_pkt_info_p,
+    ogma_frag_info_t *frag_info_p,
+    ogma_uint16 *len_p,
+    pfdep_pkt_handle_t *pkt_handle_p
+    )
+{
+
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+    ogma_frag_info_t tmp_frag_info;
+
+    pfdep_err_t pfdep_err;
+    pfdep_pkt_handle_t tmp_pkt_handle;
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
+
+    if ( ( ctrl_p == NULL) ||
+         ( rx_pkt_info_p == NULL) ||
+         ( frag_info_p == NULL) ||
+         ( len_p == NULL) ||
+         ( pkt_handle_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
+        return OGMA_ERR_PARAM;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    if ( ( pfdep_err = pfdep_acquire_soft_lock(
+              &desc_ring_p->soft_lock,
+              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    if ( desc_ring_p->rx_num == 0 ) {
+        ogma_err = OGMA_ERR_INVALID;
+        goto end;
+    }
+
+    tmp_frag_info.len = ctrl_p->rx_pkt_buf_len;
+
+    pfdep_read_mem_barrier();
+
+    if ( ( pfdep_err = pfdep_alloc_pkt_buf (
+               ctrl_p->dev_handle,
+               tmp_frag_info.len,
+               &tmp_frag_info.addr,
+               &tmp_frag_info.phys_addr,
+               &tmp_pkt_handle) ) != PFDEP_ERR_OK) {
+        ogma_set_rx_desc_entry( ctrl_p,
+                                desc_ring_p,
+                                desc_ring_p->tail_idx,
+                                &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
+                                desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
+        ogma_err = OGMA_ERR_ALLOC;
+
+    } else {
+
+        ogma_get_rx_desc_entry( ctrl_p,
+                                desc_ring_p,
+                                desc_ring_p->tail_idx,
+                                rx_pkt_info_p,
+                                frag_info_p,
+                                len_p,
+                                pkt_handle_p);
+
+
+        ogma_set_rx_desc_entry( ctrl_p,
+                                desc_ring_p,
+                                desc_ring_p->tail_idx,
+                                &tmp_frag_info,
+                                tmp_pkt_handle);
+    }
+
+    ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
+
+    --desc_ring_p->rx_num;
+
+end:
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+
+    return ogma_err;
+}
+
+ogma_err_t ogma_set_irq_coalesce_param (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint16 int_pktcnt,
+    ogma_bool int_tmr_unit_ms_flag,
+    ogma_uint16 int_tmr_cnt
+    )
+{
+
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( int_pktcnt > OGMA_INT_PKTCNT_MAX) {
+        return OGMA_ERR_RANGE;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id]) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    ogma_write_reg( ctrl_p,
+                    int_pkt_cnt_reg_addr[ring_id],
+                    int_pktcnt);
+
+    ogma_write_reg( ctrl_p,
+                    int_tmr_reg_addr[ring_id],
+                    ( ( ( ( ogma_uint32)int_tmr_unit_ms_flag) << 31) |
+                      int_tmr_cnt) );
+
+    return ogma_err;
+
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
new file mode 100644
index 000000000000..34490e2d1c78
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
@@ -0,0 +1,111 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_DESC_RING_ACCESS_INTERNAL_H
+#define OGMA_DESC_RING_ACCESS_INTERNAL_H
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "ogma_internal.h"
+
+#define OGMA_TX_PKT_DESC_RING_OWN_FIELD        (31)
+#define OGMA_TX_PKT_DESC_RING_LD_FIELD         (30)
+#define OGMA_TX_PKT_DESC_RING_DRID_FIELD       (24)
+#define OGMA_TX_PKT_DESC_RING_PT_FIELD         (21)
+#define OGMA_TX_PKT_DESC_RING_TDRID_FIELD      (16)
+#define OGMA_TX_PKT_DESC_RING_FS_FIELD         (9)
+#define OGMA_TX_PKT_DESC_RING_LS_FIELD         (8)
+#define OGMA_TX_PKT_DESC_RING_CO_FIELD         (7)
+#define OGMA_TX_PKT_DESC_RING_SO_FIELD         (6)
+#define OGMA_TX_PKT_DESC_RING_USRKEY_FIELD     (5)
+#define OGMA_TX_PKT_DESC_RING_TRS_FIELD        (4)
+
+#define OGMA_RX_PKT_DESC_RING_OWN_FIELD        (31)
+#define OGMA_RX_PKT_DESC_RING_LD_FIELD         (30)
+#define OGMA_RX_PKT_DESC_RING_SDRID_FIELD      (24)
+#define OGMA_RX_PKT_DESC_RING_FR_FIELD         (23)
+#define OGMA_RX_PKT_DESC_RING_ER_FIELD         (21)
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD (16)
+#define OGMA_RX_PKT_DESC_RING_TDRID_FIELD      (12)
+#define OGMA_RX_PKT_DESC_RING_FS_FIELD         (9)
+#define OGMA_RX_PKT_DESC_RING_LS_FIELD         (8)
+#define OGMA_RX_PKT_DESC_RING_CO_FIELD         (6)
+
+#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK (0x3)
+
+#define OGMA_MAX_TX_PKT_LEN       1518U
+#define OGMA_MAX_TX_JUMBO_PKT_LEN 9018U
+
+typedef struct ogma_tx_desc_entry_s ogma_tx_desc_entry_t;
+typedef struct ogma_rx_desc_entry_s ogma_rx_desc_entry_t;
+
+struct ogma_tx_desc_entry_s{
+
+    ogma_uint32 attr;
+
+    ogma_uint32 data_buf_addr_upper;
+
+    ogma_uint32 data_buf_addr_lower;
+
+    ogma_uint32 buf_len_info;
+};
+
+struct ogma_rx_desc_entry_s{
+
+    ogma_uint32 attr;
+
+    ogma_uint32 data_buf_addr_upper;
+
+    ogma_uint32 data_buf_addr_lower;
+
+    ogma_uint32 buf_len_info;
+};
+
+static __inline ogma_bool ogma_is_pkt_desc_ring (
+    const ogma_desc_ring_t *desc_ring_p
+    )
+{
+    return ( desc_ring_p->rx_desc_ring_flag ||
+             desc_ring_p->tx_desc_ring_flag);
+}
+
+static __inline ogma_uint32 ogma_get_desc_ring_attr (
+    const ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx
+    )
+{
+    ogma_uint32 *addr =
+        (ogma_uint32 *)
+        ((pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
+         desc_ring_p->desc_entry_len * idx);
+
+    return *addr;
+}
+
+
+
+static __inline void ogma_check_desc_own_sanity (
+    ogma_ctrl_t *ctrl_p,
+    const ogma_desc_ring_t *desc_ring_p,
+    ogma_uint16 idx,
+    ogma_uint expected_own)
+{
+    ogma_uint32 tmp;
+    ( void)ctrl_p; /* Suppress compiler warning */
+
+    tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
+    pfdep_assert( ( tmp >> 31) == expected_own);
+}
+
+#endif /* OGMA_DESC_RING_ACCESS_INTERNAL_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
new file mode 100644
index 000000000000..d08bb53a54e8
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
@@ -0,0 +1,1454 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_config.h"
+
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+
+/**
+ * Clock range index for F_GMAC4MT::GAR::CR field.
+ */
+#if (OGMA_CONFIG_GMAC_CLK_HZ < 35 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_25_35_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 60 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_35_60_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 100 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_60_100_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 150 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_100_150_MHZ
+#elif (OGMA_CONFIG_GMAC_CLK_HZ < 250 * OGMA_CLK_MHZ)
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_150_250_MHZ
+#else
+#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_250_300_MHZ
+#endif
+
+
+/**********************************************************************
+ * Local function declarations
+ **********************************************************************/
+static void ogma_set_phy_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr,
+    ogma_uint16 value
+    );
+
+static ogma_uint16 ogma_get_phy_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr
+    );
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p);
+#endif /*  OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+static void ogma_set_phy_target_mmd_reg_addr (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr
+    );
+
+static void ogma_set_phy_mmd_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr,
+    ogma_uint16 value
+    );
+
+static ogma_uint16 ogma_get_phy_mmd_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr
+    );
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+ogma_err_t ogma_start_gmac (
+    ogma_handle_t ogma_handle,
+    ogma_bool rx_flag,
+    ogma_bool tx_flag
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    pfdep_err_t pfdep_err;
+    ogma_err_t ogma_err;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( !ctrl_p->gmac_mode_valid_flag) {
+        return OGMA_ERR_INVALID;
+    }
+
+    if ( ( !rx_flag) && ( !tx_flag) ) {
+        return OGMA_ERR_OK;
+    }
+
+    if ( ctrl_p->gmac_rx_running_flag &&
+         ctrl_p->gmac_tx_running_flag) {
+        return OGMA_ERR_OK;
+    }
+
+
+    if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) &&
+         !tx_flag) {
+        return OGMA_ERR_OK;
+    }
+
+    if ( ( tx_flag && ctrl_p->gmac_tx_running_flag) &&
+         !rx_flag ) {
+        return OGMA_ERR_OK;
+    }
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "%s call.\n", __func__);
+
+    if ( (! ctrl_p->gmac_rx_running_flag) &&
+         (! ctrl_p->gmac_tx_running_flag) ) {
+
+        /* Initializes F_GMAC4MT */
+        if ( ctrl_p->gmac_mode.link_speed ==
+             OGMA_PHY_LINK_SPEED_1G) {
+            /* Writes 0 to FGMAC4 MCR */
+            ogma_set_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_MCR,
+                              0);
+        } else {
+            /* Writes PS bit to FGMAC4 MCR */
+            ogma_set_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_MCR,
+                              OGMA_GMAC_MCR_10M_HALF);/* 10M half Reset */
+        }
+
+        /* F_GMAC4MT soft reset*/
+        if ( ( ogma_err = ogma_softreset_gmac( ctrl_p)) != OGMA_ERR_OK) {
+            return ogma_err;
+        }
+
+        /* MAC desc soft reset */
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_MAC_DESC_SOFT_RST,
+                        OGMA_MAC_DESC_SOFT_RST_SOFT_RST);
+
+        /* Wait MAC desc soft reset */
+        pfdep_err = pfdep_msleep( 1);
+
+        if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                             "An error occurred at ogma_start_gmac.\n");
+
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                             "Wait for MAC desc soft reset error.\n");
+
+            return OGMA_ERR_INTERRUPT;
+        }
+
+        /* Check MAC desc soft reset done */
+        if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_SOFT_RST) &
+               OGMA_MAC_DESC_SOFT_RST_SOFT_RST) != 0) {
+
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "ogma_start_gmac():MAC desc soft reset timeout. Try Again.\n");
+
+            return OGMA_ERR_AGAIN;
+        }
+
+        /* MAC desc init */
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_MAC_DESC_INIT,
+                        OGMA_MAC_DESC_INIT_REG_INIT);
+
+        /* Wait MAC desc init done */
+        pfdep_err = pfdep_msleep( 1);
+
+        if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "An error occurred at ogma_start_gmac().\n");
+
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "Wait for MAC desc init done error.\n");
+
+            return OGMA_ERR_INTERRUPT;
+        }
+
+        /* Check MAC desc init done */
+        if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT) &
+               OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "ogma_start_gmac():MAC desc init timeout. Try Again.\n");
+
+            return OGMA_ERR_AGAIN;
+        }
+
+        /* set BMR */
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_BMR,
+                          OGMA_GMAC_BMR_REG_COMMON);
+        /* set RDLAR */
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_RDLAR,
+                          OGMA_GMAC_RDLAR_REG_COMMON);
+        /* set TDLAR*/
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_TDLAR,
+                          OGMA_GMAC_TDLAR_REG_COMMON);
+        /* set MFFR*/
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_MFFR,
+                          0x80000001UL);
+
+        /* calc MCR setting val */
+        value = ( ctrl_p->gmac_mode.half_duplex_flag ?
+                  OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON :
+                  OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON);
+
+        if ( ctrl_p->gmac_mode.link_speed != OGMA_PHY_LINK_SPEED_1G) {
+            value |= OGMA_GMAC_MCR_REG_PS;
+        }
+
+        if ( ( ctrl_p->param.gmac_config.phy_interface !=
+               OGMA_PHY_INTERFACE_GMII ) &&
+             ( ctrl_p->gmac_mode.link_speed == OGMA_PHY_LINK_SPEED_100M) ) {
+            value |= OGMA_GMAC_MCR_REG_FES;
+        }
+        /* set CST bit  */
+        value |= OGMA_GMAC_MCR_REG_CST;
+
+        /* set JE bit  */
+        value |= OGMA_GMAC_MCR_REG_JE;
+
+        if ( ctrl_p->param.gmac_config.phy_interface ==
+             OGMA_PHY_INTERFACE_RGMII) {
+            /* set ignore in-band-status watch option. force tx clk out. */
+            value |= 0x40000000U;
+        }
+
+        /* set MCR */
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_MCR,
+                          value);
+
+        if ( ctrl_p->gmac_mode.flow_ctrl_enable_flag) {
+            /* Set Flow Control Threshold */
+            value =
+                ( ctrl_p->gmac_mode.flow_ctrl_stop_threshold << 16) |
+                ctrl_p->gmac_mode.flow_ctrl_start_threshold;
+
+            ogma_write_reg( ctrl_p,
+                            OGMA_REG_ADDR_MAC_FLOW_TH,
+                            value);
+            /* Set Flow Control Threshold F_GMAC4MT*/
+            value =
+                ( ctrl_p->gmac_mode.pause_time << 16) |
+                OGMA_GMAC_FCR_REG_RFE |
+                OGMA_GMAC_FCR_REG_TFE;
+
+            ogma_set_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_FCR,
+                              value);
+        }
+
+    }
+
+    if ( ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) ||
+         ( tx_flag && (! ctrl_p->gmac_tx_running_flag) )
+        ) {
+        /* Read F_GMAC4MT OMR*/
+        value = ogma_get_mac_reg( ctrl_p,
+                                  OGMA_GMAC_REG_ADDR_OMR);
+
+        if ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) {
+            value |= OGMA_GMAC_OMR_REG_SR;
+            ctrl_p->gmac_rx_running_flag = OGMA_TRUE;
+        }
+
+        if ( tx_flag && (! ctrl_p->gmac_tx_running_flag) ) {
+            value |= OGMA_GMAC_OMR_REG_ST;
+            ctrl_p->gmac_tx_running_flag = OGMA_TRUE;
+        }
+
+        /* set OMR*/
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_OMR,
+                          value);
+
+    }
+
+    return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_stop_gmac (
+    ogma_handle_t ogma_handle,
+    ogma_bool rx_flag,
+    ogma_bool tx_flag
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+
+    if ( ( !rx_flag) && ( !tx_flag) ) {
+        return OGMA_ERR_OK;
+    }
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "%s call.\n", __func__);
+
+    if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) ||
+         ( tx_flag && ctrl_p->gmac_tx_running_flag) ) {
+        /* Read F_GMAC4MT OMR*/
+        value = ogma_get_mac_reg( ctrl_p,
+                                  OGMA_GMAC_REG_ADDR_OMR);
+
+        if ( rx_flag && ctrl_p->gmac_rx_running_flag) {
+            value &= (~OGMA_GMAC_OMR_REG_SR);
+            ctrl_p->gmac_rx_running_flag = OGMA_FALSE;
+        }
+
+        if ( tx_flag && ctrl_p->gmac_tx_running_flag) {
+            value &= (~OGMA_GMAC_OMR_REG_ST);
+            ctrl_p->gmac_tx_running_flag = OGMA_FALSE;
+        }
+
+        /* set F_GMAC4MT OMR*/
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_OMR,
+                          value);
+    }
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+    ogma_dump_gmac_stat (ctrl_p);
+#endif /*  OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+
+    return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_set_gmac_mode (
+    ogma_handle_t ogma_handle,
+    const ogma_gmac_mode_t *gmac_mode_p
+    )
+{
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( gmac_mode_p == NULL) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    if ( ( ctrl_p->gmac_rx_running_flag) ||
+         ( ctrl_p->gmac_tx_running_flag) ) {
+        return OGMA_ERR_BUSY;
+    }
+
+   if ( ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_1G  ) &&
+        ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_100M) &&
+        ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_10M ) ) {
+       return OGMA_ERR_DATA;
+    }
+
+   if ( ( gmac_mode_p->link_speed == OGMA_PHY_LINK_SPEED_1G) &&
+        ( gmac_mode_p->half_duplex_flag) ) {
+       return OGMA_ERR_DATA;
+   }
+
+   if ( gmac_mode_p->half_duplex_flag &&
+        gmac_mode_p->flow_ctrl_enable_flag) {
+       return OGMA_ERR_DATA;
+   }
+
+   if ( gmac_mode_p->flow_ctrl_enable_flag) {
+
+       if ( ( gmac_mode_p->flow_ctrl_start_threshold == 0) ||
+            ( gmac_mode_p->flow_ctrl_start_threshold >
+              OGMA_FLOW_CTRL_START_THRESHOLD_MAX) ) {
+           return OGMA_ERR_DATA;
+       }
+
+       if ( ( gmac_mode_p->flow_ctrl_stop_threshold <
+              gmac_mode_p->flow_ctrl_start_threshold) ||
+            ( gmac_mode_p->flow_ctrl_stop_threshold >
+              OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX) ) {
+           return OGMA_ERR_DATA;
+       }
+
+       if ( gmac_mode_p->pause_time < OGMA_FLOW_CTRL_PAUSE_TIME_MIN) {
+           return OGMA_ERR_DATA;
+       }
+   }
+
+   pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "%s call.\n", __func__);
+
+   pfdep_memcpy( ( void *)&ctrl_p->gmac_mode,
+                 ( void *)gmac_mode_p,
+                 sizeof( ogma_gmac_mode_t) );
+
+   ctrl_p->gmac_mode_valid_flag = OGMA_TRUE;
+
+
+   return OGMA_ERR_OK;
+
+}
+
+static void ogma_set_phy_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr,
+    ogma_uint16 value
+    )
+{
+
+    ogma_uint32 cmd;
+
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_GDR,
+                      value);
+
+    cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
+            ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
+            ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
+            OGMA_GMAC_GAR_REG_GW |
+            OGMA_GMAC_GAR_REG_GB);
+
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_GAR,
+                      cmd);
+
+    while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
+              OGMA_GMAC_GAR_REG_GB)
+            != 0) {
+        ;
+    }
+}
+
+void ogma_set_phy_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr,
+    ogma_uint16 value
+    )
+{
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if (( ctrl_p == NULL)
+        || ( !ctrl_p->param.use_gmac_flag)
+        || ( phy_addr >= 32)
+        || ( reg_addr >= 32) ) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_set_phy_reg.\nPlease set valid argument.\n");
+        return;
+    }
+
+    ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value);
+
+}
+
+static ogma_uint16 ogma_get_phy_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr
+    )
+{
+
+    ogma_uint32 cmd;
+
+    cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
+            ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
+            ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
+            OGMA_GMAC_GAR_REG_GB);
+
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_GAR,
+                      cmd);
+
+    while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
+              OGMA_GMAC_GAR_REG_GB)
+            != 0) {
+        ;
+    }
+    return (ogma_uint16)ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GDR);
+
+}
+
+ogma_uint16 ogma_get_phy_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 reg_addr
+    )
+{
+    ogma_uint16 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL)
+         || ( !ctrl_p->param.use_gmac_flag)
+         || ( phy_addr >= 32)
+         || ( reg_addr >= 32) ) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_phy_reg.\nPlease set valid argument.\n");
+        return 0;
+    }
+
+    value = ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr);
+
+
+    return value;
+}
+
+#if ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) )
+static const struct {
+    ogma_uint32 addr;
+    ogma_char *name_p;
+} ogma_gmac_mmc_reg_info[] = {
+    {OGMA_GMAC_REG_ADDR_MMC_INTR_RX         , "MMC_INTR_RX"},
+    {OGMA_GMAC_REG_ADDR_MMC_INTR_TX         , "MMC_INTR_TX"},
+    {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX    , "MMC_INTR_MASK_RX"},
+    {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX    , "MMC_INTR_MASK_TX"},
+    {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB     , "TXOCTETCOUNT_GB"},
+    {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB     , "TXFRAMECOUNT_GB"},
+    {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G , "TXBROADCASTFRAMES_G"},
+    {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G , "TXMULTICASTFRAMES_G"},
+    {OGMA_GMAC_REG_ADDR_TX64OCTETS_GB       , "TX64OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB  , "TX65TO127OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB , "TX128TO255OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB , "TX256TO511OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB, "TX512TO1023OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB, "TX1024TOMAXOCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB  , "TXUNICASTFRAMES_GB"},
+    {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB, "TXMULTICASTFRAMES_GB"},
+    {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB, "TXBROADCASTFRAMES_GB"},
+    {OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR    , "TXUNDERFLOWERROR"},
+    {OGMA_GMAC_REG_ADDR_TXSINGLECOL_G       , "TXSINGLECOL_G"},
+    {OGMA_GMAC_REG_ADDR_TXMULTICOL_G        , "TXMULTICOL_G"},
+    {OGMA_GMAC_REG_ADDR_TXDEFERRED          , "TXDEFERRED"},
+    {OGMA_GMAC_REG_ADDR_TXLATECOL           , "TXLATECOL"},
+    {OGMA_GMAC_REG_ADDR_TXEXESSCOL          , "TXEXESSCOL"},
+    {OGMA_GMAC_REG_ADDR_TXCARRIERERRROR     , "TXCARRIERERRROR"},
+    {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G      , "TXOCTETCOUNT_G"},
+    {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G      , "TXFRAMECOUNT_G"},
+    {OGMA_GMAC_REG_ADDR_TXEXECESSDEF        , "TXEXECESSDEF"},
+    {OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES       , "TXPAUSEFRAMES"},
+    {OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G      , "TXVLANFRAMES_G"},
+    {OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB     , "RXFRAMECOUNT_GB"},
+    {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB     , "RXOCTETCOUNT_GB"},
+    {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G      , "RXOCTETCOUNT_G"},
+    {OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G , "RXBROADCASTFRAMES_G"},
+    {OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G , "RXMULTICASTFRAMES_G"},
+    {OGMA_GMAC_REG_ADDR_RXCRCERROR          , "RXCRCERROR"},
+    {OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR   , "RXALLIGNMENTERROR"},
+    {OGMA_GMAC_REG_ADDR_RXRUNTERROR         , "RXRUNTERROR"},
+    {OGMA_GMAC_REG_ADDR_RXJABBERERROR       , "RXJABBERERROR"},
+    {OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G       , "RXUNDERSIZE_G"},
+    {OGMA_GMAC_REG_ADDR_RXOVERSIZE_G        , "RXOVERSIZE_G"},
+    {OGMA_GMAC_REG_ADDR_RX64OCTETS_GB       , "RX64OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB  , "RX65TO127OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB , "RX128TO255OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB , "RX256TO511OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB, "RX512TO1023OCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB, "RX1024TOMAXOCTETS_GB"},
+    {OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G   , "RXUNICASTFRAMES_G"},
+    {OGMA_GMAC_REG_ADDR_RXLENGTHERROR       , "RXLENGTHERROR"},
+    {OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE    , "RXOUTOFRANGETYPE"},
+    {OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES       , "RXPAUSEFRAMES"},
+    {OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW      , "RXFIFOOVERFLOW"},
+    {OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB     , "RXVLANFRAMES_GB"},
+    {OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR     , "RXWATCHDOGERROR"},
+    {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX, "MMC_IPC_INTR_MASK_RX"},
+    {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX     , "MMC_IPC_INTR_RX"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS      , "RXIPV4_GD_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS  , "RXIPV4_HDRERR_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS   , "RXIPV4_NOPAY_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS    , "RXIPV4_FRAG_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS   , "RXIPV4_UDSBL_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS      , "RXIPV6_GD_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS  , "RXIPV6_HDRERR_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS   , "RXIPV6_NOPAY_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS       , "RXUDP_GD_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS      , "RXUDP_ERR_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS       , "RXTCP_GD_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS      , "RXTCP_ERR_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS      , "RXICMP_GD_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS     , "RXICMP_ERR_FRMS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS    , "RXIPV4_GD_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS, "RXIPV4_HDRERR_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS , "RXIPV4_NOPAY_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS  , "RXIPV4_FRAG_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS , "RXIPV4_UDSBL_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS    , "RXIPV6_GD_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS, "RXIPV6_HDRERR_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS , "RXIPV6_NOPAY_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS     , "RXUDP_GD_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS    , "RXUDP_ERR_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS     , "RXTCP_GD_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS    , "RXTCP_ERR_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS    , "RXICMP_GD_OCTETS"},
+    {OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS   , "RXICMP_ERR_OCTETS"}
+};
+#endif /* ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) ) */
+
+#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
+void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p)
+{
+
+    ogma_uint i;
+
+    pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+                "Dumping GMAC statistics registers(MMC registers):\n");
+
+    for (i = 0;
+         i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0]);
+         i++) {
+        pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+                    "  %s => 0x%08x\n",
+                    ogma_gmac_mmc_reg_info[i].name_p,
+                    ( unsigned long)ogma_get_mac_reg(ctrl_p,
+                                                     ogma_gmac_mmc_reg_info[i].addr));
+    }
+
+
+    /* Reset all counters. */
+    ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+
+
+}
+
+#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
+
+
+ogma_err_t ogma_get_gmac_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool *valid_flag_p,
+    ogma_gmac_mode_t *gmac_mode_p,
+    ogma_bool *rx_running_flag_p,
+    ogma_bool *tx_running_flag_p
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( valid_flag_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( ( ctrl_p == NULL) ||
+         ( gmac_mode_p == NULL) ||
+         ( rx_running_flag_p == NULL) ||
+         ( tx_running_flag_p == NULL) ) {
+        *valid_flag_p = OGMA_FALSE;
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        *valid_flag_p = OGMA_FALSE;
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+
+    *valid_flag_p = ctrl_p->gmac_mode_valid_flag;
+
+    *rx_running_flag_p = ctrl_p->gmac_rx_running_flag;
+    *tx_running_flag_p = ctrl_p->gmac_tx_running_flag;
+
+    pfdep_memcpy( ( void *)gmac_mode_p,
+                  ( const void *)&ctrl_p->gmac_mode,
+                  sizeof( ogma_gmac_mode_t) );
+
+
+    return OGMA_ERR_OK;
+
+}
+
+static void ogma_set_phy_target_mmd_reg_addr (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr
+    )
+{
+    ogma_uint32 cmd;
+
+    /* set MMD ADDR */
+    cmd = ( ogma_uint32)dev_addr;
+
+    /*set command to MMD access control register */
+    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
+
+    /* set MMD access address data register Write reg_addr */
+    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr);
+
+    /* write value to MMD ADDR */
+    cmd = ( (1U << 14) | dev_addr);
+
+    /* set command to MMD access control register */
+    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
+}
+
+static void ogma_set_phy_mmd_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr,
+    ogma_uint16 value
+    )
+{
+    /* set target mmd reg_addr */
+    ogma_set_phy_target_mmd_reg_addr( ctrl_p,
+                                      phy_addr,
+                                      dev_addr,
+                                      reg_addr);
+
+    /* Write value to MMD access address data register */
+    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, value);
+
+}
+
+static ogma_uint16 ogma_get_phy_mmd_reg_sub (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr
+    )
+{
+    /* set target mmd reg_addr */
+    ogma_set_phy_target_mmd_reg_addr( ctrl_p,
+                                      phy_addr,
+                                      dev_addr,
+                                      reg_addr);
+
+    /* Read value for MMD access address data register */
+    return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD);
+}
+
+ogma_err_t ogma_set_gmac_lpictrl_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* set value tp LSIPCR Register */
+    ogma_set_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_LPICSR, value);
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_lpictrl_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 *value_p
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( value_p == NULL) ){
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Read LSIPCR Register */
+    *value_p = ogma_get_mac_reg( ctrl_p,
+                                 OGMA_GMAC_REG_ADDR_LPICSR);
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_set_gmac_lpitimer_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint16 ls_timer_ms,
+    ogma_uint16 tw_timer_ms
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( ls_timer_ms > 1024U) {
+        return OGMA_ERR_RANGE;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* make LPICTR value*/
+    value = ( ( ( ogma_uint32)ls_timer_ms << OGMA_GMAC_LPITCR_REG_LIT) |
+              ( tw_timer_ms << OGMA_GMAC_LPITCR_REG_TWT) );
+
+    /* Write timer value to LSIPCR Register */
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_LPITCR,
+                      value);
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_lpitimer_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint16 *ls_timer_ms_p,
+    ogma_uint16 *tw_timer_ms_p
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ls_timer_ms_p == NULL) ||
+         ( tw_timer_ms_p == NULL) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Read timer value for LSIPCR Register */
+    value = ogma_get_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_LPITCR);
+
+    /* make ls_timer_ms value*/
+    *ls_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_LIT) &
+                                     OGMA_GMAC_LPITCR_REG_MASK_LIT);
+
+    /* make tw_timer_ms value*/
+    *tw_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_TWT) &
+                                     OGMA_GMAC_LPITCR_REG_MASK_TWT);
+
+
+    return OGMA_ERR_OK;
+}
+
+void ogma_set_phy_mmd_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr,
+    ogma_uint16 value
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return;
+    }
+
+    if ( ( phy_addr > 31U) ||
+         ( dev_addr > 31U) ) {
+        return;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return;
+    }
+
+    ogma_set_phy_mmd_reg_sub ( ctrl_p,
+                               phy_addr,
+                               dev_addr,
+                               reg_addr,
+                               value);
+
+
+    return;
+}
+
+ogma_uint16 ogma_get_phy_mmd_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_uint8 dev_addr,
+    ogma_uint16 reg_addr
+    )
+{
+    ogma_uint16 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return 0;
+    }
+
+    if ( ( phy_addr > 31U) ||
+         ( dev_addr > 31U) ) {
+        return 0;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return 0;
+    }
+
+    value = ogma_get_phy_mmd_reg_sub ( ctrl_p,
+                                       phy_addr,
+                                       dev_addr,
+                                       reg_addr);
+
+
+    return value;
+}
+
+ogma_err_t ogma_get_phy_link_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint8 phy_addr,
+    ogma_phy_link_status_t *phy_link_status_p
+    )
+{
+    ogma_uint32 value, tmp, exp;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( phy_link_status_p == NULL) ){
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( phy_addr >= 32) {
+        return OGMA_ERR_RANGE;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) );
+
+    /* Read PHY CONTROL Register */
+    tmp = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONTROL);
+
+    /* Read PHY STATUS Register */
+    value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
+
+    /* check latched_link_down_flag */
+    if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) == 0) {
+        phy_link_status_p->latched_link_down_flag = OGMA_TRUE;
+
+        /* Read PHY STATUS Register */
+        value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
+
+    }
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "CONTROL Register value %08x\n", tmp);
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "PHY STATUS register value %08x\n", value);
+
+    /* Check Current Link Status */
+    if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) != 0 ) {
+        phy_link_status_p->up_flag = OGMA_TRUE;
+    }
+
+    /* check Auto-Negotiation Enable */
+    if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE) ) != 0) &&
+         ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY) ) != 0) ) {
+        phy_link_status_p->auto_nego_enable_flag = OGMA_TRUE;
+    }
+
+    /* Check Current Autonegotiation Complete Status */
+    if ( phy_link_status_p->up_flag &&
+         phy_link_status_p->auto_nego_enable_flag &&
+         ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP) ) != 0) ) {
+        phy_link_status_p->auto_nego_complete_flag = OGMA_TRUE;
+    }
+
+    /* start Check Current Link Speed */
+    if ( phy_link_status_p->up_flag) {
+
+        if ( phy_link_status_p->auto_nego_enable_flag == OGMA_FALSE) {
+
+            /* Speed check */
+            if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) == 0) &&
+                 ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) != 0) ) {
+
+                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+            } else if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) != 0) &&
+                        ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) == 0) ) {
+
+                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+            } else {
+
+                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+            }
+
+            /* Duplex check */
+            if ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_DUPLEX_MODE) ) == 0) {
+
+                phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+            }
+
+        } else if ( phy_link_status_p->auto_nego_complete_flag == OGMA_TRUE) {
+            /* case auto_nego_enable_flag TRUE && auto_nego_complete_flag TRUE */
+
+            /* Read MASTER-SLAVE Control Register */
+            value = ogma_get_phy_reg_sub( ctrl_p,
+                                          phy_addr,
+                                          OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL);
+
+            /* Read MASTER-SLAVE Status Register */
+            tmp = ogma_get_phy_reg_sub( ctrl_p,
+                                        phy_addr,
+                                        OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS);
+
+            /* Check Current Link Speed */
+            if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_FULL) ) != 0) &&
+                 ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_FULL) ) != 0) ) {
+
+                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+            } else if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_HALF) ) != 0) &&
+                        ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_HALF) ) != 0) ) {
+
+                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
+
+                phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+
+            } else {
+
+                /* Read Auto-Negotiation Advertisement register */
+                value = ogma_get_phy_reg_sub( ctrl_p,
+                                              phy_addr,
+                                              OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY);
+
+                /* Read Auto-Negotiation Link Partner Base Page Ability register */
+                tmp = ogma_get_phy_reg_sub( ctrl_p,
+                                             phy_addr,
+                                             OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY);
+
+                value = ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) &
+                          OGMA_PHY_ANA_REG_TAF_MASK);
+
+                pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                             "TAF value %08x\n", value);
+
+                if ( value & OGMA_PHY_TAF_REG_100BASE_FULL) { /* 100M full */
+
+                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+                } else if ( value & OGMA_PHY_TAF_REG_100BASE_HALF) { /* 100M half */
+
+                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
+
+                    phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+
+                } else if ( value & OGMA_PHY_TAF_REG_10BASE_FULL) { /* 10M full */
+
+                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+
+                } else { /* value = OGMA_PHY_TAF_REG_10BASE_HALF 10M Half */
+
+                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
+
+                    phy_link_status_p->half_duplex_flag = OGMA_TRUE;
+                }
+
+            }
+        }
+    } /* End Check Current Link Speed */
+
+    /* Check LPI Capable */
+    if ( phy_link_status_p->up_flag &&
+         phy_link_status_p->auto_nego_complete_flag &&
+         phy_link_status_p->link_speed != OGMA_PHY_LINK_SPEED_10M &&
+         phy_link_status_p->half_duplex_flag == OGMA_FALSE &&
+         ctrl_p->param.gmac_config.phy_interface != OGMA_PHY_INTERFACE_RMII) {
+
+        /* Read EEE advertisement register */
+        value = ogma_get_phy_mmd_reg_sub( ctrl_p,
+                                          phy_addr,
+                                          OGMA_PHY_DEV_ADDR_AUTO_NEGO,
+                                          OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE);
+
+        /* Read EEE link partner ability register */
+        tmp = ogma_get_phy_mmd_reg_sub( ctrl_p,
+                                        phy_addr,
+                                        OGMA_PHY_DEV_ADDR_AUTO_NEGO,
+                                        OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY);
+
+        exp = ( ( phy_link_status_p->link_speed == OGMA_PHY_LINK_SPEED_1G) ?
+                OGMA_PHY_AUTO_NEGO_1000BASE_EEE:
+                OGMA_PHY_AUTO_NEGO_100BASE_EEE);
+
+        /* Check EEE Advertise and EEE LP Ability */
+        if ( ( value & tmp & exp) != 0 ) {
+            phy_link_status_p->lpi_capable_flag = OGMA_TRUE;
+        }
+
+        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                     "EEE advertisement register        value %08x\n",
+                     value);
+
+        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                     "EEE link partner ability register value %08x\n",
+                     tmp);
+
+        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                     "EEE LPI EXP                       value %08x\n",
+                     exp);
+    }
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "phy_link_status_p->latched_link_down_flag %u\n",
+                 phy_link_status_p->latched_link_down_flag);
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "phy_link_status_p->up_flag %u\n",
+                 phy_link_status_p->up_flag);
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "phy_link_status_p->auto_nego_enable_flag %u\n",
+                 phy_link_status_p->auto_nego_enable_flag);
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "phy_link_status_p->auto_nego_complete_flag %u\n",
+                 phy_link_status_p->auto_nego_complete_flag);
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "phy_link_status_p->link_speed %u\n",
+                 phy_link_status_p->link_speed);
+
+    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
+                 "phy_link_status_p->lpi_capable_flag %u\n",
+                 phy_link_status_p->lpi_capable_flag);
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return gmac_int_sbd_regs;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return gmac_int_sbd_regs;
+    }
+
+    /* Read IER register */
+    gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
+                                               OGMA_GMAC_REG_ADDR_IER);
+    /* Read IMR register */
+    gmac_int_sbd_regs.extended = ( ( ~( ogma_get_mac_reg( ctrl_p,
+                                                          OGMA_GMAC_REG_ADDR_IMR) ) ) &
+                                   OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
+
+
+
+    return gmac_int_sbd_regs;
+}
+
+ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status_non_clear (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    )
+{
+    ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return gmac_int_sbd_regs;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return gmac_int_sbd_regs;
+    }
+
+    /* Read SR register */
+    gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
+                                               OGMA_GMAC_REG_ADDR_SR);
+
+    /* Read ISR register */
+    gmac_int_sbd_regs.extended = ogma_get_mac_reg( ctrl_p,
+                                                   OGMA_GMAC_REG_ADDR_ISR);
+
+    if ( mask_flag) {
+
+        /* Read IER register */
+        gmac_int_sbd_regs.base &= ( ogma_get_mac_reg( ctrl_p,
+                                                      OGMA_GMAC_REG_ADDR_IER) |
+                                    ( ~OGMA_GMAC_INT_SBD_IRQ_IER_ALL) );
+        /* Read IMR register */
+        gmac_int_sbd_regs.extended &= ( ( ~( ogma_get_mac_reg( ctrl_p,
+                                                               OGMA_GMAC_REG_ADDR_IMR) ) ) &
+                                        OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
+    }
+
+
+    return gmac_int_sbd_regs;
+}
+
+ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_gmac_int_sbd_regs_t int_sbd_regs
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Write Clear SR register */
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_SR,
+                      ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL) );
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_enable_gmac_int_sbd_irq (
+    ogma_handle_t ogma_handle,
+    ogma_gmac_int_sbd_regs_t int_sbd_regs
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Read IER register for No Change Value Keep */
+    value = ogma_get_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_IER);
+    /* Write IER register */
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_IER,
+                      ( value | ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_IER_ALL) ) );
+
+    /* Read IMR register for No Change Value Keep */
+    value = ogma_get_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_IMR);
+    /* Write IMR register */
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_IMR,
+                      ( value & ( ~( int_sbd_regs.extended &
+                                     OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) ) );
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_disable_gmac_int_sbd_irq (
+    ogma_handle_t ogma_handle,
+    ogma_gmac_int_sbd_regs_t int_sbd_regs
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Read IER register for No Change Value Keep */
+    value = ogma_get_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_IER);
+    /* Write IER register */
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_IER,
+                      ( value & ( ~(int_sbd_regs.base) ) ) );
+
+    /* Read IMR register for No Change Value Keep */
+    value = ogma_get_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_IMR);
+    /* Write IMR register */
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_IMR,
+                      ( value | ( int_sbd_regs.extended &
+                                  OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) );
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_get_gmac_rgmii_status_reg (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 *value_p
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( value_p == NULL) ){
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->param.use_gmac_flag) {
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Read RGMII Status Register */
+    *value_p = ogma_get_mac_reg( ctrl_p,
+                                 OGMA_GMAC_REG_ADDR_RSR);
+
+
+    return OGMA_ERR_OK;
+}
+
+#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
+ogma_err_t ogma_read_gmac_stat (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 *value_p,
+    ogma_bool reset_flag
+    )
+{
+
+    ogma_uint i;
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) ||
+         ( value_p == NULL) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+
+    for ( i = 0;
+          i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0] );
+          i++) {
+
+        value_p[i] = ogma_get_mac_reg(ctrl_p,
+                                      ogma_gmac_mmc_reg_info[i].addr);
+    }
+
+    if ( reset_flag) {
+        /* Reset all counters. */
+        ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+    }
+
+
+    return OGMA_ERR_OK;
+}
+#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
+
+ogma_err_t ogma_reset_gmac_stat (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+
+    /* Reset all counters. */
+    ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
+
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_softreset_gmac (
+    ogma_ctrl_t *ctrl_p
+    )
+{
+    ogma_uint32 value;
+    pfdep_err_t pfdep_err;
+
+    /* F_GMAC4MT soft reset*/
+    ogma_set_mac_reg( ctrl_p,
+                      OGMA_GMAC_REG_ADDR_BMR,
+                      OGMA_GMAC_BMR_REG_RESET);
+    /* Wait soft reset */
+    pfdep_err = pfdep_msleep( 1);
+
+    if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
+
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "Wait for BMR soft reset error.\n");
+
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    /* Read F_GMAC4MT BMR */
+    value = ogma_get_mac_reg( ctrl_p,
+                              OGMA_GMAC_REG_ADDR_BMR);
+
+    /* check software reset result*/
+    if ( value & OGMA_GMAC_BMR_REG_SWR) {
+        return OGMA_ERR_AGAIN;
+    }
+
+    return OGMA_ERR_OK;
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
new file mode 100644
index 000000000000..e2e25c71abaa
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
@@ -0,0 +1,210 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_INTERNAL_H
+#define OGMA_INTERNAL_H
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+#include "ogma_reg.h"
+#include "pfdep.h"
+
+/* Just a million to prevent typing errors. */
+#define OGMA_CLK_MHZ (1000000)
+
+#define OGMA_INSTANCE_NUM_MAX 1
+
+#define OGMA_RX_PKT_BUF_LEN 1522
+#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
+#define OGMA_DUMMY_DESC_ENTRY_LEN 48
+
+#define OGMA_REG_ADDR_CLK_EN OGMA_REG_ADDR_CLK_EN_0
+
+extern const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
+extern const ogma_uint32 ogma_desc_start_reg_addr[OGMA_DESC_RING_ID_MAX+1];
+
+typedef struct ogma_ctrl_s ogma_ctrl_t;
+typedef struct ogma_desc_ring_s ogma_desc_ring_t;
+typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
+typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
+
+struct ogma_clk_ctrl_s{
+    ogma_uint8 mac_req_num;
+};
+
+
+struct ogma_desc_ring_s{
+
+    ogma_desc_ring_id_t ring_id;
+
+    ogma_desc_ring_param_t param;
+
+    ogma_uint rx_desc_ring_flag:1;
+
+    ogma_uint tx_desc_ring_flag:1;
+
+    ogma_uint running_flag:1;
+
+    ogma_uint full_flag:1;
+
+    ogma_uint8 desc_entry_len;
+
+    ogma_uint16 head_idx;
+
+    ogma_uint16 tail_idx;
+
+    ogma_uint16 rx_num;
+
+    ogma_uint16 tx_done_num;
+
+    pfdep_hard_lock_t inten_reg_hard_lock;
+
+    pfdep_soft_lock_t soft_lock;
+
+    void *desc_ring_cpu_addr;
+
+    pfdep_phys_addr_t desc_ring_phys_addr;
+
+    ogma_frag_info_t *frag_info_p;
+
+    ogma_desc_entry_priv_t *priv_data_p;
+};
+
+struct ogma_ctrl_s{
+    ogma_ctrl_t *next_p;
+
+    ogma_uint core_enabled_flag:1;
+
+    ogma_uint gmac_rx_running_flag:1;
+
+    ogma_uint gmac_tx_running_flag:1;
+
+    ogma_uint gmac_mode_valid_flag:1;
+
+    ogma_uint normal_desc_ring_valid:1;
+
+    void *base_addr;
+
+    pfdep_dev_handle_t dev_handle;
+
+    ogma_param_t param;
+
+    ogma_clk_ctrl_t clk_ctrl;
+
+    ogma_uint32 rx_pkt_buf_len;
+
+    ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
+
+    ogma_gmac_mode_t gmac_mode;
+
+    pfdep_hard_lock_t inten_reg_hard_lock;
+
+    pfdep_hard_lock_t clk_ctrl_hard_lock;
+
+    void *dummy_desc_entry_addr;
+
+    pfdep_phys_addr_t dummy_desc_entry_phys_addr;
+
+#ifdef OGMA_CONFIG_REC_STAT
+    /**
+     * Statistics information.
+     *
+     * Note: Since mutual access exclusion is omitted,
+     *       these values might be inaccurate.
+     */
+    ogma_stat_info_t stat_info;
+#endif /* OGMA_CONFIG_REC_STAT */
+
+};
+
+union ogma_desc_entry_priv_u{
+    pfdep_pkt_handle_t pkt_handle;
+};
+
+/*****************************************************************
+ *****************************************************************
+ *****************************************************************/
+
+/**
+ *
+ */
+ogma_err_t ogma_alloc_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_id_t ring_idx
+    );
+/**
+ *
+ */
+void ogma_free_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    );
+
+/**
+ *
+ */
+ogma_err_t ogma_setup_rx_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    );
+
+/**
+ *
+ */
+void ogma_uninit_pkt_desc_ring (
+    ogma_ctrl_t *ctrl_p,
+    ogma_desc_ring_t *desc_ring_p
+    );
+
+/**
+ *
+ */
+void ogma_push_clk_req (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 domain
+    );
+
+void ogma_pop_clk_req(
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 domain
+    );
+
+
+ogma_err_t ogma_softreset_gmac (
+    ogma_ctrl_t *ctrl_p
+    );
+
+#ifdef OGMA_CONFIG_CHECK_CLK_SUPPLY
+#include "ogma_basic_access.h"
+/*include for ogma_read_reg*/
+static __inline void ogma_check_clk_supply (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 domain
+    )
+{
+    ogma_uint32 value;
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN);
+
+    pfdep_assert( ( ( value & domain ) == domain) );
+}
+
+#else
+
+#define ogma_check_clk_supply( ctrl_p, domain)
+
+#endif /* OGMA_CONFIG_CHECK_CLK_SUPPLY */
+
+#endif /* OGMA_INTERNAL_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
new file mode 100644
index 000000000000..3c54c63126a7
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
@@ -0,0 +1,1385 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "ogma_config.h"
+#include "ogma_internal.h"
+#include "ogma_basic_access.h"
+#include "ogma_misc_internal.h"
+
+#include <Library/IoLib.h>
+
+ogma_global_t ogma_global = {
+    OGMA_FALSE,
+    0,
+    NULL
+};
+
+
+static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
+static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
+
+static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+    OGMA_REG_ADDR_NRM_TX_STATUS,
+    OGMA_REG_ADDR_NRM_RX_STATUS,
+};
+
+static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
+    OGMA_REG_ADDR_NRM_TX_CONFIG,
+    OGMA_REG_ADDR_NRM_RX_CONFIG,
+
+};
+
+
+/* Internal function definition*/
+#ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
+STATIC void ogma_set_clk_en_reg (
+    ogma_ctrl_t *ctrl_p
+    );
+#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+STATIC void ogma_global_init ( void);
+
+STATIC ogma_err_t ogma_probe_hardware (
+    void *base_addr
+    );
+
+STATIC void ogma_reset_hardware (
+    ogma_ctrl_t *ctrl_p
+    );
+
+STATIC void ogma_set_microcode(
+    ogma_ctrl_t *ctrl_p,
+    const void *dma_hm_mc_addr,
+    ogma_uint32 dma_hm_mc_len,
+    const void *dma_mh_mc_addr,
+    ogma_uint32 dma_mh_mc_len,
+    const void *pktc_mc_addr,
+    ogma_uint32 pktc_mc_len
+    );
+
+STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
+    const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
+    );
+
+STATIC void ogma_internal_terminate (
+    ogma_ctrl_t *ctrl_p
+    );
+
+#ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
+
+#define ogma_set_clk_en_reg( ctrl_p)
+
+#else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+STATIC void ogma_set_clk_en_reg (
+    ogma_ctrl_t *ctrl_p
+    )
+{
+    ogma_uint32 value = 0;
+
+    if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
+        value |= OGMA_CLK_EN_REG_DOM_G;
+    }
+
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
+}
+#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
+
+void ogma_push_clk_req (
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 domain
+    )
+{
+    pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
+
+    pfdep_acquire_hard_lock (
+        &ctrl_p->clk_ctrl_hard_lock,
+        &clk_ctrl_hard_lock_ctx);
+
+    if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
+        ++ctrl_p->clk_ctrl.mac_req_num;
+    }
+
+    ogma_set_clk_en_reg( ctrl_p);
+
+    pfdep_release_hard_lock(
+        &ctrl_p->clk_ctrl_hard_lock,
+        &clk_ctrl_hard_lock_ctx);
+}
+
+void ogma_pop_clk_req(
+    ogma_ctrl_t *ctrl_p,
+    ogma_uint32 domain
+    )
+{
+    pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
+
+    pfdep_acquire_hard_lock(
+        &ctrl_p->clk_ctrl_hard_lock,
+        &clk_ctrl_hard_lock_ctx);
+
+    if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
+        --ctrl_p->clk_ctrl.mac_req_num;
+    }
+
+    ogma_set_clk_en_reg( ctrl_p);
+
+    pfdep_release_hard_lock(
+        &ctrl_p->clk_ctrl_hard_lock,
+        &clk_ctrl_hard_lock_ctx);
+}
+
+/* Internal function */
+STATIC void ogma_global_init ( void)
+{
+    ogma_global.valid_flag = OGMA_TRUE;
+}
+
+STATIC ogma_err_t ogma_probe_hardware (
+    void *base_addr
+    )
+{
+
+    ogma_uint32 value;
+
+    /* Read HW_VER Register */
+    value = pfdep_iomem_read((void *)
+                             ((pfdep_cpu_addr_t)base_addr +
+                              (OGMA_REG_ADDR_HW_VER << 2)));
+
+    if ( value != OGMA_VER_NETSEC) {
+        pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
+                    "Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
+                    (unsigned int)value,
+                    (unsigned int)OGMA_VER_NETSEC);
+    }
+
+    if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
+        pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
+                    "Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
+                    (unsigned int)OGMA_VER_MAJOR_NUM(value),
+                    (unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Print hardware version information. */
+    pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+                "NETSEC found. Hardware version: %08x\n",
+                value);
+
+
+    return OGMA_ERR_OK;
+}
+
+STATIC void ogma_reset_hardware (
+    ogma_ctrl_t *ctrl_p
+    )
+{
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_CLK_EN,
+                    OGMA_CLK_EN_REG_DOM_ALL);
+
+
+    /*
+     * Stop dma engines if cores are enabled
+     */
+    if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
+
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_DMA_HM_CTRL,
+                        OGMA_DMA_CTRL_REG_STOP);
+
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_DMA_MH_CTRL,
+                        OGMA_DMA_CTRL_REG_STOP);
+
+        while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
+                  & OGMA_DMA_CTRL_REG_STOP) != 0) {
+            ;
+        }
+
+        while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
+                  & OGMA_DMA_CTRL_REG_STOP) != 0) {
+            ;
+        }
+    }
+
+    if ( ctrl_p->param.use_gmac_flag) {
+
+        /* Reset F_GMAC4MT */
+        ogma_set_mac_reg( ctrl_p,
+                          OGMA_GMAC_REG_ADDR_BMR,
+                          OGMA_GMAC_BMR_REG_RESET);
+
+    }
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_SOFT_RST,
+                    OGMA_SOFT_RST_REG_RESET);
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_SOFT_RST,
+                    OGMA_SOFT_RST_REG_RUN);
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_COM_INIT,
+                    OGMA_COM_INIT_REG_ALL);
+
+    while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
+        ;
+    }
+
+    if ( ctrl_p->param.use_gmac_flag) {
+
+
+        /* MAC desc init */
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_MAC_DESC_INIT,
+                        OGMA_MAC_DESC_INIT_REG_INIT);
+
+        /* Wait MAC desc init done */
+        while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
+                  & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
+            ;
+        }
+
+
+        /* set MAC_INTF_SEL */
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_MAC_INTF_SEL,
+                        ctrl_p->param.gmac_config.phy_interface);
+
+
+    }
+}
+
+#define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
+
+STATIC void ogma_set_microcode (
+    ogma_ctrl_t *ctrl_p,
+    const void *dma_hm_mc_addr,
+    ogma_uint32 dma_hm_mc_len,
+    const void *dma_mh_mc_addr,
+    ogma_uint32 dma_mh_mc_len,
+    const void *pktc_mc_addr,
+    ogma_uint32 pktc_mc_len
+    )
+{
+    ogma_uint i;
+
+    const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
+    const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
+    const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
+
+    /* Loads microcodes to microengines. */
+    for( i = 0; i < dma_hm_mc_len; i++) {
+        UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
+                        data );
+        dmac_hm_cmd_data++;
+    }
+
+    for( i = 0; i < dma_mh_mc_len; i++) {
+        UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
+                        data );
+        dmac_mh_cmd_data++;
+    }
+
+    for( i = 0; i < pktc_mc_len; i++) {
+        UINT32 data = MmioRead32((UINTN)core_cmd_data);
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_PKTC_CMD_BUF,
+                        data );
+        core_cmd_data++;
+    }
+
+}
+
+STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
+    const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
+    )
+{
+    ogma_uint32 param = 0;
+
+    if ( pkt_ctrl_param_p->log_chksum_er_flag) {
+        param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
+    }
+
+    if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
+        param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
+    }
+
+    if ( pkt_ctrl_param_p->log_hd_er_flag) {
+        param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
+    }
+
+    if ( pkt_ctrl_param_p->drp_no_match_flag) {
+        param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
+    }
+
+    return param;
+}
+
+ogma_err_t ogma_init (
+    void *base_addr,
+    pfdep_dev_handle_t dev_handle,
+    const ogma_param_t *param_p,
+    const void *dma_hm_mc_addr,
+    ogma_uint32 dma_hm_mc_len,
+    const void *dma_mh_mc_addr,
+    ogma_uint32 dma_mh_mc_len,
+    const void *pktc_mc_addr,
+    ogma_uint32 pktc_mc_len,
+    ogma_handle_t *ogma_handle_p
+    )
+{
+    ogma_int i;
+    ogma_uint32 domain = 0, value;
+    ogma_err_t ogma_err;
+    ogma_ctrl_t *ctrl_p = NULL;
+
+    ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
+    ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
+
+    ogma_bool all_lock_init_done_flag = OGMA_FALSE;
+
+    pfdep_err_t pfdep_err;
+
+    if ( ( param_p == NULL) ||
+         ( ogma_handle_p == NULL) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
+        return OGMA_ERR_INVALID;
+    }
+
+    if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
+        (! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Please set invalid packet desc_ring_param valid_flag.\n");
+        return OGMA_ERR_DATA;
+    }
+
+    if ( param_p->use_gmac_flag) {
+        if ( ( param_p->gmac_config.phy_interface !=
+              OGMA_PHY_INTERFACE_GMII) &&
+            ( param_p->gmac_config.phy_interface !=
+              OGMA_PHY_INTERFACE_RGMII) &&
+            ( param_p->gmac_config.phy_interface !=
+              OGMA_PHY_INTERFACE_RMII) ) {
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "An error occurred at ogma_init.\n"
+                         "Please set phy_interface to valid value.\n");
+            return OGMA_ERR_DATA;
+        }
+    } else {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Please set use_gmac_flag OGMA_TRUE.\n");
+        return OGMA_ERR_DATA;
+    }
+
+    ogma_err = ogma_probe_hardware( base_addr);
+
+    if ( ogma_err != OGMA_ERR_OK) {
+        return ogma_err;
+    }
+
+    if ( !ogma_global.valid_flag) {
+        ogma_global_init();
+    }
+
+    if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Failed to ogma_handle memory allocation.\n");
+        return OGMA_ERR_ALLOC;
+    }
+
+    pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
+
+    ctrl_p->base_addr = base_addr;
+
+    ctrl_p->dev_handle = dev_handle;
+
+    pfdep_memcpy( ( void *)&ctrl_p->param,
+                  ( void *)param_p,
+                  sizeof( ogma_param_t) );
+
+    /* Initialize hardware lock */
+    pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
+    if ( pfdep_err != PFDEP_ERR_OK) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Failed to inten_reg_hard_lock's initialization.\n");
+       ogma_err = OGMA_ERR_ALLOC;
+       goto err;
+    }
+    inten_reg_hard_lock_init_flag = OGMA_TRUE;
+
+    pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
+    if ( pfdep_err != PFDEP_ERR_OK) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Failed to clk_ctrl_hard_lock's initialization.\n");
+        ogma_err = OGMA_ERR_ALLOC;
+        goto err;
+    }
+    clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
+
+    all_lock_init_done_flag = OGMA_TRUE;
+
+    pfdep_err = pfdep_dma_malloc( dev_handle,
+                                  OGMA_DUMMY_DESC_ENTRY_LEN,
+                                  &ctrl_p->dummy_desc_entry_addr,
+                                  &ctrl_p->dummy_desc_entry_phys_addr);
+
+    if ( pfdep_err != PFDEP_ERR_OK) {
+        ogma_err = OGMA_ERR_ALLOC;
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Failed to dummy_desc_entry's memory allocation.\n");
+        goto err;
+    }
+
+    /* clear dummy desc entry */
+    pfdep_memset( ctrl_p->dummy_desc_entry_addr,
+                  0,
+                  OGMA_DUMMY_DESC_ENTRY_LEN);
+
+    ogma_reset_hardware( ctrl_p);
+
+    if ( param_p->use_gmac_flag) {
+        domain |= OGMA_CLK_EN_REG_DOM_G;
+    }
+
+    ogma_push_clk_req( ctrl_p, domain);
+
+    /* set PKT_CTRL */
+    value = ogma_calc_pkt_ctrl_reg_param( &param_p->pkt_ctrl_param);
+
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_PKT_CTRL,
+                    value);
+
+    if ( param_p->use_jumbo_pkt_flag) {
+
+        ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
+
+        value = ogma_read_reg( ctrl_p,
+                               OGMA_REG_ADDR_PKT_CTRL);
+
+        value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
+
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_PKT_CTRL,
+                        value);
+    } else {
+
+        ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
+
+    }
+
+    /* set pkt desc ring config */
+    for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+        if (  ctrl_p->param.desc_ring_param[i].valid_flag) {
+            value =
+                ( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
+                  OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
+                ( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
+                  OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
+
+            ogma_write_reg( ctrl_p,
+                            desc_ring_config_reg_addr[i],
+                            value);
+
+        }
+    }
+
+    /* set microengines */
+    ogma_set_microcode(ctrl_p,
+                       dma_hm_mc_addr,
+                       dma_hm_mc_len,
+                       dma_mh_mc_addr,
+                       dma_mh_mc_len,
+                       pktc_mc_addr,
+                       pktc_mc_len);
+
+    /* alloc desc_ring*/
+    for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+        ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
+        if ( ogma_err != OGMA_ERR_OK) {
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "An error occurred at ogma_init.\n"
+                         "Failed to ring id NO.%d memory allocation.\n",
+                         i);
+            goto err;
+        }
+    }
+
+    if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
+        if ( ( ogma_err = ogma_setup_rx_desc_ring(
+                   ctrl_p,
+                   &ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
+             != OGMA_ERR_OK) {
+            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                         "An error occurred at ogma_init.\n"
+                         "Failed to NRM_RX packet memory allocation.\n");
+            goto err;
+        }
+    }
+
+    /* microengines need domain G */
+    ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+    /* set DMA tmr ctrl*/
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
+                    ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
+
+    /* start microengines */
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
+
+    if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Failed to waiting for microcode initialize end.\n");
+        ogma_err = OGMA_ERR_INTERRUPT;
+        goto err;
+    }
+
+    /* check microcode load end & start core */
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
+
+    if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_init.\n"
+                     "Failed to microcode loading.\n");
+        ogma_err = OGMA_ERR_INVALID;
+        goto err;
+    }
+
+    /* clear microcode load end status */
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
+                    OGMA_TOP_IRQ_REG_ME_START);
+
+    ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
+
+    ctrl_p->core_enabled_flag = OGMA_TRUE;
+
+    ctrl_p->next_p = ogma_global.list_head_p;
+
+    ogma_global.list_head_p = ctrl_p;
+
+    ++ogma_global.list_entry_num;
+
+    *ogma_handle_p = ctrl_p;
+
+#if 1
+    {
+
+#define OGMA_PKT_CTRL_REG_MODE_TAIKI        (1UL << 28)
+#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
+#define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL <<  4)
+#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
+
+        /* Read Pkt ctrl register */
+        value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
+        value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
+
+        /* change to noromal mode */
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_DMA_MH_CTRL,
+                        OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
+
+        ogma_write_reg( ctrl_p,
+                        OGMA_REG_ADDR_PKT_CTRL,
+                        value);
+
+        while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
+                OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
+            ;
+        }
+
+    }
+#endif
+
+    /* Print microcode version information. */
+    pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
+                "Microcode version: %08x\n",
+                ogma_read_reg( ctrl_p,
+                               mc_ver_reg_addr) );
+
+    return OGMA_ERR_OK;
+
+err:
+    if ( !all_lock_init_done_flag) {
+
+
+        if ( clk_ctrl_hard_lock_init_flag) {
+            pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
+        }
+
+        if ( inten_reg_hard_lock_init_flag) {
+            pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
+        }
+
+    } else {
+
+        ogma_internal_terminate( ctrl_p);
+
+    }
+
+    pfdep_free( ctrl_p);
+
+    return ogma_err;
+}
+
+STATIC void ogma_internal_terminate (
+    ogma_ctrl_t *ctrl_p
+    )
+{
+    ogma_int i;
+
+    ogma_reset_hardware( ctrl_p);
+
+    /* free desc_ring */
+    for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
+        ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
+    }
+
+    if ( ctrl_p->dummy_desc_entry_addr != NULL) {
+        pfdep_dma_free( ctrl_p->dev_handle,
+                        OGMA_DUMMY_DESC_ENTRY_LEN,
+                        ctrl_p->dummy_desc_entry_addr,
+                        ctrl_p->dummy_desc_entry_phys_addr);
+    }
+
+    pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
+
+
+    pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
+
+}
+
+void ogma_terminate (
+    ogma_handle_t ogma_handle
+    )
+{
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
+    ogma_uint32 domain = 0;
+
+    if ( ( ctrl_p == NULL) ||
+         ( ogma_global.list_entry_num == 0) ) {
+       return;
+    }
+
+    pfdep_assert( ogma_global.list_head_p != NULL);
+
+    if ( ctrl_p->param.use_gmac_flag) {
+        domain |= OGMA_CLK_EN_REG_DOM_G;
+    }
+
+    /* pop domain clock */
+    ogma_pop_clk_req( ctrl_p, domain);
+
+    tmp_ctrl_p = ogma_global.list_head_p;
+
+    while(1) {
+        if ( tmp_ctrl_p == NULL) {
+            /* Could not found ctrl_p specified from the list */
+            return;
+        }
+        if ( ctrl_p == tmp_ctrl_p) {
+            if ( old_tmp_ctrl_p != NULL) {
+                old_tmp_ctrl_p->next_p = ctrl_p->next_p;
+            } else {
+                ogma_global.list_head_p = ctrl_p->next_p;
+            }
+            break;
+        }
+        old_tmp_ctrl_p = tmp_ctrl_p;
+        tmp_ctrl_p = tmp_ctrl_p->next_p;
+    }
+
+    ogma_internal_terminate( ctrl_p);
+
+    --ogma_global.list_entry_num;
+
+    pfdep_free( ctrl_p);
+    return;
+}
+
+ogma_err_t ogma_enable_top_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    /* set irq_factor*/
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_disable_top_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    /* clear irq_factor*/
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
+
+    return OGMA_ERR_OK;
+}
+
+ogma_err_t ogma_enable_desc_ring_irq (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    ogma_desc_ring_t *desc_ring_p;
+
+    pfdep_err_t pfdep_err;
+    pfdep_soft_lock_ctx_t soft_lock_ctx;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_enable_desc_ring_irq.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_enable_desc_ring_irq.\n"
+                     "Please select ring id number between 0 and %d.\n",
+                     OGMA_DESC_RING_ID_MAX);
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_enable_desc_ring_irq.\n"
+                     "Please select valid desc ring.\n");
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    desc_ring_p = &ctrl_p->desc_ring[ring_id];
+
+    /* get soft lock */
+    pfdep_err = pfdep_acquire_soft_lock (
+        &desc_ring_p->soft_lock,
+        &soft_lock_ctx);
+
+    if ( pfdep_err != PFDEP_ERR_OK) {
+        return OGMA_ERR_INTERRUPT;
+    }
+
+    if ( !desc_ring_p->running_flag) {
+        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                                 &soft_lock_ctx);
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_enable_desc_ring_irq.\n"
+                     "Please select running desc ring.\n");
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* set irq_factor*/
+    ogma_write_reg( ctrl_p,
+                    desc_ring_irq_inten_set_reg_addr[ring_id],
+                    irq_factor);
+
+    /* free soft_lock*/
+    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
+                             &soft_lock_ctx);
+    return ogma_err;
+}
+
+ogma_err_t ogma_disable_desc_ring_irq (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_disable_desc_ring_irq.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_disable_desc_ring_irq.\n"
+                     "Please select ring id number between 0 and %d.\n",
+                     OGMA_DESC_RING_ID_MAX);
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_disable_desc_ring_irq.\n"
+                     "Please select valid desc ring.\n");
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Clear irq factor*/
+    ogma_write_reg( ctrl_p,
+                    desc_ring_irq_inten_clr_reg_addr[ring_id],
+                    irq_factor);
+
+    return ogma_err;
+}
+
+ogma_err_t ogma_enable_pkt_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    /* set irq_factor*/
+    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
+                    ( irq_factor & OGMA_PKT_IRQ_ALL) );
+
+    return ogma_err;
+}
+
+ogma_err_t ogma_disable_pkt_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return OGMA_ERR_PARAM;
+    }
+
+    /* clear irq_factor*/
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_PKT_INTEN_CLR,
+                    ( irq_factor & OGMA_PKT_IRQ_ALL) );
+
+    return ogma_err;
+}
+
+
+ogma_uint32 ogma_get_top_irq_enable (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_top_irq_enable.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
+
+    return value;
+
+}
+
+
+ogma_uint32 ogma_get_top_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_top_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
+
+    if ( mask_flag) {
+        value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
+    }
+
+    return value;
+}
+
+ogma_err_t ogma_clear_top_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_clear_top_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    /* Write clear irq top  status */
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_TOP_STATUS,
+
+                    ( value & OGMA_TOP_IRQ_REG_ME_START) );
+
+    return OGMA_ERR_OK;
+}
+
+ogma_uint32 ogma_get_desc_ring_irq_enable (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+                     "Please select ring id number between 0 and %d.\n",
+                     OGMA_DESC_RING_ID_MAX);
+        return 0;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_desc_ring_irq_enable.\n"
+                     "Please select valid desc ring.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p,
+                           desc_ring_irq_inten_reg_addr[ring_id] );
+
+    return value;
+}
+
+
+ogma_uint32 ogma_get_desc_ring_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_bool mask_flag
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_desc_ring_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_desc_ring_irq_status.\n"
+                     "Please select ring id number between 0 and %d.\n",
+                     OGMA_DESC_RING_ID_MAX);
+        return 0;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_desc_ring_irq_status.\n"
+                     "Please select valid desc ring.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p,
+                           desc_ring_irq_status_reg_addr[ring_id] );
+
+    if ( mask_flag) {
+        value &= ogma_read_reg( ctrl_p,
+                                desc_ring_irq_inten_reg_addr[ring_id] );
+    }
+
+    return value;
+}
+
+
+
+ogma_err_t ogma_clear_desc_ring_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_desc_ring_id_t ring_id,
+    ogma_uint32 value
+    )
+{
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+                     "Please select ring id number between 0 and %d.\n",
+                     OGMA_DESC_RING_ID_MAX);
+        return OGMA_ERR_PARAM;
+    }
+
+    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_clear_desc_ring_irq_status.\n"
+                     "Please select valid desc ring.\n");
+        return OGMA_ERR_NOTAVAIL;
+    }
+
+    /* Write clear descring irq status */
+    ogma_write_reg( ctrl_p,
+                    desc_ring_irq_status_reg_addr[ring_id],
+                    ( value & ( OGMA_CH_IRQ_REG_EMPTY |
+                                OGMA_CH_IRQ_REG_ERR) ) );
+
+    return OGMA_ERR_OK;
+
+}
+
+
+ogma_uint32 ogma_get_pkt_irq_enable (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_pkt_irq_enable.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
+
+    value &= OGMA_PKT_IRQ_ALL;
+
+    return value;
+
+}
+
+ogma_uint32 ogma_get_pkt_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
+
+    if ( mask_flag) {
+        value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
+    }
+
+    return value;
+}
+
+ogma_err_t ogma_clear_pkt_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_clear_pkt_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    /* Write clear irq pkt  status */
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_PKT_STATUS,
+                    ( value & ( ( OGMA_PKT_IRQ_MAC_ER        |
+                                  OGMA_PKT_IRQ_JUMBO_ER      |
+                                  OGMA_PKT_IRQ_CHKSUM_ER     |
+                                  OGMA_PKT_IRQ_HD_INCOMPLETE |
+                                  OGMA_PKT_IRQ_HD_ER         |
+                                  OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
+
+    return OGMA_ERR_OK;
+}
+
+#ifdef OGMA_CONFIG_REC_STAT
+ogma_err_t ogma_get_stat_info (
+    ogma_handle_t ogma_handle,
+    ogma_stat_info_t *stat_info_p,
+    ogma_bool clear_flag
+    )
+{
+
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
+        return OGMA_ERR_PARAM;
+    }
+
+    pfdep_memcpy( stat_info_p,
+                  &ctrl_p->stat_info,
+                  sizeof( ogma_stat_info_t) );
+
+
+    if ( clear_flag) {
+        pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
+    }
+
+    return OGMA_ERR_OK;
+
+}
+#endif /* OGMA_CONFIG_REC_STAT */
+
+ogma_uint32 ogma_get_hw_ver (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p,
+                           hw_ver_reg_addr);
+
+    return value;
+}
+
+
+ogma_uint32 ogma_get_mcr_ver (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p,
+                           mc_ver_reg_addr);
+
+    return value;
+}
+
+ogma_uint32 ogma_get_mac_irq_enable (
+    ogma_handle_t ogma_handle
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_ogma_get_mac_irq_enable.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
+
+
+    return value;
+}
+
+ogma_uint32 ogma_get_mac_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_bool mask_flag
+    )
+{
+    ogma_uint32 value;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_get_mac_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return 0;
+    }
+
+
+    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
+
+    if ( mask_flag) {
+        value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
+    }
+
+
+    return value;
+}
+
+ogma_err_t ogma_clear_mac_irq_status (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 value
+    )
+{
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_clear_mac_irq_status.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+
+    /* Commented out because no write-clear bit exists now. */
+#if 0
+    ogma_write_reg( ctrl_p,
+                    OGMA_REG_ADDR_MAC_STATUS,
+                    ( value & /* T.B.D. */) );
+#endif
+
+
+    return OGMA_ERR_OK;
+
+}
+
+ogma_err_t ogma_enable_mac_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_uint32 value;
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+    pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_enable_mac_irq.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    /* get inten_reg_hard_lock */
+    pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
+                             &inten_reg_hard_lock_ctx);
+
+   value = ogma_read_reg( ctrl_p,
+                          OGMA_REG_ADDR_MAC_INTEN);
+
+   value |= irq_factor;
+
+   ogma_write_reg( ctrl_p,
+                   OGMA_REG_ADDR_MAC_INTEN,
+                   value);
+
+
+    /* free inten_reg_hard_lock*/
+    pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
+                             &inten_reg_hard_lock_ctx);
+    return ogma_err;
+}
+
+ogma_err_t ogma_disable_mac_irq (
+    ogma_handle_t ogma_handle,
+    ogma_uint32 irq_factor
+    )
+{
+    ogma_uint32 value;
+    ogma_err_t ogma_err = OGMA_ERR_OK;
+    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
+
+    pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
+
+
+    if ( ctrl_p == NULL) {
+        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
+                     "An error occurred at ogma_disable_mac_irq.\n"
+                     "Please set valid ogma_handle.\n");
+        return OGMA_ERR_PARAM;
+    }
+
+    /* get inten_reg_hard_lock */
+    pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
+                             &inten_reg_hard_lock_ctx);
+
+   value = ogma_read_reg( ctrl_p,
+                          OGMA_REG_ADDR_MAC_INTEN);
+
+   value &= (~irq_factor);
+
+   ogma_write_reg( ctrl_p,
+                   OGMA_REG_ADDR_MAC_INTEN,
+                   value);
+
+
+    /* free inten_reg_hard_lock*/
+    pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
+                             &inten_reg_hard_lock_ctx);
+    return ogma_err;
+
+}
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
new file mode 100644
index 000000000000..3bbf8de57a8b
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
@@ -0,0 +1,38 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_MISC_INTERNAL_H
+#define OGMA_MISC_INTERNAL_H
+
+#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
+#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
+
+#define OGMA_CLK_EN_REG_DOM_ALL 0x24
+
+#define OGMA_PKT_IRQ_ALL ( OGMA_PKT_IRQ_MAC_ER    | OGMA_PKT_IRQ_JUMBO_ER      | \
+                           OGMA_PKT_IRQ_CHKSUM_ER | OGMA_PKT_IRQ_HD_INCOMPLETE | \
+                           OGMA_PKT_IRQ_HD_ER     | OGMA_PKT_IRQ_DRP_NO_MATCH)
+
+typedef struct ogma_global_s ogma_global_t;
+
+struct ogma_global_s{
+    ogma_uint valid_flag:1;
+
+    ogma_uint8 list_entry_num;
+
+    ogma_ctrl_t *list_head_p;
+};
+
+#endif /* OGMA_MISC_INTERNAL_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
new file mode 100644
index 000000000000..910b37a25f14
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
@@ -0,0 +1,219 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_H
+#define OGMA_REG_H
+
+#include "ogma_reg_netsec.h"
+#include "ogma_reg_f_gmac_4mt.h"
+
+/* aliases */
+#define OGMA_REG_ADDR_TOP_INTEN OGMA_REG_ADDR_TOP_INTEN_A
+#define OGMA_REG_ADDR_TOP_INTEN_SET OGMA_REG_ADDR_TOP_INTEN_A_SET
+#define OGMA_REG_ADDR_TOP_INTEN_CLR OGMA_REG_ADDR_TOP_INTEN_A_CLR
+/* aliases end here */
+
+/* need fixing */
+#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF            (0x87)
+
+
+/*bit fields for PKT_CTRL*/
+#define OGMA_PKT_CTRL_REG_EN_JUMBO          (1UL << 27)
+#define OGMA_PKT_CTRL_REG_EN_BITPATF        (1UL << 4 )
+#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER     (1UL << 3 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
+#define OGMA_PKT_CTRL_REG_LOG_HD_ER         (1UL << 1 )
+#define OGMA_PKT_CTRL_REG_DRP_NO_MATCH      (1UL << 0 )
+
+#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
+
+/************************************************************
+ * Bit fields
+ ************************************************************/
+/* bit fields for com_init */
+#define OGMA_COM_INIT_REG_DB   (1UL << 2)
+#define OGMA_COM_INIT_REG_CLS  (1UL << 1)
+#define OGMA_COM_INIT_REG_ALL  ( OGMA_COM_INIT_REG_CLS | OGMA_COM_INIT_REG_DB)
+
+/* bit fields for soft_rst */
+#define OGMA_SOFT_RST_REG_RESET (0)
+#define OGMA_SOFT_RST_REG_RUN   (1UL << 31)
+
+/* bit fields for dma_hm_ctrl */
+#define OGMA_DMA_CTRL_REG_STOP 1UL
+
+/* bit fields for gmac_cmd */
+#define OGMA_GMAC_CMD_ST_READ  (0)
+#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
+#define OGMA_GMAC_CMD_ST_BUSY  (1UL << 31)
+
+/* bit fields for F_GMAC4MT BMR*/
+#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
+#define OGMA_GMAC_BMR_REG_RESET  (0x00020181)
+#define OGMA_GMAC_BMR_REG_SWR    (0x00000001)
+
+/* bit fields for F_GMAC4MT OMR*/
+#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
+#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
+
+/* bit fields for F_GMAC4MT MCR*/
+#define OGMA_GMAC_MCR_REG_CST                (1UL << 25)
+#define OGMA_GMAC_MCR_REG_JE                 (1UL << 20)
+#define OGMA_GMAC_MCR_REG_PS                 (1UL << 15)
+#define OGMA_GMAC_MCR_REG_FES                (1UL << 14)
+#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
+#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
+
+#define OGMA_GMAC_MCR_1G_FULL ( OGMA_GMAC_MCR_REG_CST | \
+                                OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_100M_FULL ( OGMA_GMAC_MCR_REG_CST | \
+                                  OGMA_GMAC_MCR_REG_PS  | \
+                                  OGMA_GMAC_MCR_REG_FES | \
+                                  OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_100M_HALF ( OGMA_GMAC_MCR_REG_CST | \
+                                  OGMA_GMAC_MCR_REG_FES | \
+                                  OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_10M_FULL ( OGMA_GMAC_MCR_REG_CST | \
+                                 OGMA_GMAC_MCR_REG_PS  | \
+                                 OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
+
+#define OGMA_GMAC_MCR_10M_HALF ( OGMA_GMAC_MCR_REG_CST | \
+                                 OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
+
+/*bit fields for F_GMAC4MT FCR*/
+#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
+#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
+
+/* bit fields for F_GMAC4MT GAR */
+#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
+#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
+
+/* bit fields for F_GMAC4MT RDLAR*/
+#define OGMA_GMAC_RDLAR_REG_COMMON (0x00018000UL)
+
+/* bit fields for F_GMAC4MT TDLAR*/
+#define OGMA_GMAC_TDLAR_REG_COMMON (0x0001c000UL)
+
+
+#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
+#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
+#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
+
+#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ   (2)
+#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ   (3)
+#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ  (0)
+#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
+#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
+#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
+
+/* bit fields for F_GMAC4MT LPITCR */
+#define OGMA_GMAC_LPITCR_REG_LIT (16)
+#define OGMA_GMAC_LPITCR_REG_TWT (0)
+
+/* bit fileds mask for F_GMAC4MT LPITCR */
+#define OGMA_GMAC_LPITCR_REG_MASK_LIT (0x3ffU)
+#define OGMA_GMAC_LPITCR_REG_MASK_TWT (0xffffU)
+
+/**
+ * PHY regtister Address
+ */
+#define OGMA_PHY_REG_ADDR_CONTROL                      0
+#define OGMA_PHY_REG_ADDR_STATUS                       1U
+#define OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY             4U
+#define OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY 5U
+#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL         9U
+#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS          10U
+#define OGMA_PHY_REG_ADDR_MMD_AC                       13U
+#define OGMA_PHY_REG_ADDR_MMD_AAD                      14U
+
+/* bit fields for PHY CONTROL Register */
+#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6)
+#define OGMA_PHY_CONTROL_REG_DUPLEX_MODE         (8)
+#define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE    (12)
+#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13)
+
+/* bit fields for PHY STATUS Register */
+#define OGMA_PHY_STATUS_REG_LINK_STATUS       (2)
+#define OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY (3)
+#define OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP    (5)
+
+/* bit fields for PHY MASTER-SLAVE Control Register */
+#define OGMA_PHY_MSC_REG_1000BASE_FULL (9)
+#define OGMA_PHY_MSC_REG_1000BASE_HALF (8)
+
+/* bit fields for PHY MASTER-SLAVE Status Register */
+#define OGMA_PHY_MSS_REG_LP_1000BASE_FULL (11)
+#define OGMA_PHY_MSS_REG_LP_1000BASE_HALF (10)
+
+/* bit fields for PHY Auto-Negotiation Advertisement Register */
+#define OGMA_PHY_ANA_REG_TAF (5)
+
+/* bit fileds mask for F_GMAC4MT LPITCR */
+#define OGMA_PHY_ANA_REG_TAF_MASK (0x7fU)
+
+/* bit fields for PHY Technology Ability Field */
+#define OGMA_PHY_TAF_REG_100BASE_FULL (1U << 3)
+#define OGMA_PHY_TAF_REG_100BASE_HALF (1U << 2)
+#define OGMA_PHY_TAF_REG_10BASE_FULL  (1U << 1)
+#define OGMA_PHY_TAF_REG_10BASE_HALF  (1U << 0)
+
+/**
+ * PHY Device Address
+ */
+#define OGMA_PHY_DEV_ADDR_AUTO_NEGO (7U)
+
+/**
+ * PHY Register Address for Device Address 7
+ */
+#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE  (60U)
+#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY (61U)
+
+/* bit fields for PHY AutoNegotiation Field */
+#define OGMA_PHY_AUTO_NEGO_1000BASE_EEE (1U << 2)
+#define OGMA_PHY_AUTO_NEGO_100BASE_EEE  (1U << 1)
+
+/* bit fields for DESC RING CONFIG */
+#define OGMA_REG_DESC_RING_CONFIG_CFG_UP     (31)
+#define OGMA_REG_DESC_RING_CONFIG_CH_RST     (30)
+#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE   (4)
+#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
+
+
+/* bit fields for mac_desc_soft_rst */
+#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
+
+/* bit fields for mac_desc_init */
+#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
+
+/* bit fields for dis_core */
+#define OGMA_DIS_CORE_REG_DIS_PCORE  (1UL << 2)
+#define OGMA_DIS_CORE_REG_DIS_MHCORE (1UL << 1)
+#define OGMA_DIS_CORE_REG_DIS_HMCORE (1UL << 0)
+
+#define OGMA_DIS_CORE_REG_ALL ( OGMA_DIS_CORE_REG_DIS_HMCORE | \
+                                OGMA_DIS_CORE_REG_DIS_MHCORE | \
+                                OGMA_DIS_CORE_REG_DIS_PCORE)
+
+/* bit fields for dma_info */
+#define OGMA_DMA_INFO_REG_AXI_WRITE_BUSY (1UL << 3)
+#define OGMA_DMA_INFO_REG_AXI_READ_BUSY  (1UL << 2)
+
+#define OGMA_DMA_INFO_REG_AXI_BUSY ( OGMA_DMA_INFO_REG_AXI_WRITE_BUSY | \
+                                     OGMA_DMA_INFO_REG_AXI_READ_BUSY)
+
+#endif /*OGMA_REG_H*/
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
new file mode 100644
index 000000000000..e12b317218fb
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
@@ -0,0 +1,222 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_F_GMAC_4MT_H
+#define OGMA_REG_F_GMAC_4MT_H
+
+/**
+ * GMAC register
+ */
+#define OGMA_GMAC_REG_ADDR_MCR      (0x0000)
+#define OGMA_GMAC_REG_ADDR_MFFR     (0x0004)
+#define OGMA_GMAC_REG_ADDR_MHTRH    (0x0008)
+#define OGMA_GMAC_REG_ADDR_MHTRL    (0x000c)
+#define OGMA_GMAC_REG_ADDR_GAR      (0x0010)
+#define OGMA_GMAC_REG_ADDR_GDR      (0x0014)
+#define OGMA_GMAC_REG_ADDR_FCR      (0x0018)
+#define OGMA_GMAC_REG_ADDR_VTR      (0x001c)
+#define OGMA_GMAC_REG_ADDR_RWFFR    (0x0028)
+#define OGMA_GMAC_REG_ADDR_PMTR     (0x002c)
+#define OGMA_GMAC_REG_ADDR_LPICSR   (0x0030)
+#define OGMA_GMAC_REG_ADDR_LPITCR   (0x0034)
+#define OGMA_GMAC_REG_ADDR_ISR      (0x0038)
+#define OGMA_GMAC_REG_ADDR_IMR      (0x003c)
+#define OGMA_GMAC_REG_ADDR_MAR0H    (0x0040)
+#define OGMA_GMAC_REG_ADDR_MAR0L    (0x0044)
+#define OGMA_GMAC_REG_ADDR_MAR1H    (0x0048)
+#define OGMA_GMAC_REG_ADDR_MAR1L    (0x004c)
+#define OGMA_GMAC_REG_ADDR_MAR2H    (0x0050)
+#define OGMA_GMAC_REG_ADDR_MAR2L    (0x0054)
+#define OGMA_GMAC_REG_ADDR_MAR3H    (0x0058)
+#define OGMA_GMAC_REG_ADDR_MAR3L    (0x005c)
+#define OGMA_GMAC_REG_ADDR_MAR4H    (0x0060)
+#define OGMA_GMAC_REG_ADDR_MAR4L    (0x0064)
+#define OGMA_GMAC_REG_ADDR_MAR5H    (0x0068)
+#define OGMA_GMAC_REG_ADDR_MAR5L    (0x006c)
+#define OGMA_GMAC_REG_ADDR_MAR6H    (0x0070)
+#define OGMA_GMAC_REG_ADDR_MAR6L    (0x0074)
+#define OGMA_GMAC_REG_ADDR_MAR7H    (0x0078)
+#define OGMA_GMAC_REG_ADDR_MAR7L    (0x007c)
+#define OGMA_GMAC_REG_ADDR_MAR8H    (0x0080)
+#define OGMA_GMAC_REG_ADDR_MAR8L    (0x0084)
+#define OGMA_GMAC_REG_ADDR_MAR9H    (0x0088)
+#define OGMA_GMAC_REG_ADDR_MAR9L    (0x008c)
+#define OGMA_GMAC_REG_ADDR_MAR10H   (0x0090)
+#define OGMA_GMAC_REG_ADDR_MAR10L   (0x0094)
+#define OGMA_GMAC_REG_ADDR_MAR11H   (0x0098)
+#define OGMA_GMAC_REG_ADDR_MAR11L   (0x009c)
+#define OGMA_GMAC_REG_ADDR_MAR12H   (0x00a0)
+#define OGMA_GMAC_REG_ADDR_MAR12L   (0x00a4)
+#define OGMA_GMAC_REG_ADDR_MAR13H   (0x00a8)
+#define OGMA_GMAC_REG_ADDR_MAR13L   (0x00ac)
+#define OGMA_GMAC_REG_ADDR_MAR14H   (0x00b0)
+#define OGMA_GMAC_REG_ADDR_MAR14L   (0x00b4)
+#define OGMA_GMAC_REG_ADDR_MAR15H   (0x00b8)
+#define OGMA_GMAC_REG_ADDR_MAR15L   (0x00bc)
+#define OGMA_GMAC_REG_ADDR_RSR      (0x00d8)
+#define OGMA_GMAC_REG_ADDR_TSCR     (0x0700)
+#define OGMA_GMAC_REG_ADDR_SSIR     (0x0704)
+#define OGMA_GMAC_REG_ADDR_STSR     (0x0708)
+#define OGMA_GMAC_REG_ADDR_STNR     (0x070c)
+#define OGMA_GMAC_REG_ADDR_STSUR    (0x0710)
+#define OGMA_GMAC_REG_ADDR_STNUR    (0x0714)
+#define OGMA_GMAC_REG_ADDR_TSAR     (0x0718)
+#define OGMA_GMAC_REG_ADDR_TTSR     (0x071c)
+#define OGMA_GMAC_REG_ADDR_TTNR     (0x0720)
+#define OGMA_GMAC_REG_ADDR_STHWSR   (0x0724)
+#define OGMA_GMAC_REG_ADDR_TSR      (0x0728)
+#define OGMA_GMAC_REG_ADDR_PPSCR    (0x072c)
+#define OGMA_GMAC_REG_ADDR_ANTR     (0x0730)
+#define OGMA_GMAC_REG_ADDR_ATSR     (0x0734)
+#define OGMA_GMAC_REG_ADDR_MAR16H   (0x0800)
+#define OGMA_GMAC_REG_ADDR_MAR16L   (0x0804)
+#define OGMA_GMAC_REG_ADDR_MAR17H   (0x0808)
+#define OGMA_GMAC_REG_ADDR_MAR17L   (0x080c)
+#define OGMA_GMAC_REG_ADDR_MAR18H   (0x0810)
+#define OGMA_GMAC_REG_ADDR_MAR18L   (0x0814)
+#define OGMA_GMAC_REG_ADDR_MAR19H   (0x0818)
+#define OGMA_GMAC_REG_ADDR_MAR19L   (0x081c)
+#define OGMA_GMAC_REG_ADDR_MAR20H   (0x0820)
+#define OGMA_GMAC_REG_ADDR_MAR20L   (0x0824)
+#define OGMA_GMAC_REG_ADDR_MAR21H   (0x0828)
+#define OGMA_GMAC_REG_ADDR_MAR21L   (0x082c)
+#define OGMA_GMAC_REG_ADDR_MAR22H   (0x0830)
+#define OGMA_GMAC_REG_ADDR_MAR22L   (0x0834)
+#define OGMA_GMAC_REG_ADDR_MAR23H   (0x0838)
+#define OGMA_GMAC_REG_ADDR_MAR23L   (0x083c)
+#define OGMA_GMAC_REG_ADDR_MAR24H   (0x0840)
+#define OGMA_GMAC_REG_ADDR_MAR24L   (0x0844)
+#define OGMA_GMAC_REG_ADDR_MAR25H   (0x0848)
+#define OGMA_GMAC_REG_ADDR_MAR25L   (0x084c)
+#define OGMA_GMAC_REG_ADDR_MAR26H   (0x0850)
+#define OGMA_GMAC_REG_ADDR_MAR26L   (0x0854)
+#define OGMA_GMAC_REG_ADDR_MAR27H   (0x0858)
+#define OGMA_GMAC_REG_ADDR_MAR27L   (0x085c)
+#define OGMA_GMAC_REG_ADDR_MAR28H   (0x0860)
+#define OGMA_GMAC_REG_ADDR_MAR28L   (0x0864)
+#define OGMA_GMAC_REG_ADDR_MAR29H   (0x0868)
+#define OGMA_GMAC_REG_ADDR_MAR29L   (0x086c)
+#define OGMA_GMAC_REG_ADDR_MAR30H   (0x0870)
+#define OGMA_GMAC_REG_ADDR_MAR30L   (0x0874)
+#define OGMA_GMAC_REG_ADDR_MAR31H   (0x0878)
+#define OGMA_GMAC_REG_ADDR_MAR31L   (0x087c)
+
+/**
+ * GMAC MAC Management Counters(Option) register
+ */
+#define OGMA_GMAC_REG_ADDR_MMC_CNTL                  (0x0100)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX               (0x0104)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX               (0x0108)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX          (0x010c)
+#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX          (0x0110)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB           (0x0114)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB           (0x0118)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G       (0x011c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G       (0x0120)
+#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB             (0x0124)
+#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB        (0x0128)
+#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB       (0x012c)
+#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB       (0x0130)
+#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB      (0x0134)
+#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB      (0x0138)
+#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB        (0x013c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB      (0x0140)
+#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB      (0x0144)
+#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR          (0x0148)
+#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G             (0x014c)
+#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G              (0x0150)
+#define OGMA_GMAC_REG_ADDR_TXDEFERRED                (0x0154)
+#define OGMA_GMAC_REG_ADDR_TXLATECOL                 (0x0158)
+#define OGMA_GMAC_REG_ADDR_TXEXESSCOL                (0x015c)
+#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR           (0x0160)
+#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G            (0x0164)
+#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G            (0x0168)
+#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF              (0x016c)
+#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES             (0x0170)
+#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G            (0x0174)
+#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB           (0x0180)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB           (0x0184)
+#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G            (0x0188)
+#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G       (0x018c)
+#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G       (0x0190)
+#define OGMA_GMAC_REG_ADDR_RXCRCERROR                (0x0194)
+#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR         (0x0198)
+#define OGMA_GMAC_REG_ADDR_RXRUNTERROR               (0x019c)
+#define OGMA_GMAC_REG_ADDR_RXJABBERERROR             (0x01a0)
+#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G             (0x01a4)
+#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G              (0x01a8)
+#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB             (0x01ac)
+#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB        (0x01b0)
+#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB       (0x01b4)
+#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB       (0x01b8)
+#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB      (0x01bc)
+#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB      (0x01c0)
+#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G         (0x01c4)
+#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR             (0x01c8)
+#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE          (0x01cc)
+#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES             (0x01d0)
+#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW            (0x01d4)
+#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB           (0x01d8)
+#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR           (0x01dc)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX      (0x0200)
+#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX           (0x0208)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS            (0x0210)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS        (0x0214)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS         (0x0218)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS          (0x021c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS         (0x0220)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS            (0x0224)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS        (0x0228)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS         (0x022c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS             (0x0230)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS            (0x0234)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS             (0x0238)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS            (0x023c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS            (0x0240)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS           (0x0244)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS          (0x0250)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS      (0x0254)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS       (0x0258)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS        (0x025c)
+#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS       (0x0260)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS          (0x0264)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS      (0x0268)
+#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS       (0x026c)
+#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS           (0x0270)
+#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS          (0x0274)
+#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS           (0x0278)
+#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS          (0x027c)
+#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS          (0x0280)
+#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS         (0x0284)
+/**
+ * GMAC DMA register
+ */
+#define OGMA_GMAC_REG_ADDR_BMR      (0x1000)
+#define OGMA_GMAC_REG_ADDR_TPDR     (0x1004)
+#define OGMA_GMAC_REG_ADDR_RPDR     (0x1008)
+#define OGMA_GMAC_REG_ADDR_RDLAR    (0x100c)
+#define OGMA_GMAC_REG_ADDR_TDLAR    (0x1010)
+#define OGMA_GMAC_REG_ADDR_SR       (0x1014)
+#define OGMA_GMAC_REG_ADDR_OMR      (0x1018)
+#define OGMA_GMAC_REG_ADDR_IER      (0x101c)
+#define OGMA_GMAC_REG_ADDR_MFOCR    (0x1020)
+#define OGMA_GMAC_REG_ADDR_RIWTR    (0x1024)
+#define OGMA_GMAC_REG_ADDR_AHBSR    (0x102c)
+#define OGMA_GMAC_REG_ADDR_CHTDR    (0x1048)
+#define OGMA_GMAC_REG_ADDR_CHRDR    (0x104c)
+#define OGMA_GMAC_REG_ADDR_CHTBAR   (0x1050)
+#define OGMA_GMAC_REG_ADDR_CHRBAR   (0x1054)
+
+#endif /* OGMA_REG_F_GMAC_4MT_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
new file mode 100644
index 000000000000..457be2aa0cba
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
@@ -0,0 +1,368 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_REG_NETSEC_H
+#define OGMA_REG_NETSEC_H
+
+#define OGMA_REG_ADDR_SOFT_RST (0x41)
+#define OGMA_REG_ADDR_COM_INIT (0x48)
+#define OGMA_REG_ADDR_MC_BASE_ADDR (0x97)
+#define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84)
+#define OGMA_REG_ADDR_DMAC_MC_ADDR_MH (0x89)
+#define OGMA_REG_ADDR_DMAC_MC_SIZE_MH (0x8A)
+#define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34)
+#define OGMA_REG_ADDR_PKTC_MC_ADDR (0x5C)
+#define OGMA_REG_ADDR_PKTC_MC_SIZE (0x5D)
+#define OGMA_REG_ADDR_DIS_CORE (0x86)
+#define OGMA_REG_ADDR_DMA_HM_CTRL (0x85)
+#define OGMA_REG_ADDR_DMA_MH_CTRL (0x88)
+#define OGMA_REG_ADDR_CLK_EN_0 (0x40)
+#define OGMA_REG_ADDR_CLK_EN_1 (0x64)
+#define OGMA_REG_ADDR_PKT_CTRL (0x50)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START_UP (0x10D)
+#define OGMA_REG_ADDR_NRM_TX_DESC_START_LW (0x102)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START_UP (0x11D)
+#define OGMA_REG_ADDR_NRM_RX_DESC_START_LW (0x112)
+#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_UP (0x12D)
+#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_LW (0x122)
+#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_UP (0x13D)
+#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_LW (0x132)
+#define OGMA_REG_ADDR_MISC_RX_DESC_START_UP (0x14D)
+#define OGMA_REG_ADDR_MISC_RX_DESC_START_LW (0x142)
+#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_UP (0x15D)
+#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_LW (0x152)
+#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_UP (0x16D)
+#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_LW (0x162)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_UP (0x17D)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_LW (0x172)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_UP (0x18D)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_LW (0x182)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_UP (0x19D)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_LW (0x192)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_UP (0x1AD)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_LW (0x1A2)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_UP (0x1BD)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_LW (0x1B2)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_UP (0x1CD)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_LW (0x1C2)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_UP (0x1DD)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_LW (0x1D2)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_UP (0x1ED)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_LW (0x1E2)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_UP (0x20D)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_LW (0x202)
+#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_UP (0x21D)
+#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_LW (0x212)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_UP (0x22D)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_LW (0x222)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_UP (0x23D)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_LW (0x232)
+#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_UP (0x24D)
+#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_LW (0x242)
+#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_UP (0x25D)
+#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_LW (0x252)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_UP (0x26D)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_LW (0x262)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_UP (0x27D)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_LW (0x272)
+#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_UP (0x28D)
+#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_LW (0x282)
+#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_UP (0x29D)
+#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_LW (0x292)
+#define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10C)
+#define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11C)
+#define OGMA_REG_ADDR_TAIKI_RX_CONFIG (0x12C)
+#define OGMA_REG_ADDR_TAIKI_TX_CONFIG (0x13C)
+#define OGMA_REG_ADDR_MISC_RX_CONFIG (0x14C)
+#define OGMA_REG_ADDR_WL_NRM_TX_CONFIG (0x15C)
+#define OGMA_REG_ADDR_WL_NRM_RX_CONFIG (0x16C)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_CONFIG (0x17C)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_CONFIG (0x18C)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_CONFIG (0x19C)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_CONFIG (0x1AC)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_CONFIG (0x1BC)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_CONFIG (0x1CC)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_CONFIG (0x1DC)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_CONFIG (0x1EC)
+#define OGMA_REG_ADDR_DEC_PKT_TX_CONFIG (0x20C)
+#define OGMA_REG_ADDR_ENC_PKT_RX_CONFIG (0x21C)
+#define OGMA_REG_ADDR_ENC_TLS_TX_CONFIG (0x22C)
+#define OGMA_REG_ADDR_DEC_TLS_TX_CONFIG (0x23C)
+#define OGMA_REG_ADDR_ENC_TLS_RX_CONFIG (0x24C)
+#define OGMA_REG_ADDR_DEC_TLS_RX_CONFIG (0x25C)
+#define OGMA_REG_ADDR_ENC_RAW_TX_CONFIG (0x26C)
+#define OGMA_REG_ADDR_DEC_RAW_TX_CONFIG (0x27C)
+#define OGMA_REG_ADDR_ENC_RAW_RX_CONFIG (0x28C)
+#define OGMA_REG_ADDR_DEC_RAW_RX_CONFIG (0x29C)
+#define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83)
+#define OGMA_REG_ADDR_TOP_STATUS (0x80)
+#define OGMA_REG_ADDR_TOP_INTEN_A (0x81)
+#define OGMA_REG_ADDR_TOP_INTEN_A_SET (0x8D)
+#define OGMA_REG_ADDR_TOP_INTEN_A_CLR (0x8E)
+#define OGMA_REG_ADDR_TOP_INTEN_B (0x8F)
+#define OGMA_REG_ADDR_TOP_INTEN_B_SET (0x90)
+#define OGMA_REG_ADDR_TOP_INTEN_B_CLR (0x91)
+#define OGMA_REG_ADDR_PKT_STATUS (0x3)
+#define OGMA_REG_ADDR_PKT_INTEN (0x4)
+#define OGMA_REG_ADDR_PKT_INTEN_SET (0x7)
+#define OGMA_REG_ADDR_PKT_INTEN_CLR (0x8)
+#define OGMA_REG_ADDR_TLS_STATUS (0x5)
+#define OGMA_REG_ADDR_TLS_INTEN (0x6)
+#define OGMA_REG_ADDR_TLS_INTEN_SET (0x9)
+#define OGMA_REG_ADDR_TLS_INTEN_CLR (0xA)
+#define OGMA_REG_ADDR_SLAVE_0_STATUS (0xB)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN (0xC)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN_SET (0xD)
+#define OGMA_REG_ADDR_SLAVE_0_INTEN_CLR (0xE)
+#define OGMA_REG_ADDR_SLAVE_1_STATUS (0xF)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN (0x10)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN_SET (0x11)
+#define OGMA_REG_ADDR_SLAVE_1_INTEN_CLR (0x12)
+#define OGMA_REG_ADDR_MAC_STATUS (0x409)
+#define OGMA_REG_ADDR_MAC_INTEN (0x40A)
+#define OGMA_REG_ADDR_MAC_TX_RX_INFO_STATUS (0x486)
+#define OGMA_REG_ADDR_MAC_TX_RX_INFO_INTEN (0x487)
+#define OGMA_REG_ADDR_NRM_TX_STATUS (0x100)
+#define OGMA_REG_ADDR_NRM_TX_INTEN (0x101)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10A)
+#define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10B)
+#define OGMA_REG_ADDR_NRM_RX_STATUS (0x110)
+#define OGMA_REG_ADDR_NRM_RX_INTEN (0x111)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11A)
+#define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11B)
+#define OGMA_REG_ADDR_TAIKI_RX_STATUS (0x120)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN (0x121)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN_SET (0x12A)
+#define OGMA_REG_ADDR_TAIKI_RX_INTEN_CLR (0x12B)
+#define OGMA_REG_ADDR_TAIKI_TX_STATUS (0x130)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN (0x131)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN_SET (0x13A)
+#define OGMA_REG_ADDR_TAIKI_TX_INTEN_CLR (0x13B)
+#define OGMA_REG_ADDR_MISC_RX_STATUS (0x140)
+#define OGMA_REG_ADDR_MISC_RX_INTEN (0x141)
+#define OGMA_REG_ADDR_MISC_RX_INTEN_SET (0x14A)
+#define OGMA_REG_ADDR_MISC_RX_INTEN_CLR (0x14B)
+#define OGMA_REG_ADDR_WL_NRM_TX_STATUS (0x150)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN (0x151)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_SET (0x15A)
+#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_CLR (0x15B)
+#define OGMA_REG_ADDR_WL_NRM_RX_STATUS (0x160)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN (0x161)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_SET (0x16A)
+#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_CLR (0x16B)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_STATUS (0x170)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN (0x171)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_SET (0x17A)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_CLR (0x17B)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_STATUS (0x180)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN (0x181)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_SET (0x18A)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_CLR (0x18B)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_STATUS (0x190)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN (0x191)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_SET (0x19A)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_CLR (0x19B)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_STATUS (0x1A0)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN (0x1A1)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_SET (0x1AA)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_CLR (0x1AB)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_STATUS (0x1B0)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN (0x1B1)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_SET (0x1BA)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_CLR (0x1BB)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_STATUS (0x1C0)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN (0x1C1)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_SET (0x1CA)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_CLR (0x1CB)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_STATUS (0x1D0)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN (0x1D1)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_SET (0x1DA)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_CLR (0x1DB)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_STATUS (0x1E0)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN (0x1E1)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_SET (0x1EA)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_CLR (0x1EB)
+#define OGMA_REG_ADDR_DEC_TX_STATUS (0x200)
+#define OGMA_REG_ADDR_DEC_TX_INTEN (0x201)
+#define OGMA_REG_ADDR_DEC_TX_INTEN_SET (0x20A)
+#define OGMA_REG_ADDR_DEC_TX_INTEN_CLR (0x20B)
+#define OGMA_REG_ADDR_ENC_RX_STATUS (0x210)
+#define OGMA_REG_ADDR_ENC_RX_INTEN (0x211)
+#define OGMA_REG_ADDR_ENC_RX_INTEN_SET (0x21A)
+#define OGMA_REG_ADDR_ENC_RX_INTEN_CLR (0x21B)
+#define OGMA_REG_ADDR_ENC_TLS_TX_STATUS (0x220)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN (0x221)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_SET (0x22A)
+#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_CLR (0x22B)
+#define OGMA_REG_ADDR_DEC_TLS_TX_STATUS (0x230)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN (0x231)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_SET (0x23A)
+#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_CLR (0x23B)
+#define OGMA_REG_ADDR_ENC_TLS_RX_STATUS (0x240)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN (0x241)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_SET (0x24A)
+#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_CLR (0x24B)
+#define OGMA_REG_ADDR_DEC_TLS_RX_STATUS (0x250)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN (0x251)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_SET (0x25A)
+#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_CLR (0x25B)
+#define OGMA_REG_ADDR_ENC_RAW_TX_STATUS (0x260)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN (0x261)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_SET (0x26A)
+#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_CLR (0x26B)
+#define OGMA_REG_ADDR_DEC_RAW_TX_STATUS (0x270)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN (0x271)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_SET (0x27A)
+#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_CLR (0x27B)
+#define OGMA_REG_ADDR_ENC_RAW_RX_STATUS (0x280)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN (0x281)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_SET (0x28A)
+#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_CLR (0x28B)
+#define OGMA_REG_ADDR_DEC_RAW_RX_STATUS (0x290)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN (0x291)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_SET (0x29A)
+#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_CLR (0x29B)
+#define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104)
+#define OGMA_REG_ADDR_TAIKI_TX_PKTCNT (0x134)
+#define OGMA_REG_ADDR_WL_NRM_TX_PKTCNT (0x154)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_PKTCNT (0x1A4)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_PKTCNT (0x174)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_PKTCNT (0x1C4)
+#define OGMA_REG_ADDR_DEC_PKT_TX_PKTCNT (0x204)
+#define OGMA_REG_ADDR_ENC_TLS_TX_PKTCNT (0x224)
+#define OGMA_REG_ADDR_DEC_TLS_TX_PKTCNT (0x234)
+#define OGMA_REG_ADDR_ENC_RAW_TX_PKTCNT (0x264)
+#define OGMA_REG_ADDR_DEC_RAW_TX_PKTCNT (0x274)
+#define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105)
+#define OGMA_REG_ADDR_TAIKI_TX_DONE_PKTCNT (0x135)
+#define OGMA_REG_ADDR_WL_NRM_TX_DONE_PKTCNT (0x155)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_PKTCNT (0x1A5)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_PKTCNT (0x175)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_PKTCNT (0x1C5)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_PKTCNT (0x205)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_PKTCNT (0x225)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_PKTCNT (0x235)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_PKTCNT (0x265)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_PKTCNT (0x275)
+#define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106)
+#define OGMA_REG_ADDR_TAIKI_TX_DONE_TXINT_PKTCNT (0x136)
+#define OGMA_REG_ADDR_WL_NRM_TX_DONE_TXINT_PKTCNT (0x156)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_TXINT_PKTCNT (0x1A6)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_TXINT_PKTCNT (0x176)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_TXINT_PKTCNT (0x1C6)
+#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_TXINT_PKTCNT (0x206)
+#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_TXINT_PKTCNT (0x226)
+#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_TXINT_PKTCNT (0x236)
+#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_TXINT_PKTCNT (0x266)
+#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_TXINT_PKTCNT (0x276)
+#define OGMA_REG_ADDR_NRM_TX_TMR (0x107)
+#define OGMA_REG_ADDR_TAIKI_TX_TMR (0x137)
+#define OGMA_REG_ADDR_WL_NRM_TX_TMR (0x157)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TMR (0x177)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_TMR (0x1A7)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TMR (0x1C7)
+#define OGMA_REG_ADDR_DEC_TX_TMR (0x207)
+#define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108)
+#define OGMA_REG_ADDR_TAIKI_TX_TXINT_TMR (0x138)
+#define OGMA_REG_ADDR_WL_NRM_TX_TXINT_TMR (0x158)
+#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TXINT_TMR (0x178)
+#define OGMA_REG_ADDR_WL_TAIKI_TX_TXINT_TMR (0x1A8)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TXINT_TMR (0x1C8)
+#define OGMA_REG_ADDR_DEC_TX_TXINT_TMR (0x208)
+#define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115)
+#define OGMA_REG_ADDR_TAIKI_RX_PKTCNT (0x125)
+#define OGMA_REG_ADDR_MISC_RX_PKTCNT (0x145)
+#define OGMA_REG_ADDR_WL_NRM_RX_PKTCNT (0x165)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_PKTCNT (0x185)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_PKTCNT (0x195)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_PKTCNT (0x1B5)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_PKTCNT (0x1D5)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_PKTCNT (0x1E5)
+#define OGMA_REG_ADDR_ENC_PKT_RX_PKTCNT (0x215)
+#define OGMA_REG_ADDR_ENC_TLS_RX_PKTCNT (0x245)
+#define OGMA_REG_ADDR_DEC_TLS_RX_PKTCNT (0x255)
+#define OGMA_REG_ADDR_ENC_RAW_RX_PKTCNT (0x285)
+#define OGMA_REG_ADDR_DEC_RAW_RX_PKTCNT (0x295)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116)
+#define OGMA_REG_ADDR_TAIKI_RXINT_PKTCNT (0x126)
+#define OGMA_REG_ADDR_MISC_RXINT_PKTCNT (0x146)
+#define OGMA_REG_ADDR_WL_NRM_RXINT_PKTCNT (0x166)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RXINT_PKTCNT (0x186)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RXINT_PKTCNT (0x196)
+#define OGMA_REG_ADDR_WL_TAIKI_RXINT_PKTCNT (0x1B6)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RXINT_PKTCNT (0x1D6)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RXINT_PKTCNT (0x1E6)
+#define OGMA_REG_ADDR_ENC_PKT_RXINT_PKTCNT (0x216)
+#define OGMA_REG_ADDR_ENC_TLS_RXINT_PKTCNT (0x246)
+#define OGMA_REG_ADDR_DEC_TLS_RXINT_PKTCNT (0x256)
+#define OGMA_REG_ADDR_ENC_RAW_RXINT_PKTCNT (0x286)
+#define OGMA_REG_ADDR_DEC_RAW_RXINT_PKTCNT (0x296)
+#define OGMA_REG_ADDR_NRM_RX_TMR (0x117)
+#define OGMA_REG_ADDR_TAIKI_RX_TMR (0x127)
+#define OGMA_REG_ADDR_MISC_RX_TMR (0x147)
+#define OGMA_REG_ADDR_WL_NRM_RX_TMR (0x167)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_TMR (0x187)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_TMR (0x197)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_TMR (0x1B7)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_TMR (0x1D7)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_TMR (0x1E7)
+#define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118)
+#define OGMA_REG_ADDR_TAIKI_RX_RXINT_TMR (0x128)
+#define OGMA_REG_ADDR_MISC_RX_RXINT_TMR (0x148)
+#define OGMA_REG_ADDR_WL_NRM_RX_RXINT_TMR (0x168)
+#define OGMA_REG_ADDR_WL_NRM_CMD_RX_RXINT_TMR (0x188)
+#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_RXINT_TMR (0x198)
+#define OGMA_REG_ADDR_WL_TAIKI_RX_RXINT_TMR (0x1B8)
+#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_RXINT_TMR (0x1D8)
+#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_RXINT_TMR (0x1E8)
+#define OGMA_REG_ADDR_PODB_CMD_ST (0x20)
+#define OGMA_REG_ADDR_PODB_DATA (0x21)
+#define OGMA_REG_ADDR_CLS_VAL_CMD (0x2A)
+#define OGMA_REG_ADDR_CLS_VAL_DATA (0x2B)
+#define OGMA_REG_ADDR_CLS_CMD_ST (0x2C)
+#define OGMA_REG_ADDR_CLS_DATA (0x2D)
+#define OGMA_REG_ADDR_SADB_CMD_ST (0x2E)
+#define OGMA_REG_ADDR_SADB_DATA (0x2F)
+#define OGMA_REG_ADDR_MAC_CMD (0x471)
+#define OGMA_REG_ADDR_MAC_DATA (0x470)
+#define OGMA_REG_ADDR_MAC_FLOW_TH (0x473)
+#define OGMA_REG_ADDR_MAC_INTF_SEL (0x475)
+#define OGMA_REG_ADDR_MAC_TX_TSTAMP_LW (0x476)
+#define OGMA_REG_ADDR_MAC_TX_TSTAMP_UP (0x477)
+#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_UP (0x478)
+#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_LW (0x479)
+#define OGMA_REG_ADDR_MAC_TSTAM_CAP (0x47A)
+#define OGMA_REG_ADDR_MAC_SNAP_TRIG (0x47B)
+#define OGMA_REG_ADDR_MAC_SEC_CNT (0x47C)
+#define OGMA_REG_ADDR_MAC_DESC_INIT (0x47F)
+#define OGMA_REG_ADDR_MAC_TX_TS_GET (0x480)
+#define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481)
+#define OGMA_REG_ADDR_IV_INIT_VAL (0x45)
+#define OGMA_REG_ADDR_MAC_ADD_UP (0x43)
+#define OGMA_REG_ADDR_MAC_ADD_LW (0x44)
+#define OGMA_REG_ADDR_ST_INFO_ST_UP (0x65)
+#define OGMA_REG_ADDR_ST_INFO_ST_LW (0x66)
+#define OGMA_REG_ADDR_ST_INFO_SIZE (0x67)
+#define OGMA_REG_ADDR_ST_INFO_TX_ST (0x68)
+#define OGMA_REG_ADDR_LOGIC_GR_ID (0x69)
+#define OGMA_REG_ADDR_ST_FOR_PBC (0x6A)
+#define OGMA_REG_ADDR_ALARM_INFO (0x6B)
+#define OGMA_REG_ADDR_MC_VER (0x8B)
+#define OGMA_REG_ADDR_HW_VER (0x8C)
+
+#define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140)
+
+#endif /* OGMA_REG_F_TAIKI_H */
+
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
new file mode 100644
index 000000000000..1caf64e30623
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
@@ -0,0 +1,25 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef OGMA_CONFIG_H
+#define OGMA_CONFIG_H
+
+#define OGMA_CONFIG_CLK_HZ 125000000UL
+#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL
+#define OGMA_CONFIG_CHECK_CLK_SUPPLY
+
+#define OGMA_CONFIG_USE_READ_GMAC_STAT
+
+#endif /* OGMA_CONFIG_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
new file mode 100644
index 000000000000..f617f1c70183
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
@@ -0,0 +1,265 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PFDEP_H
+#define PFDEP_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <Library/BaseLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+
+#include <Protocol/Cpu.h>
+
+extern EFI_CPU_ARCH_PROTOCOL      *mCpu;
+
+/**********************************************************************
+ * Constant definitions
+ **********************************************************************/
+#define PFDEP_INT64_AVAILABLE
+
+/**********************************************************************
+ * Elementary type definitions
+ **********************************************************************/
+typedef int8_t pfdep_int8;
+typedef uint8_t pfdep_uint8;
+typedef int16_t pfdep_int16;
+typedef uint16_t pfdep_uint16;
+typedef int pfdep_int32;
+typedef unsigned int pfdep_uint32;
+typedef int64_t pfdep_int64;
+typedef uint64_t pfdep_uint64;
+typedef int pfdep_bool;
+typedef char pfdep_char;
+
+#define PFDEP_TRUE ((pfdep_bool)1)
+#define PFDEP_FALSE ((pfdep_bool)0)
+
+
+/**********************************************************************
+ * Complex type definitions
+ **********************************************************************/
+
+typedef enum pfdep_err_e {
+    PFDEP_ERR_OK = 0,
+    PFDEP_ERR_PARAM,
+    PFDEP_ERR_ALLOC,
+    PFDEP_ERR_INTERRUPT
+} pfdep_err_t;
+
+
+typedef struct {
+    LIST_ENTRY  Link;
+    VOID        *Buffer;
+    VOID        *Mapping;
+    BOOLEAN     RecycleForTx;
+    BOOLEAN     Released;
+} PACKET_HANDLE;
+
+typedef VOID *pfdep_dev_handle_t;
+typedef PACKET_HANDLE *pfdep_pkt_handle_t;
+typedef EFI_PHYSICAL_ADDRESS pfdep_phys_addr_t;
+typedef UINT64 pfdep_cpu_addr_t;
+
+typedef int pfdep_hard_lock_t;
+typedef int pfdep_soft_lock_t;
+
+typedef BOOLEAN pfdep_hard_lock_ctx_t;
+typedef int pfdep_soft_lock_ctx_t;
+
+typedef unsigned int pfdep_debug_level_t;
+
+#define PFDEP_DEBUG_LEVEL_FATAL               ((pfdep_debug_level_t)1)
+#define PFDEP_DEBUG_LEVEL_WARNING             ((pfdep_debug_level_t)2)
+#define PFDEP_DEBUG_LEVEL_NOTICE              ((pfdep_debug_level_t)3)
+#define PFDEP_DEBUG_LEVEL_DEBUG               ((pfdep_debug_level_t)4)
+#define PFDEP_DEBUG_LEVEL_DEBUG_DETAILED      ((pfdep_debug_level_t)5)
+#define PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED ((pfdep_debug_level_t)6)
+
+/**********************************************************************
+ * Variable declarations
+ **********************************************************************/
+extern pfdep_debug_level_t pfdep_debug_level; /* defined in pfdep_uefi.c */
+
+
+/**********************************************************************
+ * Function declarations
+ **********************************************************************/
+
+static __inline pfdep_uint32 pfdep_iomem_read(void *addr)
+{
+    return *((volatile pfdep_uint32 *)(addr));
+}
+
+static __inline void pfdep_iomem_write(void *addr, pfdep_uint32 val)
+{
+    *((volatile pfdep_uint32 *)(addr)) = val;
+
+
+}
+
+#define pfdep_read_mem_barrier()    MemoryFence()
+#define pfdep_write_mem_barrier()   MemoryFence()
+#define pfdep_mem_barrier()         MemoryFence()
+
+void *pfdep_malloc(pfdep_uint32 len);
+
+void pfdep_free(void *addr);
+
+pfdep_err_t pfdep_dma_malloc (
+    pfdep_dev_handle_t dev_handle,
+    pfdep_uint32 len,
+    void **addr_p,
+    pfdep_phys_addr_t *phys_addr_p
+    );
+
+void pfdep_dma_free (
+    pfdep_dev_handle_t dev_handle,
+    pfdep_uint32 len,
+    void *addr,
+    pfdep_phys_addr_t phys_addr
+    );
+
+pfdep_err_t pfdep_alloc_pkt_buf (
+    pfdep_dev_handle_t dev_handle,
+    pfdep_uint16 len,
+    void **addr_p,
+    pfdep_phys_addr_t *phys_addr_p,
+    pfdep_pkt_handle_t *pkt_handle_p
+    );
+
+void pfdep_free_pkt_buf (
+    pfdep_dev_handle_t dev_handle,
+    pfdep_uint16 len,
+    void *addr,
+    pfdep_phys_addr_t phys_addr,
+    pfdep_bool last_flag,
+    pfdep_pkt_handle_t pkt_handle
+    );
+
+static __inline pfdep_err_t pfdep_init_hard_lock(pfdep_hard_lock_t *hard_lock_p)
+{
+    (void)hard_lock_p; /* suppress compiler warning */
+    return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_uninit_hard_lock(pfdep_hard_lock_t *hard_lock_p)
+{
+    (void)hard_lock_p; /* suppress compiler warning */
+    return;
+}
+
+static __inline void pfdep_acquire_hard_lock (
+    pfdep_hard_lock_t *hard_lock_p, /* not used */
+    pfdep_hard_lock_ctx_t *ctx_p
+    )
+{
+    (void)hard_lock_p; /* suppress compiler warning */
+
+    *ctx_p = SaveAndDisableInterrupts();
+}
+
+
+static __inline void pfdep_release_hard_lock (
+    pfdep_hard_lock_t *hard_lock_p, /* not used */
+    pfdep_hard_lock_ctx_t *ctx_p
+    )
+{
+    (void)hard_lock_p; /* suppress compiler warning */
+
+    SetInterruptState(*ctx_p);
+}
+
+static __inline pfdep_err_t pfdep_init_soft_lock (
+    pfdep_soft_lock_t *soft_lock_p
+    )
+{
+    *soft_lock_p = 0; /* suppress compiler warning */
+
+    return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_uninit_soft_lock (
+    pfdep_soft_lock_t *soft_lock_p
+    )
+{
+    (void)soft_lock_p; /* suppress compiler warning */
+
+    return;
+}
+
+static __inline pfdep_err_t pfdep_acquire_soft_lock (
+    pfdep_soft_lock_t *soft_lock_p,
+    pfdep_soft_lock_ctx_t *ctx_p
+    )
+{
+    (void)soft_lock_p; /* suppress compiler warning */
+    (void)ctx_p; /* suppress compiler warning */
+
+    return PFDEP_ERR_OK;
+}
+
+static __inline void pfdep_release_soft_lock (
+    pfdep_soft_lock_t *soft_lock_p,
+    pfdep_soft_lock_ctx_t *ctx_p
+    )
+{
+    (void)soft_lock_p; /* suppress compiler warning */
+    (void)ctx_p; /* suppress compiler warning */
+}
+
+
+static __inline void pfdep_memcpy(void *dst_p, const void *src_p, pfdep_uint32 len)
+{
+    memcpy(dst_p, src_p, (size_t)len);
+}
+
+static __inline void pfdep_memset(void *dst_p, pfdep_uint8 c, pfdep_uint32 len)
+{
+    memset(dst_p, c, (size_t)len);
+}
+
+static __inline pfdep_err_t pfdep_msleep(pfdep_uint32 wait_ms)
+{
+
+    MicroSecondDelay ((UINTN)wait_ms * 1000);
+
+    return PFDEP_ERR_OK;
+}
+
+#define pfdep_print(level,...) \
+do { \
+    if (level <= pfdep_debug_level) { \
+        DEBUG ((DEBUG_INFO, "[NETSEC] " __VA_ARGS__)); \
+    } \
+} while (0)
+
+
+static __inline pfdep_debug_level_t pfdep_get_debug_level(void)
+{
+    return pfdep_debug_level;
+}
+
+static __inline void pfdep_set_debug_level(pfdep_debug_level_t level)
+{
+    pfdep_debug_level = level;
+}
+
+
+#define pfdep_assert(cond)      ASSERT(cond)
+
+#endif /* PFDEP_H */
diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
new file mode 100644
index 000000000000..b43d1aaff037
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
@@ -0,0 +1,176 @@
+/** @file
+
+  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "pfdep.h"
+
+#include <Library/DebugLib.h>
+#include <Library/DmaLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NetLib.h>
+#include <Library/SynchronizationLib.h>
+
+/**********************************************************************
+ * Variable definitions
+ **********************************************************************/
+pfdep_debug_level_t pfdep_debug_level = PFDEP_DEBUG_LEVEL_NOTICE;
+
+
+/**********************************************************************
+ * Function definitions
+ **********************************************************************/
+
+VOID*
+pfdep_malloc (
+  IN  pfdep_uint32    len
+  )
+{
+  return AllocatePool (len);
+}
+
+VOID
+pfdep_free (
+  IN  VOID       *addr
+  )
+{
+  FreePool (addr);
+}
+
+pfdep_err_t
+pfdep_dma_malloc (
+  IN  pfdep_dev_handle_t        dev_handle,
+  IN  pfdep_uint32              len,
+  OUT VOID                      **addr_p,
+  OUT pfdep_phys_addr_t         *phys_addr_p
+  )
+{
+  EFI_STATUS    Status;
+  UINTN         NumPages;
+  UINTN         NumBytes;
+  VOID          **Mapping;
+
+  NumPages = EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof *Mapping);
+  Status = DmaAllocateBuffer (EfiBootServicesData, NumPages, addr_p);
+  if (EFI_ERROR (Status)) {
+    return PFDEP_ERR_ALLOC;
+  }
+
+  //
+  // Stash the address of the MAPINFO struct at the end of the buffer,
+  // but make sure it appears aligned (the memory may be mapped uncached)
+  //
+  Mapping = (VOID **)((UINTN)*addr_p + ALIGN_VARIABLE(len));
+
+  NumBytes = EFI_PAGES_TO_SIZE (NumPages);
+  Status = DmaMap (MapOperationBusMasterCommonBuffer, *addr_p, &NumBytes,
+             phys_addr_p, Mapping);
+
+  if (EFI_ERROR (Status) || NumBytes < len) {
+    DmaFreeBuffer (NumPages, *addr_p);
+    return PFDEP_ERR_ALLOC;
+  }
+
+  return PFDEP_ERR_OK;
+}
+
+VOID
+pfdep_dma_free (
+  IN  pfdep_dev_handle_t        dev_handle,
+  IN  pfdep_uint32              len,
+  IN  VOID                      *addr,
+  IN  pfdep_phys_addr_t         phys_addr
+  )
+{
+  VOID          *Mapping;
+
+  Mapping = *(VOID **)((UINTN)addr + ALIGN_VARIABLE(len));
+
+  DmaUnmap (Mapping);
+  DmaFreeBuffer (EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof Mapping),
+    addr);
+}
+
+//
+// On the receive path, we allocate a new packet and link it into the RX ring
+// before returning the received packet to the caller. This means we perform
+// one allocation and one free operation for each buffer received.
+// So let's cache a single packet, and get rid of most of the alloc/free
+// overhead on the RX path.
+//
+STATIC pfdep_pkt_handle_t mSparePacketBuffer;
+STATIC UINT32 mSparePacketBufferSize;
+
+pfdep_err_t
+pfdep_alloc_pkt_buf (
+  IN  pfdep_dev_handle_t        dev_handle,
+  IN  pfdep_uint16              len,
+  OUT VOID                      **addr_p,
+  OUT pfdep_phys_addr_t         *phys_addr_p,
+  OUT pfdep_pkt_handle_t        *pkt_handle_p
+  )
+{
+  EFI_STATUS    Status;
+  UINTN         NumBytes;
+
+  NumBytes = ALIGN_VALUE (len, mCpu->DmaBufferAlignment);
+
+  if (InterlockedCompareExchange32 (&mSparePacketBufferSize, len, 0) == len) {
+    *pkt_handle_p = mSparePacketBuffer;
+  } else {
+    *pkt_handle_p = AllocateZeroPool (NumBytes + sizeof(PACKET_HANDLE) +
+                                      (mCpu->DmaBufferAlignment - 8));
+    if (*pkt_handle_p == NULL) {
+      return PFDEP_ERR_ALLOC;
+    }
+
+    (*pkt_handle_p)->Buffer = ALIGN_POINTER (*pkt_handle_p,
+                                             mCpu->DmaBufferAlignment);
+  }
+
+  *addr_p = (*pkt_handle_p)->Buffer;
+  Status = DmaMap (MapOperationBusMasterWrite, *addr_p, &NumBytes, phys_addr_p,
+             &(*pkt_handle_p)->Mapping);
+  if (EFI_ERROR (Status) || NumBytes < len) {
+    FreePool (*pkt_handle_p);
+    return PFDEP_ERR_ALLOC;
+  }
+  return PFDEP_ERR_OK;
+}
+
+VOID
+pfdep_free_pkt_buf (
+  IN  pfdep_dev_handle_t        dev_handle,
+  IN  pfdep_uint16              len,
+  IN  VOID                      *addr,
+  IN  pfdep_phys_addr_t         phys_addr,
+  IN  pfdep_bool                last_flag,
+  IN  pfdep_pkt_handle_t        pkt_handle
+  )
+{
+  if (last_flag != PFDEP_TRUE) {
+    return;
+  }
+
+  if (pkt_handle->Mapping != NULL) {
+    DmaUnmap (pkt_handle->Mapping);
+  }
+
+  if (pkt_handle->RecycleForTx) {
+      pkt_handle->Released = TRUE;
+  } else if (!InterlockedCompareExchange32 (&mSparePacketBufferSize, 0, len)) {
+    mSparePacketBuffer = pkt_handle;
+  } else {
+    FreePool (pkt_handle);
+  }
+}
-- 
2.11.0

_______________________________________________
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Re: [edk2] [PATCH edk2-platforms 08/14] Silicon/Socionext: add driver for NETSEC network controller
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:09PM +0100, Ard Biesheuvel wrote:
> This adds the NetSecDxe driver provided by Socionext, but reworked
> extensively to improve compliance with the SimpleNetworkProtocol API,
> and to avoid uncached allocations for streaming DMA.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c                                                     | 1000 ++++++++++++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec                                                   |   47 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h                                                     |   88 ++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf                                                   |   69 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h                   |  736 ++++++++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h            |   45 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h               |   24 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c              |   88 ++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h              |   52 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c          | 1391 +++++++++++++++++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h |  111 ++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c               | 1454 ++++++++++++++++++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h                  |  210 +++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c                      | 1385 +++++++++++++++++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h             |   38 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h                       |  219 +++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h            |  222 +++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h                |  368 +++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h                                   |   25 +
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h                                         |  265 ++++
>  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c                                    |  176 +++
>  21 files changed, 8013 insertions(+)
> 
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
> new file mode 100644
> index 000000000000..7c3f12362f14
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.c
> @@ -0,0 +1,1000 @@
> +/** @file
> +
> +  Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/DmaLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/NetLib.h>

Sorted alphabetically, please?

> +
> +#include "NetsecDxe.h"
> +#include "netsec_for_uefi/pfdep.h"

Hmm, could that be folded into NetsecDxe.h?

> +
> +EFI_CPU_ARCH_PROTOCOL      *mCpu;
> +
> +STATIC NETSEC_DEVICE_PATH NetsecPathTemplate =  {
> +  {
> +    {
> +      MESSAGING_DEVICE_PATH,
> +      MSG_MAC_ADDR_DP,
> +      {
> +        (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)),
> +        (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH) >> 8)

No space after (UINT8), space after sizeof?

> +      }
> +    },
> +    {
> +      {
> +        0
> +      }
> +    },
> +    0
> +  },
> +  {
> +    END_DEVICE_PATH_TYPE,
> +    END_ENTIRE_DEVICE_PATH_SUBTYPE,
> +    {
> +      sizeof(EFI_DEVICE_PATH_PROTOCOL), 0

Space after sizeof?

> +    }
> +  }
> +};
> +
> +STATIC
> +VOID
> +GetCurrentMacAddress(
> +  OUT UINT8   *Mac)
> +{
> +  Mac[0] = MmioRead8(MAC_ADDRESS + 3);
> +  Mac[1] = MmioRead8(MAC_ADDRESS + 2);
> +  Mac[2] = MmioRead8(MAC_ADDRESS + 1);
> +  Mac[3] = MmioRead8(MAC_ADDRESS + 0);
> +  Mac[4] = MmioRead8(MAC_ADDRESS + 7);
> +  Mac[5] = MmioRead8(MAC_ADDRESS + 6);

Spaces after MmioRead8?

> +}
> +
> +/*
> + *  Probe()
> + */
> +STATIC
> +EFI_STATUS
> +Probe (
> +  IN  EFI_HANDLE          Handle,
> +  IN  NETSEC_DRIVER       *LanDriver
> +  )
> +{
> +  ogma_param_t  Param;
> +  ogma_err_t    ogma_err;
> +  UINT64        dmac_hm_cmd_base, dmac_mh_cmd_base, core_cmd_base;
> +  UINT32        dmac_hm_cmd_size, dmac_mh_cmd_size, core_cmd_size;
> +
> +  SetMem (&Param, sizeof(Param), 0);

Space after sizeof?

> +
> +  Param.use_gmac_flag = OGMA_TRUE;
> +
> +  Param.use_jumbo_pkt_flag = PcdGet8 (PcdJumboPacket);
> +
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag = OGMA_TRUE;
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].little_endian_flag = OGMA_TRUE;
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].tmr_mode_flag = OGMA_FALSE;
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].entry_num = PcdGet16 (PcdEncTxDescNum);
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag = OGMA_TRUE;
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].little_endian_flag = OGMA_TRUE;
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].tmr_mode_flag = OGMA_FALSE;
> +  Param.desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].entry_num = PcdGet16 (PcdDecRxDescNum);
> +
> +  // phy-interface
> +  Param.gmac_config.phy_interface = OGMA_PHY_INTERFACE_RGMII;
> +
> +  // Read and save the Permanent MAC Address
> +  GetCurrentMacAddress (LanDriver->SnpMode.PermanentAddress.Addr);
> +
> +  LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress;
> +  DEBUG ((DEBUG_NET | DEBUG_INFO,
> +    "Netsec: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n",
> +    LanDriver->SnpMode.PermanentAddress.Addr[0],
> +    LanDriver->SnpMode.PermanentAddress.Addr[1],
> +    LanDriver->SnpMode.PermanentAddress.Addr[2],
> +    LanDriver->SnpMode.PermanentAddress.Addr[3],
> +    LanDriver->SnpMode.PermanentAddress.Addr[4],
> +    LanDriver->SnpMode.PermanentAddress.Addr[5]));
> +
> +  // Get hm microcode's physical addresses
> +  dmac_hm_cmd_base = MmioRead32 (HM_ME_ADDRESS_H);
> +  dmac_hm_cmd_base <<= 32;
> +  dmac_hm_cmd_base |= MmioRead32 (HM_ME_ADDRESS_L);
> +  dmac_hm_cmd_size = MmioRead32 (HM_ME_SIZE);
> +
> +  // Get mh microcode's physical addresses
> +  dmac_mh_cmd_base = MmioRead32 (MH_ME_ADDRESS_H);
> +  dmac_mh_cmd_base <<= 32;
> +  dmac_mh_cmd_base |= MmioRead32 (MH_ME_ADDRESS_L);
> +  dmac_mh_cmd_size = MmioRead32 (MH_ME_SIZE);
> +
> +  // Get core microcode's physical addresses
> +  core_cmd_base = MmioRead32 (PACKET_ME_ADDRESS);
> +  core_cmd_size = MmioRead32 (PACKET_ME_SIZE);

Could we have some clarifications in comments what hm, mh and core
are? Is their microcode self-contained in the component address space,
or do they need to come from a separate flash device?

> +
> +  ogma_err = ogma_init ((VOID *)((UINTN)PcdGet32(PcdNetsecDxeBaseAddress)),

Space after PcdGet32?

I think you mentioned rewriting this to UEFI driver model? Is that
coming later?

> +                        Handle, &Param,
> +                        (VOID *)dmac_hm_cmd_base, dmac_hm_cmd_size,
> +                        (VOID *)dmac_mh_cmd_base, dmac_mh_cmd_size,
> +                        (VOID *)core_cmd_base, core_cmd_size,
> +                        &LanDriver->Handle);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR, "NETSEC: ogma_init() failed with error code %d\n",
> +      ogma_err));
> +    return EFI_DEVICE_ERROR;
> +  }
> +
> +  ogma_enable_top_irq (LanDriver->Handle,
> +                       OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX);
> +
> +  return EFI_SUCCESS;
> +}
> +
> +/*
> + *  UEFI Stop() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpStop (
> +  IN  EFI_SIMPLE_NETWORK_PROTOCOL    *Snp
> +  )
> +{
> +  EFI_TPL       SavedTpl;
> +  EFI_STATUS    Status;
> +
> +  // Check Snp Instance
> +  if (Snp == NULL) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);

Not a fan of having a device-specific alias for which TPL to switch to
for all critical sections. Could just search and replace and drop the
definition (pointing out only here and at the definition).

> +
> +  // Check state of the driver
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkStarted:
> +  case EfiSimpleNetworkInitialized:
> +    break;
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Change the state
> +  Snp->Mode->State = EfiSimpleNetworkStopped;
> +  Status = EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +/*
> + *  UEFI Initialize() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpInitialize (
> +  IN  EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
> +  IN  UINTN                         RxBufferSize  OPTIONAL,
> +  IN  UINTN                         TxBufferSize  OPTIONAL
> +  )
> +{
> +  NETSEC_DRIVER           *LanDriver;
> +  EFI_TPL                 SavedTpl;
> +  EFI_STATUS              Status;
> +
> +  ogma_phy_link_status_t  phy_link_status;
> +  ogma_err_t              ogma_err;
> +  ogma_gmac_mode_t        ogma_gmac_mode;
> +
> +  // Check Snp Instance
> +  if (Snp == NULL) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> +  // Check that driver was started but not initialised
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkStarted:
> +    break;
> +  case EfiSimpleNetworkInitialized:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver already initialized\n"));
> +    ReturnUnlock (EFI_SUCCESS);
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Find the LanDriver structure
> +  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);

Space after _THIS?

> +
> +  // ##### open

Hmm? A bit more description please.

> +  ogma_err = ogma_clean_rx_desc_ring (LanDriver->Handle,
> +                                      OGMA_DESC_RING_ID_NRM_RX);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_clean_rx_desc_ring() failed with error code %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
> +                                      OGMA_DESC_RING_ID_NRM_TX);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_clean_tx_desc_ring() failed with error code %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_clear_desc_ring_irq_status (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
> +                                   OGMA_CH_IRQ_REG_EMPTY);
> +
> +  // ##### open_sub

A bit more description, please.

> +  ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
> +      OGMA_DESC_RING_ID_NRM_RX,
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_err = ogma_set_irq_coalesce_param(LanDriver->Handle,
> +                                         OGMA_DESC_RING_ID_NRM_RX,
> +                                         RXINT_PKTCNT,
> +                                         OGMA_FALSE,
> +                                         RXINT_TMR_CNT_US);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_set_irq_coalesce_param() failed with error code %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_err = ogma_start_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_start_desc_ring(ring_id=%d) failed with error code %d\n",
> +      OGMA_DESC_RING_ID_NRM_TX,
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX,
> +                              OGMA_CH_IRQ_REG_EMPTY);
> +
> +  // ##### configure_mac

In general, it feels like each of these comment headers indicate a
good place to break a block out into a helper function.

> +  ogma_err = ogma_stop_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);

Missing space.

> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_stop_gmac() failed with error status %d\n",
> +      ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_err = ogma_get_phy_link_status(LanDriver->Handle, PcdGet8(PcdPhyDevAddr), &phy_link_status);

Missing spaces.

> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_get_phy_link_status() failed error code %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  SetMem (&ogma_gmac_mode, sizeof(ogma_gmac_mode_t), 0);

Missing space.

> +  ogma_gmac_mode.link_speed = phy_link_status.link_speed;
> +  ogma_gmac_mode.half_duplex_flag = (ogma_bool)phy_link_status.half_duplex_flag;
> +  if ((!phy_link_status.half_duplex_flag) && PcdGet8(PcdFlowCtrl)) {

Missing space.

> +    ogma_gmac_mode.flow_ctrl_enable_flag      = (ogma_bool)PcdGet8(PcdFlowCtrl);
> +    ogma_gmac_mode.flow_ctrl_start_threshold  = (ogma_uint16)PcdGet16(PcdFlowCtrlStartThreshold);
> +    ogma_gmac_mode.flow_ctrl_stop_threshold   = (ogma_uint16)PcdGet16(PcdFlowCtrlStopThreshold);
> +    ogma_gmac_mode.pause_time                 = (ogma_uint16)PcdGet16(PcdPauseTime);
> +  }
> +
> +  ogma_err = ogma_set_gmac_mode(LanDriver->Handle, &ogma_gmac_mode);

Missing space.

> +  if(ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_set_gmac() failed with error status %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_err = ogma_start_gmac(LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);

Missing space.

> +  if(ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_start_gmac() failed with error status %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Declare the driver as initialized
> +  Snp->Mode->State = EfiSimpleNetworkInitialized;
> +  Status = EFI_SUCCESS;
> +
> +  DEBUG ((DEBUG_INFO | DEBUG_LOAD, "NETSEC: Driver started\n"));
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +/*
> + *  UEFI Shutdown () function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpShutdown (
> +  IN  EFI_SIMPLE_NETWORK_PROTOCOL    *Snp
> +  )
> +{
> +  NETSEC_DRIVER     *LanDriver;
> +  EFI_TPL           SavedTpl;
> +  EFI_STATUS        Status;
> +
> +  // Check Snp Instance
> +  if (Snp == NULL) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> +  // First check that driver has already been initialized
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkInitialized:
> +    break;
> +  case EfiSimpleNetworkStarted:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver in stopped state\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Find the LanDriver structure
> +  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
> +
> +  ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE);
> +
> +  ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX);
> +  ogma_stop_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);
> +
> +  Snp->Mode->State = EfiSimpleNetworkStarted;
> +  Status = EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +STATIC
> +VOID
> +EFIAPI
> +NotifyExitBoot (
> +  IN EFI_EVENT  Event,
> +  IN VOID       *Context
> +  )
> +{
> +  EFI_SIMPLE_NETWORK_PROTOCOL     *Snp;
> +  EFI_STATUS                      Status;
> +
> +  Snp = Context;
> +
> +  if (Snp->Mode != EfiSimpleNetworkStopped) {
> +    Status = SnpShutdown (Snp);
> +    if (!EFI_ERROR (Status)) {
> +      SnpStop (Snp);
> +    }
> +  }
> +  gBS->CloseEvent (Event);
> +}
> +
> +/*
> + *  UEFI Start() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpStart (
> +  IN  EFI_SIMPLE_NETWORK_PROTOCOL    *Snp
> +  )
> +{
> +  EFI_SIMPLE_NETWORK_MODE   *Mode;
> +  EFI_TPL                   SavedTpl;
> +  EFI_STATUS                Status;
> +  NETSEC_DRIVER             *LanDriver;
> +
> +  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);

Missing space.

> +
> +  // Check Snp instance
> +  if (Snp == NULL) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +  Mode = Snp->Mode;
> +
> +  // Check state of the driver
> +  switch (Mode->State) {
> +  case EfiSimpleNetworkStopped:
> +    break;
> +  case EfiSimpleNetworkStarted:
> +  case EfiSimpleNetworkInitialized:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver already started\n"));
> +    ReturnUnlock (EFI_ALREADY_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, NETSEC_TPL,
> +                  NotifyExitBoot, Snp, &LanDriver->ExitBootEvent);
> +  ASSERT_EFI_ERROR (Status);
> +
> +  // Change state
> +  Mode->State = EfiSimpleNetworkStarted;
> +  Status = EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +
> +}
> +
> +/*
> + *  UEFI ReceiveFilters() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpReceiveFilters (
> +  IN  EFI_SIMPLE_NETWORK_PROTOCOL     *Snp,
> +  IN  UINT32                          Enable,
> +  IN  UINT32                          Disable,
> +  IN  BOOLEAN                         Reset,
> +  IN  UINTN                           NumMfilter  OPTIONAL,
> +  IN  EFI_MAC_ADDRESS                 *Mfilter    OPTIONAL
> +  )
> +{
> +  EFI_TPL             SavedTpl;
> +  EFI_STATUS          Status;
> +
> +  // Check Snp Instance
> +  if (Snp == NULL) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> +  // First check that driver has already been initialized
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkInitialized:
> +    break;
> +  case EfiSimpleNetworkStarted:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n", (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  Status = EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +/*
> + *  UEFI GetStatus () function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpGetStatus (
> +  IN      EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
> +      OUT UINT32                        *IrqStat  OPTIONAL,
> +      OUT VOID                          **TxBuff  OPTIONAL
> +  )
> +{
> +  NETSEC_DRIVER             *LanDriver;
> +  EFI_TPL                   SavedTpl;
> +  EFI_STATUS                Status;
> +  pfdep_pkt_handle_t        pkt_handle;
> +  LIST_ENTRY                *Link;
> +
> +  ogma_phy_link_status_t  phy_link_status;
> +  ogma_err_t              ogma_err;
> +
> +  // Check preliminaries
> +  if (Snp == NULL) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> +  // Check that driver was started and initialised
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkInitialized:
> +    break;
> +  case EfiSimpleNetworkStarted:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Find the LanDriver structure
> +  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);
> +
> +  // Update the media status
> +  ogma_err = ogma_get_phy_link_status (LanDriver->Handle,
> +                                       PcdGet8(PcdPhyDevAddr),
> +                                       &phy_link_status);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_get_phy_link_status failed with error code: %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  Snp->Mode->MediaPresent = phy_link_status.up_flag;
> +
> +  ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
> +                                      OGMA_DESC_RING_ID_NRM_TX);
> +
> +  if (TxBuff != NULL) {
> +    *TxBuff = NULL;
> +    //
> +    // Find a buffer in the list that has been released
> +    //
> +    for (Link = GetFirstNode (&LanDriver->TxBufferList);
> +         !IsNull (&LanDriver->TxBufferList, Link);
> +         Link = GetNextNode (&LanDriver->TxBufferList, Link)) {
> +
> +      pkt_handle = BASE_CR (Link, PACKET_HANDLE, Link);
> +      if (pkt_handle->Released) {
> +        *TxBuff = pkt_handle->Buffer;
> +        RemoveEntryList (Link);
> +        FreePool (pkt_handle);
> +        break;
> +      }
> +    }
> +  }
> +
> +  if (IrqStat != 0) {
> +    *IrqStat = 0;
> +  }
> +
> +  Status = EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +/*
> + *  UEFI Transmit() function
> + */
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SnpTransmit (
> +  IN  EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
> +  IN  UINTN                         HdrSize,
> +  IN  UINTN                         BufSize,
> +  IN  VOID                          *BufAddr,
> +  IN  EFI_MAC_ADDRESS               *SrcAddr    OPTIONAL,
> +  IN  EFI_MAC_ADDRESS               *DstAddr    OPTIONAL,
> +  IN  UINT16                        *Protocol   OPTIONAL
> +  )
> +{
> +  NETSEC_DRIVER             *LanDriver;
> +  EFI_TPL                   SavedTpl;
> +  EFI_STATUS                Status;
> +
> +  ogma_tx_pkt_ctrl_t  tx_pkt_ctrl;
> +  ogma_frag_info_t    scat_info;
> +  ogma_uint16         tx_avail_num;
> +  ogma_err_t          ogma_err;
> +  UINT16              Proto;
> +  pfdep_pkt_handle_t  pkt_handle;
> +
> +  // Check preliminaries
> +  if ((Snp == NULL) || (BufAddr == NULL)) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n", Snp, BufAddr));
> +    return EFI_DEVICE_ERROR;
> +  }
> +
> +  pkt_handle = AllocateZeroPool (sizeof *pkt_handle);

We tend to use () with sizeof, right?

> +  if (pkt_handle == NULL) {
> +    return EFI_OUT_OF_RESOURCES;
> +  }
> +
> +  pkt_handle->Buffer = BufAddr;
> +  pkt_handle->RecycleForTx = TRUE;
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> +  // Check that driver was started and initialised
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkInitialized:
> +    break;
> +  case EfiSimpleNetworkStarted:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Find the LanDriver structure
> +  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);

Missing space.

> +
> +  ogma_err = ogma_clear_desc_ring_irq_status (LanDriver->Handle,
> +                                              OGMA_DESC_RING_ID_NRM_TX,
> +                                              OGMA_CH_IRQ_REG_EMPTY);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_clear_desc_ring_irq_status failed with error code: %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  ogma_err = ogma_clean_tx_desc_ring (LanDriver->Handle,
> +                                      OGMA_DESC_RING_ID_NRM_TX);
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_clean_tx_desc_ring failed with error code: %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Ensure header is correct size if non-zero
> +  if (HdrSize) {
> +    if (HdrSize != Snp->Mode->MediaHeaderSize) {
> +      DEBUG ((DEBUG_ERROR, "NETSEC: SnpTransmit(): Invalid HdrSize %d\n",
> +        HdrSize));
> +      ReturnUnlock (EFI_INVALID_PARAMETER);
> +    }
> +
> +    if ((DstAddr == NULL) || (Protocol == NULL)) {
> +      DEBUG ((DEBUG_ERROR,
> +        "NETSEC: SnpTransmit(): NULL DstAddr %p or Protocol %p\n",
> +        DstAddr, Protocol));
> +      ReturnUnlock (EFI_INVALID_PARAMETER);
> +    }
> +
> +    // Copy destination address
> +    CopyMem (BufAddr, (VOID *)DstAddr, NET_ETHER_ADDR_LEN);
> +    // Copy source address
> +    CopyMem (BufAddr + NET_ETHER_ADDR_LEN, (VOID *)SrcAddr, NET_ETHER_ADDR_LEN);
> +    // Copy protocol
> +    Proto = HTONS(*Protocol);

Missing space.

> +    CopyMem (BufAddr + (NET_ETHER_ADDR_LEN * 2), (VOID *)&Proto, sizeof(UINT16));

Missing space (sizeof).

> +  }
> +
> +  Status = DmaMap (MapOperationBusMasterRead, BufAddr, &BufSize,
> +             &scat_info.phys_addr, &pkt_handle->Mapping);
> +  if (EFI_ERROR (Status)) {
> +    goto ExitUnlock;
> +  }
> +
> +  scat_info.addr        = BufAddr;
> +  scat_info.len         = BufSize;
> +
> +  SetMem (&tx_pkt_ctrl, sizeof (ogma_tx_pkt_ctrl_t), 0);
> +
> +  tx_pkt_ctrl.pass_through_flag     = OGMA_TRUE;
> +  tx_pkt_ctrl.target_desc_ring_id   = OGMA_DESC_RING_ID_GMAC;
> +
> +  // check empty slot
> +  do {
> +    tx_avail_num = ogma_get_tx_avail_num (LanDriver->Handle,
> +                                          OGMA_DESC_RING_ID_NRM_TX);
> +  } while (tx_avail_num < SCAT_NUM);
> +
> +  // send
> +  ogma_err = ogma_set_tx_pkt_data (LanDriver->Handle,
> +                                   OGMA_DESC_RING_ID_NRM_TX,
> +                                   &tx_pkt_ctrl,
> +                                   SCAT_NUM,
> +                                   &scat_info,
> +                                   pkt_handle);
> +
> +  if (ogma_err != OGMA_ERR_OK) {
> +    DmaUnmap (pkt_handle->Mapping);
> +    FreePool (pkt_handle);
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC: ogma_set_tx_pkt_data failed with error code: %d\n",
> +      (INT32)ogma_err));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  //
> +  // Queue the descriptor so we can release the buffer once it has been
> +  // consumed by the hardware.
> +  //
> +  InsertTailList (&LanDriver->TxBufferList, &pkt_handle->Link);
> +
> +  gBS->RestoreTPL (SavedTpl);
> +  return EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  FreePool (pkt_handle);
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +/*
> + *  UEFI Receive() function
> + */
> +EFI_STATUS
> +EFIAPI
> +SnpReceive (
> +  IN      EFI_SIMPLE_NETWORK_PROTOCOL   *Snp,
> +      OUT UINTN                         *HdrSize    OPTIONAL,
> +  IN  OUT UINTN                         *BuffSize,
> +      OUT VOID                          *Data,
> +      OUT EFI_MAC_ADDRESS               *SrcAddr    OPTIONAL,
> +      OUT EFI_MAC_ADDRESS               *DstAddr    OPTIONAL,
> +      OUT UINT16                        *Protocol   OPTIONAL
> +  )
> +{
> +  EFI_TPL             SavedTpl;
> +  EFI_STATUS          Status;
> +  NETSEC_DRIVER       *LanDriver;
> +
> +  ogma_err_t          ogma_err;
> +  ogma_rx_pkt_info_t  rx_pkt_info;
> +  ogma_frag_info_t    rx_data;
> +  ogma_uint16         len;
> +  pfdep_pkt_handle_t  pkt_handle;
> +
> +  // Check preliminaries
> +  if ((Snp == NULL) || (Data == NULL)) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  // Serialize access to data and registers
> +  SavedTpl = gBS->RaiseTPL (NETSEC_TPL);
> +
> +  // Check that driver was started and initialised
> +  switch (Snp->Mode->State) {
> +  case EfiSimpleNetworkInitialized:
> +    break;
> +  case EfiSimpleNetworkStarted:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not yet initialized\n"));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  case EfiSimpleNetworkStopped:
> +    DEBUG ((DEBUG_WARN, "NETSEC: Driver not started\n"));
> +    ReturnUnlock (EFI_NOT_STARTED);
> +  default:
> +    DEBUG ((DEBUG_ERROR, "NETSEC: Driver in an invalid state: %u\n",
> +      (UINTN)Snp->Mode->State));
> +    ReturnUnlock (EFI_DEVICE_ERROR);
> +  }
> +
> +  // Find the LanDriver structure
> +  LanDriver = INSTANCE_FROM_SNP_THIS(Snp);

Missing space.

> +
> +  if (ogma_get_rx_num (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_RX) > 0) {
> +
> +    ogma_err = ogma_get_rx_pkt_data(LanDriver->Handle,

Missing space.

> +                                    OGMA_DESC_RING_ID_NRM_RX,
> +                                    &rx_pkt_info, &rx_data, &len, &pkt_handle);
> +    if (ogma_err != OGMA_ERR_OK) {
> +      DEBUG ((DEBUG_ERROR,
> +        "NETSEC: ogma_get_rx_pkt_data failed with error code: %d\n",
> +        (INT32)ogma_err));
> +      ReturnUnlock (EFI_DEVICE_ERROR);
> +    }
> +
> +    DmaUnmap (pkt_handle->Mapping);
> +    pkt_handle->Mapping = NULL;
> +
> +    CopyMem (Data, (VOID*)rx_data.addr, len);
> +    *BuffSize = len;
> +
> +    pfdep_free_pkt_buf (LanDriver->Handle, rx_data.len, rx_data.addr,
> +      rx_data.phys_addr, PFDEP_TRUE, pkt_handle);
> +  } else {
> +    // not received any packets
> +    ReturnUnlock (EFI_NOT_READY);
> +  }
> +
> +  if (HdrSize != NULL) {
> +    *HdrSize = LanDriver->SnpMode.MediaHeaderSize;
> +  }
> +
> +  ogma_clear_desc_ring_irq_status (LanDriver->Handle,
> +                                   OGMA_DESC_RING_ID_NRM_TX,
> +                                   OGMA_CH_IRQ_REG_EMPTY);
> +
> +  ogma_clean_tx_desc_ring(LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX);

Missing space.

> +
> +  ogma_enable_top_irq (LanDriver->Handle,
> +                       OGMA_TOP_IRQ_REG_NRM_TX | OGMA_TOP_IRQ_REG_NRM_RX);
> +
> +  Status = EFI_SUCCESS;
> +
> +  // Restore TPL and return
> +ExitUnlock:
> +  gBS->RestoreTPL (SavedTpl);
> +  return Status;
> +}
> +
> +/*
> + *  Entry point for the Netxec driver
> + */
> +EFI_STATUS
> +NetsecDxeEntry (
> +  IN  EFI_HANDLE        Handle,
> +  IN  EFI_SYSTEM_TABLE  *SystemTable)
> +{
> +  EFI_STATUS                  Status;
> +  NETSEC_DRIVER               *LanDriver;
> +  EFI_SIMPLE_NETWORK_PROTOCOL *Snp;
> +  EFI_SIMPLE_NETWORK_MODE     *SnpMode;
> +  NETSEC_DEVICE_PATH          *NetsecPath;
> +
> +  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
> +  ASSERT_EFI_ERROR(Status);
> +
> +  // Allocate Resources
> +  LanDriver = AllocateZeroPool (sizeof(NETSEC_DRIVER));
> +  NetsecPath = AllocateCopyPool (sizeof(NETSEC_DEVICE_PATH),

Missing spaces 2 lines above.
(Maybe just a global search/replace in this file. I'll stop pointing
them out.)

> +                                 &NetsecPathTemplate);
> +
> +  // Initialize pointers
> +  Snp = &(LanDriver->Snp);
> +  SnpMode = &(LanDriver->SnpMode);
> +  Snp->Mode = SnpMode;
> +
> +  // Set the signature of the LAN Driver structure
> +  LanDriver->Signature = NETSEC_SIGNATURE;
> +
> +  // Probe the device
> +  Status = Probe (Handle, LanDriver);
> +  if (EFI_ERROR(Status)) {
> +    DEBUG ((DEBUG_ERROR,
> +      "NETSEC:NetsecDxeEntry(): Probe failed with status %d\n", Status));
> +    return Status;
> +  }
> +
> +  // Assign fields and func pointers
> +  Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION;
> +  Snp->WaitForPacket = NULL;
> +  Snp->Initialize = SnpInitialize;
> +  Snp->Start = SnpStart;
> +  Snp->Stop = SnpStop;
> +  Snp->Reset = NULL;
> +  Snp->Shutdown = SnpShutdown;
> +  Snp->ReceiveFilters = SnpReceiveFilters;
> +  Snp->StationAddress = NULL;
> +  Snp->Statistics = NULL;
> +  Snp->MCastIpToMac = NULL;
> +  Snp->NvData = NULL;
> +  Snp->GetStatus = SnpGetStatus;
> +  Snp->Transmit = SnpTransmit;
> +  Snp->Receive = SnpReceive;
> +
> +  // Fill in simple network mode structure
> +  SnpMode->State = EfiSimpleNetworkStopped;
> +  SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN;    // HW address is 6 bytes
> +  SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD);  // Size of an Ethernet header
> +  SnpMode->MaxPacketSize = EFI_PAGE_SIZE;         // Ethernet Frame (with VLAN tag +4 bytes)
> +
> +  // Supported receive filters
> +  SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
> +                               EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
> +                               EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST |
> +                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS |
> +                               EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST;
> +
> +  // Initially-enabled receive filters
> +  SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST |
> +                                  EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST |
> +                                  EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST;
> +
> +  // Netsec has 64bit hash table. We can filter an infinite MACs, but
> +  // higher-level software must filter out any hash collisions.
> +  SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT;
> +  SnpMode->MCastFilterCount = 0;
> +  ZeroMem (&SnpMode->MCastFilter,
> +           MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS));
> +
> +  // Set the interface type (1: Ethernet or 6: IEEE 802 Networks)
> +  SnpMode->IfType = NET_IFTYPE_ETHERNET;
> +
> +  // Mac address is changeable
> +  SnpMode->MacAddressChangeable = TRUE;
> +
> +  // We can only transmit one packet at a time
> +  SnpMode->MultipleTxSupported = FALSE;
> +
> +  // MediaPresent checks for cable connection and partner link
> +  SnpMode->MediaPresentSupported = TRUE;
> +  SnpMode->MediaPresent = FALSE;
> +
> +  //  Set broadcast address
> +  SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF);
> +
> +  // Assign fields for device path
> +  NetsecPath->Netsec.MacAddress = SnpMode->PermanentAddress;
> +  NetsecPath->Netsec.IfType = SnpMode->IfType;
> +
> +  InitializeListHead (&LanDriver->TxBufferList);
> +
> +  // Initialise the protocol
> +  Status = gBS->InstallMultipleProtocolInterfaces (
> +                  &LanDriver->ControllerHandle,
> +                  &gEfiSimpleNetworkProtocolGuid, Snp,
> +                  &gEfiDevicePathProtocolGuid, NetsecPath,
> +                  NULL);
> +
> +  // Say what the status of loading the protocol structure is
> +  if (EFI_ERROR(Status)) {
> +    ogma_terminate (LanDriver->Handle);
> +    FreePool (LanDriver);
> +  }
> +
> +  return Status;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
> new file mode 100644
> index 000000000000..7537d1059b28
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
> @@ -0,0 +1,47 @@
> +## @file
> +#
> +#  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +#  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +#
> +#  This program and the accompanying materials
> +#  are licensed and made available under the terms and conditions of the BSD License
> +#  which accompanies this distribution.  The full text of the license may be found at
> +#  http://opensource.org/licenses/bsd-license.php
> +#
> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> +  DEC_SPECIFICATION              = 0x00010005

Bump.

> +  PACKAGE_NAME                   = OpenPlatformDriversNetNetsecDxePkg
> +  PACKAGE_GUID                   = bd8ddfdd-2e8d-4081-8117-99405df3ffc8
> +  PACKAGE_VERSION                = 0.1
> +
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +#                   Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +
> +[Guids.common]
> +  gNetsecDxeTokenSpaceGuid = { 0x47d6c028, 0x2413, 0x416d,  { 0xa8, 0xef, 0xe4, 0x5c, 0x58, 0x83, 0x5e, 0x49 }}
> +
> +[PcdsFixedAtBuild.common]
> +  # Netsec Ethernet Driver PCDs
> +  gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x0|UINT32|0x00000000
> +  gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x0|UINT32|0x00000001
> +  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|0x0|UINT16|0x00000002
> +  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|0x0|UINT16|0x00000003
> +  gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0x0|UINT8|0x00000004
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0x0|UINT8|0x00000005
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|0x0|UINT16|0x00000006
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|0x0|UINT16|0x00000007
> +  gNetsecDxeTokenSpaceGuid.PcdPauseTime|0x0|UINT16|0x00000008
> +  gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|0x0|UINT8|0x00000009
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
> new file mode 100644
> index 000000000000..f0acdc1448d7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.h
> @@ -0,0 +1,88 @@
> +/** @file
> +
> +  Copyright (c) 2016 Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NETSEC_DXE_H_
> +#define __NETSEC_DXE_H_
> +
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
> +
> +// Synchronization TPLs
> +#define NETSEC_TPL        TPL_CALLBACK

I'm not sure I like this central redefinition of a specific TPL to use
everywhere in the driver where it needs to be raised.

> +
> +/*--------------- Simple Network Driver entry point functions ----------------*/
> +
> +// Refer to the Simple Network Protocol section (21.1)
> +// in the UEFI 2.3.1 Specification for documentation.
> +
> +#define ReturnUnlock(s)   do { Status = (s); goto ExitUnlock; } while (0)
> +
> +/*------------------------------------------------------------------------------
> +  NETSEC Information Structure
> +------------------------------------------------------------------------------*/
> +
> +typedef struct {
> +  // Driver signature
> +  UINT32                            Signature;
> +  EFI_HANDLE                        ControllerHandle;
> +
> +  // EFI SNP protocol instances
> +  EFI_SIMPLE_NETWORK_PROTOCOL       Snp;
> +  EFI_SIMPLE_NETWORK_MODE           SnpMode;
> +
> +  // EFI Snp statistics instance
> +  EFI_NETWORK_STATISTICS            Stats;
> +
> +  // ogma handle
> +  ogma_handle_t                     Handle;
> +
> +  // List of submitted TX buffers
> +  LIST_ENTRY                        TxBufferList;
> +
> +  EFI_EVENT                         ExitBootEvent;
> +} NETSEC_DRIVER;
> +
> +#define NETSEC_SIGNATURE            SIGNATURE_32('n', 't', 's', 'c')
> +#define INSTANCE_FROM_SNP_THIS(a)   CR(a, NETSEC_DRIVER, Snp, NETSEC_SIGNATURE)

Parentheses around that 'a', please.

> +
> +typedef struct {
> +  MAC_ADDR_DEVICE_PATH              Netsec;
> +  EFI_DEVICE_PATH_PROTOCOL          End;
> +} NETSEC_DEVICE_PATH;
> +
> +/*------------------------------------------------------------------------------
> +
> +------------------------------------------------------------------------------*/
> +
> +#define EEPROM_BASE                 ((UINT32)PcdGet32(PcdEepRomBase))

Missing space.

> +
> +#define MAC_ADDRESS                 (0x00 + EEPROM_BASE)
> +
> +#define HM_ME_ADDRESS_H             (0x08 + EEPROM_BASE)
> +#define HM_ME_ADDRESS_L             (0x0C + EEPROM_BASE)
> +#define HM_ME_SIZE                  (0x10 + EEPROM_BASE)
> +
> +#define MH_ME_ADDRESS_H             (0x14 + EEPROM_BASE)
> +#define MH_ME_ADDRESS_L             (0x18 + EEPROM_BASE)
> +#define MH_ME_SIZE                  (0x1C + EEPROM_BASE)
> +
> +#define PACKET_ME_ADDRESS           (0x20 + EEPROM_BASE)
> +#define PACKET_ME_SIZE              (0x24 + EEPROM_BASE)

Not necessary, but you _could_ #undef EEPROM_BASE here.

> +
> +#define SCAT_NUM                    1
> +
> +#define RXINT_TMR_CNT_US            0
> +#define RXINT_PKTCNT                1
> +
> +#endif
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
> new file mode 100644
> index 000000000000..42de56d89c30
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
> @@ -0,0 +1,69 @@
> +## @file
> +#
> +# Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution.  The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010019
> +  BASE_NAME                      = NetsecDxe
> +  FILE_GUID                      = a4eed3af-9837-46b3-9275-c71cb47071f9
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 0.1
> +  ENTRY_POINT                    = NetsecDxeEntry
> +
> +[Sources]
> +  NetsecDxe.c
> +
> +  netsec_for_uefi/pfdep_uefi.c
> +  netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
> +  netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
> +  netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
> +  netsec_for_uefi/netsec_sdk/src/ogma_misc.c
> +
> +[Packages]
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  MdePkg/MdePkg.dec
> +  NetworkPkg/NetworkPkg.dec
> +  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.dec
> +
> +[LibraryClasses]
> +  BaseLib
> +  BaseMemoryLib
> +  DevicePathLib
> +  DmaLib
> +  IoLib
> +  NetLib
> +  SynchronizationLib
> +  TimerLib
> +  UefiDriverEntryPoint
> +  UefiLib
> +
> +[Protocols]
> +  gEfiSimpleNetworkProtocolGuid
> +  gEfiDevicePathProtocolGuid

Sorted, please.

> +
> +[FixedPcd]
> +  gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress
> +  gNetsecDxeTokenSpaceGuid.PcdEepRomBase
> +  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum
> +  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum
> +  gNetsecDxeTokenSpaceGuid.PcdJumboPacket
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold
> +  gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr
> +  gNetsecDxeTokenSpaceGuid.PcdPauseTime

Be nice if these were alphabetically sorted too, unless there is some
other logical order that escapes me.

> +
> +[Depex]
> +  gEfiCpuArchProtocolGuid

OK - below is imported code: I will not comment on coding style
compliance.

> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
> new file mode 100644
> index 000000000000..336325109e33
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h
> @@ -0,0 +1,736 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_API_H
> +#define OGMA_API_H
> +
> +#include "ogma_version.h"
> +#include "netsec_for_uefi/ogma_config.h"
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
> +#include "netsec_for_uefi/pfdep.h"
> +/**
> + * Check configuration macro settings.
> + */
> +#ifdef OGMA_CONFIG_CLK_HZ
> +#if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) )
> +#error "OGMA_CONFIG_CLK_HZ is not appropriate."
> +#endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */
> +#else /* ! OGMA_CONFIG_CLK_HZ */
> +#error "OGMA_CONFIG_CLK_HZ is not given."
> +#endif /* OGMA_CONFIG_CLK_HZ */
> +
> +#ifndef OGMA_CONFIG_GMAC_CLK_HZ
> +#define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ
> +#endif
> +
> +/**
> + * Number of hardware limits
> + */
> +
> +
> +/**
> + * Number of Common Descriptor ring id
> + */
> +#define OGMA_DESC_RING_ID_NRM_TX 0
> +#define OGMA_DESC_RING_ID_NRM_RX 1
> +
> +#define OGMA_DESC_RING_ID_GMAC   15
> +#define OGMA_DESC_RING_ID_MAX    1
> +
> +/**
> + * Numbre of TCP Segmentation length limits
> + */
> +#define OGMA_TCP_SEG_LEN_MAX 1460
> +#define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960
> +
> +/**
> + * Number of ER check result for received packet
> + */
> +#define OGMA_RX_ER_RESULT_NG       0x1
> +#define OGMA_RX_ER_RESULT_OK       0x0
> +
> +/**
> + * Number of checksum calculation result for received packet
> + */
> +#define OGMA_RX_CKSUM_RESULT_OK       0x1
> +#define OGMA_RX_CKSUM_RESULT_NG       0x2
> +#define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0
> +
> +/**
> + * Number of ErrorCode for received packet
> + */
> +#define OGMA_RX_ERRCODE_HEADER_INCOMLETE_ERR   0x2
> +#define OGMA_RX_ERRCODE_IP_HEADER_ERR          0x1
> +#define OGMA_RX_ERRCODE_NONE                   0x0
> +
> +/**
> + * Number of top interrupt enable register bit field
> + */
> +#define OGMA_TOP_IRQ_REG_ME_START        (1UL << 20)
> +#define OGMA_TOP_IRQ_REG_MAC             (1UL << 19)
> +#define OGMA_TOP_IRQ_REG_PKT             (1UL << 18)
> +#define OGMA_TOP_IRQ_REG_BOOTCODE_TX     (1UL <<  5)
> +#define OGMA_TOP_IRQ_REG_NRM_RX          (1UL <<  1)
> +#define OGMA_TOP_IRQ_REG_NRM_TX          (1UL <<  0)
> +
> +
> +/**
> + *  Number of top channel enable register bit field
> + */
> +#define OGMA_CH_IRQ_REG_EMPTY   (1UL << 17)
> +#define OGMA_CH_IRQ_REG_ERR     (1UL << 16)
> +#define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15)
> +#define OGMA_CH_IRQ_REG_TIMEUP  (1UL << 14)
> +#define OGMA_CH_IRQ_REG_RCV     (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP)
> +
> +/**
> + *  Number of top channel enable register bit field for F_NETSEC_C
> + */
> +#define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15)
> +#define OGMA_CH_IRQ_REG_SND     (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP)
> +
> +
> +/**
> + *  Number of packet interrupt enable register bit field
> + */
> +#define OGMA_PKT_IRQ_MAC_ER            (1UL << 5)
> +#define OGMA_PKT_IRQ_JUMBO_ER          (1UL << 4)
> +#define OGMA_PKT_IRQ_CHKSUM_ER         (1UL << 3)
> +#define OGMA_PKT_IRQ_HD_INCOMPLETE     (1UL << 2)
> +#define OGMA_PKT_IRQ_HD_ER             (1UL << 1)
> +#define OGMA_PKT_IRQ_DRP_NO_MATCH      (1UL << 0)
> +
> +
> +/**
> + *  Number of mac irq enable register bit field
> + */
> +#define OGMA_MAC_IRQ_INT_PMT (1UL << 31)
> +#define OGMA_MAC_IRQ_INT_SBD (1UL << 30)
> +#define OGMA_MAC_IRQ_INT_LPI (1UL << 29)
> +#define OGMA_MAC_IRQ_INT_MAC_TX_RX_INFO_INT (1UL << 27)
> +#define OGMA_MAC_IRQ_INT_LPI_TX_ENTRY (1UL << 26)
> +#define OGMA_MAC_IRQ_INT_LPI_RX_ENTRY (1UL << 25)
> +#define OGMA_MAC_IRQ_INT_LPI_TX_EXIT (1UL << 24)
> +#define OGMA_MAC_IRQ_INT_LPI_RX_EXIT (1UL << 23)
> +
> +
> +/**
> + *  Number of SR IER register bit field
> + */
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GLPII (1U << 30)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TTI   (1U << 29)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GPI   (1U << 28)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GMI   (1U << 27)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_GLI   (1U << 26)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_NIS   (1U << 16)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_AIS   (1U << 15)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_ERI   (1U << 14)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_FBI   (1U << 13)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_ETI   (1U << 10)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RWT   (1U << 9)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RPS   (1U << 8)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RU    (1U << 7)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_RI    (1U << 6)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_UNF   (1U << 5)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_OVF   (1U << 4)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TJT   (1U << 3)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TU    (1U << 2)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TPS   (1U << 1)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_TI    (1U << 0)
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_RU  | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_RI  | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_TU  | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
> +                                          OGMA_GMAC_INT_SBD_IRQ_SR_TI)
> +
> +#define OGMA_GMAC_INT_SBD_IRQ_SR_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_GLPII | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_TTI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_GPI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_GMI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_GLI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_NIS   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_AIS   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_ERI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_FBI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_ETI   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_RWT   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_RPS   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_RU    | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_RI    | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_UNF   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_OVF   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_TJT   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_TU    | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_TPS   | \
> +                                       OGMA_GMAC_INT_SBD_IRQ_SR_TI)
> +
> +#define OGMA_GMAC_INT_SBD_IRQ_IER_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_RU  | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_RI  | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_TU  | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_SR_TI)
> +
> +/**
> + *  Number of ISR IMR register bit field
> + */
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_LPII (1U << 10)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_TSI  (1U << 9)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_COI  (1U << 7)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_TI   (1U << 6)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_RI   (1U << 5)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_MI   (1U << 4)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_PI   (1U << 3)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_RGI  (1U << 0)
> +#define OGMA_GMAC_INT_SBD_IRQ_ISR_ALL ( OGMA_GMAC_INT_SBD_IRQ_ISR_LPII | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_TSI  | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_COI  | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_TI   | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_RI   | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_MI   | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_PI   | \
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_RGI)
> +
> +/**
> + *  Number of LPICSR register bit field
> + */
> +#define OGMA_GMAC_LPICSR_REG_LPITXA (1U << 19)
> +#define OGMA_GMAC_LPICSR_REG_PLSEN  (1U << 18)
> +#define OGMA_GMAC_LPICSR_REG_PLS    (1U << 17)
> +#define OGMA_GMAC_LPICSR_REG_LPIEN  (1U << 16)
> +#define OGMA_GMAC_LPICSR_REG_RLPIST (1U << 9)
> +#define OGMA_GMAC_LPICSR_REG_TLPIST (1U << 8)
> +#define OGMA_GMAC_LPICSR_REG_RLPIEX (1U << 3)
> +#define OGMA_GMAC_LPICSR_REG_RLPIEN (1U << 2)
> +#define OGMA_GMAC_LPICSR_REG_TLPIEX (1U << 1)
> +#define OGMA_GMAC_LPICSR_REG_TLPIEN (1U << 0)
> +
> +/**
> + *  Number of RGSR register bit field
> + */
> +#define OGMA_GMAC_RGSR_REG_LS  (1U << 3)
> +#define OGMA_GMAC_RGSR_REG_LSP (1U << 1)
> +#define OGMA_GMAC_RGSR_REG_LM  (1U << 0)
> +
> +/**
> + * Number of various limits
> + */
> +#define OGMA_DESC_ENTRY_NUM_MIN        2
> +#define OGMA_DESC_ENTRY_NUM_MAX        2047
> +#define OGMA_INT_PKTCNT_MAX            2047
> +#define OGMA_L4_MIN_LEN_MAX            64
> +
> +/**
> + * Number of ogma phy interface setting
> + */
> +#define OGMA_PHY_INTERFACE_GMII  0
> +#define OGMA_PHY_INTERFACE_RGMII 1
> +#define OGMA_PHY_INTERFACE_RMII  4
> +
> +/**
> + * Number of ogma link speed setting
> + */
> +#define OGMA_PHY_LINK_SPEED_1G          0
> +#define OGMA_PHY_LINK_SPEED_100M        1U
> +#define OGMA_PHY_LINK_SPEED_10M         2U
> +#define OGMA_PHY_LINK_SPEED_100M_OR_10M 3U
> +
> +/**
> + * Number of flow control limits
> + */
> +#define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 95
> +#define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX  95
> +#define OGMA_FLOW_CTRL_PAUSE_TIME_MIN      5
> +
> +enum ogma_err_e{
> +    OGMA_ERR_OK = 0,
> +    OGMA_ERR_PARAM,
> +    OGMA_ERR_ALLOC,
> +    OGMA_ERR_BUSY,
> +    OGMA_ERR_RANGE,
> +    OGMA_ERR_DATA,
> +    OGMA_ERR_NOTAVAIL,
> +    OGMA_ERR_INTERRUPT,
> +    OGMA_ERR_AGAIN,
> +    OGMA_ERR_INVALID,
> +};
> +
> +typedef void *ogma_handle_t;
> +typedef struct ogma_param_s ogma_param_t;
> +typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t;
> +typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t;
> +typedef enum ogma_err_e ogma_err_t;
> +typedef ogma_uint8 ogma_desc_ring_id_t;
> +typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t;
> +typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t;
> +typedef struct ogma_frag_info_s ogma_frag_info_t;
> +typedef struct ogma_gmac_config_s ogma_gmac_config_t;
> +typedef struct ogma_gmac_mode_s ogma_gmac_mode_t;
> +
> +struct ogma_gmac_config_s{
> +    ogma_uint8 phy_interface;
> +};
> +
> +struct ogma_pkt_ctrl_param_s{
> +    ogma_uint log_chksum_er_flag:1;
> +    ogma_uint log_hd_imcomplete_flag:1;
> +    ogma_uint log_hd_er_flag:1;
> +    ogma_uint drp_no_match_flag:1;
> +};
> +
> +struct ogma_desc_ring_param_s{
> +    ogma_uint valid_flag:1;
> +    ogma_uint little_endian_flag:1;
> +    ogma_uint tmr_mode_flag:1;
> +    ogma_uint16 entry_num;
> +};
> +
> +struct ogma_param_s{
> +
> +    ogma_uint use_gmac_flag:1;
> +    ogma_uint use_jumbo_pkt_flag:1;
> +    ogma_pkt_ctrl_param_t pkt_ctrl_param;
> +    ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1];
> +    ogma_gmac_config_t gmac_config;
> +    ogma_uint8 mac_addr[6];
> +};
> +
> +struct ogma_tx_pkt_ctrl_s{
> +    ogma_uint pass_through_flag:1;
> +    ogma_uint cksum_offload_flag:1;
> +    ogma_uint tcp_seg_offload_flag:1;
> +    ogma_desc_ring_id_t target_desc_ring_id;
> +    ogma_uint16 tcp_seg_len;
> +};
> +
> +struct ogma_rx_pkt_info_s{
> +    ogma_uint fragmented_flag:1;
> +    ogma_uint err_flag:1;
> +    ogma_uint rx_cksum_result:2;
> +    ogma_uint8 err_code;
> +};
> +
> +struct ogma_frag_info_s{
> +    pfdep_phys_addr_t phys_addr;
> +    void *addr;
> +    ogma_uint32 len;
> +};
> +
> +struct ogma_gmac_mode_s{
> +    ogma_uint half_duplex_flag:1;
> +    ogma_uint flow_ctrl_enable_flag:1;
> +    ogma_uint8 link_speed;
> +    ogma_uint16 flow_ctrl_start_threshold;
> +    ogma_uint16 flow_ctrl_stop_threshold;
> +    ogma_uint16 pause_time;
> +};
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +typedef struct ogma_stat_info_s {
> +    ogma_uint16 current_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
> +    ogma_uint16 max_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1];
> +} ogma_stat_info_t;
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +typedef struct ogma_gmac_int_sbd_regs_s{
> +    ogma_uint32 base;
> +    ogma_uint32 extended;
> +} ogma_gmac_int_sbd_regs_t;
> +
> +typedef struct ogma_phy_link_status_s{
> +    ogma_uint up_flag:1;
> +    ogma_uint auto_nego_enable_flag:1;
> +    ogma_uint auto_nego_complete_flag:1;
> +    ogma_uint half_duplex_flag:1;
> +    ogma_uint latched_link_down_flag:1;
> +    ogma_uint lpi_capable_flag:1;
> +    ogma_uint8 link_speed;
> +} ogma_phy_link_status_t;
> +
> +/**************************
> +***************************
> +***************************/
> +
> +ogma_err_t ogma_init (
> +    void *base_addr,
> +    pfdep_dev_handle_t dev_handle,
> +    const ogma_param_t *param_p,
> +    const void *dma_hm_mc_addr,
> +    ogma_uint32 dma_hm_mc_len,
> +    const void *dma_mh_mc_addr,
> +    ogma_uint32 dma_mh_mc_len,
> +    const void *pktc_mc_addr,
> +    ogma_uint32 pktc_mc_len,
> +    ogma_handle_t *ogma_handle_p
> +    );
> +
> +void ogma_terminate (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +ogma_err_t ogma_start_gmac (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool rx_flag,
> +    ogma_bool tx_flag
> +    );
> +
> +ogma_err_t ogma_stop_gmac (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool rx_flag,
> +    ogma_bool tx_flag
> +    );
> +
> +ogma_err_t ogma_set_gmac_mode (
> +    ogma_handle_t ogma_handle,
> +    const ogma_gmac_mode_t *gmac_mode_p
> +    );
> +
> +void ogma_set_phy_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr,
> +    ogma_uint16 value
> +    );
> +
> +ogma_uint16 ogma_get_phy_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr
> +    );
> +
> +ogma_err_t ogma_get_gmac_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool *valid_flag_p,
> +    ogma_gmac_mode_t *gmac_mode_p,
> +    ogma_bool *rx_running_flag_p,
> +    ogma_bool *tx_running_flag_p
> +    );
> +
> +ogma_uint32 ogma_get_top_irq_enable (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +ogma_uint32 ogma_get_top_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    );
> +
> +#define ogma_get_top_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_top_irq_status(ogma_handle,mask_flag)
> +
> +ogma_err_t ogma_clear_top_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    );
> +
> +ogma_uint32 ogma_get_desc_ring_irq_enable (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_uint32 ogma_get_desc_ring_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_bool mask_flag
> +    );
> +
> +#define ogma_get_desc_ring_irq_status_non_clear(ogma_handle,ring_id,mask_flag) \
> +ogma_get_desc_ring_irq_status(ogma_handle,ring_id,mask_flag)
> +
> +
> +
> +ogma_err_t ogma_clear_desc_ring_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint32 value
> +    );
> +
> +ogma_uint32 ogma_get_pkt_irq_enable (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +ogma_uint32 ogma_get_pkt_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    );
> +
> +#define ogma_get_pkt_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_pkt_irq_status(ogma_handle,mask_flag)
> +
> +
> +ogma_err_t ogma_clear_pkt_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    );
> +
> +/* ogma_desc_ring_access.c */
> +ogma_err_t ogma_start_desc_ring (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_err_t ogma_stop_desc_ring (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_uint16 ogma_get_rx_num (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_uint16 ogma_get_tx_avail_num (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_err_t ogma_clean_tx_desc_ring(
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_err_t ogma_clean_rx_desc_ring(
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    );
> +
> +ogma_err_t ogma_set_tx_pkt_data (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> +    ogma_uint8 scat_num,
> +    const ogma_frag_info_t *scat_info_p,
> +    pfdep_pkt_handle_t pkt_handle
> +    );
> +
> +ogma_err_t ogma_get_rx_pkt_data (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_rx_pkt_info_t *rx_pkt_info_p,
> +    ogma_frag_info_t *frag_info_p,
> +    ogma_uint16 *len_p,
> +    pfdep_pkt_handle_t *pkt_handle_p
> +    );
> +
> +ogma_err_t ogma_enable_top_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_err_t ogma_disable_top_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_err_t ogma_enable_desc_ring_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_err_t ogma_disable_desc_ring_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_err_t ogma_enable_pkt_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_err_t ogma_disable_pkt_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_uint32 ogma_get_hw_ver (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +ogma_uint32 ogma_get_mcr_ver (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +/**
> + * Set up IRQ coalesce parameters.
> + *
> + * [Note]
> + *  - This is a tentative implementation.
> + *    Not tested enough. Use with care.
> + *
> + *  - Call this function after every invocation of ogma_start_desc_ring()
> + *    because ogma_start_desc_ring() resets IRQ coalesce settings.
> + *
> + */
> +ogma_err_t ogma_set_irq_coalesce_param (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint16 int_pktcnt,
> +    ogma_bool int_tmr_unit_ms_flag,
> +    ogma_uint16 int_tmr_cnt
> +    );
> +
> +ogma_uint32 ogma_get_mac_irq_enable (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +
> +ogma_uint32 ogma_get_mac_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    );
> +
> +#define ogma_get_mac_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_mac_irq_status(ogma_handle,mask_flag)
> +
> +
> +ogma_err_t ogma_clear_mac_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    );
> +
> +ogma_err_t ogma_enable_mac_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    );
> +
> +ogma_err_t ogma_disable_mac_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    );
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +/**
> + * Get statistics information.
> + */
> +ogma_err_t ogma_get_stat_info (
> +    ogma_handle_t ogma_handle,
> +    ogma_stat_info_t *stat_info_p,
> +    ogma_bool clear_flag
> +    );
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +ogma_err_t ogma_set_gmac_lpictrl_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    );
> +
> +ogma_err_t ogma_get_gmac_lpictrl_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 *value_p
> +    );
> +
> +ogma_err_t ogma_set_gmac_lpitimer_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint16 ls_timer_ms,
> +    ogma_uint16 tw_timer_ms
> +    );
> +
> +ogma_err_t ogma_get_gmac_lpitimer_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint16 *ls_timer_ms_p,
> +    ogma_uint16 *tw_timer_ms_p
> +    );
> +
> +void ogma_set_phy_mmd_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr,
> +    ogma_uint16 value
> +    );
> +
> +ogma_uint16 ogma_get_phy_mmd_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr
> +    );
> +
> +ogma_err_t ogma_get_phy_link_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_phy_link_status_t *phy_link_status_p
> +    );
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    );
> +
> +#define ogma_get_gmac_int_sbd_irq_status_non_clear(ogma_handle,mask_flag) \
> +ogma_get_gmac_int_sbd_irq_status(ogma_handle,mask_flag)
> +
> +ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_gmac_int_sbd_regs_t int_sbd_regs
> +    );
> +
> +ogma_err_t ogma_enable_gmac_int_sbd_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_gmac_int_sbd_regs_t int_sbd_regs
> +    );
> +
> +ogma_err_t ogma_disable_gmac_int_sbd_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_gmac_int_sbd_regs_t int_sbd_regs
> +    );
> +
> +ogma_err_t ogma_get_gmac_rgmii_status_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 *value_p
> +    );
> +
> +#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
> +ogma_err_t ogma_read_gmac_stat (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 *value_p,
> +    ogma_bool reset_flag
> +    );
> +#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
> +
> +ogma_err_t ogma_reset_gmac_stat (
> +    ogma_handle_t ogma_handle
> +    );
> +
> +/**************************
> +***************************
> +***************************/
> +
> +#endif /* OGMA_API_H*/
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
> new file mode 100644
> index 000000000000..7c39b7c9cdd7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h
> @@ -0,0 +1,45 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_BASIC_TYPE_H
> +#define OGMA_BASIC_TYPE_H
> +#include "netsec_for_uefi/pfdep.h"
> +
> +/**
> + *
> + */
> +#define OGMA_TRUE  PFDEP_TRUE
> +#define OGMA_FALSE PFDEP_FALSE
> +
> +/**
> + * OGMA SDK BASIC DATA TYPE
> + */
> +typedef pfdep_int8 ogma_int8;
> +typedef pfdep_uint8 ogma_uint8;
> +typedef pfdep_int16 ogma_int16;
> +typedef pfdep_uint16 ogma_uint16;
> +typedef pfdep_int32 ogma_int32;
> +typedef pfdep_uint32 ogma_uint32;
> +typedef int ogma_int;
> +typedef unsigned int ogma_uint;
> +typedef pfdep_bool ogma_bool;
> +typedef pfdep_char ogma_char;
> +
> +#ifdef PFDEP_INT64_AVAILABLE
> +typedef signed long long ogma_int64;
> +typedef unsigned long long ogma_uint64;
> +#endif /* PFDEP_INT64_AVAILABLE*/
> +
> +#endif /* OGMA_BASIC_TYPE_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
> new file mode 100644
> index 000000000000..61335b96db77
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_version.h
> @@ -0,0 +1,24 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_VERSION_H
> +#define OGMA_VERSION_H
> +
> +#define OGMA_VER_NETSEC   (0x00050050UL)
> +
> +#define OGMA_INVALID_VER             0x0
> +#define OGMA_VER_MAJOR_NUM(x) (x&0xffff0000UL)

*twitch*
Although I will point out that the above macro is buggy.

> +
> +#endif /* OGMA_VERSION_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
> new file mode 100644
> index 000000000000..7b399beaedb2
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.c
> @@ -0,0 +1,88 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +void ogma_set_mac_reg (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 addr,
> +    ogma_uint32 value)
> +{
> +
> +    ogma_uint32 cmd;
> +
> +    ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> +    /*
> +     * Argument check is omitted because this function is
> +     * of private use only.
> +     */
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_MAC_DATA,
> +                    value);
> +
> +    cmd = addr | OGMA_GMAC_CMD_ST_WRITE;
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_MAC_CMD,
> +                    cmd);
> +
> +    /*
> +     * Waits until BUSY bit is cleared.
> +     */
> +    while ( ( ogma_read_reg( ctrl_p,
> +                             OGMA_REG_ADDR_MAC_CMD)
> +              & OGMA_GMAC_CMD_ST_BUSY)
> +            != 0) {
> +        ;
> +    }
> +}
> +
> +ogma_uint32 ogma_get_mac_reg (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 addr)
> +{
> +    ogma_uint32 cmd;
> +
> +    ogma_check_clk_supply( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> +    /*
> +     * Argument check is omitted because this function is
> +     * of private use only.
> +     */
> +
> +    cmd = addr | OGMA_GMAC_CMD_ST_READ;
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_MAC_CMD,
> +                    cmd);
> +
> +    /*
> +     * Waits until BUSY bit is cleared.
> +     */
> +    while ( ( ogma_read_reg( ctrl_p,
> +                             OGMA_REG_ADDR_MAC_CMD)
> +              & OGMA_GMAC_CMD_ST_BUSY)
> +            != 0) {
> +        ;
> +    }
> +    return ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DATA);
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
> new file mode 100644
> index 000000000000..a81b9249f4a2
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_basic_access.h
> @@ -0,0 +1,52 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_BASIC_ACCESS_H
> +#define OGMA_BASIC_ACCESS_H
> +
> +#include "ogma_internal.h"
> +
> +static __inline void ogma_write_reg (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 reg_addr,
> +    ogma_uint32 value
> +    )
> +{
> +
> +    pfdep_iomem_write( (void *) ( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
> +                                  ( reg_addr << 2) ),
> +                       value);
> +}
> +
> +static __inline ogma_uint32 ogma_read_reg (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 reg_addr
> +    )
> +{
> +
> +    return ( ogma_uint32)pfdep_iomem_read( (void *)( ( pfdep_cpu_addr_t)ctrl_p->base_addr +
> +                                                     ( reg_addr << 2) ) );
> +}
> +
> +void ogma_set_mac_reg (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 addr,
> +    ogma_uint32 value);
> +
> +ogma_uint32 ogma_get_mac_reg (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 addr);
> +
> +#endif/* OGMA_BASIC_ACCESS_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
> new file mode 100644
> index 000000000000..a38aff3ce4a5
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access.c
> @@ -0,0 +1,1391 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +#include "ogma_desc_ring_access_internal.h"
> +
> +
> +const ogma_uint32 ogma_desc_start_reg_addr_upper[OGMA_DESC_RING_ID_MAX+1] = {
> +    OGMA_REG_ADDR_NRM_TX_DESC_START_UP,
> +    OGMA_REG_ADDR_NRM_RX_DESC_START_UP,
> +};
> +
> +const ogma_uint32 ogma_desc_start_reg_addr_lower[OGMA_DESC_RING_ID_MAX+1] = {
> +    OGMA_REG_ADDR_NRM_TX_DESC_START_LW,
> +    OGMA_REG_ADDR_NRM_RX_DESC_START_LW,
> +};
> +
> +const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> +    OGMA_REG_ADDR_NRM_TX_INTEN,
> +    OGMA_REG_ADDR_NRM_RX_INTEN,
> +};
> +
> +const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> +    OGMA_REG_ADDR_NRM_TX_INTEN_SET,
> +    OGMA_REG_ADDR_NRM_RX_INTEN_SET,
> +};
> +
> +const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> +    OGMA_REG_ADDR_NRM_TX_INTEN_CLR,
> +    OGMA_REG_ADDR_NRM_RX_INTEN_CLR,
> +};
> +
> +static const ogma_uint32 int_tmr_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> +    OGMA_REG_ADDR_NRM_TX_TXINT_TMR,
> +    OGMA_REG_ADDR_NRM_RX_RXINT_TMR,
> +};
> +
> +static const ogma_uint32 rx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> +    0,
> +    OGMA_REG_ADDR_NRM_RX_PKTCNT,
> +};
> +
> +static const ogma_uint32 tx_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> +    OGMA_REG_ADDR_NRM_TX_PKTCNT,
> +    0,
> +
> +};
> +
> +static const ogma_uint32 int_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> +    OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT,
> +    OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT,
> +};
> +
> +static const ogma_uint32 tx_done_pkt_cnt_reg_addr[OGMA_DESC_RING_ID_MAX+1] = {
> +    OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT,
> +    0,
> +};
> +
> +
> +STATIC void ogma_set_tx_desc_entry (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> +    ogma_bool first_flag,
> +    ogma_bool last_flag,
> +    ogma_bool trs_flag,
> +    const ogma_frag_info_t *frag_info_p,
> +    pfdep_pkt_handle_t pkt_handle);
> +
> +STATIC void ogma_set_rx_desc_entry (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    const ogma_frag_info_t *frag_info_p,
> +    pfdep_pkt_handle_t pkt_handle);
> +
> +STATIC void ogma_get_rx_desc_entry (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    ogma_rx_pkt_info_t *rx_pkt_info_p,
> +    ogma_frag_info_t *frag_info_p,
> +    ogma_uint16 *len_p,
> +    pfdep_pkt_handle_t *pkt_handle_p);
> +
> +STATIC void ogma_clean_tx_desc_ring_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +STATIC void ogma_clean_rx_desc_ring_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +STATIC void ogma_inc_desc_head_idx (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 increment);
> +
> +STATIC void ogma_inc_desc_tail_idx (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 increment);
> +
> +STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    const ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +STATIC ogma_uint16 ogma_get_tx_done_num_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +static __inline void ogma_desc_ring_cpy_to_mem(
> +        void *dst_p,
> +        void *src_p,
> +        ogma_uint32 len)
> +{
> +    pfdep_memcpy(dst_p,src_p,len);
> +}
> +
> +static __inline void ogma_desc_ring_cpy_from_mem(
> +        void *dst_p,
> +        void *src_p,
> +        ogma_uint32 len)
> +{
> +    pfdep_memcpy(dst_p,src_p,len);
> +}
> +
> +static __inline void ogma_desc_ring_memclr(
> +        void *dst_p,
> +        ogma_uint32 len)
> +{
> +    pfdep_memset(dst_p,0,len);
> +}
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +ogma_err_t ogma_alloc_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_desc_ring_t *desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +    ogma_desc_ring_param_t *desc_ring_param_p = &ctrl_p->desc_ring[ring_id].param;
> +    pfdep_err_t pfdep_err;
> +
> +    if ( ( ctrl_p->param.desc_ring_param[ring_id].valid_flag) &&
> +         ( ( ctrl_p->param.desc_ring_param[ring_id].entry_num <
> +             OGMA_DESC_ENTRY_NUM_MIN) ||
> +           ( ctrl_p->param.desc_ring_param[ring_id].entry_num >
> +             OGMA_DESC_ENTRY_NUM_MAX) ) ) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_alloc_desc_ring.\n"
> +                     "Please set entry_num between %d and %d.\n",
> +                     OGMA_DESC_ENTRY_NUM_MIN, OGMA_DESC_ENTRY_NUM_MAX);
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    desc_ring_p->ring_id = ring_id;
> +
> +    pfdep_memcpy( desc_ring_param_p,
> +                  &ctrl_p->param.desc_ring_param[ring_id],
> +                  sizeof( ogma_desc_ring_param_t) );
> +
> +    if ( !desc_ring_param_p->valid_flag) {
> +
> +        desc_ring_p->desc_ring_phys_addr = ctrl_p->dummy_desc_entry_phys_addr;
> +
> +        ogma_write_reg( ctrl_p,
> +                        ogma_desc_start_reg_addr_upper[ring_id],
> +                        (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
> +        ogma_write_reg( ctrl_p,
> +                        ogma_desc_start_reg_addr_lower[ring_id],
> +                        (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
> +
> +        return OGMA_ERR_OK;
> +    }
> +
> +    switch ( ring_id) {
> +    case OGMA_DESC_RING_ID_NRM_TX:
> +        desc_ring_p->tx_desc_ring_flag = OGMA_TRUE;
> +        desc_ring_p->desc_entry_len = sizeof( ogma_tx_desc_entry_t);
> +        break;
> +
> +    case OGMA_DESC_RING_ID_NRM_RX:
> +        desc_ring_p->rx_desc_ring_flag = OGMA_TRUE;
> +        desc_ring_p->desc_entry_len = sizeof( ogma_rx_desc_entry_t);
> +        break;
> +
> +    default:
> +        pfdep_assert(0);
> +    }
> +
> +    if ( ( pfdep_err = pfdep_init_hard_lock ( &desc_ring_p->inten_reg_hard_lock) )
> +         != PFDEP_ERR_OK) {
> +        pfdep_memset( desc_ring_param_p,
> +                      0,
> +                      sizeof( ogma_desc_ring_param_t) );
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_alloc_desc_ring.\n"
> +                     "Failed to inten_reg_hard_lock's initialization.\n");
> +        return OGMA_ERR_ALLOC;
> +    }
> +
> +    if ( ( pfdep_err = pfdep_init_soft_lock ( &desc_ring_p->soft_lock) )
> +         != PFDEP_ERR_OK) {
> +        pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
> +        pfdep_memset( desc_ring_param_p,
> +                      0,
> +                      sizeof( ogma_desc_ring_param_t) );
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_alloc_desc_ring.\n"
> +                     "Failed to soft_lock's initialization.\n");
> +        return OGMA_ERR_ALLOC;
> +    }
> +
> +    if ( ( pfdep_err = pfdep_dma_malloc (
> +               ( pfdep_dev_handle_t) ctrl_p->dev_handle,
> +               ( pfdep_uint32) desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num,
> +               ( void **) &desc_ring_p->desc_ring_cpu_addr,
> +               ( pfdep_phys_addr_t *) &desc_ring_p->desc_ring_phys_addr) )
> +         != PFDEP_ERR_OK) {
> +        ogma_err = OGMA_ERR_ALLOC;
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_alloc_desc_ring.\n"
> +                     "Failed to desc_ring entry memory allocation.\n");
> +        goto err;
> +    }
> +
> +    ogma_desc_ring_memclr(
> +        desc_ring_p->desc_ring_cpu_addr,
> +        ( ogma_uint32)desc_ring_p->desc_entry_len * desc_ring_param_p->entry_num);
> +
> +    ogma_write_reg( ctrl_p,
> +                    ogma_desc_start_reg_addr_upper[ring_id],
> +                    (ogma_uint32)(desc_ring_p->desc_ring_phys_addr >> 32));
> +    ogma_write_reg( ctrl_p,
> +                    ogma_desc_start_reg_addr_lower[ring_id],
> +                    (ogma_uint32)desc_ring_p->desc_ring_phys_addr);
> +
> +    if ( ( desc_ring_p->frag_info_p =
> +           pfdep_malloc( sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num) )
> +         == NULL) {
> +        ogma_err = OGMA_ERR_ALLOC;
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_alloc_desc_ring.\n"
> +                     "Failed to fragment infomation memory allocation.\n");
> +        goto err;
> +    }
> +
> +    pfdep_memset(
> +        desc_ring_p->frag_info_p,
> +        0,
> +        sizeof( ogma_frag_info_t) * desc_ring_param_p->entry_num);
> +
> +    if ( ( desc_ring_p->priv_data_p =
> +           pfdep_malloc( sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num) )
> +         == NULL) {
> +        ogma_err = OGMA_ERR_ALLOC;
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_alloc_desc_ring.\n"
> +                     "Failed to private data memory allocation.\n");
> +        goto err;
> +    }
> +
> +    pfdep_memset(
> +        desc_ring_p->priv_data_p,
> +        0,
> +        sizeof( ogma_desc_entry_priv_t) * desc_ring_param_p->entry_num);
> +
> +    return OGMA_ERR_OK;
> +
> +err:
> +    ogma_free_desc_ring( ctrl_p, desc_ring_p);
> +    return ogma_err;
> +}
> +
> +void ogma_free_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +
> +    if ( !desc_ring_p->param.valid_flag) {
> +        return ;
> +    }
> +    if ( ogma_is_pkt_desc_ring ( desc_ring_p) ) {
> +        if ( ( desc_ring_p->desc_ring_cpu_addr != NULL) &&
> +             ( desc_ring_p->frag_info_p != NULL) &&
> +             ( desc_ring_p->priv_data_p != NULL) ) {
> +            ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
> +        }
> +    }
> +    if ( desc_ring_p->desc_ring_cpu_addr != NULL) {
> +        pfdep_dma_free( ctrl_p->dev_handle,
> +                        ( ogma_uint32)desc_ring_p->desc_entry_len *
> +                        desc_ring_p->param.entry_num,
> +                        desc_ring_p->desc_ring_cpu_addr,
> +                        desc_ring_p->desc_ring_phys_addr);
> +    }
> +
> +    if ( desc_ring_p->frag_info_p != NULL) {
> +        pfdep_free(desc_ring_p->frag_info_p);
> +    }
> +
> +    if ( desc_ring_p->priv_data_p != NULL) {
> +        pfdep_free( desc_ring_p->priv_data_p);
> +    }
> +
> +    pfdep_uninit_hard_lock ( &desc_ring_p->inten_reg_hard_lock);
> +
> +    pfdep_uninit_soft_lock ( &desc_ring_p->soft_lock);
> +
> +    pfdep_memset( desc_ring_p, 0, sizeof( ogma_desc_ring_t) );
> +}
> +
> +ogma_err_t ogma_setup_rx_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +    ogma_uint16 idx;
> +    ogma_frag_info_t frag_info= {0,0,0};
> +
> +    pfdep_err_t pfdep_err;
> +    pfdep_pkt_handle_t tmp_pkt_handle;
> +
> +    frag_info.len = ctrl_p->rx_pkt_buf_len;
> +
> +    for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
> +        if ( ( pfdep_err = pfdep_alloc_pkt_buf (
> +                   ( pfdep_dev_handle_t)ctrl_p->dev_handle,
> +                   ( ogma_uint16)frag_info.len,
> +                   ( void **)&frag_info.addr,
> +                   ( pfdep_phys_addr_t *)&frag_info.phys_addr,
> +                   ( pfdep_pkt_handle_t *)&tmp_pkt_handle) )
> +             != PFDEP_ERR_OK) {
> +            ogma_uninit_pkt_desc_ring( ctrl_p, desc_ring_p);
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "An error occurred at ogma_setup_rx_desc_ring.\n"
> +                         "Failed to rx packet memory allocation.\n");
> +            return OGMA_ERR_ALLOC;
> +        }
> +        ogma_set_rx_desc_entry( ctrl_p,
> +                                desc_ring_p,
> +                                idx,
> +                                &frag_info,
> +                                tmp_pkt_handle);
> +    }
> +    return OGMA_ERR_OK;
> +}
> +
> +void ogma_uninit_pkt_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +    ogma_uint16 idx;
> +    ogma_uint32 tmp;
> +    ogma_bool last_flag;
> +
> +    for ( idx = 0; idx < desc_ring_p->param.entry_num; idx++) {
> +        if ( desc_ring_p->frag_info_p[idx].addr == NULL ) {
> +            continue;
> +        }
> +
> +        tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
> +
> +        last_flag = ( ( ( tmp >> 8) & 0x1) != 0);
> +
> +        pfdep_free_pkt_buf (
> +            ctrl_p->dev_handle,
> +            desc_ring_p->frag_info_p[idx].len,
> +            desc_ring_p->frag_info_p[idx].addr,
> +            desc_ring_p->frag_info_p[idx].phys_addr,
> +            last_flag,
> +            desc_ring_p->priv_data_p[idx].pkt_handle);
> +    }
> +
> +    /* clear frag_info_p */
> +    pfdep_memset( desc_ring_p->frag_info_p,
> +                  0,
> +                  sizeof( ogma_frag_info_t) * desc_ring_p->param.entry_num);
> +
> +    /* clear pkt_handle_p */
> +    pfdep_memset( desc_ring_p->priv_data_p,
> +                  0,
> +                  sizeof( ogma_desc_entry_priv_t) * desc_ring_p->param.entry_num);
> +
> +    /* clear desc ring entry*/
> +    ogma_desc_ring_memclr ( desc_ring_p->desc_ring_cpu_addr,
> +                            ( ogma_uint32)desc_ring_p->desc_entry_len *
> +                            desc_ring_p->param.entry_num);
> +}
> +
> +STATIC void ogma_set_tx_desc_entry (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> +    ogma_bool first_flag,
> +    ogma_bool last_flag,
> +    ogma_bool trs_flag,
> +    const ogma_frag_info_t *frag_info_p,
> +    pfdep_pkt_handle_t pkt_handle
> +    )
> +{
> +    ogma_tx_desc_entry_t tx_desc_entry;
> +    ogma_uint32 attr, i, *debug_desc_entry_p;
> +
> +    ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
> +
> +    pfdep_memset( &tx_desc_entry, 0, sizeof( ogma_tx_desc_entry_t) );
> +
> +    attr = ( 1UL << OGMA_TX_PKT_DESC_RING_OWN_FIELD) |
> +        ( desc_ring_p->ring_id << OGMA_TX_PKT_DESC_RING_DRID_FIELD) |
> +        ( tx_pkt_ctrl_p->pass_through_flag <<
> +          OGMA_TX_PKT_DESC_RING_PT_FIELD) |
> +        ( tx_pkt_ctrl_p->target_desc_ring_id <<
> +          OGMA_TX_PKT_DESC_RING_TDRID_FIELD) |
> +        ( first_flag << OGMA_TX_PKT_DESC_RING_FS_FIELD) |
> +        ( last_flag << OGMA_TX_PKT_DESC_RING_LS_FIELD) |
> +        ( tx_pkt_ctrl_p->cksum_offload_flag <<
> +          OGMA_TX_PKT_DESC_RING_CO_FIELD) |
> +        ( tx_pkt_ctrl_p->tcp_seg_offload_flag <<
> +          OGMA_TX_PKT_DESC_RING_SO_FIELD) |
> +        ( trs_flag << OGMA_TX_PKT_DESC_RING_TRS_FIELD);
> +
> +    if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
> +        attr |= ( 0x1U << OGMA_TX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
> +    }
> +
> +    tx_desc_entry.attr = attr;
> +
> +    tx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
> +
> +    tx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
> +
> +    tx_desc_entry.buf_len_info =
> +        ( tx_pkt_ctrl_p->tcp_seg_len << 16) | frag_info_p->len;
> +
> +    ogma_desc_ring_cpy_to_mem( ( (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> +                               desc_ring_p->desc_entry_len * idx) ),
> +                               ( void *)&tx_desc_entry,
> +                               desc_ring_p->desc_entry_len);
> +
> +    debug_desc_entry_p = ( ogma_uint32 *)&tx_desc_entry;
> +
> +    for ( i = 0; i < ( sizeof( ogma_tx_desc_entry_t) >> 2); i++) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                     "%08x\n", debug_desc_entry_p[i]);
> +    }
> +
> +    desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
> +    desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
> +    desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
> +    desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
> +
> +}
> +
> +STATIC void ogma_set_rx_desc_entry (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    const ogma_frag_info_t *frag_info_p,
> +    pfdep_pkt_handle_t pkt_handle
> +    )
> +{
> +    ogma_rx_desc_entry_t rx_desc_entry;
> +
> +    ogma_check_desc_own_sanity(ctrl_p, desc_ring_p, idx, 0);
> +
> +    pfdep_memset( &rx_desc_entry, 0, sizeof ( ogma_rx_desc_entry_t) );
> +
> +    rx_desc_entry.attr = ( 1UL << OGMA_RX_PKT_DESC_RING_OWN_FIELD) |
> +        ( 1UL << OGMA_RX_PKT_DESC_RING_FS_FIELD) |
> +        ( 1UL << OGMA_RX_PKT_DESC_RING_LS_FIELD) ; /* OWN = FS = LS = 1 */
> +
> +    rx_desc_entry.data_buf_addr_upper = (ogma_uint32)(frag_info_p->phys_addr >> 32);
> +
> +    rx_desc_entry.data_buf_addr_lower = (ogma_uint32)frag_info_p->phys_addr;
> +
> +    rx_desc_entry.buf_len_info = frag_info_p->len;
> +
> +    if ( idx == ( desc_ring_p->param.entry_num - 1) ) {
> +        rx_desc_entry.attr |= ( 0x1U << OGMA_RX_PKT_DESC_RING_LD_FIELD); /* LD = 1 */
> +    }
> +
> +    ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> +                               desc_ring_p->desc_entry_len * idx + 4) ),
> +                               ( void *) ( ( pfdep_cpu_addr_t)&rx_desc_entry + 4),
> +                               ( ogma_uint32)( desc_ring_p->desc_entry_len - 4U) );
> +
> +    pfdep_write_mem_barrier();
> +
> +    ogma_desc_ring_cpy_to_mem( ( ( void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> +                               desc_ring_p->desc_entry_len * idx) ),
> +                               ( void *)&rx_desc_entry,
> +                               4);
> +
> +    desc_ring_p->frag_info_p[idx].phys_addr = frag_info_p->phys_addr;
> +    desc_ring_p->frag_info_p[idx].addr = frag_info_p->addr;
> +    desc_ring_p->frag_info_p[idx].len = frag_info_p->len;
> +    desc_ring_p->priv_data_p[idx].pkt_handle = pkt_handle;
> +}
> +
> +STATIC void ogma_get_rx_desc_entry (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    ogma_rx_pkt_info_t *rx_pkt_info_p,
> +    ogma_frag_info_t *frag_info_p,
> +    ogma_uint16 *len_p,
> +    pfdep_pkt_handle_t *pkt_handle_p)
> +{
> +    ogma_uint32 *debug_desc_entry_p;
> +    ogma_rx_desc_entry_t rx_desc_entry;
> +
> +    ogma_check_desc_own_sanity( ctrl_p, desc_ring_p, idx, 0);
> +
> +    pfdep_memset( &rx_desc_entry, 0, sizeof( ogma_rx_desc_entry_t) );
> +    pfdep_memset( rx_pkt_info_p, 0, sizeof( ogma_rx_pkt_info_t) );
> +
> +    ogma_desc_ring_cpy_from_mem( &rx_desc_entry,
> +                                 (void *) ( ( pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> +                                 desc_ring_p->desc_entry_len * idx),
> +                                 desc_ring_p->desc_entry_len);
> +
> +    debug_desc_entry_p = (ogma_uint32 *)&rx_desc_entry;
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "%08x\n", *debug_desc_entry_p);
> +
> +    *len_p = rx_desc_entry.buf_len_info >> 16;
> +
> +    rx_pkt_info_p->fragmented_flag =
> +        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_FR_FIELD) & 0x1; /* FR*/
> +
> +    rx_pkt_info_p->err_flag =
> +        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ER_FIELD) & 0x1; /* ER */
> +
> +    rx_pkt_info_p->rx_cksum_result =
> +        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_CO_FIELD) & 0x3; /* CO */
> +
> +    rx_pkt_info_p->err_code =
> +        ( rx_desc_entry.attr >> OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD) &
> +        OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK; /* Error Code */
> +
> +    pfdep_memcpy( frag_info_p,
> +                  &desc_ring_p->frag_info_p[idx],
> +                  sizeof(ogma_frag_info_t) );
> +
> +    *pkt_handle_p = desc_ring_p->priv_data_p[idx].pkt_handle;
> +}
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +STATIC __inline ogma_uint16 ogma_calc_busy_entry_num (
> +    ogma_uint16 head_idx,
> +    ogma_uint16 tail_idx,
> +    ogma_uint16 entry_num,
> +    ogma_bool full_flag
> +    )
> +{
> +
> +    ogma_int16 busy_entry_num;
> +
> +    if (full_flag) {
> +        busy_entry_num = entry_num;
> +    } else if (head_idx >= tail_idx) {
> +        busy_entry_num = head_idx - tail_idx;
> +    } else {
> +        busy_entry_num = entry_num + head_idx - tail_idx;
> +    }
> +
> +    return busy_entry_num;
> +
> +}
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +STATIC void ogma_clean_tx_desc_ring_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +
> +    ogma_uint32 tmp;
> +
> +    ogma_get_tx_done_num_sub( ctrl_p, desc_ring_p);
> +
> +    while( ( (desc_ring_p->tail_idx != desc_ring_p->head_idx) ||
> +             desc_ring_p->full_flag) && ( desc_ring_p->tx_done_num != 0) ) {
> +
> +        tmp = ogma_get_desc_ring_attr(desc_ring_p,
> +                                      desc_ring_p->tail_idx);
> +
> +        pfdep_free_pkt_buf (
> +            ctrl_p->dev_handle,
> +            desc_ring_p->frag_info_p[desc_ring_p->tail_idx].len,
> +            desc_ring_p->frag_info_p[desc_ring_p->tail_idx].addr,
> +            desc_ring_p->frag_info_p[desc_ring_p->tail_idx].phys_addr,
> +            ( ( ( tmp >> OGMA_TX_PKT_DESC_RING_LS_FIELD) & 0x1) != 0),
> +            desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
> +
> +        pfdep_memset( &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
> +                      0,
> +                      sizeof( ogma_frag_info_t) );
> +
> +        ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
> +
> +        if ( ( tmp & ( 1UL << OGMA_TX_PKT_DESC_RING_LS_FIELD) ) != 0) {
> +
> +            pfdep_assert( desc_ring_p->tx_done_num != 0);
> +
> +            desc_ring_p->tx_done_num--;
> +
> +        }
> +    }
> +
> +}
> +
> +STATIC void ogma_clean_rx_desc_ring_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +
> +    while( desc_ring_p->full_flag ||
> +           ( desc_ring_p->tail_idx != desc_ring_p->head_idx) ) {
> +
> +        ogma_set_rx_desc_entry(
> +            ctrl_p,
> +            desc_ring_p,
> +            desc_ring_p->tail_idx,
> +            &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
> +            desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
> +
> +        --desc_ring_p->rx_num;
> +        ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
> +    }
> +
> +    pfdep_assert( desc_ring_p->rx_num == 0);/* error check*/
> +
> +}
> +
> +STATIC void ogma_inc_desc_head_idx (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 increment)
> +{
> +    ogma_uint32 sum;
> +
> +    if ( ( desc_ring_p->tail_idx > desc_ring_p->head_idx) ||
> +         desc_ring_p->full_flag) {
> +        pfdep_assert( increment <=
> +                      ( desc_ring_p->tail_idx -
> +                       desc_ring_p->head_idx));
> +    } else {
> +        pfdep_assert( increment <=
> +                      ( desc_ring_p->param.entry_num +
> +                        desc_ring_p->tail_idx -
> +                        desc_ring_p->head_idx) );
> +    }
> +
> +    sum = (ogma_uint32) desc_ring_p->head_idx + increment;
> +
> +    if ( sum >= desc_ring_p->param.entry_num) {
> +        sum -= desc_ring_p->param.entry_num;
> +    }
> +
> +    desc_ring_p->head_idx = ( ogma_uint16)sum;
> +
> +    if ( desc_ring_p->head_idx == desc_ring_p->tail_idx) {
> +        desc_ring_p->full_flag = OGMA_TRUE;
> +    }
> +
> +}
> +
> +STATIC void ogma_inc_desc_tail_idx (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 increment)
> +{
> +    ogma_uint32 sum;
> +
> +    if ( ( desc_ring_p->head_idx >= desc_ring_p->tail_idx) &&
> +         ( !desc_ring_p->full_flag) ) {
> +        pfdep_assert( increment <=
> +                      ( desc_ring_p->head_idx -
> +                        desc_ring_p->tail_idx) );
> +    } else {
> +        pfdep_assert( increment <=
> +                      ( desc_ring_p->param.entry_num +
> +                        desc_ring_p->head_idx -
> +                        desc_ring_p->tail_idx) );
> +    }
> +
> +    sum = (ogma_uint32) desc_ring_p->tail_idx + increment;
> +
> +    if ( sum >= desc_ring_p->param.entry_num) {
> +        sum -= desc_ring_p->param.entry_num;
> +    }
> +
> +    desc_ring_p->tail_idx = ( ogma_uint16)sum;
> +
> +    desc_ring_p->full_flag = OGMA_FALSE;
> +}
> +
> +
> +STATIC ogma_uint16 ogma_get_tx_avail_num_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    const ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +    ogma_uint16 tx_avail_num;
> +
> +    if ( desc_ring_p->full_flag) {
> +
> +        tx_avail_num = 0;
> +
> +    } else if ( desc_ring_p->tail_idx > desc_ring_p->head_idx) {
> +
> +        tx_avail_num = desc_ring_p->tail_idx - desc_ring_p->head_idx;
> +
> +    } else {
> +
> +        tx_avail_num =
> +            desc_ring_p->param.entry_num +
> +            desc_ring_p->tail_idx -
> +            desc_ring_p->head_idx;
> +    }
> +
> +    return tx_avail_num;
> +}
> +
> +STATIC ogma_uint16 ogma_get_tx_done_num_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +    ogma_uint32 value;
> +
> +    value = ogma_read_reg ( ctrl_p,
> +                            tx_done_pkt_cnt_reg_addr[desc_ring_p->ring_id] );
> +
> +    desc_ring_p->tx_done_num += value;
> +
> +    return desc_ring_p->tx_done_num;
> +}
> +
> +
> +ogma_err_t ogma_start_desc_ring (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +    pfdep_err_t pfdep_err;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    if ( desc_ring_p->running_flag) {
> +        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                                 &soft_lock_ctx);
> +        return OGMA_ERR_BUSY;
> +    }
> +
> +    if ( desc_ring_p->rx_desc_ring_flag) {
> +
> +        ogma_write_reg ( ctrl_p,
> +                         desc_ring_irq_inten_set_reg_addr[ring_id],
> +                         OGMA_CH_IRQ_REG_RCV);
> +
> +        ogma_write_reg ( ctrl_p,
> +                         int_pkt_cnt_reg_addr[ring_id],
> +                         1);
> +    }
> +
> +    if ( desc_ring_p->tx_desc_ring_flag) {
> +
> +
> +        value = OGMA_CH_IRQ_REG_EMPTY;
> +
> +
> +        ogma_write_reg ( ctrl_p,
> +                         desc_ring_irq_inten_set_reg_addr[ring_id],
> +                         value);
> +
> +        ogma_write_reg ( ctrl_p,
> +                         int_pkt_cnt_reg_addr[ring_id],
> +                         1);
> +
> +    }
> +
> +    desc_ring_p->running_flag = OGMA_TRUE;
> +
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +
> +    return ogma_err;
> +}
> +
> +
> +ogma_err_t ogma_stop_desc_ring (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +    pfdep_err_t pfdep_err;
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id] ) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    if ( !desc_ring_p->running_flag) {
> +        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                                 &soft_lock_ctx);
> +        return OGMA_ERR_INVALID;
> +    }
> +
> +    value = ( OGMA_CH_IRQ_REG_RCV |
> +              OGMA_CH_IRQ_REG_EMPTY |
> +              OGMA_CH_IRQ_REG_SND);
> +
> +    ogma_write_reg ( ctrl_p,
> +                     desc_ring_irq_inten_clr_reg_addr[ring_id],
> +                     value);
> +
> +    desc_ring_p->running_flag = OGMA_FALSE;
> +
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_uint16 ogma_get_rx_num (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +
> +    ogma_uint32 result;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p = NULL;
> +    ogma_desc_ring_id_t tmp_ring_id;
> +
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +    pfdep_err_t pfdep_err;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_rx_num.\n"
> +                     "Please set valid argument.\n");
> +        return 0;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_rx_num.\n"
> +                     "Please set valid argument.\n");
> +        return 0;
> +    }
> +
> +    tmp_ring_id = ring_id;
> +
> +    if (! ctrl_p->desc_ring[tmp_ring_id].rx_desc_ring_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_rx_num.\n"
> +                     "Please select rx packet desc ring or bulk desc ring.\n");
> +        return 0;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +               &desc_ring_p->soft_lock,
> +               &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_rx_num.\n"
> +                     "Failed to get soft lock.\n");
> +        return 0;
> +    }
> +
> +    result = ogma_read_reg( ctrl_p, rx_pkt_cnt_reg_addr[tmp_ring_id]);
> +
> +    desc_ring_p->rx_num += result;
> +
> +    if ( desc_ring_p->rx_desc_ring_flag && ( result != 0) ) {
> +        ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, ( ogma_uint16)result);
> +    }
> +
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +
> +    return desc_ring_p->rx_num;
> +}
> +
> +
> +ogma_uint16 ogma_get_tx_avail_num (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +
> +    ogma_uint16 result;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_id_t tmp_ring_id;
> +    ogma_desc_ring_t *desc_ring_p = NULL;
> +
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +    pfdep_err_t pfdep_err;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ||
> +         ( !ctrl_p->desc_ring[ring_id].param.valid_flag) ) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_tx_avail_num.\n"
> +                     "Please select valid argument.\n");
> +        return 0;
> +    }
> +
> +    tmp_ring_id = ring_id;
> +
> +    if (! ctrl_p->desc_ring[tmp_ring_id].tx_desc_ring_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_tx_avail_num.\n"
> +                     "Please select tx packet desc ring or bulk desc ring.\n");
> +        return 0;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[tmp_ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_tx_avail_num.\n"
> +                     "Failed to get soft lock.\n");
> +        return 0;
> +    }
> +
> +    if ( !desc_ring_p->running_flag) {
> +        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                                 &soft_lock_ctx);
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_tx_avail_num.\n"
> +                     "Please select running desc ring.\n");
> +        return 0;
> +    }
> +
> +    result = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
> +
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +    return result;
> +}
> +
> +ogma_err_t ogma_clean_tx_desc_ring (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +
> +    pfdep_err_t pfdep_err;
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    ogma_clean_tx_desc_ring_sub(ctrl_p, desc_ring_p);
> +
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +    return OGMA_ERR_OK;
> +
> +
> +}
> +
> +ogma_err_t ogma_clean_rx_desc_ring (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +
> +    pfdep_err_t pfdep_err;
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    ogma_clean_rx_desc_ring_sub(ctrl_p, desc_ring_p);
> +
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +    return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_set_tx_pkt_data (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p,
> +    ogma_uint8 scat_num,
> +    const ogma_frag_info_t *scat_info_p,
> +    pfdep_pkt_handle_t pkt_handle
> +    )
> +{
> +    ogma_uint i;
> +    ogma_uint16 tx_avail_num;
> +    ogma_uint32 sum_len = 0;
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +
> +    pfdep_err_t pfdep_err;
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( tx_pkt_ctrl_p == NULL) ||
> +         ( scat_info_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].tx_desc_ring_flag) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    {
> +        if ( !ctrl_p->param.use_gmac_flag ||
> +             ( tx_pkt_ctrl_p->target_desc_ring_id != OGMA_DESC_RING_ID_GMAC) ) {
> +            return OGMA_ERR_DATA;
> +        }
> +    }
> +
> +
> +    if ( tx_pkt_ctrl_p->tcp_seg_offload_flag &&
> +         ( !tx_pkt_ctrl_p->cksum_offload_flag) ) {
> +        return OGMA_ERR_DATA;
> +    }
> +
> +    if ( tx_pkt_ctrl_p->tcp_seg_offload_flag) {
> +
> +        if ( tx_pkt_ctrl_p->tcp_seg_len == 0) {
> +            return OGMA_ERR_DATA;
> +        }
> +
> +        if ( ctrl_p->param.use_jumbo_pkt_flag) {
> +            if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_JUMBO_SEG_LEN_MAX) {
> +                return OGMA_ERR_DATA;
> +            }
> +        } else {
> +            if (tx_pkt_ctrl_p->tcp_seg_len > OGMA_TCP_SEG_LEN_MAX) {
> +                return OGMA_ERR_DATA;
> +            }
> +        }
> +
> +    } else {
> +        if ( tx_pkt_ctrl_p->tcp_seg_len != 0) {
> +            return OGMA_ERR_DATA;
> +        }
> +    }
> +
> +
> +    if ( scat_num == 0) {
> +        return OGMA_ERR_RANGE;
> +    }
> +
> +    for ( i = 0; i < scat_num; i++) {
> +        if ( ( scat_info_p[i].len == 0) ||
> +             ( scat_info_p[i].len > 0xffffU) ) {
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "An error occurred at ogma_set_tx_pkt_data.\n"
> +                         "Pleas check scat_info_p[%u].len.\n",
> +                         i);
> +            return OGMA_ERR_DATA;
> +        }
> +        sum_len += scat_info_p[i].len;
> +    }
> +
> +    if ( !tx_pkt_ctrl_p->tcp_seg_offload_flag) {
> +
> +        if ( ctrl_p->param.use_jumbo_pkt_flag) {
> +            if ( sum_len > OGMA_MAX_TX_JUMBO_PKT_LEN) {
> +                return OGMA_ERR_DATA;
> +            }
> +        } else {
> +            if ( sum_len > OGMA_MAX_TX_PKT_LEN) {
> +                return OGMA_ERR_DATA;
> +            }
> +        }
> +
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    if ( !desc_ring_p->running_flag) {
> +        ogma_err = OGMA_ERR_NOTAVAIL;
> +        goto end;
> +    }
> +
> +    tx_avail_num = ogma_get_tx_avail_num_sub( ctrl_p, desc_ring_p);
> +
> +    if ( scat_num > tx_avail_num ) {
> +        ogma_err = OGMA_ERR_BUSY;
> +        goto end;
> +    }
> +
> +    for ( i = 0; i < scat_num; i++) {
> +
> +
> +        ogma_set_tx_desc_entry(
> +            ctrl_p,
> +            desc_ring_p,
> +            desc_ring_p->head_idx,
> +            tx_pkt_ctrl_p,
> +            ( i == 0),
> +            ( i == ( scat_num - 1U) ),
> +            OGMA_TRUE,
> +            &scat_info_p[i],
> +            pkt_handle);
> +        ogma_inc_desc_head_idx( ctrl_p, desc_ring_p, 1);
> +    }
> +
> +    pfdep_write_mem_barrier();
> +
> +    ogma_write_reg( ctrl_p,
> +                    tx_pkt_cnt_reg_addr[ring_id],
> +                    (ogma_uint32)1);
> +
> +end:
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +
> +    return ogma_err;
> +}
> +
> +ogma_err_t ogma_get_rx_pkt_data (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_rx_pkt_info_t *rx_pkt_info_p,
> +    ogma_frag_info_t *frag_info_p,
> +    ogma_uint16 *len_p,
> +    pfdep_pkt_handle_t *pkt_handle_p
> +    )
> +{
> +
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +    ogma_frag_info_t tmp_frag_info;
> +
> +    pfdep_err_t pfdep_err;
> +    pfdep_pkt_handle_t tmp_pkt_handle;
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG, "%s call.\n", __func__);
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( rx_pkt_info_p == NULL) ||
> +         ( frag_info_p == NULL) ||
> +         ( len_p == NULL) ||
> +         ( pkt_handle_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].rx_desc_ring_flag) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    if ( ( pfdep_err = pfdep_acquire_soft_lock(
> +              &desc_ring_p->soft_lock,
> +              &soft_lock_ctx ) ) != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    if ( desc_ring_p->rx_num == 0 ) {
> +        ogma_err = OGMA_ERR_INVALID;
> +        goto end;
> +    }
> +
> +    tmp_frag_info.len = ctrl_p->rx_pkt_buf_len;
> +
> +    pfdep_read_mem_barrier();
> +
> +    if ( ( pfdep_err = pfdep_alloc_pkt_buf (
> +               ctrl_p->dev_handle,
> +               tmp_frag_info.len,
> +               &tmp_frag_info.addr,
> +               &tmp_frag_info.phys_addr,
> +               &tmp_pkt_handle) ) != PFDEP_ERR_OK) {
> +        ogma_set_rx_desc_entry( ctrl_p,
> +                                desc_ring_p,
> +                                desc_ring_p->tail_idx,
> +                                &desc_ring_p->frag_info_p[desc_ring_p->tail_idx],
> +                                desc_ring_p->priv_data_p[desc_ring_p->tail_idx].pkt_handle);
> +        ogma_err = OGMA_ERR_ALLOC;
> +
> +    } else {
> +
> +        ogma_get_rx_desc_entry( ctrl_p,
> +                                desc_ring_p,
> +                                desc_ring_p->tail_idx,
> +                                rx_pkt_info_p,
> +                                frag_info_p,
> +                                len_p,
> +                                pkt_handle_p);
> +
> +
> +        ogma_set_rx_desc_entry( ctrl_p,
> +                                desc_ring_p,
> +                                desc_ring_p->tail_idx,
> +                                &tmp_frag_info,
> +                                tmp_pkt_handle);
> +    }
> +
> +    ogma_inc_desc_tail_idx( ctrl_p, desc_ring_p, 1);
> +
> +    --desc_ring_p->rx_num;
> +
> +end:
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +
> +    return ogma_err;
> +}
> +
> +ogma_err_t ogma_set_irq_coalesce_param (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint16 int_pktcnt,
> +    ogma_bool int_tmr_unit_ms_flag,
> +    ogma_uint16 int_tmr_cnt
> +    )
> +{
> +
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ring_id > OGMA_DESC_RING_ID_MAX) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( int_pktcnt > OGMA_INT_PKTCNT_MAX) {
> +        return OGMA_ERR_RANGE;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( !ogma_is_pkt_desc_ring( &ctrl_p->desc_ring[ring_id]) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    ogma_write_reg( ctrl_p,
> +                    int_pkt_cnt_reg_addr[ring_id],
> +                    int_pktcnt);
> +
> +    ogma_write_reg( ctrl_p,
> +                    int_tmr_reg_addr[ring_id],
> +                    ( ( ( ( ogma_uint32)int_tmr_unit_ms_flag) << 31) |
> +                      int_tmr_cnt) );
> +
> +    return ogma_err;
> +
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
> new file mode 100644
> index 000000000000..34490e2d1c78
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_desc_ring_access_internal.h
> @@ -0,0 +1,111 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_DESC_RING_ACCESS_INTERNAL_H
> +#define OGMA_DESC_RING_ACCESS_INTERNAL_H
> +
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
> +#include "ogma_internal.h"
> +
> +#define OGMA_TX_PKT_DESC_RING_OWN_FIELD        (31)
> +#define OGMA_TX_PKT_DESC_RING_LD_FIELD         (30)
> +#define OGMA_TX_PKT_DESC_RING_DRID_FIELD       (24)
> +#define OGMA_TX_PKT_DESC_RING_PT_FIELD         (21)
> +#define OGMA_TX_PKT_DESC_RING_TDRID_FIELD      (16)
> +#define OGMA_TX_PKT_DESC_RING_FS_FIELD         (9)
> +#define OGMA_TX_PKT_DESC_RING_LS_FIELD         (8)
> +#define OGMA_TX_PKT_DESC_RING_CO_FIELD         (7)
> +#define OGMA_TX_PKT_DESC_RING_SO_FIELD         (6)
> +#define OGMA_TX_PKT_DESC_RING_USRKEY_FIELD     (5)
> +#define OGMA_TX_PKT_DESC_RING_TRS_FIELD        (4)
> +
> +#define OGMA_RX_PKT_DESC_RING_OWN_FIELD        (31)
> +#define OGMA_RX_PKT_DESC_RING_LD_FIELD         (30)
> +#define OGMA_RX_PKT_DESC_RING_SDRID_FIELD      (24)
> +#define OGMA_RX_PKT_DESC_RING_FR_FIELD         (23)
> +#define OGMA_RX_PKT_DESC_RING_ER_FIELD         (21)
> +#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD (16)
> +#define OGMA_RX_PKT_DESC_RING_TDRID_FIELD      (12)
> +#define OGMA_RX_PKT_DESC_RING_FS_FIELD         (9)
> +#define OGMA_RX_PKT_DESC_RING_LS_FIELD         (8)
> +#define OGMA_RX_PKT_DESC_RING_CO_FIELD         (6)
> +
> +#define OGMA_RX_PKT_DESC_RING_ERROR_CODE_FIELD_MASK (0x3)
> +
> +#define OGMA_MAX_TX_PKT_LEN       1518U
> +#define OGMA_MAX_TX_JUMBO_PKT_LEN 9018U
> +
> +typedef struct ogma_tx_desc_entry_s ogma_tx_desc_entry_t;
> +typedef struct ogma_rx_desc_entry_s ogma_rx_desc_entry_t;
> +
> +struct ogma_tx_desc_entry_s{
> +
> +    ogma_uint32 attr;
> +
> +    ogma_uint32 data_buf_addr_upper;
> +
> +    ogma_uint32 data_buf_addr_lower;
> +
> +    ogma_uint32 buf_len_info;
> +};
> +
> +struct ogma_rx_desc_entry_s{
> +
> +    ogma_uint32 attr;
> +
> +    ogma_uint32 data_buf_addr_upper;
> +
> +    ogma_uint32 data_buf_addr_lower;
> +
> +    ogma_uint32 buf_len_info;
> +};
> +
> +static __inline ogma_bool ogma_is_pkt_desc_ring (
> +    const ogma_desc_ring_t *desc_ring_p
> +    )
> +{
> +    return ( desc_ring_p->rx_desc_ring_flag ||
> +             desc_ring_p->tx_desc_ring_flag);
> +}
> +
> +static __inline ogma_uint32 ogma_get_desc_ring_attr (
> +    const ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx
> +    )
> +{
> +    ogma_uint32 *addr =
> +        (ogma_uint32 *)
> +        ((pfdep_cpu_addr_t)desc_ring_p->desc_ring_cpu_addr +
> +         desc_ring_p->desc_entry_len * idx);
> +
> +    return *addr;
> +}
> +
> +
> +
> +static __inline void ogma_check_desc_own_sanity (
> +    ogma_ctrl_t *ctrl_p,
> +    const ogma_desc_ring_t *desc_ring_p,
> +    ogma_uint16 idx,
> +    ogma_uint expected_own)
> +{
> +    ogma_uint32 tmp;
> +    ( void)ctrl_p; /* Suppress compiler warning */
> +
> +    tmp = ogma_get_desc_ring_attr(desc_ring_p, idx);
> +    pfdep_assert( ( tmp >> 31) == expected_own);
> +}
> +
> +#endif /* OGMA_DESC_RING_ACCESS_INTERNAL_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
> new file mode 100644
> index 000000000000..d08bb53a54e8
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c
> @@ -0,0 +1,1454 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_config.h"
> +
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +
> +
> +/**********************************************************************
> + * Constant definitions
> + **********************************************************************/
> +
> +/**
> + * Clock range index for F_GMAC4MT::GAR::CR field.
> + */
> +#if (OGMA_CONFIG_GMAC_CLK_HZ < 35 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_25_35_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 60 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_35_60_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 100 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_60_100_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 150 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_100_150_MHZ
> +#elif (OGMA_CONFIG_GMAC_CLK_HZ < 250 * OGMA_CLK_MHZ)
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_150_250_MHZ
> +#else
> +#define OGMA_CLOCK_RANGE_IDX OGMA_GMAC_GAR_REG_CR_250_300_MHZ
> +#endif
> +
> +
> +/**********************************************************************
> + * Local function declarations
> + **********************************************************************/
> +static void ogma_set_phy_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr,
> +    ogma_uint16 value
> +    );
> +
> +static ogma_uint16 ogma_get_phy_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr
> +    );
> +
> +#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
> +void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p);
> +#endif /*  OGMA_CONFIG_USE_DUMP_GMAC_STAT */
> +
> +static void ogma_set_phy_target_mmd_reg_addr (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr
> +    );
> +
> +static void ogma_set_phy_mmd_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr,
> +    ogma_uint16 value
> +    );
> +
> +static ogma_uint16 ogma_get_phy_mmd_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr
> +    );
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +ogma_err_t ogma_start_gmac (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool rx_flag,
> +    ogma_bool tx_flag
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    pfdep_err_t pfdep_err;
> +    ogma_err_t ogma_err;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( !ctrl_p->gmac_mode_valid_flag) {
> +        return OGMA_ERR_INVALID;
> +    }
> +
> +    if ( ( !rx_flag) && ( !tx_flag) ) {
> +        return OGMA_ERR_OK;
> +    }
> +
> +    if ( ctrl_p->gmac_rx_running_flag &&
> +         ctrl_p->gmac_tx_running_flag) {
> +        return OGMA_ERR_OK;
> +    }
> +
> +
> +    if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) &&
> +         !tx_flag) {
> +        return OGMA_ERR_OK;
> +    }
> +
> +    if ( ( tx_flag && ctrl_p->gmac_tx_running_flag) &&
> +         !rx_flag ) {
> +        return OGMA_ERR_OK;
> +    }
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "%s call.\n", __func__);
> +
> +    if ( (! ctrl_p->gmac_rx_running_flag) &&
> +         (! ctrl_p->gmac_tx_running_flag) ) {
> +
> +        /* Initializes F_GMAC4MT */
> +        if ( ctrl_p->gmac_mode.link_speed ==
> +             OGMA_PHY_LINK_SPEED_1G) {
> +            /* Writes 0 to FGMAC4 MCR */
> +            ogma_set_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_MCR,
> +                              0);
> +        } else {
> +            /* Writes PS bit to FGMAC4 MCR */
> +            ogma_set_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_MCR,
> +                              OGMA_GMAC_MCR_10M_HALF);/* 10M half Reset */
> +        }
> +
> +        /* F_GMAC4MT soft reset*/
> +        if ( ( ogma_err = ogma_softreset_gmac( ctrl_p)) != OGMA_ERR_OK) {
> +            return ogma_err;
> +        }
> +
> +        /* MAC desc soft reset */
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_MAC_DESC_SOFT_RST,
> +                        OGMA_MAC_DESC_SOFT_RST_SOFT_RST);
> +
> +        /* Wait MAC desc soft reset */
> +        pfdep_err = pfdep_msleep( 1);
> +
> +        if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
> +
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                             "An error occurred at ogma_start_gmac.\n");
> +
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                             "Wait for MAC desc soft reset error.\n");
> +
> +            return OGMA_ERR_INTERRUPT;
> +        }
> +
> +        /* Check MAC desc soft reset done */
> +        if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_SOFT_RST) &
> +               OGMA_MAC_DESC_SOFT_RST_SOFT_RST) != 0) {
> +
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "ogma_start_gmac():MAC desc soft reset timeout. Try Again.\n");
> +
> +            return OGMA_ERR_AGAIN;
> +        }
> +
> +        /* MAC desc init */
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_MAC_DESC_INIT,
> +                        OGMA_MAC_DESC_INIT_REG_INIT);
> +
> +        /* Wait MAC desc init done */
> +        pfdep_err = pfdep_msleep( 1);
> +
> +        if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
> +
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "An error occurred at ogma_start_gmac().\n");
> +
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "Wait for MAC desc init done error.\n");
> +
> +            return OGMA_ERR_INTERRUPT;
> +        }
> +
> +        /* Check MAC desc init done */
> +        if ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT) &
> +               OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
> +
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "ogma_start_gmac():MAC desc init timeout. Try Again.\n");
> +
> +            return OGMA_ERR_AGAIN;
> +        }
> +
> +        /* set BMR */
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_BMR,
> +                          OGMA_GMAC_BMR_REG_COMMON);
> +        /* set RDLAR */
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_RDLAR,
> +                          OGMA_GMAC_RDLAR_REG_COMMON);
> +        /* set TDLAR*/
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_TDLAR,
> +                          OGMA_GMAC_TDLAR_REG_COMMON);
> +        /* set MFFR*/
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_MFFR,
> +                          0x80000001UL);
> +
> +        /* calc MCR setting val */
> +        value = ( ctrl_p->gmac_mode.half_duplex_flag ?
> +                  OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON :
> +                  OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON);
> +
> +        if ( ctrl_p->gmac_mode.link_speed != OGMA_PHY_LINK_SPEED_1G) {
> +            value |= OGMA_GMAC_MCR_REG_PS;
> +        }
> +
> +        if ( ( ctrl_p->param.gmac_config.phy_interface !=
> +               OGMA_PHY_INTERFACE_GMII ) &&
> +             ( ctrl_p->gmac_mode.link_speed == OGMA_PHY_LINK_SPEED_100M) ) {
> +            value |= OGMA_GMAC_MCR_REG_FES;
> +        }
> +        /* set CST bit  */
> +        value |= OGMA_GMAC_MCR_REG_CST;
> +
> +        /* set JE bit  */
> +        value |= OGMA_GMAC_MCR_REG_JE;
> +
> +        if ( ctrl_p->param.gmac_config.phy_interface ==
> +             OGMA_PHY_INTERFACE_RGMII) {
> +            /* set ignore in-band-status watch option. force tx clk out. */
> +            value |= 0x40000000U;
> +        }
> +
> +        /* set MCR */
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_MCR,
> +                          value);
> +
> +        if ( ctrl_p->gmac_mode.flow_ctrl_enable_flag) {
> +            /* Set Flow Control Threshold */
> +            value =
> +                ( ctrl_p->gmac_mode.flow_ctrl_stop_threshold << 16) |
> +                ctrl_p->gmac_mode.flow_ctrl_start_threshold;
> +
> +            ogma_write_reg( ctrl_p,
> +                            OGMA_REG_ADDR_MAC_FLOW_TH,
> +                            value);
> +            /* Set Flow Control Threshold F_GMAC4MT*/
> +            value =
> +                ( ctrl_p->gmac_mode.pause_time << 16) |
> +                OGMA_GMAC_FCR_REG_RFE |
> +                OGMA_GMAC_FCR_REG_TFE;
> +
> +            ogma_set_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_FCR,
> +                              value);
> +        }
> +
> +    }
> +
> +    if ( ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) ||
> +         ( tx_flag && (! ctrl_p->gmac_tx_running_flag) )
> +        ) {
> +        /* Read F_GMAC4MT OMR*/
> +        value = ogma_get_mac_reg( ctrl_p,
> +                                  OGMA_GMAC_REG_ADDR_OMR);
> +
> +        if ( rx_flag && (! ctrl_p->gmac_rx_running_flag) ) {
> +            value |= OGMA_GMAC_OMR_REG_SR;
> +            ctrl_p->gmac_rx_running_flag = OGMA_TRUE;
> +        }
> +
> +        if ( tx_flag && (! ctrl_p->gmac_tx_running_flag) ) {
> +            value |= OGMA_GMAC_OMR_REG_ST;
> +            ctrl_p->gmac_tx_running_flag = OGMA_TRUE;
> +        }
> +
> +        /* set OMR*/
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_OMR,
> +                          value);
> +
> +    }
> +
> +    return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_stop_gmac (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool rx_flag,
> +    ogma_bool tx_flag
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +
> +    if ( ( !rx_flag) && ( !tx_flag) ) {
> +        return OGMA_ERR_OK;
> +    }
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "%s call.\n", __func__);
> +
> +    if ( ( rx_flag && ctrl_p->gmac_rx_running_flag) ||
> +         ( tx_flag && ctrl_p->gmac_tx_running_flag) ) {
> +        /* Read F_GMAC4MT OMR*/
> +        value = ogma_get_mac_reg( ctrl_p,
> +                                  OGMA_GMAC_REG_ADDR_OMR);
> +
> +        if ( rx_flag && ctrl_p->gmac_rx_running_flag) {
> +            value &= (~OGMA_GMAC_OMR_REG_SR);
> +            ctrl_p->gmac_rx_running_flag = OGMA_FALSE;
> +        }
> +
> +        if ( tx_flag && ctrl_p->gmac_tx_running_flag) {
> +            value &= (~OGMA_GMAC_OMR_REG_ST);
> +            ctrl_p->gmac_tx_running_flag = OGMA_FALSE;
> +        }
> +
> +        /* set F_GMAC4MT OMR*/
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_OMR,
> +                          value);
> +    }
> +
> +#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
> +    ogma_dump_gmac_stat (ctrl_p);
> +#endif /*  OGMA_CONFIG_USE_DUMP_GMAC_STAT */
> +
> +
> +    return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_set_gmac_mode (
> +    ogma_handle_t ogma_handle,
> +    const ogma_gmac_mode_t *gmac_mode_p
> +    )
> +{
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( gmac_mode_p == NULL) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    if ( ( ctrl_p->gmac_rx_running_flag) ||
> +         ( ctrl_p->gmac_tx_running_flag) ) {
> +        return OGMA_ERR_BUSY;
> +    }
> +
> +   if ( ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_1G  ) &&
> +        ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_100M) &&
> +        ( gmac_mode_p->link_speed != OGMA_PHY_LINK_SPEED_10M ) ) {
> +       return OGMA_ERR_DATA;
> +    }
> +
> +   if ( ( gmac_mode_p->link_speed == OGMA_PHY_LINK_SPEED_1G) &&
> +        ( gmac_mode_p->half_duplex_flag) ) {
> +       return OGMA_ERR_DATA;
> +   }
> +
> +   if ( gmac_mode_p->half_duplex_flag &&
> +        gmac_mode_p->flow_ctrl_enable_flag) {
> +       return OGMA_ERR_DATA;
> +   }
> +
> +   if ( gmac_mode_p->flow_ctrl_enable_flag) {
> +
> +       if ( ( gmac_mode_p->flow_ctrl_start_threshold == 0) ||
> +            ( gmac_mode_p->flow_ctrl_start_threshold >
> +              OGMA_FLOW_CTRL_START_THRESHOLD_MAX) ) {
> +           return OGMA_ERR_DATA;
> +       }
> +
> +       if ( ( gmac_mode_p->flow_ctrl_stop_threshold <
> +              gmac_mode_p->flow_ctrl_start_threshold) ||
> +            ( gmac_mode_p->flow_ctrl_stop_threshold >
> +              OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX) ) {
> +           return OGMA_ERR_DATA;
> +       }
> +
> +       if ( gmac_mode_p->pause_time < OGMA_FLOW_CTRL_PAUSE_TIME_MIN) {
> +           return OGMA_ERR_DATA;
> +       }
> +   }
> +
> +   pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "%s call.\n", __func__);
> +
> +   pfdep_memcpy( ( void *)&ctrl_p->gmac_mode,
> +                 ( void *)gmac_mode_p,
> +                 sizeof( ogma_gmac_mode_t) );
> +
> +   ctrl_p->gmac_mode_valid_flag = OGMA_TRUE;
> +
> +
> +   return OGMA_ERR_OK;
> +
> +}
> +
> +static void ogma_set_phy_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr,
> +    ogma_uint16 value
> +    )
> +{
> +
> +    ogma_uint32 cmd;
> +
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_GDR,
> +                      value);
> +
> +    cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
> +            ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
> +            ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
> +            OGMA_GMAC_GAR_REG_GW |
> +            OGMA_GMAC_GAR_REG_GB);
> +
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_GAR,
> +                      cmd);
> +
> +    while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
> +              OGMA_GMAC_GAR_REG_GB)
> +            != 0) {
> +        ;
> +    }
> +}
> +
> +void ogma_set_phy_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr,
> +    ogma_uint16 value
> +    )
> +{
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if (( ctrl_p == NULL)
> +        || ( !ctrl_p->param.use_gmac_flag)
> +        || ( phy_addr >= 32)
> +        || ( reg_addr >= 32) ) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_set_phy_reg.\nPlease set valid argument.\n");
> +        return;
> +    }
> +
> +    ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value);
> +
> +}
> +
> +static ogma_uint16 ogma_get_phy_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr
> +    )
> +{
> +
> +    ogma_uint32 cmd;
> +
> +    cmd = ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) |
> +            ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) |
> +            ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) |
> +            OGMA_GMAC_GAR_REG_GB);
> +
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_GAR,
> +                      cmd);
> +
> +    while ( ( ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GAR) &
> +              OGMA_GMAC_GAR_REG_GB)
> +            != 0) {
> +        ;
> +    }
> +    return (ogma_uint16)ogma_get_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_GDR);
> +
> +}
> +
> +ogma_uint16 ogma_get_phy_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 reg_addr
> +    )
> +{
> +    ogma_uint16 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL)
> +         || ( !ctrl_p->param.use_gmac_flag)
> +         || ( phy_addr >= 32)
> +         || ( reg_addr >= 32) ) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_phy_reg.\nPlease set valid argument.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr);
> +
> +
> +    return value;
> +}
> +
> +#if ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) )
> +static const struct {
> +    ogma_uint32 addr;
> +    ogma_char *name_p;
> +} ogma_gmac_mmc_reg_info[] = {
> +    {OGMA_GMAC_REG_ADDR_MMC_INTR_RX         , "MMC_INTR_RX"},
> +    {OGMA_GMAC_REG_ADDR_MMC_INTR_TX         , "MMC_INTR_TX"},
> +    {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX    , "MMC_INTR_MASK_RX"},
> +    {OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX    , "MMC_INTR_MASK_TX"},
> +    {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB     , "TXOCTETCOUNT_GB"},
> +    {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB     , "TXFRAMECOUNT_GB"},
> +    {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G , "TXBROADCASTFRAMES_G"},
> +    {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G , "TXMULTICASTFRAMES_G"},
> +    {OGMA_GMAC_REG_ADDR_TX64OCTETS_GB       , "TX64OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB  , "TX65TO127OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB , "TX128TO255OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB , "TX256TO511OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB, "TX512TO1023OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB, "TX1024TOMAXOCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB  , "TXUNICASTFRAMES_GB"},
> +    {OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB, "TXMULTICASTFRAMES_GB"},
> +    {OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB, "TXBROADCASTFRAMES_GB"},
> +    {OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR    , "TXUNDERFLOWERROR"},
> +    {OGMA_GMAC_REG_ADDR_TXSINGLECOL_G       , "TXSINGLECOL_G"},
> +    {OGMA_GMAC_REG_ADDR_TXMULTICOL_G        , "TXMULTICOL_G"},
> +    {OGMA_GMAC_REG_ADDR_TXDEFERRED          , "TXDEFERRED"},
> +    {OGMA_GMAC_REG_ADDR_TXLATECOL           , "TXLATECOL"},
> +    {OGMA_GMAC_REG_ADDR_TXEXESSCOL          , "TXEXESSCOL"},
> +    {OGMA_GMAC_REG_ADDR_TXCARRIERERRROR     , "TXCARRIERERRROR"},
> +    {OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G      , "TXOCTETCOUNT_G"},
> +    {OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G      , "TXFRAMECOUNT_G"},
> +    {OGMA_GMAC_REG_ADDR_TXEXECESSDEF        , "TXEXECESSDEF"},
> +    {OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES       , "TXPAUSEFRAMES"},
> +    {OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G      , "TXVLANFRAMES_G"},
> +    {OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB     , "RXFRAMECOUNT_GB"},
> +    {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB     , "RXOCTETCOUNT_GB"},
> +    {OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G      , "RXOCTETCOUNT_G"},
> +    {OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G , "RXBROADCASTFRAMES_G"},
> +    {OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G , "RXMULTICASTFRAMES_G"},
> +    {OGMA_GMAC_REG_ADDR_RXCRCERROR          , "RXCRCERROR"},
> +    {OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR   , "RXALLIGNMENTERROR"},
> +    {OGMA_GMAC_REG_ADDR_RXRUNTERROR         , "RXRUNTERROR"},
> +    {OGMA_GMAC_REG_ADDR_RXJABBERERROR       , "RXJABBERERROR"},
> +    {OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G       , "RXUNDERSIZE_G"},
> +    {OGMA_GMAC_REG_ADDR_RXOVERSIZE_G        , "RXOVERSIZE_G"},
> +    {OGMA_GMAC_REG_ADDR_RX64OCTETS_GB       , "RX64OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB  , "RX65TO127OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB , "RX128TO255OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB , "RX256TO511OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB, "RX512TO1023OCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB, "RX1024TOMAXOCTETS_GB"},
> +    {OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G   , "RXUNICASTFRAMES_G"},
> +    {OGMA_GMAC_REG_ADDR_RXLENGTHERROR       , "RXLENGTHERROR"},
> +    {OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE    , "RXOUTOFRANGETYPE"},
> +    {OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES       , "RXPAUSEFRAMES"},
> +    {OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW      , "RXFIFOOVERFLOW"},
> +    {OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB     , "RXVLANFRAMES_GB"},
> +    {OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR     , "RXWATCHDOGERROR"},
> +    {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX, "MMC_IPC_INTR_MASK_RX"},
> +    {OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX     , "MMC_IPC_INTR_RX"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS      , "RXIPV4_GD_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS  , "RXIPV4_HDRERR_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS   , "RXIPV4_NOPAY_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS    , "RXIPV4_FRAG_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS   , "RXIPV4_UDSBL_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS      , "RXIPV6_GD_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS  , "RXIPV6_HDRERR_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS   , "RXIPV6_NOPAY_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS       , "RXUDP_GD_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS      , "RXUDP_ERR_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS       , "RXTCP_GD_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS      , "RXTCP_ERR_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS      , "RXICMP_GD_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS     , "RXICMP_ERR_FRMS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS    , "RXIPV4_GD_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS, "RXIPV4_HDRERR_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS , "RXIPV4_NOPAY_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS  , "RXIPV4_FRAG_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS , "RXIPV4_UDSBL_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS    , "RXIPV6_GD_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS, "RXIPV6_HDRERR_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS , "RXIPV6_NOPAY_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS     , "RXUDP_GD_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS    , "RXUDP_ERR_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS     , "RXTCP_GD_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS    , "RXTCP_ERR_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS    , "RXICMP_GD_OCTETS"},
> +    {OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS   , "RXICMP_ERR_OCTETS"}
> +};
> +#endif /* ( defined(OGMA_CONFIG_USE_READ_GMAC_STAT) || defined(OGMA_CONFIG_USE_DUMP_GMAC_STAT) ) */
> +
> +#ifdef OGMA_CONFIG_USE_DUMP_GMAC_STAT
> +void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p)
> +{
> +
> +    ogma_uint i;
> +
> +    pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> +                "Dumping GMAC statistics registers(MMC registers):\n");
> +
> +    for (i = 0;
> +         i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0]);
> +         i++) {
> +        pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> +                    "  %s => 0x%08x\n",
> +                    ogma_gmac_mmc_reg_info[i].name_p,
> +                    ( unsigned long)ogma_get_mac_reg(ctrl_p,
> +                                                     ogma_gmac_mmc_reg_info[i].addr));
> +    }
> +
> +
> +    /* Reset all counters. */
> +    ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
> +
> +
> +}
> +
> +#endif /* OGMA_CONFIG_USE_DUMP_GMAC_STAT */
> +
> +
> +ogma_err_t ogma_get_gmac_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool *valid_flag_p,
> +    ogma_gmac_mode_t *gmac_mode_p,
> +    ogma_bool *rx_running_flag_p,
> +    ogma_bool *tx_running_flag_p
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( valid_flag_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( gmac_mode_p == NULL) ||
> +         ( rx_running_flag_p == NULL) ||
> +         ( tx_running_flag_p == NULL) ) {
> +        *valid_flag_p = OGMA_FALSE;
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        *valid_flag_p = OGMA_FALSE;
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +
> +    *valid_flag_p = ctrl_p->gmac_mode_valid_flag;
> +
> +    *rx_running_flag_p = ctrl_p->gmac_rx_running_flag;
> +    *tx_running_flag_p = ctrl_p->gmac_tx_running_flag;
> +
> +    pfdep_memcpy( ( void *)gmac_mode_p,
> +                  ( const void *)&ctrl_p->gmac_mode,
> +                  sizeof( ogma_gmac_mode_t) );
> +
> +
> +    return OGMA_ERR_OK;
> +
> +}
> +
> +static void ogma_set_phy_target_mmd_reg_addr (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr
> +    )
> +{
> +    ogma_uint32 cmd;
> +
> +    /* set MMD ADDR */
> +    cmd = ( ogma_uint32)dev_addr;
> +
> +    /*set command to MMD access control register */
> +    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
> +
> +    /* set MMD access address data register Write reg_addr */
> +    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr);
> +
> +    /* write value to MMD ADDR */
> +    cmd = ( (1U << 14) | dev_addr);
> +
> +    /* set command to MMD access control register */
> +    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd);
> +}
> +
> +static void ogma_set_phy_mmd_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr,
> +    ogma_uint16 value
> +    )
> +{
> +    /* set target mmd reg_addr */
> +    ogma_set_phy_target_mmd_reg_addr( ctrl_p,
> +                                      phy_addr,
> +                                      dev_addr,
> +                                      reg_addr);
> +
> +    /* Write value to MMD access address data register */
> +    ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, value);
> +
> +}
> +
> +static ogma_uint16 ogma_get_phy_mmd_reg_sub (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr
> +    )
> +{
> +    /* set target mmd reg_addr */
> +    ogma_set_phy_target_mmd_reg_addr( ctrl_p,
> +                                      phy_addr,
> +                                      dev_addr,
> +                                      reg_addr);
> +
> +    /* Read value for MMD access address data register */
> +    return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD);
> +}
> +
> +ogma_err_t ogma_set_gmac_lpictrl_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* set value tp LSIPCR Register */
> +    ogma_set_mac_reg( ctrl_p, OGMA_GMAC_REG_ADDR_LPICSR, value);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_get_gmac_lpictrl_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 *value_p
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( value_p == NULL) ){
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Read LSIPCR Register */
> +    *value_p = ogma_get_mac_reg( ctrl_p,
> +                                 OGMA_GMAC_REG_ADDR_LPICSR);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_set_gmac_lpitimer_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint16 ls_timer_ms,
> +    ogma_uint16 tw_timer_ms
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( ls_timer_ms > 1024U) {
> +        return OGMA_ERR_RANGE;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* make LPICTR value*/
> +    value = ( ( ( ogma_uint32)ls_timer_ms << OGMA_GMAC_LPITCR_REG_LIT) |
> +              ( tw_timer_ms << OGMA_GMAC_LPITCR_REG_TWT) );
> +
> +    /* Write timer value to LSIPCR Register */
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_LPITCR,
> +                      value);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_get_gmac_lpitimer_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint16 *ls_timer_ms_p,
> +    ogma_uint16 *tw_timer_ms_p
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ls_timer_ms_p == NULL) ||
> +         ( tw_timer_ms_p == NULL) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Read timer value for LSIPCR Register */
> +    value = ogma_get_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_LPITCR);
> +
> +    /* make ls_timer_ms value*/
> +    *ls_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_LIT) &
> +                                     OGMA_GMAC_LPITCR_REG_MASK_LIT);
> +
> +    /* make tw_timer_ms value*/
> +    *tw_timer_ms_p = ( ogma_uint16)( ( value >> OGMA_GMAC_LPITCR_REG_TWT) &
> +                                     OGMA_GMAC_LPITCR_REG_MASK_TWT);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +void ogma_set_phy_mmd_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr,
> +    ogma_uint16 value
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return;
> +    }
> +
> +    if ( ( phy_addr > 31U) ||
> +         ( dev_addr > 31U) ) {
> +        return;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return;
> +    }
> +
> +    ogma_set_phy_mmd_reg_sub ( ctrl_p,
> +                               phy_addr,
> +                               dev_addr,
> +                               reg_addr,
> +                               value);
> +
> +
> +    return;
> +}
> +
> +ogma_uint16 ogma_get_phy_mmd_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_uint8 dev_addr,
> +    ogma_uint16 reg_addr
> +    )
> +{
> +    ogma_uint16 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return 0;
> +    }
> +
> +    if ( ( phy_addr > 31U) ||
> +         ( dev_addr > 31U) ) {
> +        return 0;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return 0;
> +    }
> +
> +    value = ogma_get_phy_mmd_reg_sub ( ctrl_p,
> +                                       phy_addr,
> +                                       dev_addr,
> +                                       reg_addr);
> +
> +
> +    return value;
> +}
> +
> +ogma_err_t ogma_get_phy_link_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint8 phy_addr,
> +    ogma_phy_link_status_t *phy_link_status_p
> +    )
> +{
> +    ogma_uint32 value, tmp, exp;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( phy_link_status_p == NULL) ){
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( phy_addr >= 32) {
> +        return OGMA_ERR_RANGE;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) );
> +
> +    /* Read PHY CONTROL Register */
> +    tmp = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONTROL);
> +
> +    /* Read PHY STATUS Register */
> +    value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
> +
> +    /* check latched_link_down_flag */
> +    if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) == 0) {
> +        phy_link_status_p->latched_link_down_flag = OGMA_TRUE;
> +
> +        /* Read PHY STATUS Register */
> +        value = ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_STATUS);
> +
> +    }
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "CONTROL Register value %08x\n", tmp);
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "PHY STATUS register value %08x\n", value);
> +
> +    /* Check Current Link Status */
> +    if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) != 0 ) {
> +        phy_link_status_p->up_flag = OGMA_TRUE;
> +    }
> +
> +    /* check Auto-Negotiation Enable */
> +    if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE) ) != 0) &&
> +         ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY) ) != 0) ) {
> +        phy_link_status_p->auto_nego_enable_flag = OGMA_TRUE;
> +    }
> +
> +    /* Check Current Autonegotiation Complete Status */
> +    if ( phy_link_status_p->up_flag &&
> +         phy_link_status_p->auto_nego_enable_flag &&
> +         ( ( value & ( 1U << OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP) ) != 0) ) {
> +        phy_link_status_p->auto_nego_complete_flag = OGMA_TRUE;
> +    }
> +
> +    /* start Check Current Link Speed */
> +    if ( phy_link_status_p->up_flag) {
> +
> +        if ( phy_link_status_p->auto_nego_enable_flag == OGMA_FALSE) {
> +
> +            /* Speed check */
> +            if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) == 0) &&
> +                 ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) != 0) ) {
> +
> +                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
> +
> +            } else if ( ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB) ) != 0) &&
> +                        ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB) ) == 0) ) {
> +
> +                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
> +
> +            } else {
> +
> +                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
> +            }
> +
> +            /* Duplex check */
> +            if ( ( tmp & ( 1U << OGMA_PHY_CONTROL_REG_DUPLEX_MODE) ) == 0) {
> +
> +                phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> +            }
> +
> +        } else if ( phy_link_status_p->auto_nego_complete_flag == OGMA_TRUE) {
> +            /* case auto_nego_enable_flag TRUE && auto_nego_complete_flag TRUE */
> +
> +            /* Read MASTER-SLAVE Control Register */
> +            value = ogma_get_phy_reg_sub( ctrl_p,
> +                                          phy_addr,
> +                                          OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL);
> +
> +            /* Read MASTER-SLAVE Status Register */
> +            tmp = ogma_get_phy_reg_sub( ctrl_p,
> +                                        phy_addr,
> +                                        OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS);
> +
> +            /* Check Current Link Speed */
> +            if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_FULL) ) != 0) &&
> +                 ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_FULL) ) != 0) ) {
> +
> +                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
> +
> +            } else if ( ( ( value & ( 1U << OGMA_PHY_MSC_REG_1000BASE_HALF) ) != 0) &&
> +                        ( ( tmp & ( 1U << OGMA_PHY_MSS_REG_LP_1000BASE_HALF) ) != 0) ) {
> +
> +                phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_1G;
> +
> +                phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> +
> +            } else {
> +
> +                /* Read Auto-Negotiation Advertisement register */
> +                value = ogma_get_phy_reg_sub( ctrl_p,
> +                                              phy_addr,
> +                                              OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY);
> +
> +                /* Read Auto-Negotiation Link Partner Base Page Ability register */
> +                tmp = ogma_get_phy_reg_sub( ctrl_p,
> +                                             phy_addr,
> +                                             OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY);
> +
> +                value = ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) &
> +                          OGMA_PHY_ANA_REG_TAF_MASK);
> +
> +                pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                             "TAF value %08x\n", value);
> +
> +                if ( value & OGMA_PHY_TAF_REG_100BASE_FULL) { /* 100M full */
> +
> +                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
> +
> +                } else if ( value & OGMA_PHY_TAF_REG_100BASE_HALF) { /* 100M half */
> +
> +                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_100M;
> +
> +                    phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> +
> +                } else if ( value & OGMA_PHY_TAF_REG_10BASE_FULL) { /* 10M full */
> +
> +                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
> +
> +                } else { /* value = OGMA_PHY_TAF_REG_10BASE_HALF 10M Half */
> +
> +                    phy_link_status_p->link_speed = OGMA_PHY_LINK_SPEED_10M;
> +
> +                    phy_link_status_p->half_duplex_flag = OGMA_TRUE;
> +                }
> +
> +            }
> +        }
> +    } /* End Check Current Link Speed */
> +
> +    /* Check LPI Capable */
> +    if ( phy_link_status_p->up_flag &&
> +         phy_link_status_p->auto_nego_complete_flag &&
> +         phy_link_status_p->link_speed != OGMA_PHY_LINK_SPEED_10M &&
> +         phy_link_status_p->half_duplex_flag == OGMA_FALSE &&
> +         ctrl_p->param.gmac_config.phy_interface != OGMA_PHY_INTERFACE_RMII) {
> +
> +        /* Read EEE advertisement register */
> +        value = ogma_get_phy_mmd_reg_sub( ctrl_p,
> +                                          phy_addr,
> +                                          OGMA_PHY_DEV_ADDR_AUTO_NEGO,
> +                                          OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE);
> +
> +        /* Read EEE link partner ability register */
> +        tmp = ogma_get_phy_mmd_reg_sub( ctrl_p,
> +                                        phy_addr,
> +                                        OGMA_PHY_DEV_ADDR_AUTO_NEGO,
> +                                        OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY);
> +
> +        exp = ( ( phy_link_status_p->link_speed == OGMA_PHY_LINK_SPEED_1G) ?
> +                OGMA_PHY_AUTO_NEGO_1000BASE_EEE:
> +                OGMA_PHY_AUTO_NEGO_100BASE_EEE);
> +
> +        /* Check EEE Advertise and EEE LP Ability */
> +        if ( ( value & tmp & exp) != 0 ) {
> +            phy_link_status_p->lpi_capable_flag = OGMA_TRUE;
> +        }
> +
> +        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                     "EEE advertisement register        value %08x\n",
> +                     value);
> +
> +        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                     "EEE link partner ability register value %08x\n",
> +                     tmp);
> +
> +        pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                     "EEE LPI EXP                       value %08x\n",
> +                     exp);
> +    }
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "phy_link_status_p->latched_link_down_flag %u\n",
> +                 phy_link_status_p->latched_link_down_flag);
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "phy_link_status_p->up_flag %u\n",
> +                 phy_link_status_p->up_flag);
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "phy_link_status_p->auto_nego_enable_flag %u\n",
> +                 phy_link_status_p->auto_nego_enable_flag);
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "phy_link_status_p->auto_nego_complete_flag %u\n",
> +                 phy_link_status_p->auto_nego_complete_flag);
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "phy_link_status_p->link_speed %u\n",
> +                 phy_link_status_p->link_speed);
> +
> +    pfdep_print( PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED,
> +                 "phy_link_status_p->lpi_capable_flag %u\n",
> +                 phy_link_status_p->lpi_capable_flag);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return gmac_int_sbd_regs;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return gmac_int_sbd_regs;
> +    }
> +
> +    /* Read IER register */
> +    gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
> +                                               OGMA_GMAC_REG_ADDR_IER);
> +    /* Read IMR register */
> +    gmac_int_sbd_regs.extended = ( ( ~( ogma_get_mac_reg( ctrl_p,
> +                                                          OGMA_GMAC_REG_ADDR_IMR) ) ) &
> +                                   OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
> +
> +
> +
> +    return gmac_int_sbd_regs;
> +}
> +
> +ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status_non_clear (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    )
> +{
> +    ogma_gmac_int_sbd_regs_t gmac_int_sbd_regs = {0};
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return gmac_int_sbd_regs;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return gmac_int_sbd_regs;
> +    }
> +
> +    /* Read SR register */
> +    gmac_int_sbd_regs.base = ogma_get_mac_reg( ctrl_p,
> +                                               OGMA_GMAC_REG_ADDR_SR);
> +
> +    /* Read ISR register */
> +    gmac_int_sbd_regs.extended = ogma_get_mac_reg( ctrl_p,
> +                                                   OGMA_GMAC_REG_ADDR_ISR);
> +
> +    if ( mask_flag) {
> +
> +        /* Read IER register */
> +        gmac_int_sbd_regs.base &= ( ogma_get_mac_reg( ctrl_p,
> +                                                      OGMA_GMAC_REG_ADDR_IER) |
> +                                    ( ~OGMA_GMAC_INT_SBD_IRQ_IER_ALL) );
> +        /* Read IMR register */
> +        gmac_int_sbd_regs.extended &= ( ( ~( ogma_get_mac_reg( ctrl_p,
> +                                                               OGMA_GMAC_REG_ADDR_IMR) ) ) &
> +                                        OGMA_GMAC_INT_SBD_IRQ_ISR_ALL);
> +    }
> +
> +
> +    return gmac_int_sbd_regs;
> +}
> +
> +ogma_err_t ogma_clear_gmac_int_sbd_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_gmac_int_sbd_regs_t int_sbd_regs
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Write Clear SR register */
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_SR,
> +                      ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL) );
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_enable_gmac_int_sbd_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_gmac_int_sbd_regs_t int_sbd_regs
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Read IER register for No Change Value Keep */
> +    value = ogma_get_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_IER);
> +    /* Write IER register */
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_IER,
> +                      ( value | ( int_sbd_regs.base & OGMA_GMAC_INT_SBD_IRQ_IER_ALL) ) );
> +
> +    /* Read IMR register for No Change Value Keep */
> +    value = ogma_get_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_IMR);
> +    /* Write IMR register */
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_IMR,
> +                      ( value & ( ~( int_sbd_regs.extended &
> +                                     OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) ) );
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_disable_gmac_int_sbd_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_gmac_int_sbd_regs_t int_sbd_regs
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Read IER register for No Change Value Keep */
> +    value = ogma_get_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_IER);
> +    /* Write IER register */
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_IER,
> +                      ( value & ( ~(int_sbd_regs.base) ) ) );
> +
> +    /* Read IMR register for No Change Value Keep */
> +    value = ogma_get_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_IMR);
> +    /* Write IMR register */
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_IMR,
> +                      ( value | ( int_sbd_regs.extended &
> +                                  OGMA_GMAC_INT_SBD_IRQ_ISR_ALL) ) );
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_get_gmac_rgmii_status_reg (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 *value_p
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( value_p == NULL) ){
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->param.use_gmac_flag) {
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Read RGMII Status Register */
> +    *value_p = ogma_get_mac_reg( ctrl_p,
> +                                 OGMA_GMAC_REG_ADDR_RSR);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +#ifdef OGMA_CONFIG_USE_READ_GMAC_STAT
> +ogma_err_t ogma_read_gmac_stat (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 *value_p,
> +    ogma_bool reset_flag
> +    )
> +{
> +
> +    ogma_uint i;
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( value_p == NULL) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +
> +    for ( i = 0;
> +          i < sizeof(ogma_gmac_mmc_reg_info)/sizeof(ogma_gmac_mmc_reg_info[0] );
> +          i++) {
> +
> +        value_p[i] = ogma_get_mac_reg(ctrl_p,
> +                                      ogma_gmac_mmc_reg_info[i].addr);
> +    }
> +
> +    if ( reset_flag) {
> +        /* Reset all counters. */
> +        ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
> +    }
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +#endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */
> +
> +ogma_err_t ogma_reset_gmac_stat (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +
> +    /* Reset all counters. */
> +    ogma_set_mac_reg(ctrl_p, OGMA_GMAC_REG_ADDR_MMC_CNTL, 1);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_softreset_gmac (
> +    ogma_ctrl_t *ctrl_p
> +    )
> +{
> +    ogma_uint32 value;
> +    pfdep_err_t pfdep_err;
> +
> +    /* F_GMAC4MT soft reset*/
> +    ogma_set_mac_reg( ctrl_p,
> +                      OGMA_GMAC_REG_ADDR_BMR,
> +                      OGMA_GMAC_BMR_REG_RESET);
> +    /* Wait soft reset */
> +    pfdep_err = pfdep_msleep( 1);
> +
> +    if ( pfdep_err == PFDEP_ERR_INTERRUPT) {
> +
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "Wait for BMR soft reset error.\n");
> +
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    /* Read F_GMAC4MT BMR */
> +    value = ogma_get_mac_reg( ctrl_p,
> +                              OGMA_GMAC_REG_ADDR_BMR);
> +
> +    /* check software reset result*/
> +    if ( value & OGMA_GMAC_BMR_REG_SWR) {
> +        return OGMA_ERR_AGAIN;
> +    }
> +
> +    return OGMA_ERR_OK;
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
> new file mode 100644
> index 000000000000..e2e25c71abaa
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h
> @@ -0,0 +1,210 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_INTERNAL_H
> +#define OGMA_INTERNAL_H
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
> +#include "ogma_reg.h"
> +#include "pfdep.h"
> +
> +/* Just a million to prevent typing errors. */
> +#define OGMA_CLK_MHZ (1000000)
> +
> +#define OGMA_INSTANCE_NUM_MAX 1
> +
> +#define OGMA_RX_PKT_BUF_LEN 1522
> +#define OGMA_RX_JUMBO_PKT_BUF_LEN 9022
> +#define OGMA_DUMMY_DESC_ENTRY_LEN 48
> +
> +#define OGMA_REG_ADDR_CLK_EN OGMA_REG_ADDR_CLK_EN_0
> +
> +extern const ogma_uint32 desc_ring_irq_inten_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
> +extern const ogma_uint32 desc_ring_irq_inten_set_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
> +extern const ogma_uint32 desc_ring_irq_inten_clr_reg_addr[OGMA_DESC_RING_ID_MAX + 1];
> +extern const ogma_uint32 ogma_desc_start_reg_addr[OGMA_DESC_RING_ID_MAX+1];
> +
> +typedef struct ogma_ctrl_s ogma_ctrl_t;
> +typedef struct ogma_desc_ring_s ogma_desc_ring_t;
> +typedef struct ogma_clk_ctrl_s ogma_clk_ctrl_t;
> +typedef union ogma_desc_entry_priv_u ogma_desc_entry_priv_t;
> +
> +struct ogma_clk_ctrl_s{
> +    ogma_uint8 mac_req_num;
> +};
> +
> +
> +struct ogma_desc_ring_s{
> +
> +    ogma_desc_ring_id_t ring_id;
> +
> +    ogma_desc_ring_param_t param;
> +
> +    ogma_uint rx_desc_ring_flag:1;
> +
> +    ogma_uint tx_desc_ring_flag:1;
> +
> +    ogma_uint running_flag:1;
> +
> +    ogma_uint full_flag:1;
> +
> +    ogma_uint8 desc_entry_len;
> +
> +    ogma_uint16 head_idx;
> +
> +    ogma_uint16 tail_idx;
> +
> +    ogma_uint16 rx_num;
> +
> +    ogma_uint16 tx_done_num;
> +
> +    pfdep_hard_lock_t inten_reg_hard_lock;
> +
> +    pfdep_soft_lock_t soft_lock;
> +
> +    void *desc_ring_cpu_addr;
> +
> +    pfdep_phys_addr_t desc_ring_phys_addr;
> +
> +    ogma_frag_info_t *frag_info_p;
> +
> +    ogma_desc_entry_priv_t *priv_data_p;
> +};
> +
> +struct ogma_ctrl_s{
> +    ogma_ctrl_t *next_p;
> +
> +    ogma_uint core_enabled_flag:1;
> +
> +    ogma_uint gmac_rx_running_flag:1;
> +
> +    ogma_uint gmac_tx_running_flag:1;
> +
> +    ogma_uint gmac_mode_valid_flag:1;
> +
> +    ogma_uint normal_desc_ring_valid:1;
> +
> +    void *base_addr;
> +
> +    pfdep_dev_handle_t dev_handle;
> +
> +    ogma_param_t param;
> +
> +    ogma_clk_ctrl_t clk_ctrl;
> +
> +    ogma_uint32 rx_pkt_buf_len;
> +
> +    ogma_desc_ring_t desc_ring[OGMA_DESC_RING_ID_MAX+1];
> +
> +    ogma_gmac_mode_t gmac_mode;
> +
> +    pfdep_hard_lock_t inten_reg_hard_lock;
> +
> +    pfdep_hard_lock_t clk_ctrl_hard_lock;
> +
> +    void *dummy_desc_entry_addr;
> +
> +    pfdep_phys_addr_t dummy_desc_entry_phys_addr;
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +    /**
> +     * Statistics information.
> +     *
> +     * Note: Since mutual access exclusion is omitted,
> +     *       these values might be inaccurate.
> +     */
> +    ogma_stat_info_t stat_info;
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +};
> +
> +union ogma_desc_entry_priv_u{
> +    pfdep_pkt_handle_t pkt_handle;
> +};
> +
> +/*****************************************************************
> + *****************************************************************
> + *****************************************************************/
> +
> +/**
> + *
> + */
> +ogma_err_t ogma_alloc_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_id_t ring_idx
> +    );
> +/**
> + *
> + */
> +void ogma_free_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +/**
> + *
> + */
> +ogma_err_t ogma_setup_rx_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +/**
> + *
> + */
> +void ogma_uninit_pkt_desc_ring (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_desc_ring_t *desc_ring_p
> +    );
> +
> +/**
> + *
> + */
> +void ogma_push_clk_req (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 domain
> +    );
> +
> +void ogma_pop_clk_req(
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 domain
> +    );
> +
> +
> +ogma_err_t ogma_softreset_gmac (
> +    ogma_ctrl_t *ctrl_p
> +    );
> +
> +#ifdef OGMA_CONFIG_CHECK_CLK_SUPPLY
> +#include "ogma_basic_access.h"
> +/*include for ogma_read_reg*/
> +static __inline void ogma_check_clk_supply (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 domain
> +    )
> +{
> +    ogma_uint32 value;
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN);
> +
> +    pfdep_assert( ( ( value & domain ) == domain) );
> +}
> +
> +#else
> +
> +#define ogma_check_clk_supply( ctrl_p, domain)
> +
> +#endif /* OGMA_CONFIG_CHECK_CLK_SUPPLY */
> +
> +#endif /* OGMA_INTERNAL_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
> new file mode 100644
> index 000000000000..3c54c63126a7
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c
> @@ -0,0 +1,1385 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "ogma_config.h"
> +#include "ogma_internal.h"
> +#include "ogma_basic_access.h"
> +#include "ogma_misc_internal.h"
> +
> +#include <Library/IoLib.h>
> +
> +ogma_global_t ogma_global = {
> +    OGMA_FALSE,
> +    0,
> +    NULL
> +};
> +
> +
> +static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
> +static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
> +
> +static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> +    OGMA_REG_ADDR_NRM_TX_STATUS,
> +    OGMA_REG_ADDR_NRM_RX_STATUS,
> +};
> +
> +static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
> +    OGMA_REG_ADDR_NRM_TX_CONFIG,
> +    OGMA_REG_ADDR_NRM_RX_CONFIG,
> +
> +};
> +
> +
> +/* Internal function definition*/
> +#ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
> +STATIC void ogma_set_clk_en_reg (
> +    ogma_ctrl_t *ctrl_p
> +    );
> +#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
> +STATIC void ogma_global_init ( void);
> +
> +STATIC ogma_err_t ogma_probe_hardware (
> +    void *base_addr
> +    );
> +
> +STATIC void ogma_reset_hardware (
> +    ogma_ctrl_t *ctrl_p
> +    );
> +
> +STATIC void ogma_set_microcode(
> +    ogma_ctrl_t *ctrl_p,
> +    const void *dma_hm_mc_addr,
> +    ogma_uint32 dma_hm_mc_len,
> +    const void *dma_mh_mc_addr,
> +    ogma_uint32 dma_mh_mc_len,
> +    const void *pktc_mc_addr,
> +    ogma_uint32 pktc_mc_len
> +    );
> +
> +STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
> +    const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
> +    );
> +
> +STATIC void ogma_internal_terminate (
> +    ogma_ctrl_t *ctrl_p
> +    );
> +
> +#ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
> +
> +#define ogma_set_clk_en_reg( ctrl_p)
> +
> +#else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
> +STATIC void ogma_set_clk_en_reg (
> +    ogma_ctrl_t *ctrl_p
> +    )
> +{
> +    ogma_uint32 value = 0;
> +
> +    if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
> +        value |= OGMA_CLK_EN_REG_DOM_G;
> +    }
> +
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
> +}
> +#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
> +
> +void ogma_push_clk_req (
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 domain
> +    )
> +{
> +    pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
> +
> +    pfdep_acquire_hard_lock (
> +        &ctrl_p->clk_ctrl_hard_lock,
> +        &clk_ctrl_hard_lock_ctx);
> +
> +    if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
> +        ++ctrl_p->clk_ctrl.mac_req_num;
> +    }
> +
> +    ogma_set_clk_en_reg( ctrl_p);
> +
> +    pfdep_release_hard_lock(
> +        &ctrl_p->clk_ctrl_hard_lock,
> +        &clk_ctrl_hard_lock_ctx);
> +}
> +
> +void ogma_pop_clk_req(
> +    ogma_ctrl_t *ctrl_p,
> +    ogma_uint32 domain
> +    )
> +{
> +    pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
> +
> +    pfdep_acquire_hard_lock(
> +        &ctrl_p->clk_ctrl_hard_lock,
> +        &clk_ctrl_hard_lock_ctx);
> +
> +    if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
> +        --ctrl_p->clk_ctrl.mac_req_num;
> +    }
> +
> +    ogma_set_clk_en_reg( ctrl_p);
> +
> +    pfdep_release_hard_lock(
> +        &ctrl_p->clk_ctrl_hard_lock,
> +        &clk_ctrl_hard_lock_ctx);
> +}
> +
> +/* Internal function */
> +STATIC void ogma_global_init ( void)
> +{
> +    ogma_global.valid_flag = OGMA_TRUE;
> +}
> +
> +STATIC ogma_err_t ogma_probe_hardware (
> +    void *base_addr
> +    )
> +{
> +
> +    ogma_uint32 value;
> +
> +    /* Read HW_VER Register */
> +    value = pfdep_iomem_read((void *)
> +                             ((pfdep_cpu_addr_t)base_addr +
> +                              (OGMA_REG_ADDR_HW_VER << 2)));
> +
> +    if ( value != OGMA_VER_NETSEC) {
> +        pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
> +                    "Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
> +                    (unsigned int)value,
> +                    (unsigned int)OGMA_VER_NETSEC);
> +    }
> +
> +    if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
> +        pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
> +                    "Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
> +                    (unsigned int)OGMA_VER_MAJOR_NUM(value),
> +                    (unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Print hardware version information. */
> +    pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> +                "NETSEC found. Hardware version: %08x\n",
> +                value);
> +
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +STATIC void ogma_reset_hardware (
> +    ogma_ctrl_t *ctrl_p
> +    )
> +{
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_CLK_EN,
> +                    OGMA_CLK_EN_REG_DOM_ALL);
> +
> +
> +    /*
> +     * Stop dma engines if cores are enabled
> +     */
> +    if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
> +
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_DMA_HM_CTRL,
> +                        OGMA_DMA_CTRL_REG_STOP);
> +
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_DMA_MH_CTRL,
> +                        OGMA_DMA_CTRL_REG_STOP);
> +
> +        while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
> +                  & OGMA_DMA_CTRL_REG_STOP) != 0) {
> +            ;
> +        }
> +
> +        while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
> +                  & OGMA_DMA_CTRL_REG_STOP) != 0) {
> +            ;
> +        }
> +    }
> +
> +    if ( ctrl_p->param.use_gmac_flag) {
> +
> +        /* Reset F_GMAC4MT */
> +        ogma_set_mac_reg( ctrl_p,
> +                          OGMA_GMAC_REG_ADDR_BMR,
> +                          OGMA_GMAC_BMR_REG_RESET);
> +
> +    }
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_SOFT_RST,
> +                    OGMA_SOFT_RST_REG_RESET);
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_SOFT_RST,
> +                    OGMA_SOFT_RST_REG_RUN);
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_COM_INIT,
> +                    OGMA_COM_INIT_REG_ALL);
> +
> +    while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
> +        ;
> +    }
> +
> +    if ( ctrl_p->param.use_gmac_flag) {
> +
> +
> +        /* MAC desc init */
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_MAC_DESC_INIT,
> +                        OGMA_MAC_DESC_INIT_REG_INIT);
> +
> +        /* Wait MAC desc init done */
> +        while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
> +                  & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
> +            ;
> +        }
> +
> +
> +        /* set MAC_INTF_SEL */
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_MAC_INTF_SEL,
> +                        ctrl_p->param.gmac_config.phy_interface);
> +
> +
> +    }
> +}
> +
> +#define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
> +
> +STATIC void ogma_set_microcode (
> +    ogma_ctrl_t *ctrl_p,
> +    const void *dma_hm_mc_addr,
> +    ogma_uint32 dma_hm_mc_len,
> +    const void *dma_mh_mc_addr,
> +    ogma_uint32 dma_mh_mc_len,
> +    const void *pktc_mc_addr,
> +    ogma_uint32 pktc_mc_len
> +    )
> +{
> +    ogma_uint i;
> +
> +    const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
> +    const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
> +    const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
> +
> +    /* Loads microcodes to microengines. */
> +    for( i = 0; i < dma_hm_mc_len; i++) {
> +        UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
> +                        data );
> +        dmac_hm_cmd_data++;
> +    }
> +
> +    for( i = 0; i < dma_mh_mc_len; i++) {
> +        UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
> +                        data );
> +        dmac_mh_cmd_data++;
> +    }
> +
> +    for( i = 0; i < pktc_mc_len; i++) {
> +        UINT32 data = MmioRead32((UINTN)core_cmd_data);
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_PKTC_CMD_BUF,
> +                        data );
> +        core_cmd_data++;
> +    }
> +
> +}
> +
> +STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
> +    const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
> +    )
> +{
> +    ogma_uint32 param = 0;
> +
> +    if ( pkt_ctrl_param_p->log_chksum_er_flag) {
> +        param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
> +    }
> +
> +    if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
> +        param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
> +    }
> +
> +    if ( pkt_ctrl_param_p->log_hd_er_flag) {
> +        param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
> +    }
> +
> +    if ( pkt_ctrl_param_p->drp_no_match_flag) {
> +        param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
> +    }
> +
> +    return param;
> +}
> +
> +ogma_err_t ogma_init (
> +    void *base_addr,
> +    pfdep_dev_handle_t dev_handle,
> +    const ogma_param_t *param_p,
> +    const void *dma_hm_mc_addr,
> +    ogma_uint32 dma_hm_mc_len,
> +    const void *dma_mh_mc_addr,
> +    ogma_uint32 dma_mh_mc_len,
> +    const void *pktc_mc_addr,
> +    ogma_uint32 pktc_mc_len,
> +    ogma_handle_t *ogma_handle_p
> +    )
> +{
> +    ogma_int i;
> +    ogma_uint32 domain = 0, value;
> +    ogma_err_t ogma_err;
> +    ogma_ctrl_t *ctrl_p = NULL;
> +
> +    ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
> +    ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
> +
> +    ogma_bool all_lock_init_done_flag = OGMA_FALSE;
> +
> +    pfdep_err_t pfdep_err;
> +
> +    if ( ( param_p == NULL) ||
> +         ( ogma_handle_p == NULL) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
> +        return OGMA_ERR_INVALID;
> +    }
> +
> +    if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
> +        (! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Please set invalid packet desc_ring_param valid_flag.\n");
> +        return OGMA_ERR_DATA;
> +    }
> +
> +    if ( param_p->use_gmac_flag) {
> +        if ( ( param_p->gmac_config.phy_interface !=
> +              OGMA_PHY_INTERFACE_GMII) &&
> +            ( param_p->gmac_config.phy_interface !=
> +              OGMA_PHY_INTERFACE_RGMII) &&
> +            ( param_p->gmac_config.phy_interface !=
> +              OGMA_PHY_INTERFACE_RMII) ) {
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "An error occurred at ogma_init.\n"
> +                         "Please set phy_interface to valid value.\n");
> +            return OGMA_ERR_DATA;
> +        }
> +    } else {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Please set use_gmac_flag OGMA_TRUE.\n");
> +        return OGMA_ERR_DATA;
> +    }
> +
> +    ogma_err = ogma_probe_hardware( base_addr);
> +
> +    if ( ogma_err != OGMA_ERR_OK) {
> +        return ogma_err;
> +    }
> +
> +    if ( !ogma_global.valid_flag) {
> +        ogma_global_init();
> +    }
> +
> +    if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Failed to ogma_handle memory allocation.\n");
> +        return OGMA_ERR_ALLOC;
> +    }
> +
> +    pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
> +
> +    ctrl_p->base_addr = base_addr;
> +
> +    ctrl_p->dev_handle = dev_handle;
> +
> +    pfdep_memcpy( ( void *)&ctrl_p->param,
> +                  ( void *)param_p,
> +                  sizeof( ogma_param_t) );
> +
> +    /* Initialize hardware lock */
> +    pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
> +    if ( pfdep_err != PFDEP_ERR_OK) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Failed to inten_reg_hard_lock's initialization.\n");
> +       ogma_err = OGMA_ERR_ALLOC;
> +       goto err;
> +    }
> +    inten_reg_hard_lock_init_flag = OGMA_TRUE;
> +
> +    pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
> +    if ( pfdep_err != PFDEP_ERR_OK) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Failed to clk_ctrl_hard_lock's initialization.\n");
> +        ogma_err = OGMA_ERR_ALLOC;
> +        goto err;
> +    }
> +    clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
> +
> +    all_lock_init_done_flag = OGMA_TRUE;
> +
> +    pfdep_err = pfdep_dma_malloc( dev_handle,
> +                                  OGMA_DUMMY_DESC_ENTRY_LEN,
> +                                  &ctrl_p->dummy_desc_entry_addr,
> +                                  &ctrl_p->dummy_desc_entry_phys_addr);
> +
> +    if ( pfdep_err != PFDEP_ERR_OK) {
> +        ogma_err = OGMA_ERR_ALLOC;
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Failed to dummy_desc_entry's memory allocation.\n");
> +        goto err;
> +    }
> +
> +    /* clear dummy desc entry */
> +    pfdep_memset( ctrl_p->dummy_desc_entry_addr,
> +                  0,
> +                  OGMA_DUMMY_DESC_ENTRY_LEN);
> +
> +    ogma_reset_hardware( ctrl_p);
> +
> +    if ( param_p->use_gmac_flag) {
> +        domain |= OGMA_CLK_EN_REG_DOM_G;
> +    }
> +
> +    ogma_push_clk_req( ctrl_p, domain);
> +
> +    /* set PKT_CTRL */
> +    value = ogma_calc_pkt_ctrl_reg_param( &param_p->pkt_ctrl_param);
> +
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_PKT_CTRL,
> +                    value);
> +
> +    if ( param_p->use_jumbo_pkt_flag) {
> +
> +        ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
> +
> +        value = ogma_read_reg( ctrl_p,
> +                               OGMA_REG_ADDR_PKT_CTRL);
> +
> +        value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
> +
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_PKT_CTRL,
> +                        value);
> +    } else {
> +
> +        ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
> +
> +    }
> +
> +    /* set pkt desc ring config */
> +    for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
> +        if (  ctrl_p->param.desc_ring_param[i].valid_flag) {
> +            value =
> +                ( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
> +                  OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
> +                ( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
> +                  OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
> +
> +            ogma_write_reg( ctrl_p,
> +                            desc_ring_config_reg_addr[i],
> +                            value);
> +
> +        }
> +    }
> +
> +    /* set microengines */
> +    ogma_set_microcode(ctrl_p,
> +                       dma_hm_mc_addr,
> +                       dma_hm_mc_len,
> +                       dma_mh_mc_addr,
> +                       dma_mh_mc_len,
> +                       pktc_mc_addr,
> +                       pktc_mc_len);
> +
> +    /* alloc desc_ring*/
> +    for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
> +        ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
> +        if ( ogma_err != OGMA_ERR_OK) {
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "An error occurred at ogma_init.\n"
> +                         "Failed to ring id NO.%d memory allocation.\n",
> +                         i);
> +            goto err;
> +        }
> +    }
> +
> +    if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
> +        if ( ( ogma_err = ogma_setup_rx_desc_ring(
> +                   ctrl_p,
> +                   &ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
> +             != OGMA_ERR_OK) {
> +            pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                         "An error occurred at ogma_init.\n"
> +                         "Failed to NRM_RX packet memory allocation.\n");
> +            goto err;
> +        }
> +    }
> +
> +    /* microengines need domain G */
> +    ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> +    /* set DMA tmr ctrl*/
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
> +                    ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
> +
> +    /* start microengines */
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
> +
> +    if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Failed to waiting for microcode initialize end.\n");
> +        ogma_err = OGMA_ERR_INTERRUPT;
> +        goto err;
> +    }
> +
> +    /* check microcode load end & start core */
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
> +
> +    if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_init.\n"
> +                     "Failed to microcode loading.\n");
> +        ogma_err = OGMA_ERR_INVALID;
> +        goto err;
> +    }
> +
> +    /* clear microcode load end status */
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
> +                    OGMA_TOP_IRQ_REG_ME_START);
> +
> +    ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
> +
> +    ctrl_p->core_enabled_flag = OGMA_TRUE;
> +
> +    ctrl_p->next_p = ogma_global.list_head_p;
> +
> +    ogma_global.list_head_p = ctrl_p;
> +
> +    ++ogma_global.list_entry_num;
> +
> +    *ogma_handle_p = ctrl_p;
> +
> +#if 1
> +    {
> +
> +#define OGMA_PKT_CTRL_REG_MODE_TAIKI        (1UL << 28)
> +#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
> +#define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL <<  4)
> +#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
> +
> +        /* Read Pkt ctrl register */
> +        value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
> +        value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
> +
> +        /* change to noromal mode */
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_DMA_MH_CTRL,
> +                        OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
> +
> +        ogma_write_reg( ctrl_p,
> +                        OGMA_REG_ADDR_PKT_CTRL,
> +                        value);
> +
> +        while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
> +                OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
> +            ;
> +        }
> +
> +    }
> +#endif
> +
> +    /* Print microcode version information. */
> +    pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
> +                "Microcode version: %08x\n",
> +                ogma_read_reg( ctrl_p,
> +                               mc_ver_reg_addr) );
> +
> +    return OGMA_ERR_OK;
> +
> +err:
> +    if ( !all_lock_init_done_flag) {
> +
> +
> +        if ( clk_ctrl_hard_lock_init_flag) {
> +            pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
> +        }
> +
> +        if ( inten_reg_hard_lock_init_flag) {
> +            pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
> +        }
> +
> +    } else {
> +
> +        ogma_internal_terminate( ctrl_p);
> +
> +    }
> +
> +    pfdep_free( ctrl_p);
> +
> +    return ogma_err;
> +}
> +
> +STATIC void ogma_internal_terminate (
> +    ogma_ctrl_t *ctrl_p
> +    )
> +{
> +    ogma_int i;
> +
> +    ogma_reset_hardware( ctrl_p);
> +
> +    /* free desc_ring */
> +    for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
> +        ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
> +    }
> +
> +    if ( ctrl_p->dummy_desc_entry_addr != NULL) {
> +        pfdep_dma_free( ctrl_p->dev_handle,
> +                        OGMA_DUMMY_DESC_ENTRY_LEN,
> +                        ctrl_p->dummy_desc_entry_addr,
> +                        ctrl_p->dummy_desc_entry_phys_addr);
> +    }
> +
> +    pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
> +
> +
> +    pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
> +
> +}
> +
> +void ogma_terminate (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
> +    ogma_uint32 domain = 0;
> +
> +    if ( ( ctrl_p == NULL) ||
> +         ( ogma_global.list_entry_num == 0) ) {
> +       return;
> +    }
> +
> +    pfdep_assert( ogma_global.list_head_p != NULL);
> +
> +    if ( ctrl_p->param.use_gmac_flag) {
> +        domain |= OGMA_CLK_EN_REG_DOM_G;
> +    }
> +
> +    /* pop domain clock */
> +    ogma_pop_clk_req( ctrl_p, domain);
> +
> +    tmp_ctrl_p = ogma_global.list_head_p;
> +
> +    while(1) {
> +        if ( tmp_ctrl_p == NULL) {
> +            /* Could not found ctrl_p specified from the list */
> +            return;
> +        }
> +        if ( ctrl_p == tmp_ctrl_p) {
> +            if ( old_tmp_ctrl_p != NULL) {
> +                old_tmp_ctrl_p->next_p = ctrl_p->next_p;
> +            } else {
> +                ogma_global.list_head_p = ctrl_p->next_p;
> +            }
> +            break;
> +        }
> +        old_tmp_ctrl_p = tmp_ctrl_p;
> +        tmp_ctrl_p = tmp_ctrl_p->next_p;
> +    }
> +
> +    ogma_internal_terminate( ctrl_p);
> +
> +    --ogma_global.list_entry_num;
> +
> +    pfdep_free( ctrl_p);
> +    return;
> +}
> +
> +ogma_err_t ogma_enable_top_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* set irq_factor*/
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_disable_top_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* clear irq_factor*/
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_err_t ogma_enable_desc_ring_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    ogma_desc_ring_t *desc_ring_p;
> +
> +    pfdep_err_t pfdep_err;
> +    pfdep_soft_lock_ctx_t soft_lock_ctx;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_enable_desc_ring_irq.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_enable_desc_ring_irq.\n"
> +                     "Please select ring id number between 0 and %d.\n",
> +                     OGMA_DESC_RING_ID_MAX);
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_enable_desc_ring_irq.\n"
> +                     "Please select valid desc ring.\n");
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    desc_ring_p = &ctrl_p->desc_ring[ring_id];
> +
> +    /* get soft lock */
> +    pfdep_err = pfdep_acquire_soft_lock (
> +        &desc_ring_p->soft_lock,
> +        &soft_lock_ctx);
> +
> +    if ( pfdep_err != PFDEP_ERR_OK) {
> +        return OGMA_ERR_INTERRUPT;
> +    }
> +
> +    if ( !desc_ring_p->running_flag) {
> +        pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                                 &soft_lock_ctx);
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_enable_desc_ring_irq.\n"
> +                     "Please select running desc ring.\n");
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* set irq_factor*/
> +    ogma_write_reg( ctrl_p,
> +                    desc_ring_irq_inten_set_reg_addr[ring_id],
> +                    irq_factor);
> +
> +    /* free soft_lock*/
> +    pfdep_release_soft_lock( &desc_ring_p->soft_lock,
> +                             &soft_lock_ctx);
> +    return ogma_err;
> +}
> +
> +ogma_err_t ogma_disable_desc_ring_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_disable_desc_ring_irq.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_disable_desc_ring_irq.\n"
> +                     "Please select ring id number between 0 and %d.\n",
> +                     OGMA_DESC_RING_ID_MAX);
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_disable_desc_ring_irq.\n"
> +                     "Please select valid desc ring.\n");
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Clear irq factor*/
> +    ogma_write_reg( ctrl_p,
> +                    desc_ring_irq_inten_clr_reg_addr[ring_id],
> +                    irq_factor);
> +
> +    return ogma_err;
> +}
> +
> +ogma_err_t ogma_enable_pkt_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* set irq_factor*/
> +    ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
> +                    ( irq_factor & OGMA_PKT_IRQ_ALL) );
> +
> +    return ogma_err;
> +}
> +
> +ogma_err_t ogma_disable_pkt_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* clear irq_factor*/
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_PKT_INTEN_CLR,
> +                    ( irq_factor & OGMA_PKT_IRQ_ALL) );
> +
> +    return ogma_err;
> +}
> +
> +
> +ogma_uint32 ogma_get_top_irq_enable (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_top_irq_enable.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
> +
> +    return value;
> +
> +}
> +
> +
> +ogma_uint32 ogma_get_top_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_top_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
> +
> +    if ( mask_flag) {
> +        value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
> +    }
> +
> +    return value;
> +}
> +
> +ogma_err_t ogma_clear_top_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_clear_top_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* Write clear irq top  status */
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_TOP_STATUS,
> +
> +                    ( value & OGMA_TOP_IRQ_REG_ME_START) );
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +ogma_uint32 ogma_get_desc_ring_irq_enable (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_desc_ring_irq_enable.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_desc_ring_irq_enable.\n"
> +                     "Please select ring id number between 0 and %d.\n",
> +                     OGMA_DESC_RING_ID_MAX);
> +        return 0;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_desc_ring_irq_enable.\n"
> +                     "Please select valid desc ring.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p,
> +                           desc_ring_irq_inten_reg_addr[ring_id] );
> +
> +    return value;
> +}
> +
> +
> +ogma_uint32 ogma_get_desc_ring_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_bool mask_flag
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_desc_ring_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_desc_ring_irq_status.\n"
> +                     "Please select ring id number between 0 and %d.\n",
> +                     OGMA_DESC_RING_ID_MAX);
> +        return 0;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_desc_ring_irq_status.\n"
> +                     "Please select valid desc ring.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p,
> +                           desc_ring_irq_status_reg_addr[ring_id] );
> +
> +    if ( mask_flag) {
> +        value &= ogma_read_reg( ctrl_p,
> +                                desc_ring_irq_inten_reg_addr[ring_id] );
> +    }
> +
> +    return value;
> +}
> +
> +
> +
> +ogma_err_t ogma_clear_desc_ring_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_desc_ring_id_t ring_id,
> +    ogma_uint32 value
> +    )
> +{
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_clear_desc_ring_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( ring_id > OGMA_DESC_RING_ID_MAX) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_clear_desc_ring_irq_status.\n"
> +                     "Please select ring id number between 0 and %d.\n",
> +                     OGMA_DESC_RING_ID_MAX);
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_clear_desc_ring_irq_status.\n"
> +                     "Please select valid desc ring.\n");
> +        return OGMA_ERR_NOTAVAIL;
> +    }
> +
> +    /* Write clear descring irq status */
> +    ogma_write_reg( ctrl_p,
> +                    desc_ring_irq_status_reg_addr[ring_id],
> +                    ( value & ( OGMA_CH_IRQ_REG_EMPTY |
> +                                OGMA_CH_IRQ_REG_ERR) ) );
> +
> +    return OGMA_ERR_OK;
> +
> +}
> +
> +
> +ogma_uint32 ogma_get_pkt_irq_enable (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_pkt_irq_enable.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
> +
> +    value &= OGMA_PKT_IRQ_ALL;
> +
> +    return value;
> +
> +}
> +
> +ogma_uint32 ogma_get_pkt_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
> +
> +    if ( mask_flag) {
> +        value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
> +    }
> +
> +    return value;
> +}
> +
> +ogma_err_t ogma_clear_pkt_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_clear_pkt_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* Write clear irq pkt  status */
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_PKT_STATUS,
> +                    ( value & ( ( OGMA_PKT_IRQ_MAC_ER        |
> +                                  OGMA_PKT_IRQ_JUMBO_ER      |
> +                                  OGMA_PKT_IRQ_CHKSUM_ER     |
> +                                  OGMA_PKT_IRQ_HD_INCOMPLETE |
> +                                  OGMA_PKT_IRQ_HD_ER         |
> +                                  OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
> +
> +    return OGMA_ERR_OK;
> +}
> +
> +#ifdef OGMA_CONFIG_REC_STAT
> +ogma_err_t ogma_get_stat_info (
> +    ogma_handle_t ogma_handle,
> +    ogma_stat_info_t *stat_info_p,
> +    ogma_bool clear_flag
> +    )
> +{
> +
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    pfdep_memcpy( stat_info_p,
> +                  &ctrl_p->stat_info,
> +                  sizeof( ogma_stat_info_t) );
> +
> +
> +    if ( clear_flag) {
> +        pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
> +    }
> +
> +    return OGMA_ERR_OK;
> +
> +}
> +#endif /* OGMA_CONFIG_REC_STAT */
> +
> +ogma_uint32 ogma_get_hw_ver (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p,
> +                           hw_ver_reg_addr);
> +
> +    return value;
> +}
> +
> +
> +ogma_uint32 ogma_get_mcr_ver (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p,
> +                           mc_ver_reg_addr);
> +
> +    return value;
> +}
> +
> +ogma_uint32 ogma_get_mac_irq_enable (
> +    ogma_handle_t ogma_handle
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_ogma_get_mac_irq_enable.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
> +
> +
> +    return value;
> +}
> +
> +ogma_uint32 ogma_get_mac_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_bool mask_flag
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_get_mac_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return 0;
> +    }
> +
> +
> +    value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
> +
> +    if ( mask_flag) {
> +        value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
> +    }
> +
> +
> +    return value;
> +}
> +
> +ogma_err_t ogma_clear_mac_irq_status (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 value
> +    )
> +{
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_clear_mac_irq_status.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +
> +    /* Commented out because no write-clear bit exists now. */
> +#if 0
> +    ogma_write_reg( ctrl_p,
> +                    OGMA_REG_ADDR_MAC_STATUS,
> +                    ( value & /* T.B.D. */) );
> +#endif
> +
> +
> +    return OGMA_ERR_OK;
> +
> +}
> +
> +ogma_err_t ogma_enable_mac_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +    pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_enable_mac_irq.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* get inten_reg_hard_lock */
> +    pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
> +                             &inten_reg_hard_lock_ctx);
> +
> +   value = ogma_read_reg( ctrl_p,
> +                          OGMA_REG_ADDR_MAC_INTEN);
> +
> +   value |= irq_factor;
> +
> +   ogma_write_reg( ctrl_p,
> +                   OGMA_REG_ADDR_MAC_INTEN,
> +                   value);
> +
> +
> +    /* free inten_reg_hard_lock*/
> +    pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
> +                             &inten_reg_hard_lock_ctx);
> +    return ogma_err;
> +}
> +
> +ogma_err_t ogma_disable_mac_irq (
> +    ogma_handle_t ogma_handle,
> +    ogma_uint32 irq_factor
> +    )
> +{
> +    ogma_uint32 value;
> +    ogma_err_t ogma_err = OGMA_ERR_OK;
> +    ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
> +
> +    pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
> +
> +
> +    if ( ctrl_p == NULL) {
> +        pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
> +                     "An error occurred at ogma_disable_mac_irq.\n"
> +                     "Please set valid ogma_handle.\n");
> +        return OGMA_ERR_PARAM;
> +    }
> +
> +    /* get inten_reg_hard_lock */
> +    pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
> +                             &inten_reg_hard_lock_ctx);
> +
> +   value = ogma_read_reg( ctrl_p,
> +                          OGMA_REG_ADDR_MAC_INTEN);
> +
> +   value &= (~irq_factor);
> +
> +   ogma_write_reg( ctrl_p,
> +                   OGMA_REG_ADDR_MAC_INTEN,
> +                   value);
> +
> +
> +    /* free inten_reg_hard_lock*/
> +    pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
> +                             &inten_reg_hard_lock_ctx);
> +    return ogma_err;
> +
> +}
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
> new file mode 100644
> index 000000000000..3bbf8de57a8b
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc_internal.h
> @@ -0,0 +1,38 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_MISC_INTERNAL_H
> +#define OGMA_MISC_INTERNAL_H
> +
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h"
> +#include "netsec_for_uefi/netsec_sdk/include/ogma_api.h"
> +
> +#define OGMA_CLK_EN_REG_DOM_ALL 0x24
> +
> +#define OGMA_PKT_IRQ_ALL ( OGMA_PKT_IRQ_MAC_ER    | OGMA_PKT_IRQ_JUMBO_ER      | \
> +                           OGMA_PKT_IRQ_CHKSUM_ER | OGMA_PKT_IRQ_HD_INCOMPLETE | \
> +                           OGMA_PKT_IRQ_HD_ER     | OGMA_PKT_IRQ_DRP_NO_MATCH)
> +
> +typedef struct ogma_global_s ogma_global_t;
> +
> +struct ogma_global_s{
> +    ogma_uint valid_flag:1;
> +
> +    ogma_uint8 list_entry_num;
> +
> +    ogma_ctrl_t *list_head_p;
> +};
> +
> +#endif /* OGMA_MISC_INTERNAL_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
> new file mode 100644
> index 000000000000..910b37a25f14
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h
> @@ -0,0 +1,219 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_REG_H
> +#define OGMA_REG_H
> +
> +#include "ogma_reg_netsec.h"
> +#include "ogma_reg_f_gmac_4mt.h"
> +
> +/* aliases */
> +#define OGMA_REG_ADDR_TOP_INTEN OGMA_REG_ADDR_TOP_INTEN_A
> +#define OGMA_REG_ADDR_TOP_INTEN_SET OGMA_REG_ADDR_TOP_INTEN_A_SET
> +#define OGMA_REG_ADDR_TOP_INTEN_CLR OGMA_REG_ADDR_TOP_INTEN_A_CLR
> +/* aliases end here */
> +
> +/* need fixing */
> +#define OGMA_REG_ADDR_DMAC_MH_CMD_BUF            (0x87)
> +
> +
> +/*bit fields for PKT_CTRL*/
> +#define OGMA_PKT_CTRL_REG_EN_JUMBO          (1UL << 27)
> +#define OGMA_PKT_CTRL_REG_EN_BITPATF        (1UL << 4 )
> +#define OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER     (1UL << 3 )
> +#define OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE (1UL << 2 )
> +#define OGMA_PKT_CTRL_REG_LOG_HD_ER         (1UL << 1 )
> +#define OGMA_PKT_CTRL_REG_DRP_NO_MATCH      (1UL << 0 )
> +
> +#define OGMA_CLK_EN_REG_DOM_G (1UL << 5)
> +
> +/************************************************************
> + * Bit fields
> + ************************************************************/
> +/* bit fields for com_init */
> +#define OGMA_COM_INIT_REG_DB   (1UL << 2)
> +#define OGMA_COM_INIT_REG_CLS  (1UL << 1)
> +#define OGMA_COM_INIT_REG_ALL  ( OGMA_COM_INIT_REG_CLS | OGMA_COM_INIT_REG_DB)
> +
> +/* bit fields for soft_rst */
> +#define OGMA_SOFT_RST_REG_RESET (0)
> +#define OGMA_SOFT_RST_REG_RUN   (1UL << 31)
> +
> +/* bit fields for dma_hm_ctrl */
> +#define OGMA_DMA_CTRL_REG_STOP 1UL
> +
> +/* bit fields for gmac_cmd */
> +#define OGMA_GMAC_CMD_ST_READ  (0)
> +#define OGMA_GMAC_CMD_ST_WRITE (1UL << 28)
> +#define OGMA_GMAC_CMD_ST_BUSY  (1UL << 31)
> +
> +/* bit fields for F_GMAC4MT BMR*/
> +#define OGMA_GMAC_BMR_REG_COMMON (0x00412080)
> +#define OGMA_GMAC_BMR_REG_RESET  (0x00020181)
> +#define OGMA_GMAC_BMR_REG_SWR    (0x00000001)
> +
> +/* bit fields for F_GMAC4MT OMR*/
> +#define OGMA_GMAC_OMR_REG_ST (1UL << 13)
> +#define OGMA_GMAC_OMR_REG_SR (1UL << 1)
> +
> +/* bit fields for F_GMAC4MT MCR*/
> +#define OGMA_GMAC_MCR_REG_CST                (1UL << 25)
> +#define OGMA_GMAC_MCR_REG_JE                 (1UL << 20)
> +#define OGMA_GMAC_MCR_REG_PS                 (1UL << 15)
> +#define OGMA_GMAC_MCR_REG_FES                (1UL << 14)
> +#define OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON (0x0000280c)
> +#define OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON (0x0001a00c)
> +
> +#define OGMA_GMAC_MCR_1G_FULL ( OGMA_GMAC_MCR_REG_CST | \
> +                                OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_100M_FULL ( OGMA_GMAC_MCR_REG_CST | \
> +                                  OGMA_GMAC_MCR_REG_PS  | \
> +                                  OGMA_GMAC_MCR_REG_FES | \
> +                                  OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_100M_HALF ( OGMA_GMAC_MCR_REG_CST | \
> +                                  OGMA_GMAC_MCR_REG_FES | \
> +                                  OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_10M_FULL ( OGMA_GMAC_MCR_REG_CST | \
> +                                 OGMA_GMAC_MCR_REG_PS  | \
> +                                 OGMA_GMAC_MCR_REG_FULL_DUPLEX_COMMON)
> +
> +#define OGMA_GMAC_MCR_10M_HALF ( OGMA_GMAC_MCR_REG_CST | \
> +                                 OGMA_GMAC_MCR_REG_HALF_DUPLEX_COMMON)
> +
> +/*bit fields for F_GMAC4MT FCR*/
> +#define OGMA_GMAC_FCR_REG_RFE (1UL << 2)
> +#define OGMA_GMAC_FCR_REG_TFE (1UL << 1)
> +
> +/* bit fields for F_GMAC4MT GAR */
> +#define OGMA_GMAC_GAR_REG_GW (1UL << 1)
> +#define OGMA_GMAC_GAR_REG_GB (1UL << 0)
> +
> +/* bit fields for F_GMAC4MT RDLAR*/
> +#define OGMA_GMAC_RDLAR_REG_COMMON (0x00018000UL)
> +
> +/* bit fields for F_GMAC4MT TDLAR*/
> +#define OGMA_GMAC_TDLAR_REG_COMMON (0x0001c000UL)
> +
> +
> +#define OGMA_GMAC_GAR_REG_SHIFT_PA (11)
> +#define OGMA_GMAC_GAR_REG_SHIFT_GR (6)
> +#define OGMA_GMAC_GAR_REG_SHIFT_CR (2)
> +
> +#define OGMA_GMAC_GAR_REG_CR_25_35_MHZ   (2)
> +#define OGMA_GMAC_GAR_REG_CR_35_60_MHZ   (3)
> +#define OGMA_GMAC_GAR_REG_CR_60_100_MHZ  (0)
> +#define OGMA_GMAC_GAR_REG_CR_100_150_MHZ (1)
> +#define OGMA_GMAC_GAR_REG_CR_150_250_MHZ (4)
> +#define OGMA_GMAC_GAR_REG_CR_250_300_MHZ (5)
> +
> +/* bit fields for F_GMAC4MT LPITCR */
> +#define OGMA_GMAC_LPITCR_REG_LIT (16)
> +#define OGMA_GMAC_LPITCR_REG_TWT (0)
> +
> +/* bit fileds mask for F_GMAC4MT LPITCR */
> +#define OGMA_GMAC_LPITCR_REG_MASK_LIT (0x3ffU)
> +#define OGMA_GMAC_LPITCR_REG_MASK_TWT (0xffffU)
> +
> +/**
> + * PHY regtister Address
> + */
> +#define OGMA_PHY_REG_ADDR_CONTROL                      0
> +#define OGMA_PHY_REG_ADDR_STATUS                       1U
> +#define OGMA_PHY_REG_ADDR_AUTO_NEGO_ABILTY             4U
> +#define OGMA_PHY_REG_ADDR_AUTO_NEGO_LINK_PATNER_ABILTY 5U
> +#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_CONTROL         9U
> +#define OGMA_PHY_REG_ADDR_MASTER_SLAVE_STATUS          10U
> +#define OGMA_PHY_REG_ADDR_MMD_AC                       13U
> +#define OGMA_PHY_REG_ADDR_MMD_AAD                      14U
> +
> +/* bit fields for PHY CONTROL Register */
> +#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6)
> +#define OGMA_PHY_CONTROL_REG_DUPLEX_MODE         (8)
> +#define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE    (12)
> +#define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13)
> +
> +/* bit fields for PHY STATUS Register */
> +#define OGMA_PHY_STATUS_REG_LINK_STATUS       (2)
> +#define OGMA_PHY_STATUS_REG_AUTO_NEGO_ABILITY (3)
> +#define OGMA_PHY_STATUS_REG_AUTO_NEGO_COMP    (5)
> +
> +/* bit fields for PHY MASTER-SLAVE Control Register */
> +#define OGMA_PHY_MSC_REG_1000BASE_FULL (9)
> +#define OGMA_PHY_MSC_REG_1000BASE_HALF (8)
> +
> +/* bit fields for PHY MASTER-SLAVE Status Register */
> +#define OGMA_PHY_MSS_REG_LP_1000BASE_FULL (11)
> +#define OGMA_PHY_MSS_REG_LP_1000BASE_HALF (10)
> +
> +/* bit fields for PHY Auto-Negotiation Advertisement Register */
> +#define OGMA_PHY_ANA_REG_TAF (5)
> +
> +/* bit fileds mask for F_GMAC4MT LPITCR */
> +#define OGMA_PHY_ANA_REG_TAF_MASK (0x7fU)
> +
> +/* bit fields for PHY Technology Ability Field */
> +#define OGMA_PHY_TAF_REG_100BASE_FULL (1U << 3)
> +#define OGMA_PHY_TAF_REG_100BASE_HALF (1U << 2)
> +#define OGMA_PHY_TAF_REG_10BASE_FULL  (1U << 1)
> +#define OGMA_PHY_TAF_REG_10BASE_HALF  (1U << 0)
> +
> +/**
> + * PHY Device Address
> + */
> +#define OGMA_PHY_DEV_ADDR_AUTO_NEGO (7U)
> +
> +/**
> + * PHY Register Address for Device Address 7
> + */
> +#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_ADVERTISE  (60U)
> +#define OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP_ABILITY (61U)
> +
> +/* bit fields for PHY AutoNegotiation Field */
> +#define OGMA_PHY_AUTO_NEGO_1000BASE_EEE (1U << 2)
> +#define OGMA_PHY_AUTO_NEGO_100BASE_EEE  (1U << 1)
> +
> +/* bit fields for DESC RING CONFIG */
> +#define OGMA_REG_DESC_RING_CONFIG_CFG_UP     (31)
> +#define OGMA_REG_DESC_RING_CONFIG_CH_RST     (30)
> +#define OGMA_REG_DESC_RING_CONFIG_TMR_MODE   (4)
> +#define OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN (0)
> +
> +
> +/* bit fields for mac_desc_soft_rst */
> +#define OGMA_MAC_DESC_SOFT_RST_SOFT_RST 1UL
> +
> +/* bit fields for mac_desc_init */
> +#define OGMA_MAC_DESC_INIT_REG_INIT 1UL
> +
> +/* bit fields for dis_core */
> +#define OGMA_DIS_CORE_REG_DIS_PCORE  (1UL << 2)
> +#define OGMA_DIS_CORE_REG_DIS_MHCORE (1UL << 1)
> +#define OGMA_DIS_CORE_REG_DIS_HMCORE (1UL << 0)
> +
> +#define OGMA_DIS_CORE_REG_ALL ( OGMA_DIS_CORE_REG_DIS_HMCORE | \
> +                                OGMA_DIS_CORE_REG_DIS_MHCORE | \
> +                                OGMA_DIS_CORE_REG_DIS_PCORE)
> +
> +/* bit fields for dma_info */
> +#define OGMA_DMA_INFO_REG_AXI_WRITE_BUSY (1UL << 3)
> +#define OGMA_DMA_INFO_REG_AXI_READ_BUSY  (1UL << 2)
> +
> +#define OGMA_DMA_INFO_REG_AXI_BUSY ( OGMA_DMA_INFO_REG_AXI_WRITE_BUSY | \
> +                                     OGMA_DMA_INFO_REG_AXI_READ_BUSY)
> +
> +#endif /*OGMA_REG_H*/
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
> new file mode 100644
> index 000000000000..e12b317218fb
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_f_gmac_4mt.h
> @@ -0,0 +1,222 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_REG_F_GMAC_4MT_H
> +#define OGMA_REG_F_GMAC_4MT_H
> +
> +/**
> + * GMAC register
> + */
> +#define OGMA_GMAC_REG_ADDR_MCR      (0x0000)
> +#define OGMA_GMAC_REG_ADDR_MFFR     (0x0004)
> +#define OGMA_GMAC_REG_ADDR_MHTRH    (0x0008)
> +#define OGMA_GMAC_REG_ADDR_MHTRL    (0x000c)
> +#define OGMA_GMAC_REG_ADDR_GAR      (0x0010)
> +#define OGMA_GMAC_REG_ADDR_GDR      (0x0014)
> +#define OGMA_GMAC_REG_ADDR_FCR      (0x0018)
> +#define OGMA_GMAC_REG_ADDR_VTR      (0x001c)
> +#define OGMA_GMAC_REG_ADDR_RWFFR    (0x0028)
> +#define OGMA_GMAC_REG_ADDR_PMTR     (0x002c)
> +#define OGMA_GMAC_REG_ADDR_LPICSR   (0x0030)
> +#define OGMA_GMAC_REG_ADDR_LPITCR   (0x0034)
> +#define OGMA_GMAC_REG_ADDR_ISR      (0x0038)
> +#define OGMA_GMAC_REG_ADDR_IMR      (0x003c)
> +#define OGMA_GMAC_REG_ADDR_MAR0H    (0x0040)
> +#define OGMA_GMAC_REG_ADDR_MAR0L    (0x0044)
> +#define OGMA_GMAC_REG_ADDR_MAR1H    (0x0048)
> +#define OGMA_GMAC_REG_ADDR_MAR1L    (0x004c)
> +#define OGMA_GMAC_REG_ADDR_MAR2H    (0x0050)
> +#define OGMA_GMAC_REG_ADDR_MAR2L    (0x0054)
> +#define OGMA_GMAC_REG_ADDR_MAR3H    (0x0058)
> +#define OGMA_GMAC_REG_ADDR_MAR3L    (0x005c)
> +#define OGMA_GMAC_REG_ADDR_MAR4H    (0x0060)
> +#define OGMA_GMAC_REG_ADDR_MAR4L    (0x0064)
> +#define OGMA_GMAC_REG_ADDR_MAR5H    (0x0068)
> +#define OGMA_GMAC_REG_ADDR_MAR5L    (0x006c)
> +#define OGMA_GMAC_REG_ADDR_MAR6H    (0x0070)
> +#define OGMA_GMAC_REG_ADDR_MAR6L    (0x0074)
> +#define OGMA_GMAC_REG_ADDR_MAR7H    (0x0078)
> +#define OGMA_GMAC_REG_ADDR_MAR7L    (0x007c)
> +#define OGMA_GMAC_REG_ADDR_MAR8H    (0x0080)
> +#define OGMA_GMAC_REG_ADDR_MAR8L    (0x0084)
> +#define OGMA_GMAC_REG_ADDR_MAR9H    (0x0088)
> +#define OGMA_GMAC_REG_ADDR_MAR9L    (0x008c)
> +#define OGMA_GMAC_REG_ADDR_MAR10H   (0x0090)
> +#define OGMA_GMAC_REG_ADDR_MAR10L   (0x0094)
> +#define OGMA_GMAC_REG_ADDR_MAR11H   (0x0098)
> +#define OGMA_GMAC_REG_ADDR_MAR11L   (0x009c)
> +#define OGMA_GMAC_REG_ADDR_MAR12H   (0x00a0)
> +#define OGMA_GMAC_REG_ADDR_MAR12L   (0x00a4)
> +#define OGMA_GMAC_REG_ADDR_MAR13H   (0x00a8)
> +#define OGMA_GMAC_REG_ADDR_MAR13L   (0x00ac)
> +#define OGMA_GMAC_REG_ADDR_MAR14H   (0x00b0)
> +#define OGMA_GMAC_REG_ADDR_MAR14L   (0x00b4)
> +#define OGMA_GMAC_REG_ADDR_MAR15H   (0x00b8)
> +#define OGMA_GMAC_REG_ADDR_MAR15L   (0x00bc)
> +#define OGMA_GMAC_REG_ADDR_RSR      (0x00d8)
> +#define OGMA_GMAC_REG_ADDR_TSCR     (0x0700)
> +#define OGMA_GMAC_REG_ADDR_SSIR     (0x0704)
> +#define OGMA_GMAC_REG_ADDR_STSR     (0x0708)
> +#define OGMA_GMAC_REG_ADDR_STNR     (0x070c)
> +#define OGMA_GMAC_REG_ADDR_STSUR    (0x0710)
> +#define OGMA_GMAC_REG_ADDR_STNUR    (0x0714)
> +#define OGMA_GMAC_REG_ADDR_TSAR     (0x0718)
> +#define OGMA_GMAC_REG_ADDR_TTSR     (0x071c)
> +#define OGMA_GMAC_REG_ADDR_TTNR     (0x0720)
> +#define OGMA_GMAC_REG_ADDR_STHWSR   (0x0724)
> +#define OGMA_GMAC_REG_ADDR_TSR      (0x0728)
> +#define OGMA_GMAC_REG_ADDR_PPSCR    (0x072c)
> +#define OGMA_GMAC_REG_ADDR_ANTR     (0x0730)
> +#define OGMA_GMAC_REG_ADDR_ATSR     (0x0734)
> +#define OGMA_GMAC_REG_ADDR_MAR16H   (0x0800)
> +#define OGMA_GMAC_REG_ADDR_MAR16L   (0x0804)
> +#define OGMA_GMAC_REG_ADDR_MAR17H   (0x0808)
> +#define OGMA_GMAC_REG_ADDR_MAR17L   (0x080c)
> +#define OGMA_GMAC_REG_ADDR_MAR18H   (0x0810)
> +#define OGMA_GMAC_REG_ADDR_MAR18L   (0x0814)
> +#define OGMA_GMAC_REG_ADDR_MAR19H   (0x0818)
> +#define OGMA_GMAC_REG_ADDR_MAR19L   (0x081c)
> +#define OGMA_GMAC_REG_ADDR_MAR20H   (0x0820)
> +#define OGMA_GMAC_REG_ADDR_MAR20L   (0x0824)
> +#define OGMA_GMAC_REG_ADDR_MAR21H   (0x0828)
> +#define OGMA_GMAC_REG_ADDR_MAR21L   (0x082c)
> +#define OGMA_GMAC_REG_ADDR_MAR22H   (0x0830)
> +#define OGMA_GMAC_REG_ADDR_MAR22L   (0x0834)
> +#define OGMA_GMAC_REG_ADDR_MAR23H   (0x0838)
> +#define OGMA_GMAC_REG_ADDR_MAR23L   (0x083c)
> +#define OGMA_GMAC_REG_ADDR_MAR24H   (0x0840)
> +#define OGMA_GMAC_REG_ADDR_MAR24L   (0x0844)
> +#define OGMA_GMAC_REG_ADDR_MAR25H   (0x0848)
> +#define OGMA_GMAC_REG_ADDR_MAR25L   (0x084c)
> +#define OGMA_GMAC_REG_ADDR_MAR26H   (0x0850)
> +#define OGMA_GMAC_REG_ADDR_MAR26L   (0x0854)
> +#define OGMA_GMAC_REG_ADDR_MAR27H   (0x0858)
> +#define OGMA_GMAC_REG_ADDR_MAR27L   (0x085c)
> +#define OGMA_GMAC_REG_ADDR_MAR28H   (0x0860)
> +#define OGMA_GMAC_REG_ADDR_MAR28L   (0x0864)
> +#define OGMA_GMAC_REG_ADDR_MAR29H   (0x0868)
> +#define OGMA_GMAC_REG_ADDR_MAR29L   (0x086c)
> +#define OGMA_GMAC_REG_ADDR_MAR30H   (0x0870)
> +#define OGMA_GMAC_REG_ADDR_MAR30L   (0x0874)
> +#define OGMA_GMAC_REG_ADDR_MAR31H   (0x0878)
> +#define OGMA_GMAC_REG_ADDR_MAR31L   (0x087c)
> +
> +/**
> + * GMAC MAC Management Counters(Option) register
> + */
> +#define OGMA_GMAC_REG_ADDR_MMC_CNTL                  (0x0100)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_RX               (0x0104)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_TX               (0x0108)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_RX          (0x010c)
> +#define OGMA_GMAC_REG_ADDR_MMC_INTR_MASK_TX          (0x0110)
> +#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_GB           (0x0114)
> +#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_GB           (0x0118)
> +#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_G       (0x011c)
> +#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_G       (0x0120)
> +#define OGMA_GMAC_REG_ADDR_TX64OCTETS_GB             (0x0124)
> +#define OGMA_GMAC_REG_ADDR_TX65TO127OCTETS_GB        (0x0128)
> +#define OGMA_GMAC_REG_ADDR_TX128TO255OCTETS_GB       (0x012c)
> +#define OGMA_GMAC_REG_ADDR_TX256TO511OCTETS_GB       (0x0130)
> +#define OGMA_GMAC_REG_ADDR_TX512TO1023OCTETS_GB      (0x0134)
> +#define OGMA_GMAC_REG_ADDR_TX1024TOMAXOCTETS_GB      (0x0138)
> +#define OGMA_GMAC_REG_ADDR_TXUNICASTFRAMES_GB        (0x013c)
> +#define OGMA_GMAC_REG_ADDR_TXMULTICASTFRAMES_GB      (0x0140)
> +#define OGMA_GMAC_REG_ADDR_TXBROADCASTFRAMES_GB      (0x0144)
> +#define OGMA_GMAC_REG_ADDR_TXUNDERFLOWERROR          (0x0148)
> +#define OGMA_GMAC_REG_ADDR_TXSINGLECOL_G             (0x014c)
> +#define OGMA_GMAC_REG_ADDR_TXMULTICOL_G              (0x0150)
> +#define OGMA_GMAC_REG_ADDR_TXDEFERRED                (0x0154)
> +#define OGMA_GMAC_REG_ADDR_TXLATECOL                 (0x0158)
> +#define OGMA_GMAC_REG_ADDR_TXEXESSCOL                (0x015c)
> +#define OGMA_GMAC_REG_ADDR_TXCARRIERERRROR           (0x0160)
> +#define OGMA_GMAC_REG_ADDR_TXOCTETCOUNT_G            (0x0164)
> +#define OGMA_GMAC_REG_ADDR_TXFRAMECOUNT_G            (0x0168)
> +#define OGMA_GMAC_REG_ADDR_TXEXECESSDEF              (0x016c)
> +#define OGMA_GMAC_REG_ADDR_TXPAUSEFRAMES             (0x0170)
> +#define OGMA_GMAC_REG_ADDR_TXVLANFRAMES_G            (0x0174)
> +#define OGMA_GMAC_REG_ADDR_RXFRAMECOUNT_GB           (0x0180)
> +#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_GB           (0x0184)
> +#define OGMA_GMAC_REG_ADDR_RXOCTETCOUNT_G            (0x0188)
> +#define OGMA_GMAC_REG_ADDR_RXBROADCASTFRAMES_G       (0x018c)
> +#define OGMA_GMAC_REG_ADDR_RXMULTICASTFRAMES_G       (0x0190)
> +#define OGMA_GMAC_REG_ADDR_RXCRCERROR                (0x0194)
> +#define OGMA_GMAC_REG_ADDR_RXALLIGNMENTERROR         (0x0198)
> +#define OGMA_GMAC_REG_ADDR_RXRUNTERROR               (0x019c)
> +#define OGMA_GMAC_REG_ADDR_RXJABBERERROR             (0x01a0)
> +#define OGMA_GMAC_REG_ADDR_RXUNDERSIZE_G             (0x01a4)
> +#define OGMA_GMAC_REG_ADDR_RXOVERSIZE_G              (0x01a8)
> +#define OGMA_GMAC_REG_ADDR_RX64OCTETS_GB             (0x01ac)
> +#define OGMA_GMAC_REG_ADDR_RX65TO127OCTETS_GB        (0x01b0)
> +#define OGMA_GMAC_REG_ADDR_RX128TO255OCTETS_GB       (0x01b4)
> +#define OGMA_GMAC_REG_ADDR_RX256TO511OCTETS_GB       (0x01b8)
> +#define OGMA_GMAC_REG_ADDR_RX512TO1023OCTETS_GB      (0x01bc)
> +#define OGMA_GMAC_REG_ADDR_RX1024TOMAXOCTETS_GB      (0x01c0)
> +#define OGMA_GMAC_REG_ADDR_RXUNICASTFRAMES_G         (0x01c4)
> +#define OGMA_GMAC_REG_ADDR_RXLENGTHERROR             (0x01c8)
> +#define OGMA_GMAC_REG_ADDR_RXOUTOFRANGETYPE          (0x01cc)
> +#define OGMA_GMAC_REG_ADDR_RXPAUSEFRAMES             (0x01d0)
> +#define OGMA_GMAC_REG_ADDR_RXFIFOOVERFLOW            (0x01d4)
> +#define OGMA_GMAC_REG_ADDR_RXVLANFRAMES_GB           (0x01d8)
> +#define OGMA_GMAC_REG_ADDR_RXWATCHDOGERROR           (0x01dc)
> +#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_MASK_RX      (0x0200)
> +#define OGMA_GMAC_REG_ADDR_MMC_IPC_INTR_RX           (0x0208)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_FRMS            (0x0210)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_FRMS        (0x0214)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_FRMS         (0x0218)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_FRMS          (0x021c)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_FRMS         (0x0220)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_FRMS            (0x0224)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_FRMS        (0x0228)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_FRMS         (0x022c)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_GD_FRMS             (0x0230)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_FRMS            (0x0234)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_GD_FRMS             (0x0238)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_FRMS            (0x023c)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_GD_FRMS            (0x0240)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_FRMS           (0x0244)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_GD_OCTETS          (0x0250)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_HDRERR_OCTETS      (0x0254)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_NOPAY_OCTETS       (0x0258)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_FRAG_OCTETS        (0x025c)
> +#define OGMA_GMAC_REG_ADDR_RXIPV4_UDSBL_OCTETS       (0x0260)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_GD_OCTETS          (0x0264)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_HDRERR_OCTETS      (0x0268)
> +#define OGMA_GMAC_REG_ADDR_RXIPV6_NOPAY_OCTETS       (0x026c)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_GD_OCTETS           (0x0270)
> +#define OGMA_GMAC_REG_ADDR_RXUDP_ERR_OCTETS          (0x0274)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_GD_OCTETS           (0x0278)
> +#define OGMA_GMAC_REG_ADDR_RXTCP_ERR_OCTETS          (0x027c)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_GD_OCTETS          (0x0280)
> +#define OGMA_GMAC_REG_ADDR_RXICMP_ERR_OCTETS         (0x0284)
> +/**
> + * GMAC DMA register
> + */
> +#define OGMA_GMAC_REG_ADDR_BMR      (0x1000)
> +#define OGMA_GMAC_REG_ADDR_TPDR     (0x1004)
> +#define OGMA_GMAC_REG_ADDR_RPDR     (0x1008)
> +#define OGMA_GMAC_REG_ADDR_RDLAR    (0x100c)
> +#define OGMA_GMAC_REG_ADDR_TDLAR    (0x1010)
> +#define OGMA_GMAC_REG_ADDR_SR       (0x1014)
> +#define OGMA_GMAC_REG_ADDR_OMR      (0x1018)
> +#define OGMA_GMAC_REG_ADDR_IER      (0x101c)
> +#define OGMA_GMAC_REG_ADDR_MFOCR    (0x1020)
> +#define OGMA_GMAC_REG_ADDR_RIWTR    (0x1024)
> +#define OGMA_GMAC_REG_ADDR_AHBSR    (0x102c)
> +#define OGMA_GMAC_REG_ADDR_CHTDR    (0x1048)
> +#define OGMA_GMAC_REG_ADDR_CHRDR    (0x104c)
> +#define OGMA_GMAC_REG_ADDR_CHTBAR   (0x1050)
> +#define OGMA_GMAC_REG_ADDR_CHRBAR   (0x1054)
> +
> +#endif /* OGMA_REG_F_GMAC_4MT_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
> new file mode 100644
> index 000000000000..457be2aa0cba
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg_netsec.h
> @@ -0,0 +1,368 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_REG_NETSEC_H
> +#define OGMA_REG_NETSEC_H
> +
> +#define OGMA_REG_ADDR_SOFT_RST (0x41)
> +#define OGMA_REG_ADDR_COM_INIT (0x48)
> +#define OGMA_REG_ADDR_MC_BASE_ADDR (0x97)
> +#define OGMA_REG_ADDR_DMAC_HM_CMD_BUF (0x84)
> +#define OGMA_REG_ADDR_DMAC_MC_ADDR_MH (0x89)
> +#define OGMA_REG_ADDR_DMAC_MC_SIZE_MH (0x8A)
> +#define OGMA_REG_ADDR_PKTC_CMD_BUF (0x34)
> +#define OGMA_REG_ADDR_PKTC_MC_ADDR (0x5C)
> +#define OGMA_REG_ADDR_PKTC_MC_SIZE (0x5D)
> +#define OGMA_REG_ADDR_DIS_CORE (0x86)
> +#define OGMA_REG_ADDR_DMA_HM_CTRL (0x85)
> +#define OGMA_REG_ADDR_DMA_MH_CTRL (0x88)
> +#define OGMA_REG_ADDR_CLK_EN_0 (0x40)
> +#define OGMA_REG_ADDR_CLK_EN_1 (0x64)
> +#define OGMA_REG_ADDR_PKT_CTRL (0x50)
> +#define OGMA_REG_ADDR_NRM_TX_DESC_START_UP (0x10D)
> +#define OGMA_REG_ADDR_NRM_TX_DESC_START_LW (0x102)
> +#define OGMA_REG_ADDR_NRM_RX_DESC_START_UP (0x11D)
> +#define OGMA_REG_ADDR_NRM_RX_DESC_START_LW (0x112)
> +#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_UP (0x12D)
> +#define OGMA_REG_ADDR_TAIKI_RX_DESC_START_LW (0x122)
> +#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_UP (0x13D)
> +#define OGMA_REG_ADDR_TAIKI_TX_DESC_START_LW (0x132)
> +#define OGMA_REG_ADDR_MISC_RX_DESC_START_UP (0x14D)
> +#define OGMA_REG_ADDR_MISC_RX_DESC_START_LW (0x142)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_UP (0x15D)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DESC_START_LW (0x152)
> +#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_UP (0x16D)
> +#define OGMA_REG_ADDR_WL_NRM_RX_DESC_START_LW (0x162)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_UP (0x17D)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DESC_START_LW (0x172)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_UP (0x18D)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_DESC_START_LW (0x182)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_UP (0x19D)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_DESC_START_LW (0x192)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_UP (0x1AD)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DESC_START_LW (0x1A2)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_UP (0x1BD)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_DESC_START_LW (0x1B2)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_UP (0x1CD)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DESC_START_LW (0x1C2)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_UP (0x1DD)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_DESC_START_LW (0x1D2)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_UP (0x1ED)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_DESC_START_LW (0x1E2)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_UP (0x20D)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DESC_START_LW (0x202)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_UP (0x21D)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_DESC_START_LW (0x212)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_UP (0x22D)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DESC_START_LW (0x222)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_UP (0x23D)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DESC_START_LW (0x232)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_UP (0x24D)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_DESC_START_LW (0x242)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_UP (0x25D)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_DESC_START_LW (0x252)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_UP (0x26D)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DESC_START_LW (0x262)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_UP (0x27D)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DESC_START_LW (0x272)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_UP (0x28D)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_DESC_START_LW (0x282)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_UP (0x29D)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_DESC_START_LW (0x292)
> +#define OGMA_REG_ADDR_NRM_TX_CONFIG (0x10C)
> +#define OGMA_REG_ADDR_NRM_RX_CONFIG (0x11C)
> +#define OGMA_REG_ADDR_TAIKI_RX_CONFIG (0x12C)
> +#define OGMA_REG_ADDR_TAIKI_TX_CONFIG (0x13C)
> +#define OGMA_REG_ADDR_MISC_RX_CONFIG (0x14C)
> +#define OGMA_REG_ADDR_WL_NRM_TX_CONFIG (0x15C)
> +#define OGMA_REG_ADDR_WL_NRM_RX_CONFIG (0x16C)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_CONFIG (0x17C)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_CONFIG (0x18C)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_CONFIG (0x19C)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_CONFIG (0x1AC)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_CONFIG (0x1BC)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_CONFIG (0x1CC)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_CONFIG (0x1DC)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_CONFIG (0x1EC)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_CONFIG (0x20C)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_CONFIG (0x21C)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_CONFIG (0x22C)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_CONFIG (0x23C)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_CONFIG (0x24C)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_CONFIG (0x25C)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_CONFIG (0x26C)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_CONFIG (0x27C)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_CONFIG (0x28C)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_CONFIG (0x29C)
> +#define OGMA_REG_ADDR_DMA_TMR_CTRL (0x83)
> +#define OGMA_REG_ADDR_TOP_STATUS (0x80)
> +#define OGMA_REG_ADDR_TOP_INTEN_A (0x81)
> +#define OGMA_REG_ADDR_TOP_INTEN_A_SET (0x8D)
> +#define OGMA_REG_ADDR_TOP_INTEN_A_CLR (0x8E)
> +#define OGMA_REG_ADDR_TOP_INTEN_B (0x8F)
> +#define OGMA_REG_ADDR_TOP_INTEN_B_SET (0x90)
> +#define OGMA_REG_ADDR_TOP_INTEN_B_CLR (0x91)
> +#define OGMA_REG_ADDR_PKT_STATUS (0x3)
> +#define OGMA_REG_ADDR_PKT_INTEN (0x4)
> +#define OGMA_REG_ADDR_PKT_INTEN_SET (0x7)
> +#define OGMA_REG_ADDR_PKT_INTEN_CLR (0x8)
> +#define OGMA_REG_ADDR_TLS_STATUS (0x5)
> +#define OGMA_REG_ADDR_TLS_INTEN (0x6)
> +#define OGMA_REG_ADDR_TLS_INTEN_SET (0x9)
> +#define OGMA_REG_ADDR_TLS_INTEN_CLR (0xA)
> +#define OGMA_REG_ADDR_SLAVE_0_STATUS (0xB)
> +#define OGMA_REG_ADDR_SLAVE_0_INTEN (0xC)
> +#define OGMA_REG_ADDR_SLAVE_0_INTEN_SET (0xD)
> +#define OGMA_REG_ADDR_SLAVE_0_INTEN_CLR (0xE)
> +#define OGMA_REG_ADDR_SLAVE_1_STATUS (0xF)
> +#define OGMA_REG_ADDR_SLAVE_1_INTEN (0x10)
> +#define OGMA_REG_ADDR_SLAVE_1_INTEN_SET (0x11)
> +#define OGMA_REG_ADDR_SLAVE_1_INTEN_CLR (0x12)
> +#define OGMA_REG_ADDR_MAC_STATUS (0x409)
> +#define OGMA_REG_ADDR_MAC_INTEN (0x40A)
> +#define OGMA_REG_ADDR_MAC_TX_RX_INFO_STATUS (0x486)
> +#define OGMA_REG_ADDR_MAC_TX_RX_INFO_INTEN (0x487)
> +#define OGMA_REG_ADDR_NRM_TX_STATUS (0x100)
> +#define OGMA_REG_ADDR_NRM_TX_INTEN (0x101)
> +#define OGMA_REG_ADDR_NRM_TX_INTEN_SET (0x10A)
> +#define OGMA_REG_ADDR_NRM_TX_INTEN_CLR (0x10B)
> +#define OGMA_REG_ADDR_NRM_RX_STATUS (0x110)
> +#define OGMA_REG_ADDR_NRM_RX_INTEN (0x111)
> +#define OGMA_REG_ADDR_NRM_RX_INTEN_SET (0x11A)
> +#define OGMA_REG_ADDR_NRM_RX_INTEN_CLR (0x11B)
> +#define OGMA_REG_ADDR_TAIKI_RX_STATUS (0x120)
> +#define OGMA_REG_ADDR_TAIKI_RX_INTEN (0x121)
> +#define OGMA_REG_ADDR_TAIKI_RX_INTEN_SET (0x12A)
> +#define OGMA_REG_ADDR_TAIKI_RX_INTEN_CLR (0x12B)
> +#define OGMA_REG_ADDR_TAIKI_TX_STATUS (0x130)
> +#define OGMA_REG_ADDR_TAIKI_TX_INTEN (0x131)
> +#define OGMA_REG_ADDR_TAIKI_TX_INTEN_SET (0x13A)
> +#define OGMA_REG_ADDR_TAIKI_TX_INTEN_CLR (0x13B)
> +#define OGMA_REG_ADDR_MISC_RX_STATUS (0x140)
> +#define OGMA_REG_ADDR_MISC_RX_INTEN (0x141)
> +#define OGMA_REG_ADDR_MISC_RX_INTEN_SET (0x14A)
> +#define OGMA_REG_ADDR_MISC_RX_INTEN_CLR (0x14B)
> +#define OGMA_REG_ADDR_WL_NRM_TX_STATUS (0x150)
> +#define OGMA_REG_ADDR_WL_NRM_TX_INTEN (0x151)
> +#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_SET (0x15A)
> +#define OGMA_REG_ADDR_WL_NRM_TX_INTEN_CLR (0x15B)
> +#define OGMA_REG_ADDR_WL_NRM_RX_STATUS (0x160)
> +#define OGMA_REG_ADDR_WL_NRM_RX_INTEN (0x161)
> +#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_SET (0x16A)
> +#define OGMA_REG_ADDR_WL_NRM_RX_INTEN_CLR (0x16B)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_STATUS (0x170)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN (0x171)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_SET (0x17A)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_INTEN_CLR (0x17B)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_STATUS (0x180)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN (0x181)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_SET (0x18A)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_INTEN_CLR (0x18B)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_STATUS (0x190)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN (0x191)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_SET (0x19A)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_INTEN_CLR (0x19B)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_STATUS (0x1A0)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN (0x1A1)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_SET (0x1AA)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_INTEN_CLR (0x1AB)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_STATUS (0x1B0)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN (0x1B1)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_SET (0x1BA)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_INTEN_CLR (0x1BB)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_STATUS (0x1C0)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN (0x1C1)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_SET (0x1CA)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_INTEN_CLR (0x1CB)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_STATUS (0x1D0)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN (0x1D1)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_SET (0x1DA)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_INTEN_CLR (0x1DB)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_STATUS (0x1E0)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN (0x1E1)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_SET (0x1EA)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_INTEN_CLR (0x1EB)
> +#define OGMA_REG_ADDR_DEC_TX_STATUS (0x200)
> +#define OGMA_REG_ADDR_DEC_TX_INTEN (0x201)
> +#define OGMA_REG_ADDR_DEC_TX_INTEN_SET (0x20A)
> +#define OGMA_REG_ADDR_DEC_TX_INTEN_CLR (0x20B)
> +#define OGMA_REG_ADDR_ENC_RX_STATUS (0x210)
> +#define OGMA_REG_ADDR_ENC_RX_INTEN (0x211)
> +#define OGMA_REG_ADDR_ENC_RX_INTEN_SET (0x21A)
> +#define OGMA_REG_ADDR_ENC_RX_INTEN_CLR (0x21B)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_STATUS (0x220)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN (0x221)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_SET (0x22A)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_INTEN_CLR (0x22B)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_STATUS (0x230)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN (0x231)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_SET (0x23A)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_INTEN_CLR (0x23B)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_STATUS (0x240)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN (0x241)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_SET (0x24A)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_INTEN_CLR (0x24B)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_STATUS (0x250)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN (0x251)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_SET (0x25A)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_INTEN_CLR (0x25B)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_STATUS (0x260)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN (0x261)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_SET (0x26A)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_INTEN_CLR (0x26B)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_STATUS (0x270)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN (0x271)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_SET (0x27A)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_INTEN_CLR (0x27B)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_STATUS (0x280)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN (0x281)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_SET (0x28A)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_INTEN_CLR (0x28B)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_STATUS (0x290)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN (0x291)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_SET (0x29A)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_INTEN_CLR (0x29B)
> +#define OGMA_REG_ADDR_NRM_TX_PKTCNT (0x104)
> +#define OGMA_REG_ADDR_TAIKI_TX_PKTCNT (0x134)
> +#define OGMA_REG_ADDR_WL_NRM_TX_PKTCNT (0x154)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_PKTCNT (0x1A4)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_PKTCNT (0x174)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_PKTCNT (0x1C4)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_PKTCNT (0x204)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_PKTCNT (0x224)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_PKTCNT (0x234)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_PKTCNT (0x264)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_PKTCNT (0x274)
> +#define OGMA_REG_ADDR_NRM_TX_DONE_PKTCNT (0x105)
> +#define OGMA_REG_ADDR_TAIKI_TX_DONE_PKTCNT (0x135)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DONE_PKTCNT (0x155)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_PKTCNT (0x1A5)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_PKTCNT (0x175)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_PKTCNT (0x1C5)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_PKTCNT (0x205)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_PKTCNT (0x225)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_PKTCNT (0x235)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_PKTCNT (0x265)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_PKTCNT (0x275)
> +#define OGMA_REG_ADDR_NRM_TX_DONE_TXINT_PKTCNT (0x106)
> +#define OGMA_REG_ADDR_TAIKI_TX_DONE_TXINT_PKTCNT (0x136)
> +#define OGMA_REG_ADDR_WL_NRM_TX_DONE_TXINT_PKTCNT (0x156)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_DONE_TXINT_PKTCNT (0x1A6)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_DONE_TXINT_PKTCNT (0x176)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_DONE_TXINT_PKTCNT (0x1C6)
> +#define OGMA_REG_ADDR_DEC_PKT_TX_DONE_TXINT_PKTCNT (0x206)
> +#define OGMA_REG_ADDR_ENC_TLS_TX_DONE_TXINT_PKTCNT (0x226)
> +#define OGMA_REG_ADDR_DEC_TLS_TX_DONE_TXINT_PKTCNT (0x236)
> +#define OGMA_REG_ADDR_ENC_RAW_TX_DONE_TXINT_PKTCNT (0x266)
> +#define OGMA_REG_ADDR_DEC_RAW_TX_DONE_TXINT_PKTCNT (0x276)
> +#define OGMA_REG_ADDR_NRM_TX_TMR (0x107)
> +#define OGMA_REG_ADDR_TAIKI_TX_TMR (0x137)
> +#define OGMA_REG_ADDR_WL_NRM_TX_TMR (0x157)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TMR (0x177)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_TMR (0x1A7)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TMR (0x1C7)
> +#define OGMA_REG_ADDR_DEC_TX_TMR (0x207)
> +#define OGMA_REG_ADDR_NRM_TX_TXINT_TMR (0x108)
> +#define OGMA_REG_ADDR_TAIKI_TX_TXINT_TMR (0x138)
> +#define OGMA_REG_ADDR_WL_NRM_TX_TXINT_TMR (0x158)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_TX_TXINT_TMR (0x178)
> +#define OGMA_REG_ADDR_WL_TAIKI_TX_TXINT_TMR (0x1A8)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_TX_TXINT_TMR (0x1C8)
> +#define OGMA_REG_ADDR_DEC_TX_TXINT_TMR (0x208)
> +#define OGMA_REG_ADDR_NRM_RX_PKTCNT (0x115)
> +#define OGMA_REG_ADDR_TAIKI_RX_PKTCNT (0x125)
> +#define OGMA_REG_ADDR_MISC_RX_PKTCNT (0x145)
> +#define OGMA_REG_ADDR_WL_NRM_RX_PKTCNT (0x165)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_PKTCNT (0x185)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_PKTCNT (0x195)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_PKTCNT (0x1B5)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_PKTCNT (0x1D5)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_PKTCNT (0x1E5)
> +#define OGMA_REG_ADDR_ENC_PKT_RX_PKTCNT (0x215)
> +#define OGMA_REG_ADDR_ENC_TLS_RX_PKTCNT (0x245)
> +#define OGMA_REG_ADDR_DEC_TLS_RX_PKTCNT (0x255)
> +#define OGMA_REG_ADDR_ENC_RAW_RX_PKTCNT (0x285)
> +#define OGMA_REG_ADDR_DEC_RAW_RX_PKTCNT (0x295)
> +#define OGMA_REG_ADDR_NRM_RX_RXINT_PKTCNT (0x116)
> +#define OGMA_REG_ADDR_TAIKI_RXINT_PKTCNT (0x126)
> +#define OGMA_REG_ADDR_MISC_RXINT_PKTCNT (0x146)
> +#define OGMA_REG_ADDR_WL_NRM_RXINT_PKTCNT (0x166)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RXINT_PKTCNT (0x186)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RXINT_PKTCNT (0x196)
> +#define OGMA_REG_ADDR_WL_TAIKI_RXINT_PKTCNT (0x1B6)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RXINT_PKTCNT (0x1D6)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RXINT_PKTCNT (0x1E6)
> +#define OGMA_REG_ADDR_ENC_PKT_RXINT_PKTCNT (0x216)
> +#define OGMA_REG_ADDR_ENC_TLS_RXINT_PKTCNT (0x246)
> +#define OGMA_REG_ADDR_DEC_TLS_RXINT_PKTCNT (0x256)
> +#define OGMA_REG_ADDR_ENC_RAW_RXINT_PKTCNT (0x286)
> +#define OGMA_REG_ADDR_DEC_RAW_RXINT_PKTCNT (0x296)
> +#define OGMA_REG_ADDR_NRM_RX_TMR (0x117)
> +#define OGMA_REG_ADDR_TAIKI_RX_TMR (0x127)
> +#define OGMA_REG_ADDR_MISC_RX_TMR (0x147)
> +#define OGMA_REG_ADDR_WL_NRM_RX_TMR (0x167)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_TMR (0x187)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_TMR (0x197)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_TMR (0x1B7)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_TMR (0x1D7)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_TMR (0x1E7)
> +#define OGMA_REG_ADDR_NRM_RX_RXINT_TMR (0x118)
> +#define OGMA_REG_ADDR_TAIKI_RX_RXINT_TMR (0x128)
> +#define OGMA_REG_ADDR_MISC_RX_RXINT_TMR (0x148)
> +#define OGMA_REG_ADDR_WL_NRM_RX_RXINT_TMR (0x168)
> +#define OGMA_REG_ADDR_WL_NRM_CMD_RX_RXINT_TMR (0x188)
> +#define OGMA_REG_ADDR_WL_NRM_EVENT_RX_RXINT_TMR (0x198)
> +#define OGMA_REG_ADDR_WL_TAIKI_RX_RXINT_TMR (0x1B8)
> +#define OGMA_REG_ADDR_WL_TAIKI_CMD_RX_RXINT_TMR (0x1D8)
> +#define OGMA_REG_ADDR_WL_TAIKI_EVENT_RX_RXINT_TMR (0x1E8)
> +#define OGMA_REG_ADDR_PODB_CMD_ST (0x20)
> +#define OGMA_REG_ADDR_PODB_DATA (0x21)
> +#define OGMA_REG_ADDR_CLS_VAL_CMD (0x2A)
> +#define OGMA_REG_ADDR_CLS_VAL_DATA (0x2B)
> +#define OGMA_REG_ADDR_CLS_CMD_ST (0x2C)
> +#define OGMA_REG_ADDR_CLS_DATA (0x2D)
> +#define OGMA_REG_ADDR_SADB_CMD_ST (0x2E)
> +#define OGMA_REG_ADDR_SADB_DATA (0x2F)
> +#define OGMA_REG_ADDR_MAC_CMD (0x471)
> +#define OGMA_REG_ADDR_MAC_DATA (0x470)
> +#define OGMA_REG_ADDR_MAC_FLOW_TH (0x473)
> +#define OGMA_REG_ADDR_MAC_INTF_SEL (0x475)
> +#define OGMA_REG_ADDR_MAC_TX_TSTAMP_LW (0x476)
> +#define OGMA_REG_ADDR_MAC_TX_TSTAMP_UP (0x477)
> +#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_UP (0x478)
> +#define OGMA_REG_ADDR_MAC_CAP_TSTAMP_LW (0x479)
> +#define OGMA_REG_ADDR_MAC_TSTAM_CAP (0x47A)
> +#define OGMA_REG_ADDR_MAC_SNAP_TRIG (0x47B)
> +#define OGMA_REG_ADDR_MAC_SEC_CNT (0x47C)
> +#define OGMA_REG_ADDR_MAC_DESC_INIT (0x47F)
> +#define OGMA_REG_ADDR_MAC_TX_TS_GET (0x480)
> +#define OGMA_REG_ADDR_MAC_DESC_SOFT_RST (0x481)
> +#define OGMA_REG_ADDR_IV_INIT_VAL (0x45)
> +#define OGMA_REG_ADDR_MAC_ADD_UP (0x43)
> +#define OGMA_REG_ADDR_MAC_ADD_LW (0x44)
> +#define OGMA_REG_ADDR_ST_INFO_ST_UP (0x65)
> +#define OGMA_REG_ADDR_ST_INFO_ST_LW (0x66)
> +#define OGMA_REG_ADDR_ST_INFO_SIZE (0x67)
> +#define OGMA_REG_ADDR_ST_INFO_TX_ST (0x68)
> +#define OGMA_REG_ADDR_LOGIC_GR_ID (0x69)
> +#define OGMA_REG_ADDR_ST_FOR_PBC (0x6A)
> +#define OGMA_REG_ADDR_ALARM_INFO (0x6B)
> +#define OGMA_REG_ADDR_MC_VER (0x8B)
> +#define OGMA_REG_ADDR_HW_VER (0x8C)
> +
> +#define OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS (0x140)
> +
> +#endif /* OGMA_REG_F_TAIKI_H */
> +
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
> new file mode 100644
> index 000000000000..1caf64e30623
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
> @@ -0,0 +1,25 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef OGMA_CONFIG_H
> +#define OGMA_CONFIG_H
> +
> +#define OGMA_CONFIG_CLK_HZ 125000000UL
> +#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL
> +#define OGMA_CONFIG_CHECK_CLK_SUPPLY
> +
> +#define OGMA_CONFIG_USE_READ_GMAC_STAT
> +
> +#endif /* OGMA_CONFIG_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
> new file mode 100644
> index 000000000000..f617f1c70183
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep.h
> @@ -0,0 +1,265 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef PFDEP_H
> +#define PFDEP_H
> +
> +#include <stdio.h>
> +#include <stdint.h>
> +#include <string.h>

Whut?
Can we get rid of these?

/
    Leif

> +#include <Library/BaseLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <Protocol/Cpu.h>
> +
> +extern EFI_CPU_ARCH_PROTOCOL      *mCpu;
> +
> +/**********************************************************************
> + * Constant definitions
> + **********************************************************************/
> +#define PFDEP_INT64_AVAILABLE
> +
> +/**********************************************************************
> + * Elementary type definitions
> + **********************************************************************/
> +typedef int8_t pfdep_int8;
> +typedef uint8_t pfdep_uint8;
> +typedef int16_t pfdep_int16;
> +typedef uint16_t pfdep_uint16;
> +typedef int pfdep_int32;
> +typedef unsigned int pfdep_uint32;
> +typedef int64_t pfdep_int64;
> +typedef uint64_t pfdep_uint64;
> +typedef int pfdep_bool;
> +typedef char pfdep_char;
> +
> +#define PFDEP_TRUE ((pfdep_bool)1)
> +#define PFDEP_FALSE ((pfdep_bool)0)
> +
> +
> +/**********************************************************************
> + * Complex type definitions
> + **********************************************************************/
> +
> +typedef enum pfdep_err_e {
> +    PFDEP_ERR_OK = 0,
> +    PFDEP_ERR_PARAM,
> +    PFDEP_ERR_ALLOC,
> +    PFDEP_ERR_INTERRUPT
> +} pfdep_err_t;
> +
> +
> +typedef struct {
> +    LIST_ENTRY  Link;
> +    VOID        *Buffer;
> +    VOID        *Mapping;
> +    BOOLEAN     RecycleForTx;
> +    BOOLEAN     Released;
> +} PACKET_HANDLE;
> +
> +typedef VOID *pfdep_dev_handle_t;
> +typedef PACKET_HANDLE *pfdep_pkt_handle_t;
> +typedef EFI_PHYSICAL_ADDRESS pfdep_phys_addr_t;
> +typedef UINT64 pfdep_cpu_addr_t;
> +
> +typedef int pfdep_hard_lock_t;
> +typedef int pfdep_soft_lock_t;
> +
> +typedef BOOLEAN pfdep_hard_lock_ctx_t;
> +typedef int pfdep_soft_lock_ctx_t;
> +
> +typedef unsigned int pfdep_debug_level_t;
> +
> +#define PFDEP_DEBUG_LEVEL_FATAL               ((pfdep_debug_level_t)1)
> +#define PFDEP_DEBUG_LEVEL_WARNING             ((pfdep_debug_level_t)2)
> +#define PFDEP_DEBUG_LEVEL_NOTICE              ((pfdep_debug_level_t)3)
> +#define PFDEP_DEBUG_LEVEL_DEBUG               ((pfdep_debug_level_t)4)
> +#define PFDEP_DEBUG_LEVEL_DEBUG_DETAILED      ((pfdep_debug_level_t)5)
> +#define PFDEP_DEBUG_LEVEL_DEBUG_MORE_DETAILED ((pfdep_debug_level_t)6)
> +
> +/**********************************************************************
> + * Variable declarations
> + **********************************************************************/
> +extern pfdep_debug_level_t pfdep_debug_level; /* defined in pfdep_uefi.c */
> +
> +
> +/**********************************************************************
> + * Function declarations
> + **********************************************************************/
> +
> +static __inline pfdep_uint32 pfdep_iomem_read(void *addr)
> +{
> +    return *((volatile pfdep_uint32 *)(addr));
> +}
> +
> +static __inline void pfdep_iomem_write(void *addr, pfdep_uint32 val)
> +{
> +    *((volatile pfdep_uint32 *)(addr)) = val;
> +
> +
> +}
> +
> +#define pfdep_read_mem_barrier()    MemoryFence()
> +#define pfdep_write_mem_barrier()   MemoryFence()
> +#define pfdep_mem_barrier()         MemoryFence()
> +
> +void *pfdep_malloc(pfdep_uint32 len);
> +
> +void pfdep_free(void *addr);
> +
> +pfdep_err_t pfdep_dma_malloc (
> +    pfdep_dev_handle_t dev_handle,
> +    pfdep_uint32 len,
> +    void **addr_p,
> +    pfdep_phys_addr_t *phys_addr_p
> +    );
> +
> +void pfdep_dma_free (
> +    pfdep_dev_handle_t dev_handle,
> +    pfdep_uint32 len,
> +    void *addr,
> +    pfdep_phys_addr_t phys_addr
> +    );
> +
> +pfdep_err_t pfdep_alloc_pkt_buf (
> +    pfdep_dev_handle_t dev_handle,
> +    pfdep_uint16 len,
> +    void **addr_p,
> +    pfdep_phys_addr_t *phys_addr_p,
> +    pfdep_pkt_handle_t *pkt_handle_p
> +    );
> +
> +void pfdep_free_pkt_buf (
> +    pfdep_dev_handle_t dev_handle,
> +    pfdep_uint16 len,
> +    void *addr,
> +    pfdep_phys_addr_t phys_addr,
> +    pfdep_bool last_flag,
> +    pfdep_pkt_handle_t pkt_handle
> +    );
> +
> +static __inline pfdep_err_t pfdep_init_hard_lock(pfdep_hard_lock_t *hard_lock_p)
> +{
> +    (void)hard_lock_p; /* suppress compiler warning */
> +    return PFDEP_ERR_OK;
> +}
> +
> +static __inline void pfdep_uninit_hard_lock(pfdep_hard_lock_t *hard_lock_p)
> +{
> +    (void)hard_lock_p; /* suppress compiler warning */
> +    return;
> +}
> +
> +static __inline void pfdep_acquire_hard_lock (
> +    pfdep_hard_lock_t *hard_lock_p, /* not used */
> +    pfdep_hard_lock_ctx_t *ctx_p
> +    )
> +{
> +    (void)hard_lock_p; /* suppress compiler warning */
> +
> +    *ctx_p = SaveAndDisableInterrupts();
> +}
> +
> +
> +static __inline void pfdep_release_hard_lock (
> +    pfdep_hard_lock_t *hard_lock_p, /* not used */
> +    pfdep_hard_lock_ctx_t *ctx_p
> +    )
> +{
> +    (void)hard_lock_p; /* suppress compiler warning */
> +
> +    SetInterruptState(*ctx_p);
> +}
> +
> +static __inline pfdep_err_t pfdep_init_soft_lock (
> +    pfdep_soft_lock_t *soft_lock_p
> +    )
> +{
> +    *soft_lock_p = 0; /* suppress compiler warning */
> +
> +    return PFDEP_ERR_OK;
> +}
> +
> +static __inline void pfdep_uninit_soft_lock (
> +    pfdep_soft_lock_t *soft_lock_p
> +    )
> +{
> +    (void)soft_lock_p; /* suppress compiler warning */
> +
> +    return;
> +}
> +
> +static __inline pfdep_err_t pfdep_acquire_soft_lock (
> +    pfdep_soft_lock_t *soft_lock_p,
> +    pfdep_soft_lock_ctx_t *ctx_p
> +    )
> +{
> +    (void)soft_lock_p; /* suppress compiler warning */
> +    (void)ctx_p; /* suppress compiler warning */
> +
> +    return PFDEP_ERR_OK;
> +}
> +
> +static __inline void pfdep_release_soft_lock (
> +    pfdep_soft_lock_t *soft_lock_p,
> +    pfdep_soft_lock_ctx_t *ctx_p
> +    )
> +{
> +    (void)soft_lock_p; /* suppress compiler warning */
> +    (void)ctx_p; /* suppress compiler warning */
> +}
> +
> +
> +static __inline void pfdep_memcpy(void *dst_p, const void *src_p, pfdep_uint32 len)
> +{
> +    memcpy(dst_p, src_p, (size_t)len);
> +}
> +
> +static __inline void pfdep_memset(void *dst_p, pfdep_uint8 c, pfdep_uint32 len)
> +{
> +    memset(dst_p, c, (size_t)len);
> +}
> +
> +static __inline pfdep_err_t pfdep_msleep(pfdep_uint32 wait_ms)
> +{
> +
> +    MicroSecondDelay ((UINTN)wait_ms * 1000);
> +
> +    return PFDEP_ERR_OK;
> +}
> +
> +#define pfdep_print(level,...) \
> +do { \
> +    if (level <= pfdep_debug_level) { \
> +        DEBUG ((DEBUG_INFO, "[NETSEC] " __VA_ARGS__)); \
> +    } \
> +} while (0)
> +
> +
> +static __inline pfdep_debug_level_t pfdep_get_debug_level(void)
> +{
> +    return pfdep_debug_level;
> +}
> +
> +static __inline void pfdep_set_debug_level(pfdep_debug_level_t level)
> +{
> +    pfdep_debug_level = level;
> +}
> +
> +
> +#define pfdep_assert(cond)      ASSERT(cond)
> +
> +#endif /* PFDEP_H */
> diff --git a/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
> new file mode 100644
> index 000000000000..b43d1aaff037
> --- /dev/null
> +++ b/Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/netsec_for_uefi/pfdep_uefi.c
> @@ -0,0 +1,176 @@
> +/** @file
> +
> +  Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
> +  Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
> +
> +  This program and the accompanying materials
> +  are licensed and made available under the terms and conditions of the BSD License
> +  which accompanies this distribution.  The full text of the license may be found at
> +  http://opensource.org/licenses/bsd-license.php
> +
> +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "pfdep.h"
> +
> +#include <Library/DebugLib.h>
> +#include <Library/DmaLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/NetLib.h>
> +#include <Library/SynchronizationLib.h>
> +
> +/**********************************************************************
> + * Variable definitions
> + **********************************************************************/
> +pfdep_debug_level_t pfdep_debug_level = PFDEP_DEBUG_LEVEL_NOTICE;
> +
> +
> +/**********************************************************************
> + * Function definitions
> + **********************************************************************/
> +
> +VOID*
> +pfdep_malloc (
> +  IN  pfdep_uint32    len
> +  )
> +{
> +  return AllocatePool (len);
> +}
> +
> +VOID
> +pfdep_free (
> +  IN  VOID       *addr
> +  )
> +{
> +  FreePool (addr);
> +}
> +
> +pfdep_err_t
> +pfdep_dma_malloc (
> +  IN  pfdep_dev_handle_t        dev_handle,
> +  IN  pfdep_uint32              len,
> +  OUT VOID                      **addr_p,
> +  OUT pfdep_phys_addr_t         *phys_addr_p
> +  )
> +{
> +  EFI_STATUS    Status;
> +  UINTN         NumPages;
> +  UINTN         NumBytes;
> +  VOID          **Mapping;
> +
> +  NumPages = EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof *Mapping);
> +  Status = DmaAllocateBuffer (EfiBootServicesData, NumPages, addr_p);
> +  if (EFI_ERROR (Status)) {
> +    return PFDEP_ERR_ALLOC;
> +  }
> +
> +  //
> +  // Stash the address of the MAPINFO struct at the end of the buffer,
> +  // but make sure it appears aligned (the memory may be mapped uncached)
> +  //
> +  Mapping = (VOID **)((UINTN)*addr_p + ALIGN_VARIABLE(len));
> +
> +  NumBytes = EFI_PAGES_TO_SIZE (NumPages);
> +  Status = DmaMap (MapOperationBusMasterCommonBuffer, *addr_p, &NumBytes,
> +             phys_addr_p, Mapping);
> +
> +  if (EFI_ERROR (Status) || NumBytes < len) {
> +    DmaFreeBuffer (NumPages, *addr_p);
> +    return PFDEP_ERR_ALLOC;
> +  }
> +
> +  return PFDEP_ERR_OK;
> +}
> +
> +VOID
> +pfdep_dma_free (
> +  IN  pfdep_dev_handle_t        dev_handle,
> +  IN  pfdep_uint32              len,
> +  IN  VOID                      *addr,
> +  IN  pfdep_phys_addr_t         phys_addr
> +  )
> +{
> +  VOID          *Mapping;
> +
> +  Mapping = *(VOID **)((UINTN)addr + ALIGN_VARIABLE(len));
> +
> +  DmaUnmap (Mapping);
> +  DmaFreeBuffer (EFI_SIZE_TO_PAGES (ALIGN_VARIABLE(len) + sizeof Mapping),
> +    addr);
> +}
> +
> +//
> +// On the receive path, we allocate a new packet and link it into the RX ring
> +// before returning the received packet to the caller. This means we perform
> +// one allocation and one free operation for each buffer received.
> +// So let's cache a single packet, and get rid of most of the alloc/free
> +// overhead on the RX path.
> +//
> +STATIC pfdep_pkt_handle_t mSparePacketBuffer;
> +STATIC UINT32 mSparePacketBufferSize;
> +
> +pfdep_err_t
> +pfdep_alloc_pkt_buf (
> +  IN  pfdep_dev_handle_t        dev_handle,
> +  IN  pfdep_uint16              len,
> +  OUT VOID                      **addr_p,
> +  OUT pfdep_phys_addr_t         *phys_addr_p,
> +  OUT pfdep_pkt_handle_t        *pkt_handle_p
> +  )
> +{
> +  EFI_STATUS    Status;
> +  UINTN         NumBytes;
> +
> +  NumBytes = ALIGN_VALUE (len, mCpu->DmaBufferAlignment);
> +
> +  if (InterlockedCompareExchange32 (&mSparePacketBufferSize, len, 0) == len) {
> +    *pkt_handle_p = mSparePacketBuffer;
> +  } else {
> +    *pkt_handle_p = AllocateZeroPool (NumBytes + sizeof(PACKET_HANDLE) +
> +                                      (mCpu->DmaBufferAlignment - 8));
> +    if (*pkt_handle_p == NULL) {
> +      return PFDEP_ERR_ALLOC;
> +    }
> +
> +    (*pkt_handle_p)->Buffer = ALIGN_POINTER (*pkt_handle_p,
> +                                             mCpu->DmaBufferAlignment);
> +  }
> +
> +  *addr_p = (*pkt_handle_p)->Buffer;
> +  Status = DmaMap (MapOperationBusMasterWrite, *addr_p, &NumBytes, phys_addr_p,
> +             &(*pkt_handle_p)->Mapping);
> +  if (EFI_ERROR (Status) || NumBytes < len) {
> +    FreePool (*pkt_handle_p);
> +    return PFDEP_ERR_ALLOC;
> +  }
> +  return PFDEP_ERR_OK;
> +}
> +
> +VOID
> +pfdep_free_pkt_buf (
> +  IN  pfdep_dev_handle_t        dev_handle,
> +  IN  pfdep_uint16              len,
> +  IN  VOID                      *addr,
> +  IN  pfdep_phys_addr_t         phys_addr,
> +  IN  pfdep_bool                last_flag,
> +  IN  pfdep_pkt_handle_t        pkt_handle
> +  )
> +{
> +  if (last_flag != PFDEP_TRUE) {
> +    return;
> +  }
> +
> +  if (pkt_handle->Mapping != NULL) {
> +    DmaUnmap (pkt_handle->Mapping);
> +  }
> +
> +  if (pkt_handle->RecycleForTx) {
> +      pkt_handle->Released = TRUE;
> +  } else if (!InterlockedCompareExchange32 (&mSparePacketBufferSize, 0, len)) {
> +    mSparePacketBuffer = pkt_handle;
> +  } else {
> +    FreePool (pkt_handle);
> +  }
> +}
> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver
Posted by Ard Biesheuvel, 2 weeks ago
Add the NETSEC driver to the SynquacerEvalBoard platform.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 34 ++++++++++++++++++++
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 17 ++++++++++
 2 files changed, 51 insertions(+)

diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index aea39b46d91b..3d4fbc87e2fa 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -217,6 +217,20 @@
   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
 
+  #
+  # NETSEC Info
+  #
+  gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x522D0000
+  gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x10000000
+  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|128
+  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|128
+  gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36
+  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48
+  gNetsecDxeTokenSpaceGuid.PcdPauseTime|256
+  gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|1
+
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
@@ -441,3 +455,23 @@
   # RNG
   #
   Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
+
+  #
+  # Networking stack
+  #
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
+    <LibraryClasses>
+      DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+  }
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index befad354918e..bd06adf93b3c 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -166,6 +166,23 @@ READ_LOCK_STATUS   = TRUE
   #
   INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
 
+  #
+  # Networking stack
+  #
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+  INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
+
 [FV.FVMAIN_COMPACT]
 FvAlignment        = 8
 ERASE_POLARITY     = 1
-- 
2.11.0

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Re: [edk2] [PATCH edk2-platforms 09/14] Platform/SynquacerEvalBoard: add NETSEC driver
Posted by Leif Lindholm, 1 week ago
On Fri, Sep 08, 2017 at 07:23:10PM +0100, Ard Biesheuvel wrote:
> Add the NETSEC driver to the SynquacerEvalBoard platform.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc | 34 ++++++++++++++++++++
>  Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf | 17 ++++++++++
>  2 files changed, 51 insertions(+)
> 
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> index aea39b46d91b..3d4fbc87e2fa 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
> @@ -217,6 +217,20 @@
>    gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a440000
>    gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a450000
>  
> +  #
> +  # NETSEC Info
> +  #
> +  gNetsecDxeTokenSpaceGuid.PcdNetsecDxeBaseAddress|0x522D0000
> +  gNetsecDxeTokenSpaceGuid.PcdEepRomBase|0x10000000
> +  gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|128
> +  gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|128
> +  gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36
> +  gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48
> +  gNetsecDxeTokenSpaceGuid.PcdPauseTime|256
> +  gNetsecDxeTokenSpaceGuid.PcdPhyDevAddr|1
> +
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> @@ -441,3 +455,23 @@
>    # RNG
>    #
>    Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
> +
> +  #
> +  # Networking stack
> +  #
> +  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> +  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> +  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> +  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> +  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> +  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> +  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> +  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> +  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> +  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf

So, I'm going to take my couple of days to hack on config fragments
from tomorrow, so you may just want to wait on that - but otherwise,
IPv6 and HTTP boot would be nice.

/
    Leif

> +  Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
> +    <LibraryClasses>
> +      DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> +  }
> diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> index befad354918e..bd06adf93b3c 100644
> --- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> +++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
> @@ -166,6 +166,23 @@ READ_LOCK_STATUS   = TRUE
>    #
>    INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf
>  
> +  #
> +  # Networking stack
> +  #
> +  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> +  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> +  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> +  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> +  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> +  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> +  INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> +  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> +  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> +  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +  INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
> +
>  [FV.FVMAIN_COMPACT]
>  FvAlignment        = 8
>  ERASE_POLARITY     = 1
> -- 
> 2.11.0
> 
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[edk2] [PATCH edk2-platforms 10/14] Silicon/Synquacer: add ACPI support
Posted by Ard Biesheuvel, 2 weeks ago
Enable ACPI support for the SynquacerEvalBoard platform: add descriptions
of the CPUs, the GIC, the serial port, the timers and the PCIe RCs,
including the MSI routing via the GICv3 ITS.

Note that PCIe support is limited to a single bus per RC. Anything beyond
that is unsupported due to a limitation in the hardware that makes it
impossible to expose the PCIe RCs in a fully ECAM compliant manner.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc |  14 +
 Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf |  13 +
 Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl   | 292 ++++++++++++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h          |  58 ++++
 Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf        |  58 ++++
 Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl              | 168 +++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc             |  88 ++++++
 Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc             |  98 +++++++
 Silicon/Socionext/Synquacer/AcpiTables/Iort.aslc             | 164 +++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/Madt.aslc             | 152 ++++++++++
 Silicon/Socionext/Synquacer/AcpiTables/Mcfg.aslc             |  63 +++++
 Silicon/Socionext/Synquacer/AcpiTables/Spcr.aslc             | 127 +++++++++
 12 files changed, 1295 insertions(+)

diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
index 3d4fbc87e2fa..b2befd2480c4 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.dsc
@@ -475,3 +475,17 @@
     <LibraryClasses>
       DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
   }
+
+  #
+  # ACPI support
+  #
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+    <LibraryClasses>
+      #NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
+
+    <PcdsFixedAtBuild>
+      # support ACPI v5.0 or later
+      gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+  }
+  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
diff --git a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
index bd06adf93b3c..35742ad5a347 100644
--- a/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
+++ b/Platform/Socionext/SynquacerEvalBoard/SynquacerEvalBoard.fdf
@@ -183,6 +183,13 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
   INF Silicon/Socionext/Synquacer/Drivers/Net/NetsecDxe/NetsecDxe.inf
 
+  #
+  # ACPI support
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+  INF RuleOverride = ACPITABLE Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
+
 [FV.FVMAIN_COMPACT]
 FvAlignment        = 8
 ERASE_POLARITY     = 1
@@ -329,3 +336,9 @@ READ_LOCK_STATUS   = TRUE
     UI        STRING="$(MODULE_NAME)" Optional
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
   }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
new file mode 100644
index 000000000000..f8d503d65ead
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiSsdtRootPci.asl
@@ -0,0 +1,292 @@
+/** @file
+  Secondary System Description Table (SSDT) for Synquacer PCIe RCs
+
+  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Platform/Pcie.h>
+
+#include "AcpiTables.h"
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
+  Scope(_SB) {
+    //
+    // PCI Root Complex
+    //
+    Device(PCI0)
+    {
+        Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge
+        Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge
+        Name(_SEG, Zero)                // PCI Segment Group number
+        Name(_BBN, Zero)                // PCI Base Bus Number
+        Name(_CCA, 1)                   // Cache Coherency Attribute
+
+        // PCI Routing Table
+        Name(_PRT, Package() {
+            Package () { 0xFFFF, 0, Zero, 222 },   // INTA
+            Package () { 0xFFFF, 1, Zero, 222 },   // INTB
+            Package () { 0xFFFF, 2, Zero, 222 },   // INTC
+            Package () { 0xFFFF, 3, Zero, 222 },   // INTD
+        })
+        // Root complex resources
+        Method (_CRS, 0, Serialized) {
+            Name (RBUF, ResourceTemplate () {
+                WordBusNumber ( // Bus numbers assigned to this root
+                    ResourceProducer,
+                    MinFixed, MaxFixed, PosDecode,
+                    0,                              // AddressGranularity
+                    SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMinimum - Minimum Bus Number
+                    SYNQUACER_PCI_SEG0_BUSNUM_MIN,  // AddressMaximum - Maximum Bus Number
+                    0,                              // AddressTranslation - Set to 0
+                    1                               // RangeLength - Number of Busses
+                )
+
+                DWordMemory ( // 32-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG0_MMIO32_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG0_MMIO32_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG0_MMIO32_SIZE      // Length
+                )
+
+                QWordMemory ( // 64-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG0_MMIO64_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG0_MMIO64_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG0_MMIO64_SIZE      // Length
+                )
+
+                DWordIo ( // IO window
+                    ResourceProducer,
+                    MinFixed,
+                    MaxFixed,
+                    PosDecode,
+                    EntireRange,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG0_PORTIO_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG0_PORTIO_MAX,      // Max Base Address
+                    SYNQUACER_PCI_SEG0_PORTIO_MEMBASE,  // Translate
+                    SYNQUACER_PCI_SEG0_PORTIO_SIZE,     // Length
+                    ,
+                    ,
+                    ,
+                    TypeTranslation
+                )
+            }) // Name(RBUF)
+
+            Return (RBUF)
+        } // Method(_CRS)
+
+        Device (RES0)
+        {
+            Name (_HID, "PNP0C02")
+            Name (_CRS, ResourceTemplate ()
+            {
+                Memory32Fixed (ReadWrite,
+                               SYNQUACER_PCI_SEG0_CONFIG_BASE,
+                               SYNQUACER_PCI_SEG0_CONFIG_SIZE)
+            })
+        }
+
+        //
+        // OS Control Handoff
+        //
+        Name(SUPP, Zero) // PCI _OSC Support Field value
+        Name(CTRL, Zero) // PCI _OSC Control Field value
+
+        /*
+      See [1] 6.2.10, [2] 4.5
+        */
+        Method(_OSC,4) {
+            // Check for proper UUID
+            If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+                // Create DWord-adressable fields from the Capabilities Buffer
+                CreateDWordField(Arg3,0,CDW1)
+                CreateDWordField(Arg3,4,CDW2)
+                CreateDWordField(Arg3,8,CDW3)
+
+                // Save Capabilities DWord2 & 3
+                Store(CDW2,SUPP)
+                Store(CDW3,CTRL)
+
+                // Only allow native hot plug control if OS supports:
+                // * ASPM
+                // * Clock PM
+                // * MSI/MSI-X
+                If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+                    And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+                }
+
+                // Always allow native PME, AER (no dependencies)
+
+                // Never allow SHPC (no SHPC controller in this system)
+                And(CTRL,0x1D,CTRL)
+
+                If(LNotEqual(Arg1,One)) {    // Unknown revision
+                    Or(CDW1,0x08,CDW1)
+                }
+
+                If(LNotEqual(CDW3,CTRL)) {    // Capabilities bits were masked
+                    Or(CDW1,0x10,CDW1)
+                }
+                // Update DWORD3 in the buffer
+                Store(CTRL,CDW3)
+                Return(Arg3)
+            } Else {
+                Or(CDW1,4,CDW1) // Unrecognized UUID
+                Return(Arg3)
+            }
+        } // End _OSC
+    } // PCI0
+
+    Device(PCI1)
+    {
+        Name(_HID, EISAID("PNP0A08"))   // PCI Express Root Bridge
+        Name(_CID, EISAID("PNP0A03"))   // Compatible PCI Root Bridge
+        Name(_SEG, 1)                   // PCI Segment Group number
+        Name(_BBN, Zero)                // PCI Base Bus Number
+        Name(_CCA, 1)                   // Cache Coherency Attribute
+
+        // PCI Routing Table
+        Name(_PRT, Package() {
+            Package () { 0xFFFF, 0, Zero, 214 },   // INTA
+            Package () { 0xFFFF, 1, Zero, 214 },   // INTB
+            Package () { 0xFFFF, 2, Zero, 214 },   // INTC
+            Package () { 0xFFFF, 3, Zero, 214 },   // INTD
+        })
+        // Root complex resources
+        Method (_CRS, 0, Serialized) {
+            Name (RBUF, ResourceTemplate () {
+                WordBusNumber ( // Bus numbers assigned to this root
+                    ResourceProducer,
+                    MinFixed, MaxFixed, PosDecode,
+                    0,                              // AddressGranularity
+                    SYNQUACER_PCI_SEG1_BUSNUM_MIN,  // AddressMinimum - Minimum Bus Number
+                    SYNQUACER_PCI_SEG1_BUSNUM_MIN,  // AddressMaximum - Maximum Bus Number
+                    0,                              // AddressTranslation - Set to 0
+                    1                               // RangeLength - Number of Busses
+                )
+
+                DWordMemory ( // 32-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG1_MMIO32_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG1_MMIO32_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG1_MMIO32_SIZE      // Length
+                )
+
+                QWordMemory ( // 64-bit BAR Windows
+                    ResourceProducer, PosDecode,
+                    MinFixed, MaxFixed,
+                    Cacheable, ReadWrite,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG1_MMIO64_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG1_MMIO64_MAX,      // Max Base Address
+                    0x00000000,                         // Translate
+                    SYNQUACER_PCI_SEG1_MMIO64_SIZE      // Length
+                )
+
+                DWordIo ( // IO window
+                    ResourceProducer,
+                    MinFixed,
+                    MaxFixed,
+                    PosDecode,
+                    EntireRange,
+                    0x00000000,                         // Granularity
+                    SYNQUACER_PCI_SEG1_PORTIO_MIN,      // Min Base Address
+                    SYNQUACER_PCI_SEG1_PORTIO_MAX,      // Max Base Address
+                    SYNQUACER_PCI_SEG1_PORTIO_MEMBASE,  // Translate
+                    SYNQUACER_PCI_SEG1_PORTIO_SIZE,     // Length
+                    ,
+                    ,
+                    ,
+                    TypeTranslation
+                )
+            }) // Name(RBUF)
+
+            Return (RBUF)
+        } // Method(_CRS)
+
+        Device (RES0)
+        {
+            Name (_HID, "PNP0C02")
+            Name (_CRS, ResourceTemplate ()
+            {
+                Memory32Fixed (ReadWrite,
+                               SYNQUACER_PCI_SEG1_CONFIG_BASE,
+                               SYNQUACER_PCI_SEG1_CONFIG_SIZE)
+            })
+        }
+
+        //
+        // OS Control Handoff
+        //
+        Name(SUPP, Zero) // PCI _OSC Support Field value
+        Name(CTRL, Zero) // PCI _OSC Control Field value
+
+        /*
+      See [1] 6.2.10, [2] 4.5
+        */
+        Method(_OSC,4) {
+            // Check for proper UUID
+            If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+                // Create DWord-adressable fields from the Capabilities Buffer
+                CreateDWordField(Arg3,0,CDW1)
+                CreateDWordField(Arg3,4,CDW2)
+                CreateDWordField(Arg3,8,CDW3)
+
+                // Save Capabilities DWord2 & 3
+                Store(CDW2,SUPP)
+                Store(CDW3,CTRL)
+
+                // Only allow native hot plug control if OS supports:
+                // * ASPM
+                // * Clock PM
+                // * MSI/MSI-X
+                If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+                    And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+                }
+
+                // Always allow native PME, AER (no dependencies)
+
+                // Never allow SHPC (no SHPC controller in this system)
+                And(CTRL,0x1D,CTRL)
+
+                If(LNotEqual(Arg1,One)) {    // Unknown revision
+                    Or(CDW1,0x08,CDW1)
+                }
+
+                If(LNotEqual(CDW3,CTRL)) {    // Capabilities bits were masked
+                    Or(CDW1,0x10,CDW1)
+                }
+                // Update DWORD3 in the buffer
+                Store(CTRL,CDW3)
+                Return(Arg3)
+            } Else {
+                Or(CDW1,4,CDW1) // Unrecognized UUID
+                Return(Arg3)
+            }
+        } // End _OSC
+    } // PCI0
+  }
+}
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
new file mode 100644
index 000000000000..73fe4f5caa3e
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.h
@@ -0,0 +1,58 @@
+/** @file
+*
+*  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ACPITABLES_H__
+#define __ACPITABLES_H__
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID           'L','I','N','A','R','O'   // OEMID 6 bytes long
+#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('S','Y','N','Q','U','A','C','R') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION     0x20170802
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('L','N','R','O')
+#define EFI_ACPI_CREATOR_REVISION 0x00000001
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define __ACPI_HEADER(Signature, Type, Revision) {                \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_OEM_ID },            /* UINT8   OemId[6] */        \
+    EFI_ACPI_OEM_TABLE_ID,          /* UINT64  OemTableId */      \
+    EFI_ACPI_OEM_REVISION,          /* UINT32  OemRevision */     \
+    EFI_ACPI_CREATOR_ID,            /* UINT32  CreatorId */       \
+    EFI_ACPI_CREATOR_REVISION       /* UINT32  CreatorRevision */ \
+  }
+
+#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+  { \
+    EFI_ACPI_6_0_GICR, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), 0, RedisRegionAddr, RedisDiscLength \
+  }
+
+#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \
+  { EFI_ACPI_6_0_GIC_ITS, sizeof(EFI_ACPI_6_0_GIC_ITS_STRUCTURE), 0, Id, PhysAddress, 0 }
+
+#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhysicalAddress,                  \
+    ControlFramePhysicalAddress, WatchdogTimerGSIV, WatchdogTimerFlags)                                 \
+  {                                                                                                     \
+    EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \
+    EFI_ACPI_RESERVED_WORD, RefreshFramePhysicalAddress, ControlFramePhysicalAddress,                   \
+    WatchdogTimerGSIV, WatchdogTimerFlags                                                               \
+  }
+
+#endif
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..f390797b9d4f
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/AcpiTables.inf
@@ -0,0 +1,58 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+#  Copyright (c) 2017, Linaro Ltd. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SynquacerAcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  AcpiTables.h
+  AcpiSsdtRootPci.asl
+  Dsdt.asl
+  Fadt.aslc
+  Gtdt.aslc
+  Iort.aslc
+  Madt.aslc
+  Mcfg.aslc
+  Spcr.aslc
+
+[Packages]
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  ArmPkg/ArmPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Socionext/Synquacer/Synquacer.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
new file mode 100644
index 000000000000..dc32a34ccfa2
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Dsdt.asl
@@ -0,0 +1,168 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "AcpiTables.h"
+
+#include <Platform/MemoryMap.h>
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "LINARO", "SYNQUACR", EFI_ACPI_OEM_REVISION) {
+  Scope(_SB) {
+    //
+    // A53x4 Processor declaration
+    //
+    Device(CP00) { // A53-0: Cluster 0, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 0)
+    }
+    Device(CP01) { // A53-0: Cluster 0, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 1)
+    }
+
+    Device(CP04) { // A53-0: Cluster 1, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 2)
+    }
+    Device(CP05) { // A53-0: Cluster 1, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 3)
+    }
+
+    Device(CP08) { // A53-0: Cluster 2, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 4)
+    }
+    Device(CP09) { // A53-0: Cluster 2, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 5)
+    }
+
+    Device(CP12) { // A53-0: Cluster 3, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 6)
+    }
+    Device(CP13) { // A53-0: Cluster 3, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 7)
+    }
+
+    Device(CP16) { // A53-0: Cluster 4, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 8)
+    }
+    Device(CP17) { // A53-0: Cluster 4, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 9)
+    }
+
+    Device(CP20) { // A53-0: Cluster 5, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 10)
+    }
+    Device(CP21) { // A53-0: Cluster 5, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 11)
+    }
+
+    Device(CP24) { // A53-0: Cluster 6, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 12)
+    }
+    Device(CP25) { // A53-0: Cluster 6, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 13)
+    }
+
+    Device(CP28) { // A53-0: Cluster 7, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 14)
+    }
+    Device(CP29) { // A53-0: Cluster 7, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 15)
+    }
+
+    Device(CP32) { // A53-0: Cluster 8, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 16)
+    }
+    Device(CP33) { // A53-0: Cluster 8, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 17)
+    }
+
+    Device(CP36) { // A53-0: Cluster 9, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 18)
+    }
+    Device(CP37) { // A53-0: Cluster 9, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 19)
+    }
+
+    Device(CP40) { // A53-0: Cluster 10, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 20)
+    }
+    Device(CP41) { // A53-0: Cluster 10, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 21)
+    }
+
+    Device(CP44) { // A53-0: Cluster 11, Cpu 0
+      Name(_HID, "ACPI0007")
+      Name(_UID, 22)
+    }
+    Device(CP45) { // A53-0: Cluster 11, Cpu 1
+      Name(_HID, "ACPI0007")
+      Name(_UID, 23)
+    }
+
+    // UART PL011
+    Device(COM0) {
+      Name(_HID, "ARMH0011")
+      Name(_CID, "PL011")
+      Name(_UID, Zero)
+      Name(_CRS, ResourceTemplate() {
+        Memory32Fixed(ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000)
+        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 }
+      })
+    }
+
+    Device(NET0) {
+      Name(_HID, "SCX0001")
+      Name(_UID, Zero)
+      Name(_CCA, Zero)
+      Name(_CRS, ResourceTemplate() {
+        Memory32Fixed(ReadWrite, SYNQUACER_NETSEC_BASE,
+                                 SYNQUACER_NETSEC_BASE_SZ)
+        Memory32Fixed(ReadWrite, SYNQUACER_EEPROM_BASE,
+                                 SYNQUACER_EEPROM_BASE_SZ)
+        Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 }
+      })
+
+      Name (_DSD, Package ()  // _DSD: Device-Specific Data
+      {
+        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+          Package (2) { "phy-mode", "rgmii" },
+          Package (2) { "phy-channel", 0x1 },
+          Package (2) { "max-speed", 1000 },
+          Package (2) { "max-frame-size", 9000 },
+          Package (2) { "socionext,phy-clock-frequency", 125000000 },
+        }
+      })
+    }
+  } // Scope(_SB)
+}
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
new file mode 100644
index 000000000000..26e4e0fc8964
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Fadt.aslc
@@ -0,0 +1,88 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  __ACPI_HEADER (
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER,                                // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_6_0_HW_REDUCED_ACPI | EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_6_0_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS,                                                                 // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+  0                                                                         // UINT64     HypervisorVendorIdentity;
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
new file mode 100644
index 000000000000..f22c27f05454
--- /dev/null
+++ b/Silicon/Socionext/Synquacer/AcpiTables/Gtdt.aslc
@@ -0,0 +1,98 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiTables.h"
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_6_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+#define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE                  TimerBase;
+  EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE            TimerFrame;
+  EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdog;
+} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    __ACPI_HEADER(
+      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+    0,                                            // UINT32  Reserved
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32