From nobody Thu May 2 22:01:18 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504184925273637.2706578631911; Thu, 31 Aug 2017 06:08:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AF38321EB529D; Thu, 31 Aug 2017 06:05:59 -0700 (PDT) Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 570F621EB529B for ; Thu, 31 Aug 2017 06:05:58 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id v2so4507104wmf.0 for ; Thu, 31 Aug 2017 06:08:41 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sOpO9EmG8qTqsE7+miruXtj8DT3wH5zN2mGDgyOGSrY=; b=E8bczuc/VK29k6U7AmMOH0YPmo0FI5ETFRyOG+PmosmxPohD+keQvSITI0WF5v9zng 3kW9hpy+OzZ8XGeW7T+SMoZUirAdFiogtKSRqxQcoQjY02WOjht1M5Cx+4/oDvwkSo2H 9uO4CQTRHcYV5pOAAAT6r/OOHuFbLcFZsE4zk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sOpO9EmG8qTqsE7+miruXtj8DT3wH5zN2mGDgyOGSrY=; b=JfO3f7/eLmqZpXP+qt77iUTLEVcyrdSabhnTuB7L8darTAyH8NYG+qpzTnMxI5vHDC uolmCPN5qKuElM95VdrBJzy6zaQrHoG2YDKAjz2UsoteRGmi5ZRec6dxXCcn2sPBbNJG S4rywqG1VqG7N92mzT17XtFDYTK99pRNI1D7MgR2U+tDLWj4UrRLJe+Mer4TpnSJ+VjW 4YDzZrqo7eBVhoxi7QPUWg39ZR+vceJ5onwrK7Tb+M+Yd1H4F7knHrYFHkCcSeO297Th z6R5irDSjF/ycP3ihzdwWOKf2nQ4zXn5qBCPfts9Np2x+X4p7OUjF2xKW4ziS8Bd1J/1 tn4A== X-Gm-Message-State: AHPjjUgE+SwRqqkt7BAYFKxf97e8CNYiY80oePk4HsOdI9RduRbvqGzJ yA/YbgEugcA3s2usV8sTTQ== X-Received: by 10.28.153.202 with SMTP id b193mr470382wme.117.1504184919625; Thu, 31 Aug 2017 06:08:39 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:27 +0100 Message-Id: <20170831130830.12833-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 1/4] Platform/OverdriveBoard: move device tree compilation into build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Use the proposed BaseTools support for device tree compilation to build the device tree binary from source at build time. Give it its own .inf and a build rule so the tools take care of everything. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb = | Bin 9357 -> 0 bytes Platform/AMD/OverdriveBoard/OverdriveBoard.dsc = | 1 + Platform/AMD/OverdriveBoard/OverdriveBoard.fdf = | 9 ++++--- Platform/AMD/OverdriveBoard/{FdtBlob/styx-overdrive.dts =3D> OverdriveBoar= dDeviceTree/OverdriveBoardDeviceTree.dts} | 0 Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceT= ree.inf | 28 ++++++++++++++++++++ 5 files changed, 34 insertions(+), 4 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platf= orm/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb deleted file mode 100644 index c8e5fd980bce305186214aab10a7d399faa22500..000000000000000000000000000= 0000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9357 zcmdT~O>7-k6`rw)A*6q4AOZx68>b{vrSMPo6pFwcq`#}(#4}ym-;d%e>`K#U!qCFXYpJ__@2FbM7^7V1BMQld1p?MBm$Ds5ad}xfF@t2T|YT2sY7j8RrH{5Pg!KMhmsiH-m1D>f)@g2B zC)A(B#<;AXkD6N65u@he-XM6Je%P=3D3JpPc!zt`~+r^>r970j>+rm8eAG81*zDyl_K zf5%a1ulRL-Q6>>8dFK8Flok<=3DP?%(^n0fiil_g0n+i)DGmeWnsi;`@ZtkO{9yhs70 z@~;m3dt2rE!CZ@b**ttMS*NVB`Gao$u?55tm9*bioTJYidIe1x7kLb>B}u_BzE8;? z=3D}9)xLAS`eVR3Ls@Yw+(}+P@)w!Oj3qdVBsIigokDv< z98Q7#=3DhcfNdF|!WT`x@2pScB@C+BV}&V7G>`KrSw{mIiRVSlVsx@_hY^NMxT$jmEc z&8wTQx7S~9zH@rl}uQ?56u3PRQpzw?M;hG0EytcUxC9zN@y@8^2#Lh8Qnb;}& z*pq!@e+3>$d&B+(SSohq70<1(bDpRzu~W9#u_lrC`4)EeZK@g+)tTN#62&V?3I&Kh zM!9zbCEjcu$4hgafG1v!`xf|d`9+)X0O}Z%bPUDE)@xzIc^KZ)ORKn>nVz(;G4_V} zRo8+UxDj&~y8U3bUOdd{T!LE=3DL9E$f|9RrOe3~ll4>sb`M6iW=3DXHMk=3Dpmubo`Z?uB z*2dSYXNleEV878NB)<0?dyAtW#37cpe(bM8w`=3DUmlxdu?>(Y5`&$TCKdy#c!XXVbT zC~^EJCd<@@!6Xseb{#+*8~<~t(D=3DOb;Cy0kwH(I0IKn*$8&D7z-6fuCs3+O^R22j$ zdyG{}TOZ@x+^sOulTd>ZQph<=3D9Dcq&4_Wc@>f_}cK5`R`vL4ZfM8EsP$QDAk#P}r4 z_Jfh0VIQ8wm80ckxrg#)*{Eq#^%6WBEOx+?XwUgNmFG!>vm&apVa*DV`bw;*a<~xA zMp}(o;r{CT7(mU$s79$Gnn1B22 z=3DKwBlyPw_ydguD7qc+;F0D0fzncqo2y$3m>xwCQOt}1j#{`h>;j_WwvOT{Y5c)cb zGKIQmWmwgbN#Z=3D}n*q+e1Qj6Ku+PUGuQK;R`c?TNc-<#~IQ$!Al0`ql4qxGQ#A6-X za^HKM0*Lo-&R_T@c+E9^Bq)IzTBl+Qb^^Q4+pJc4HyHQ{w@`<9gX42VL}Jl2x^UX+ zcGyYI8WUl{hsM|uZ`&Vp1>FvR>`U8j#_ITp(GYFgb|Z6Qo7?9bK$Bfatg-XXHthdv zD2zjy`=3DLIMJO!Thpip^jbDc^Q%A_|?w2seyTuLevJ7vM1B!k7yrjc#f-F4Hh!H)W9 zp>qx@Y0q{Eg@5n|>Y9(-QSZTyMZ*L9144GJ|$91B!QFXvt?5jxy z=3D%a@MXSW-6=3D!2=3DW$kPZ7=3D>$Z-*t^2()QiUInp|$VKA?^#SR3DS&?!FnpXkuf(oX-x zy$Cyc(tbP%p6%>7XRGd=3Djr2`p?D^fE_s-`1@Of>skC#JuKItssEs_7`rim}_aM5qY zBl|w(7M@wCnm*qJJVjmXj%TWchjI(g++D>pd-MFbGfc*b>ymN{&-`7+bJP6j{NubK z9?F8JShg}>$F--g1SQx$!B8ZIhWxNx z_;ZOrkpIIghz2@;b-#Js)1!XkYcvEoyNLum*M_b%)pL!qe=3DIr{*c&FEhm3deQg|S% z{g1)(oe2x;RsRdeQ`R*|KYxO(#C)=3Dz__-$|ca6+C$~$w7H*(OC*zPXon%f_#$@Ntc zgWwXc$n}4nJTBK4P^Wra|1WZ_V@2G|HD$@QJG&p<_t||39!PdZ>A3E8c7F+$j13Bv z*EZLoBo@k~_Stkd&g(MYyX}B zZ?h7F-}3lxd;E7CPd}iEE&PzjSu*kF#EU=3Du+0S2sWOYQq_htuB^z3;6A&&6WeC7E@m@FFxK+!nR9}448{48J?4-nGyjx#dguf79_U7p?sN`sLsJ_II$bdC>fGZzs<-d&$4< z7kkY=3D=3DQXLFf38Ix59XgT^DkqN;9=3DbGEs?ds9H0EqBly$zkufi$wM|haZYqdhd9LTZ zGWAjCtb6_27`fP!C#yVR9F2W2ANEX!yW+fv>lA-P1f!1;3cTAN)WJ;L>*3b9iukU( z3TCSGigEnNcJ$#wFym>ZMQQpYuT@aSgTASPEFG+Eo+(!1K@U;$D)l~o2(T(5XE!7N zH@kqA$DRDMYi5vK4y-&}tBbWd8sMLP;Ol3@Zk$C83aHW{AH6Jox=3Dw~GM*1f0t3c|j zpsM2<|EXK2)*D~#dVL$L%c(0w0CgP61{S z^vrsin5Fu1VFG+KU_naC-4HjqqB%;nIvOzXfFX409huq$v4%4u5T=3DNebkMh-#1sY} z3sk0dAIOwFQ$^iuBk|>=3DR{~9Kd|mNuRIQo~Uxh5hdEsk%%O FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/= OverdriveBoard/OverdriveBoard.fdf index 23e57befcdd9..aa2a1a6fa053 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -145,10 +145,7 @@ READ_LOCK_STATUS =3D TRUE # FDT support # INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf - - FILE FREEFORM =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 { - SECTION RAW =3D Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb - } + INF RuleOverride =3D DTB Platform/AMD/OverdriveBoard/OverdriveBoardDevic= eTree/OverdriveBoardDeviceTree.inf =20 # # PCI support @@ -413,3 +410,7 @@ READ_LOCK_STATUS =3D TRUE RAW ASL |.aml } =20 +[Rule.Common.USER_DEFINED.DTB] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW BIN |.dtb + } diff --git a/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platf= orm/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts similarity index 100% rename from Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dts rename to Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoa= rdDeviceTree.dts diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/Overdrive= BoardDeviceTree.inf b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/= OverdriveBoardDeviceTree.inf new file mode 100644 index 000000000000..9ecf993cafac --- /dev/null +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.inf @@ -0,0 +1,28 @@ +## @file +# +# Device tree description of the AMD Seattle Overdrive platform +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D OverdriveBoardDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPl= atformDefaultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + OverdriveBoardDeviceTree.dts + +[Packages] + MdePkg/MdePkg.dec --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 22:01:18 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504184929061356.3782385725218; Thu, 31 Aug 2017 06:08:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EC88F21EB529B; Thu, 31 Aug 2017 06:06:01 -0700 (PDT) Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E362F21EB529F for ; Thu, 31 Aug 2017 06:06:00 -0700 (PDT) Received: by mail-wm0-x230.google.com with SMTP id u26so4174803wma.0 for ; Thu, 31 Aug 2017 06:08:44 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:41 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Tbe8mZLAxAbzLmQN0oQvyXwe7xLwIk6DMc3Y9Rq466g=; b=koPu3DPZfADOkIOQgxb5OrfX6zaweLTVYhZbHLEAw3PUTcBdolMWKJ7UsrkbAd73g6 Ci1Hqcf1iMrHZAKyjhxzumYuqXUcOdsckhUPCuI9nXPEyO8J0/V7WiavYMo/0Nz7R4yt 8qn6Wfgdl3uk2QFYLWyTREZLwpl+8+VaJojs4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Tbe8mZLAxAbzLmQN0oQvyXwe7xLwIk6DMc3Y9Rq466g=; b=guRZXdBFXDF+Wd2CCy229puMepR1QNhQaPxsvER884+drADrE0HoiBUyfwSSc83xPq f01wpoD6qtvLkqE1Qzk8ITUhjAhwgqCU1rrRutMhfdoytQUcFQGMKLi32OHXIYK7cl8J A1oDnY83Mjjol/lGdSsle9xWe9rYgOYsJRqjWKc6rCuxJUE6Abzt5+UgIYlYq0lYpjG6 PYfsE1adOMUNciGyx7I8CxglCs/DhTY6Cp9AMqnRkKySRiVinJ7TMPIt33OjAE+91/vh RvLZRGACB1237tuk8gNxz9s99KcoAunoRjx8vqTzqzHidyGLzMGLfIJRsjPMeFk5rB4f iOrQ== X-Gm-Message-State: AHPjjUhQIyXjNsBCbbwsoojBEJCpe7d3iRHevjACHXyYk+tJkMPbna06 wOrO2ybloSEngcGDl1Hfig== X-Received: by 10.28.70.69 with SMTP id t66mr470955wma.123.1504184922226; Thu, 31 Aug 2017 06:08:42 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:28 +0100 Message-Id: <20170831130830.12833-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 2/4] Platform/OverdriveBoard: clean up device tree source file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Clean up the device tree source file, by switching to Tianocore conventions for line endings and whitespace etc, and by replacing open coded values with symbol constants and/or phandle references. The resulting .dtb will likely not be identical at the bit level, but the modifications are cosmetic only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceT= ree.dts | 957 ++++++++++---------- 1 file changed, 467 insertions(+), 490 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/Overdrive= BoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/= OverdriveBoardDeviceTree.dts index 4039f666004a..81477fe43cdd 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.dts @@ -2,6 +2,7 @@ * DTS file for AMD Seattle (Rev.B) Overdrive Development Board * * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserve= d. + * Copyright 2015 - 2017 Linaro, Ltd. All Rights Reserved. * * This program and the accompanying materials are licensed and made avai= lable * under the terms and conditions of the BSD License which accompanies th= is @@ -14,497 +15,473 @@ * */ =20 +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#define GIC_CPU_MASK(num) (((1 << (num)) - 1) << 8) + /dts-v1/; =20 / { - model =3D "AMD Seattle (Rev.B) Development Board (Overdrive)"; - compatible =3D "amd,seattle-overdrive", "amd,seattle"; - interrupt-parent =3D <0x1>; - #address-cells =3D <0x2>; - #size-cells =3D <0x2>; - - interrupt-controller@e1101000 { - compatible =3D "arm,gic-400", "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells =3D <0x3>; - #address-cells =3D <0x2>; - #size-cells =3D <0x2>; - reg =3D <0x0 0xe1110000 0x0 0x1000>, - <0x0 0xe112f000 0x0 0x2000>, - <0x0 0xe1140000 0x0 0x2000>, - <0x0 0xe1160000 0x0 0x2000>; - interrupts =3D <0x1 0x9 0xf04>; - ranges =3D <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; - linux,phandle =3D <0x1>; - phandle =3D <0x1>; - - v2m@e0080000 { - compatible =3D "arm,gic-v2m-frame"; - msi-controller; - reg =3D <0x0 0x80000 0x0 0x1000>; - linux,phandle =3D <0x4>; - phandle =3D <0x4>; - }; - }; - - timer { - compatible =3D "arm,armv8-timer"; - interrupts =3D <0x1 0xd 0xff04>, - <0x1 0xe 0xff04>, - <0x1 0xb 0xff04>, - <0x1 0xa 0xff04>; - }; - - smb { - compatible =3D "simple-bus"; - #address-cells =3D <0x2>; - #size-cells =3D <0x2>; - ranges; - /* - * dma-ranges is 40-bit address space containing: - * - GICv2m MSI register is at 0xe0080000 - * - DRAM range [0x8000000000 to 0xffffffffff] - */ - dma-ranges =3D <0x0 0x0 0x0 0x0 0x100 0x0>; - - clk100mhz_0 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <100000000>; - clock-output-names =3D "adl3clk_100mhz"; - }; - - clk375mhz { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <375000000>; - clock-output-names =3D "ccpclk_375mhz"; - }; - - clk333mhz { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <333000000>; - clock-output-names =3D "sataclk_333mhz"; - linux,phandle =3D <0x2>; - phandle =3D <0x2>; - }; - - clk500mhz_0 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <500000000>; - clock-output-names =3D "pcieclk_500mhz"; - }; - - clk500mhz_1 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <500000000>; - clock-output-names =3D "dmaclk_500mhz"; - }; - - clk250mhz_4 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <250000000>; - clock-output-names =3D "miscclk_250mhz"; - linux,phandle =3D <0xd>; - phandle =3D <0xd>; - }; - - clk100mhz_1 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <100000000>; - clock-output-names =3D "uartspiclk_100mhz"; - linux,phandle =3D <0x3>; - phandle =3D <0x3>; - }; - - sata0_smmu: smmu@e0200000 { - compatible =3D "arm,mmu-401"; - reg =3D <0 0xe0200000 0 0x10000>; - #global-interrupts =3D <1>; - interrupts =3D /* Uses combined intr for both - * global and context - */ - <0 332 4>, - <0 332 4>; - #iommu-cells =3D <2>; - dma-coherent; - }; - - sata1_smmu: smmu@e0c00000 { - compatible =3D "arm,mmu-401"; - reg =3D <0 0xe0c00000 0 0x10000>; - #global-interrupts =3D <1>; - interrupts =3D /* Uses combined intr for both - * global and context - */ - <0 331 4>, - <0 331 4>; - #iommu-cells =3D <2>; - dma-coherent; - }; - - sata@e0300000 { - compatible =3D "snps,dwc-ahci"; - reg =3D <0x0 0xe0300000 0x0 0xf0000>; - interrupts =3D <0x0 0x163 0x4>; - clocks =3D <0x2>; - dma-coherent; - iommus =3D <&sata0_smmu 0x00 0x1f>; /* 0-31 */ - }; - - sata@e0d00000 { - status =3D "disabled"; - compatible =3D "snps,dwc-ahci"; - reg =3D <0x0 0xe0d00000 0x0 0xf0000>; - interrupts =3D <0x0 0x162 0x4>; - clocks =3D <0x2>; - dma-coherent; - iommus =3D <&sata1_smmu 0x00 0x1f>; /* 0-31 */ - }; - - i2c@e1000000 { - compatible =3D "snps,designware-i2c"; - reg =3D <0x0 0xe1000000 0x0 0x1000>; - interrupts =3D <0x0 0x165 0x4>; - clocks =3D <0xd>; - }; - - i2c@e0050000 { - compatible =3D "snps,designware-i2c"; - reg =3D <0x0 0xe0050000 0x0 0x1000>; - interrupts =3D <0x0 0x154 0x4>; - clocks =3D <0xd>; - }; - - serial@e1010000 { - compatible =3D "arm,pl011", "arm,primecell"; - reg =3D <0x0 0xe1010000 0x0 0x1000>; - interrupts =3D <0x0 0x148 0x4>; - clocks =3D <0x3 0x3>; - clock-names =3D "uartclk", "apb_pclk"; - }; - - ssp@e1020000 { - compatible =3D "arm,pl022", "arm,primecell"; - reg =3D <0x0 0xe1020000 0x0 0x1000>; - spi-controller; - interrupts =3D <0x0 0x14a 0x4>; - clocks =3D <0x3>; - clock-names =3D "apb_pclk"; - }; - - ssp@e1030000 { - compatible =3D "arm,pl022", "arm,primecell"; - reg =3D <0x0 0xe1030000 0x0 0x1000>; - spi-controller; - interrupts =3D <0x0 0x149 0x4>; - clocks =3D <0x3>; - clock-names =3D "apb_pclk"; - num-cs =3D <0x1>; - #address-cells =3D <0x1>; - #size-cells =3D <0x0>; - - sdcard@0 { - compatible =3D "mmc-spi-slot"; - reg =3D <0x0>; - spi-max-frequency =3D <20000000>; - voltage-ranges =3D <3200 3400>; - pl022,hierarchy =3D <0x0>; - pl022,interface =3D <0x0>; - pl022,com-mode =3D <0x0>; - pl022,rx-level-trig =3D <0x0>; - pl022,tx-level-trig =3D <0x0>; - }; - }; - - gpio@e1050000 { /* [0 : 7] */ - compatible =3D "arm,pl061", "arm,primecell"; - #gpio-cells =3D <0x2>; - reg =3D <0x0 0xe1050000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells =3D <0x2>; - interrupts =3D <0x0 0x166 0x4>; - clocks =3D <0x3>; - clock-names =3D "apb_pclk"; - }; - - gpio@e0020000 { /* [8 : 15] */ - status =3D "disabled"; - compatible =3D "arm,pl061", "arm,primecell"; - #gpio-cells =3D <0x2>; - reg =3D <0x0 0xe0020000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells =3D <0x2>; - interrupts =3D <0x0 0x16e 0x4>; - clocks =3D <0x3>; - clock-names =3D "apb_pclk"; - }; - - gpio@e0030000 { /* [16 : 23] */ - status =3D "disabled"; - compatible =3D "arm,pl061", "arm,primecell"; - #gpio-cells =3D <0x2>; - reg =3D <0x0 0xe0030000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells =3D <0x2>; - interrupts =3D <0x0 0x16d 0x4>; - clocks =3D <0x3>; - clock-names =3D "apb_pclk"; - }; - - gpio@e0080000 { /* [24] */ - compatible =3D "arm,pl061", "arm,primecell"; - #gpio-cells =3D <0x2>; - reg =3D <0x0 0xe0080000 0x0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells =3D <0x2>; - interrupts =3D <0x0 0x169 0x4>; - clocks =3D <0x3>; - clock-names =3D "apb_pclk"; - }; - - ccp: ccp@e0100000 { - compatible =3D "amd,ccp-seattle-v1a"; - reg =3D <0x0 0xe0100000 0x0 0x10000>; - interrupts =3D <0x0 0x3 0x4>; - dma-coherent; - amd,zlib-support =3D <0x1>; - }; - - pcie: pcie@f0000000 { - compatible =3D "pci-host-ecam-generic"; - #address-cells =3D <0x3>; - #size-cells =3D <0x2>; - #interrupt-cells =3D <0x1>; - iommu-map =3D <0x0 &pcie_smmu 0x0 0x10000>; - device_type =3D "pci"; - bus-range =3D <0x0 0x7f>; - msi-parent =3D <0x4>; - reg =3D <0x0 0xf0000000 0x0 0x10000000>; - interrupt-map-mask =3D <0xff00 0x0 0x0 0x7>; - interrupt-map =3D <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, - <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, - <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, - <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>, - - <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>, - <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>, - <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>, - <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>, - - <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>, - <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>, - <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>, - <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>; - dma-coherent; - dma-ranges =3D <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; - ranges =3D <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /= * I/O Memory (size=3D64K) */ - <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit = MMIO (size=3D2G) */ - <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit = MMIO (size=3D 124G) */ - }; - - pcie_smmu: smmu@e0a00000 { - compatible =3D "arm,mmu-401"; - reg =3D <0 0xe0a00000 0 0x10000>; - #global-interrupts =3D <1>; - interrupts =3D /* Uses combined intr for both - * global and context - */ - <0 333 4>, - <0 333 4>; - #iommu-cells =3D <1>; - dma-coherent; - }; - - ccn@0xe8000000 { - compatible =3D "arm,ccn-504"; - reg =3D <0x0 0xe8000000 0x0 0x1000000>; - interrupts =3D <0x0 0x17c 0x4>; - }; - - gwdt@e0bb0000 { - status =3D "disabled"; - compatible =3D "arm,sbsa-gwdt"; - reg =3D <0x0 0xe0bb0000 0x0 0x10000 - 0x0 0xe0bc0000 0x0 0x10000>; - reg-names =3D "refresh", "control"; - interrupts =3D <0x0 0x151 0x4>; - interrupt-names =3D "ws0"; - }; - - kcs@e0010000 { - status =3D "disabled"; - compatible =3D "ipmi-kcs"; - device_type =3D "ipmi"; - reg =3D <0x0 0xe0010000 0 0x8>; - interrupts =3D <0 389 4>; - interrupt-names =3D "ipmi_kcs"; - reg-size =3D <1>; - reg-spacing =3D <4>; - }; - - clk250mhz_0 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <250000000>; - clock-output-names =3D "xgmacclk0_dma_250mhz"; - linux,phandle =3D <0x5>; - phandle =3D <0x5>; - }; - - clk250mhz_1 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <250000000>; - clock-output-names =3D "xgmacclk0_ptp_250mhz"; - linux,phandle =3D <0x6>; - phandle =3D <0x6>; - }; - - clk250mhz_2 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <250000000>; - clock-output-names =3D "xgmacclk1_dma_250mhz"; - linux,phandle =3D <0x7>; - phandle =3D <0x7>; - }; - - clk250mhz_3 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0x0>; - clock-frequency =3D <250000000>; - clock-output-names =3D "xgmacclk1_ptp_250mhz"; - linux,phandle =3D <0x8>; - phandle =3D <0x8>; - }; - - phy@e1240800 { - status =3D "disabled"; - compatible =3D "amd,xgbe-phy-seattle-v1a"; - reg =3D <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ - <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ - <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ - interrupts =3D <0x0 0x143 0x4>; - amd,speed-set =3D <0x0>; - amd,serdes-blwc =3D <0x1 0x1 0x0>; - amd,serdes-cdr-rate =3D <0x2 0x2 0x7>; - amd,serdes-pq-skew =3D <0xa 0xa 0x12>; - amd,serdes-tx-amp =3D <0xf 0xf 0xa>; - amd,serdes-dfe-tap-config =3D <0x3 0x3 0x1>; - amd,serdes-dfe-tap-enable =3D <0x0 0x0 0x7f>; - linux,phandle =3D <0x9>; - phandle =3D <0x9>; - }; - - phy@e1240c00 { - status =3D "disabled"; - compatible =3D "amd,xgbe-phy-seattle-v1a"; - reg =3D <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ - <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ - <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ - interrupts =3D <0x0 0x142 0x4>; - amd,speed-set =3D <0x0>; - amd,serdes-blwc =3D <0x1 0x1 0x0>; - amd,serdes-cdr-rate =3D <0x2 0x2 0x7>; - amd,serdes-pq-skew =3D <0xa 0xa 0x12>; - amd,serdes-tx-amp =3D <0xf 0xf 0xa>; - amd,serdes-dfe-tap-config =3D <0x3 0x3 0x1>; - amd,serdes-dfe-tap-enable =3D <0x0 0x0 0x7f>; - linux,phandle =3D <0xa>; - phandle =3D <0xa>; - }; - - xgmac0_smmu: smmu@e0600000 { - compatible =3D "arm,mmu-401"; - reg =3D <0 0xe0600000 0 0x10000>; - #global-interrupts =3D <1>; - interrupts =3D /* Uses combined intr for both - * global and context - */ - <0 336 4>, - <0 336 4>; - #iommu-cells =3D <2>; - dma-coherent; - }; - - xgmac1_smmu: smmu@e0800000 { - compatible =3D "arm,mmu-401"; - reg =3D <0 0xe0800000 0 0x10000>; - #global-interrupts =3D <1>; - interrupts =3D /* Uses combined intr for both - * global and context - */ - <0 335 4>, - <0 335 4>; - #iommu-cells =3D <2>; - dma-coherent; - }; - - xgmac@e0700000 { - status =3D "disabled"; - compatible =3D "amd,xgbe-seattle-v1a"; - reg =3D <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; - interrupts =3D <0x0 0x145 0x4>, - <0x0 0x15a 0x1>, - <0x0 0x15b 0x1>, - <0x0 0x15c 0x1>, - <0x0 0x15d 0x1>; - amd,per-channel-interrupt; - mac-address =3D [02 a1 a2 a3 a4 a5]; - clocks =3D <0x5 0x6>; - clock-names =3D "dma_clk", "ptp_clk"; - phy-handle =3D <0x9>; - phy-mode =3D "xgmii"; - dma-coherent; - iommus =3D <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle =3D <0xb>; - phandle =3D <0xb>; - }; - - xgmac@e0900000 { - status =3D "disabled"; - compatible =3D "amd,xgbe-seattle-v1a"; - reg =3D <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; - interrupts =3D <0x0 0x144 0x4>, - <0x0 0x155 0x1>, - <0x0 0x156 0x1>, - <0x0 0x157 0x1>, - <0x0 0x158 0x1>; - amd,per-channel-interrupt; - mac-address =3D [02 b1 b2 b3 b4 b5]; - clocks =3D <0x7 0x8>; - clock-names =3D "dma_clk", "ptp_clk"; - phy-handle =3D <0xa>; - phy-mode =3D "xgmii"; - dma-coherent; - iommus =3D <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle =3D <0xc>; - phandle =3D <0xc>; - }; - }; - - chosen { - stdout-path =3D "/smb/serial@e1010000"; - /* Note: - * Linux support for pci-probe-only DT is not - * stable. Disable this for now and let Linux - * take care of the resource assignment. - */ - // linux,pci-probe-only; - }; - - psci { - compatible =3D "arm,psci-0.2", "arm,psci"; - method =3D "smc"; - }; + model =3D "AMD Seattle (Rev.B) Development Board (Overdrive)"; + compatible =3D "amd,seattle-overdrive", "amd,seattle"; + interrupt-parent =3D <&gic>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + + gic: interrupt-controller@e1101000 { + compatible =3D "arm,gic-400", "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells =3D <0x3>; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + reg =3D <0x0 0xe1110000 0x0 0x1000>, + <0x0 0xe112f000 0x0 0x2000>, + <0x0 0xe1140000 0x0 0x2000>, + <0x0 0xe1160000 0x0 0x2000>; + interrupts =3D ; + ranges =3D <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; + + msi: v2m@e0080000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x80000 0x0 0x1000>; + msi-controller; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + smb { + compatible =3D "simple-bus"; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + ranges; + /* + * dma-ranges is 40-bit address space containing: + * - GICv2m MSI register is at 0xe0080000 + * - DRAM range [0x8000000000 to 0xffffffffff] + */ + dma-ranges =3D <0x0 0x0 0x0 0x0 0x100 0x0>; + + adl3clk: clk100mhz_0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <100000000>; + clock-output-names =3D "adl3clk_100mhz"; + }; + + ccpclk: clk375mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <375000000>; + clock-output-names =3D "ccpclk_375mhz"; + }; + + sataclk: clk333mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <333000000>; + clock-output-names =3D "sataclk_333mhz"; + }; + + pcieclk: clk500mhz_0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <500000000>; + clock-output-names =3D "pcieclk_500mhz"; + }; + + dmaclk: clk500mhz_1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <500000000>; + clock-output-names =3D "dmaclk_500mhz"; + }; + + miscclk: clk250mhz_4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "miscclk_250mhz"; + }; + + uartspiclk: clk100mhz_1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <100000000>; + clock-output-names =3D "uartspiclk_100mhz"; + }; + + sata0_smmu: smmu@e0200000 { + compatible =3D "arm,mmu-401"; + reg =3D <0 0xe0200000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts =3D <1>; + interrupts =3D , + ; + #iommu-cells =3D <2>; + dma-coherent; + }; + + sata1_smmu: smmu@e0c00000 { + compatible =3D "arm,mmu-401"; + reg =3D <0 0xe0c00000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts =3D <1>; + interrupts =3D , + ; + #iommu-cells =3D <2>; + dma-coherent; + }; + + sata@e0300000 { + compatible =3D "snps,dwc-ahci"; + reg =3D <0x0 0xe0300000 0x0 0xf0000>; + interrupts =3D ; + clocks =3D <&sataclk>; + dma-coherent; + iommus =3D <&sata0_smmu 0x00 0x1f>; /* 0-31 */ + }; + + sata@e0d00000 { + status =3D "disabled"; + compatible =3D "snps,dwc-ahci"; + reg =3D <0x0 0xe0d00000 0x0 0xf0000>; + interrupts =3D ; + clocks =3D <&sataclk>; + dma-coherent; + iommus =3D <&sata1_smmu 0x00 0x1f>; /* 0-31 */ + }; + + i2c@e1000000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0xe1000000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&miscclk>; + }; + + i2c@e0050000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0xe0050000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&miscclk>; + }; + + serial@e1010000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xe1010000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&uartspiclk &uartspiclk>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + ssp@e1020000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0xe1020000 0x0 0x1000>; + spi-controller; + interrupts =3D ; + clocks =3D <&uartspiclk>; + clock-names =3D "apb_pclk"; + }; + + ssp@e1030000 { + compatible =3D "arm,pl022", "arm,primecell"; + reg =3D <0x0 0xe1030000 0x0 0x1000>; + spi-controller; + interrupts =3D ; + clocks =3D <&uartspiclk>; + clock-names =3D "apb_pclk"; + num-cs =3D <0x1>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + + sdcard@0 { + compatible =3D "mmc-spi-slot"; + reg =3D <0x0>; + spi-max-frequency =3D <20000000>; + voltage-ranges =3D <3200 3400>; + pl022,hierarchy =3D <0x0>; + pl022,interface =3D <0x0>; + pl022,com-mode =3D <0x0>; + pl022,rx-level-trig =3D <0x0>; + pl022,tx-level-trig =3D <0x0>; + }; + }; + + gpio@e1050000 { /* [0 : 7] */ + compatible =3D "arm,pl061", "arm,primecell"; + #gpio-cells =3D <0x2>; + reg =3D <0x0 0xe1050000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <0x2>; + interrupts =3D ; + clocks =3D <&uartspiclk>; + clock-names =3D "apb_pclk"; + }; + + gpio@e0020000 { /* [8 : 15] */ + status =3D "disabled"; + compatible =3D "arm,pl061", "arm,primecell"; + #gpio-cells =3D <0x2>; + reg =3D <0x0 0xe0020000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <0x2>; + interrupts =3D ; + clocks =3D <&uartspiclk>; + clock-names =3D "apb_pclk"; + }; + + gpio@e0030000 { /* [16 : 23] */ + status =3D "disabled"; + compatible =3D "arm,pl061", "arm,primecell"; + #gpio-cells =3D <0x2>; + reg =3D <0x0 0xe0030000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <0x2>; + interrupts =3D ; + clocks =3D <&uartspiclk>; + clock-names =3D "apb_pclk"; + }; + + gpio@e0080000 { /* [24] */ + compatible =3D "arm,pl061", "arm,primecell"; + #gpio-cells =3D <0x2>; + reg =3D <0x0 0xe0080000 0x0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <0x2>; + interrupts =3D ; + clocks =3D <&uartspiclk>; + clock-names =3D "apb_pclk"; + }; + + ccp: ccp@e0100000 { + compatible =3D "amd,ccp-seattle-v1a"; + reg =3D <0x0 0xe0100000 0x0 0x10000>; + interrupts =3D ; + dma-coherent; + amd,zlib-support =3D <0x1>; + }; + + pcie: pcie@f0000000 { + compatible =3D "pci-host-ecam-generic"; + #address-cells =3D <0x3>; + #size-cells =3D <0x2>; + #interrupt-cells =3D <0x1>; + iommu-map =3D <0x0 &pcie_smmu 0x0 0x10000>; + device_type =3D "pci"; + bus-range =3D <0x0 0x7f>; + msi-parent =3D <&msi>; + reg =3D <0x0 0xf0000000 0x0 0x10000000>; + interrupt-map-mask =3D <0xff00 0x0 0x0 0x7>; + interrupt-map =3D <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ= _TYPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_T= YPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_T= YPE_EDGE_RISING>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_T= YPE_EDGE_RISING>, + + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_T= YPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_T= YPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_T= YPE_EDGE_RISING>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_T= YPE_EDGE_RISING>, + + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_T= YPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_T= YPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_T= YPE_EDGE_RISING>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_T= YPE_EDGE_RISING>; + dma-coherent; + dma-ranges =3D <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; + ranges =3D <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>= , /* I/O Memory (size=3D64K) */ + <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, = /* 32-bit MMIO (size=3D2G) */ + <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; = /* 64-bit MMIO (size=3D 124G) */ + }; + + pcie_smmu: smmu@e0a00000 { + compatible =3D "arm,mmu-401"; + reg =3D <0 0xe0a00000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts =3D <1>; + interrupts =3D , + ; + #iommu-cells =3D <1>; + dma-coherent; + }; + + ccn@0xe8000000 { + compatible =3D "arm,ccn-504"; + reg =3D <0x0 0xe8000000 0x0 0x1000000>; + interrupts =3D ; + }; + + gwdt@e0bb0000 { + status =3D "disabled"; + compatible =3D "arm,sbsa-gwdt"; + reg =3D <0x0 0xe0bb0000 0x0 0x10000 + 0x0 0xe0bc0000 0x0 0x10000>; + reg-names =3D "refresh", "control"; + interrupts =3D ; + interrupt-names =3D "ws0"; + }; + + kcs@e0010000 { + status =3D "disabled"; + compatible =3D "ipmi-kcs"; + device_type =3D "ipmi"; + reg =3D <0x0 0xe0010000 0 0x8>; + interrupts =3D ; + interrupt-names =3D "ipmi_kcs"; + reg-size =3D <1>; + reg-spacing =3D <4>; + }; + + xgmacclk0_dma: clk250mhz_0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "xgmacclk0_dma_250mhz"; + }; + + xgmacclk0_ptp: clk250mhz_1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "xgmacclk0_ptp_250mhz"; + }; + + xgmacclk1_dma: clk250mhz_2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "xgmacclk1_dma_250mhz"; + }; + + xgmacclk1_ptp: clk250mhz_3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0x0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "xgmacclk1_ptp_250mhz"; + }; + + xgmac0_phy: phy@e1240800 { + compatible =3D "amd,xgbe-phy-seattle-v1a"; + reg =3D <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts =3D ; + amd,speed-set =3D <0x0>; + amd,serdes-blwc =3D <0x1 0x1 0x0>; + amd,serdes-cdr-rate =3D <0x2 0x2 0x7>; + amd,serdes-pq-skew =3D <0xa 0xa 0x12>; + amd,serdes-tx-amp =3D <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config =3D <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable =3D <0x0 0x0 0x7f>; + status =3D "disabled"; + }; + + xgmac1_phy: phy@e1240c00 { + compatible =3D "amd,xgbe-phy-seattle-v1a"; + reg =3D <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ + <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */ + <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */ + interrupts =3D ; + amd,speed-set =3D <0x0>; + amd,serdes-blwc =3D <0x1 0x1 0x0>; + amd,serdes-cdr-rate =3D <0x2 0x2 0x7>; + amd,serdes-pq-skew =3D <0xa 0xa 0x12>; + amd,serdes-tx-amp =3D <0xf 0xf 0xa>; + amd,serdes-dfe-tap-config =3D <0x3 0x3 0x1>; + amd,serdes-dfe-tap-enable =3D <0x0 0x0 0x7f>; + status =3D "disabled"; + }; + + xgmac0_smmu: smmu@e0600000 { + compatible =3D "arm,mmu-401"; + reg =3D <0 0xe0600000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts =3D <1>; + interrupts =3D , + ; + #iommu-cells =3D <2>; + dma-coherent; + }; + + xgmac1_smmu: smmu@e0800000 { + compatible =3D "arm,mmu-401"; + reg =3D <0 0xe0800000 0 0x10000>; + + /* Uses combined intr for both global and context */ + #global-interrupts =3D <1>; + interrupts =3D , + ; + #iommu-cells =3D <2>; + dma-coherent; + }; + + xgmac@e0700000 { + compatible =3D "amd,xgbe-seattle-v1a"; + reg =3D <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>; + interrupts =3D , + , + , + , + ; + amd,per-channel-interrupt; + mac-address =3D [02 a1 a2 a3 a4 a5]; + clocks =3D <&xgmacclk0_dma &xgmacclk0_ptp>; + clock-names =3D "dma_clk", "ptp_clk"; + phy-handle =3D <&xgmac0_phy>; + phy-mode =3D "xgmii"; + + iommus =3D <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ + dma-coherent; + status =3D "disabled"; + }; + + xgmac@e0900000 { + compatible =3D "amd,xgbe-seattle-v1a"; + reg =3D <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>; + interrupts =3D , + , + , + , + ; + amd,per-channel-interrupt; + mac-address =3D [02 b1 b2 b3 b4 b5]; + clocks =3D <&xgmacclk1_dma &xgmacclk1_ptp>; + clock-names =3D "dma_clk", "ptp_clk"; + phy-handle =3D <&xgmac1_phy>; + phy-mode =3D "xgmii"; + + iommus =3D <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ + dma-coherent; + status =3D "disabled"; + }; + }; + + chosen { + stdout-path =3D "/smb/serial@e1010000"; + }; + + psci { + compatible =3D "arm,psci-0.2", "arm,psci"; + method =3D "smc"; + }; }; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 22:01:18 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504184931857235.53165486224134; Thu, 31 Aug 2017 06:08:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 321412095BB64; Thu, 31 Aug 2017 06:06:05 -0700 (PDT) Received: from mail-wm0-x234.google.com (mail-wm0-x234.google.com [IPv6:2a00:1450:400c:c09::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7C5AA208F7AD6 for ; Thu, 31 Aug 2017 06:06:03 -0700 (PDT) Received: by mail-wm0-x234.google.com with SMTP id 187so4137171wmn.1 for ; Thu, 31 Aug 2017 06:08:46 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MF0lroNQNzh7kEu/y9kDkInWrMAAfd7m8HgikGHgtdM=; b=i/rMDRJcCUqlomy9aUnhnN7NT7kp5DfmGq/iCzJYb3vTvFiacPvjEaR0TjeYvzV4Rj dsWumE9RvyWKFYdi7mTQdeP39XoUsYxQp5BDpjN+wXuc5QILBveFE4PRyvFp13ZNp6g8 xZxwMIOifHpxLxZJwZHLxb0QtM9FFHD0ZLQjs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MF0lroNQNzh7kEu/y9kDkInWrMAAfd7m8HgikGHgtdM=; b=RFJhCyO+zA1pohf1clRpY/p4xo7E2K2x/so22QBvQOt6mr9d0Bhqx3shM7JJvPEzFc uMdYrxEiB+eHnaG+O6Yh6B6mRl/bZnBsZJQfz3ohXqPrxmtNhc5vc4O5Bqv+vOd/D3C4 1s96/eQGpplDNtHBOEdZhgNjs5h+EoUBkfaiQUEXNpEPdBAfsTQ+iSXMHaVZEmDB2+rE LJEQU0TmQNBxp9EGIRlJCGfBUn034jRw2aSxt3bU0PQK3jnWKWPKM+4d1avrGSX44YXH DFChtmSmG5EqKvIwxkWrgzIc92swuws2ecdksM1I2wr544/hrCr0kanSfjSFpVoJt98v DM0w== X-Gm-Message-State: AHYfb5jFDZfooWV332o+x1ImufulxoBZ9OdUW+h0VZGdr7TS0FuqtNup Bsnxw6Ypgdmo/AwBFBNoZQ== X-Received: by 10.28.0.196 with SMTP id 187mr480349wma.178.1504184925026; Thu, 31 Aug 2017 06:08:45 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:29 +0100 Message-Id: <20170831130830.12833-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 3/4] Platform/OverdriveBoard: fix CPU affinity for vGIC maintenace interrupt X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The CPU affinity for the vGIC maintenance interrupt was set to CPUs #0 .. #3 for no good reason. So set it to all CPUs instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceT= ree.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/Overdrive= BoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/= OverdriveBoardDeviceTree.dts index 81477fe43cdd..e57e702029ba 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.dts @@ -45,7 +45,7 @@ <0x0 0xe112f000 0x0 0x2000>, <0x0 0xe1140000 0x0 0x2000>, <0x0 0xe1160000 0x0 0x2000>; - interrupts =3D ; + interrupts =3D ; ranges =3D <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; =20 msi: v2m@e0080000 { --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 22:01:18 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504184939983620.3112814890444; Thu, 31 Aug 2017 06:08:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6E8A42095BB8A; Thu, 31 Aug 2017 06:06:07 -0700 (PDT) Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3881C208F7AD6 for ; Thu, 31 Aug 2017 06:06:06 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id f127so4483153wmf.1 for ; Thu, 31 Aug 2017 06:08:49 -0700 (PDT) Received: from localhost.localdomain ([154.144.95.132]) by smtp.gmail.com with ESMTPSA id u38sm5571203wrb.12.2017.08.31.06.08.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:08:46 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CSKk8eg/zbzLr82Du/n3YaH9vhPak8FyK8CHCSxNpA0=; b=LIB4hexRr9EPGsI9J2oQmIvJeLHgQY3t/fyeH5hQsCiaH1Y1PurZ+dMyFkrAaCVLnO 795n4qec8FfzrgjrOW9HajA7XWbFbw8GgiaNOFA0XjI2sH5e+OPeLLxPegDF9LW6OKEQ YfhgP5FOHRbv/sNFcX4Prkq5yAOh9D0Kesr6s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CSKk8eg/zbzLr82Du/n3YaH9vhPak8FyK8CHCSxNpA0=; b=ld6Zh0jFgRvCv1vaH0VNNAu+FPG1t0WVKIhk1vK3qDDvz18AL1lJ5heBnD1ayq2Dim IoVBPu5AnjMqcOeRppWQLF22y7YH6UTLKKJ4QhIA6KbA1BS7fqoylzBBr10qwPBd8J3h hpkIk5mXEdoASbrz2bnFJ00po2obaGAABkgmZOnSn15ttkfE8gWAr0nc9GSwTnKg0grm WWL+0z4tknCJuC6xHZPWGDI4dFZn5CcocS6/wjv/sFLd3quTb9SNuxtsUvVXXcJbUQXE SIhX0++U5cTJaTk52J/VozUCHu3l7EBo5I9vpt75txMXphC6j3E0SLI+PZoj778cYMJP bdag== X-Gm-Message-State: AHYfb5ibgzm0LVVWF+oyW4+UHAoCudBe7wSy7zkkAxOBodlDh3uXKXnp +6DrLRWaC1qQvBclHQv3rw== X-Received: by 10.28.113.207 with SMTP id d76mr486446wmi.140.1504184927725; Thu, 31 Aug 2017 06:08:47 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 31 Aug 2017 14:08:30 +0100 Message-Id: <20170831130830.12833-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170831130830.12833-1-ard.biesheuvel@linaro.org> References: <20170831130830.12833-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 4/4] Platform/OverdriveBoard: classify legacy INTx interrupts as level high X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.com, Ard Biesheuvel , liming.gao@intel.com, leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Fix the trigger type of the legacy INTx interrupts. The Seattle SoC manual classifies them as level high, not rising edge. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceT= ree.dts | 28 ++++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/Overdrive= BoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/= OverdriveBoardDeviceTree.dts index e57e702029ba..2c05fdbb8b71 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.dts +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDe= viceTree.dts @@ -291,20 +291,20 @@ msi-parent =3D <&msi>; reg =3D <0x0 0xf0000000 0x0 0x10000000>; interrupt-map-mask =3D <0xff00 0x0 0x0 0x7>; - interrupt-map =3D <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ= _TYPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_T= YPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_T= YPE_EDGE_RISING>, - <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_T= YPE_EDGE_RISING>, - - <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_T= YPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_T= YPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_T= YPE_EDGE_RISING>, - <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_T= YPE_EDGE_RISING>, - - <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_T= YPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_T= YPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_T= YPE_EDGE_RISING>, - <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_T= YPE_EDGE_RISING>; + interrupt-map =3D <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ= _TYPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_T= YPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_T= YPE_LEVEL_HIGH>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_T= YPE_LEVEL_HIGH>, + + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_T= YPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_T= YPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_T= YPE_LEVEL_HIGH>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_T= YPE_LEVEL_HIGH>, + + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_T= YPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_T= YPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_T= YPE_LEVEL_HIGH>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_T= YPE_LEVEL_HIGH>; dma-coherent; dma-ranges =3D <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges =3D <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>= , /* I/O Memory (size=3D64K) */ --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel