From nobody Sun May 5 20:16:07 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1494469455800860.0118989452334; Wed, 10 May 2017 19:24:15 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CB23C21A13488; Wed, 10 May 2017 19:24:12 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 330CF21A16E5C for ; Wed, 10 May 2017 19:24:11 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 May 2017 19:24:10 -0700 Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.197.159]) by orsmga001.jf.intel.com with ESMTP; 10 May 2017 19:24:09 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,322,1491289200"; d="scan'208";a="1128836848" From: zwei4 To: edk2-devel@lists.01.org Date: Thu, 11 May 2017 10:24:05 +0800 Message-Id: <20170511022405.13920-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3] Fixed some GCC build errors. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- .../Cpu/Include/Private/Library/CpuS3Lib.h | 4 +- .../Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c | 6 +- .../PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 4 +- .../Cpu/Library/Private/PeiCpuS3Lib/CpuS3Lib.c | 4 +- .../Library/Private/PeiMpServiceLib/Microcode.c | 5 +- .../Library/Private/PeiMpServiceLib/MpService.c | 16 +-- .../BroxtonSiPkg/Include/Library/PmcIpcLib.h | 10 +- .../Private/Library/CseVariableStorageLib.h | 34 +++--- .../Library/CseVariableStorageSelectorLib.h | 8 +- .../BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c | 5 +- .../BaseCseVariableStorageLib.c | 34 +++--- .../CseVariableStorageSelectorLib.c | 6 +- .../PeiCseVariableStorageSelectorLib.c | 6 +- .../Library/DxeSmbiosMemoryLib/SmbiosMemory.h | 6 +- .../Library/DxeSmbiosMemoryLib/SmbiosType16.c | 5 +- .../NorthCluster/PciHostBridge/Dxe/PciHostBridge.c | 41 ++++--- .../NorthCluster/SaInit/Dxe/IgdOpRegion.c | 4 +- .../MdeModulePkg/Include/Ppi/SmmControl.h | 4 +- .../PeiDxeSmmPchSerialIoLib.c | 8 +- .../PeiDxeSmmPchSerialIoLib.inf | 4 - .../SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c | 120 ++++++++++++-----= ---- .../SouthCluster/ScSmiDispatcher/Smm/ScSmmGpi.c | 6 +- .../SouthCluster/ScSmiDispatcher/Smm/ScSmmIchn.c | 26 ++--- .../ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c | 10 +- .../ScSmiDispatcher/Smm/ScSmmPowerButton.c | 6 +- .../SouthCluster/ScSmiDispatcher/Smm/ScSmmSw.c | 6 +- .../SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c | 6 +- .../SouthCluster/ScSmiDispatcher/Smm/ScSmmUsb.c | 10 +- .../Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c | 1 + .../Sdio/Dxe/SD/SdControllerDxe/SdController.c | 3 +- .../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c | 4 +- .../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c | 24 ++--- .../BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c | 22 ++-- .../Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.c | 4 +- .../Library/Private/PeiDxeHeciInitLib/HeciCore.c | 12 +-- .../Txe/Library/Private/PeiSeCUma/SeCUma.c | 12 +-- .../SmmHeci2PowerManagementLib.c | 4 +- 37 files changed, 256 insertions(+), 234 deletions(-) diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/Cp= uS3Lib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS= 3Lib.h index 48b4ac574..54e0e5bb2 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS3Lib.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS3Lib.h @@ -1,7 +1,7 @@ /** @file Header file for Cpu Init Lib Pei Phase. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -27,7 +27,7 @@ **/ EFI_STATUS S3InitializeCpu ( - IN CONST EFI_PEI_SERVICES **PeiServices + IN EFI_PEI_SERVICES **PeiServices ); #endif =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/Pe= iCpuPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyL= ib/PeiCpuPolicyLib.c index 1b67c9813..a645e17a9 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -27,9 +27,7 @@ LoadCpuPreMemDefault ( IN VOID *ConfigBlockPointer ) { - CPU_CONFIG_PREMEM *CpuConfigPreMem; =20 - CpuConfigPreMem =3D ConfigBlockPointer; =20 return EFI_SUCCESS; } @@ -41,9 +39,7 @@ LoadBiosGuardDefault ( IN VOID *ConfigBlockPointer ) { - BIOS_GUARD_CONFIG *BiosGuardConfig; =20 - BiosGuardConfig =3D ConfigBlockPointer; =20 return EFI_SUCCESS; } diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPre= Mem/PeiCpuPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuP= olicyLibPreMem/PeiCpuPolicyLib.c index 92e8a5520..edfdd10fb 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pei= CpuPolicyLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPreMem/Pei= CpuPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -22,9 +22,7 @@ LoadCpuPreMemDefault ( IN VOID *ConfigBlockPointer ) { - CPU_CONFIG_PREMEM *CpuConfigPreMem; =20 - CpuConfigPreMem =3D ConfigBlockPointer; =20 return EFI_SUCCESS; } diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Li= b/CpuS3Lib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3= Lib/CpuS3Lib.c index 8c4c8f34e..f5fde35db 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Lib/CpuS3= Lib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Lib/CpuS3= Lib.c @@ -1,7 +1,7 @@ /** @file Cpu S3 library running on S3 resume paths. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -561,7 +561,7 @@ RestoreSmramCpuData ( **/ EFI_STATUS S3InitializeCpu ( - IN CONST EFI_PEI_SERVICES **PeiServices + IN EFI_PEI_SERVICES **PeiServices ) { EFI_STATUS Status; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServi= ceLib/Microcode.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/Pei= MpServiceLib/Microcode.c index 1b4a0b581..f0c8dd90c 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/M= icrocode.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/M= icrocode.c @@ -1,7 +1,7 @@ /** @file CPU microcode update library. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -194,11 +194,10 @@ InitializeMicrocode ( EFI_STATUS Status; EFI_CPUID_REGISTER Cpuid; UINT32 UcodeRevision; - ACPI_CPU_DATA *mAcpiCpuData; =20 Status =3D EFI_NOT_FOUND; =20 - mAcpiCpuData =3D (ACPI_CPU_DATA *) (ExchangeInfo->AcpiCpuDataAddress); + AsmCpuid ( CPUID_VERSION_INFO, &Cpuid.RegEax, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServi= ceLib/MpService.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/Pei= MpServiceLib/MpService.c index 55e38c632..103ef2ac5 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/M= pService.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/M= pService.c @@ -1,7 +1,7 @@ /** @file PEIM to initialize multi-processor. =20 - Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -730,7 +730,7 @@ SwitchBsp ( IN BOOLEAN EnableOldBsp ) { - EFI_STATUS Status; + CPU_DATA_BLOCK *CpuData; CPU_STATE CpuState; UINT64 *MtrrValues; @@ -804,7 +804,7 @@ SwitchBsp ( } } =20 - Status =3D ChangeCpuState (mMpSystemData->BSP, EnableOldBsp= , CPU_CAUSE_NOT_DISABLED); + ChangeCpuState (mMpSystemData->BSP, EnableOldBsp, CPU_CAUSE_NOT_DISABLED= ); mMpSystemData->BSP =3D CpuNumber; =20 return EFI_SUCCESS; @@ -1004,7 +1004,7 @@ FillMpData ( IN UINTN MaximumCPUsForThisSystem ) { - EFI_STATUS Status; + BOOLEAN HyperThreadingEnabled; =20 mMpSystemData =3D &mMpCpuRuntimeData->MpSystemData; @@ -1025,10 +1025,10 @@ FillMpData ( mMpCpuRuntimeData->AcpiCpuData.APState =3D HyperThreadingEnabled; mMpCpuRuntimeData->AcpiCpuData.StackAddress =3D (EFI_PHYSICAL_ADDRESS= ) (UINTN) StackAddressStart; =20 - Status =3D PrepareGdtIdtForAP ( - (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.Gd= trProfile, - (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.Id= trProfile - ); + PrepareGdtIdtForAP ( + (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.GdtrProfile, + (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.IdtrProfile + ); =20 // // First BSP fills and inits all known values, including it's own record= s. diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h b/= Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h index 905211bc7..923feca42 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h @@ -1,7 +1,7 @@ /** @file Base IPC library implementation. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -169,7 +169,7 @@ typedef union { @retval EFI_NOT_READY Not ready for a new IPC =20 **/ -RETURN_STATUS +EFI_STATUS EFIAPI ReadyForNewIpc ( VOID @@ -182,7 +182,7 @@ ReadyForNewIpc ( @param[in] MessageId The message identifier to send in the IPC pack= et. =20 **/ -RETURN_STATUS +EFI_STATUS EFIAPI IpcSendCommand ( IN UINT32 MessageId @@ -199,7 +199,7 @@ IpcSendCommand ( @param[in, out] BufferSize The size, in bytes, of Buffer= . Ignored if Buffer is NULL. =20 **/ -RETURN_STATUS +EFI_STATUS EFIAPI IpcSendCommandEx ( IN UINT32 Command, @@ -222,7 +222,7 @@ IpcSendCommandEx ( @param[in, out] BufferSize The size, in bytes, of Buffer= . Ignored if Buffer is NULL. =20 **/ -RETURN_STATUS +EFI_STATUS EFIAPI IpcSendCommandBar0Ex ( IN UINT32 PciBar0, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVar= iableStorageLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library= /CseVariableStorageLib.h index 34100b83a..1a2a06eeb 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableSt= orageLib.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableSt= orageLib.h @@ -1,7 +1,7 @@ /** @file CSE Variable Storage Library. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -131,11 +131,11 @@ InitializeCseStorageGlobalVariableStructures ( EFI_STATUS EFIAPI GetNextCseVariableName ( - IN CHAR16 *VariableName, - IN EFI_GUID *VariableGuid, - IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, - OUT VARIABLE_NVM_HEADER **VariablePtr, - OUT BOOLEAN *IsAuthVariable + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, + OUT VARIABLE_NVM_HEADER **VariablePtr, + OUT BOOLEAN *IsAuthVariable ); =20 /** @@ -246,10 +246,10 @@ BuildCseDataFileName ( EFI_STATUS EFIAPI FindVariable ( - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VendorGuid, - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, - OUT VARIABLE_NVM_POINTER_TRACK *VariablePtrTrack + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, + OUT VARIABLE_NVM_POINTER_TRACK *VariablePtrTrack ); =20 /** @@ -312,13 +312,13 @@ FindDeletedVariable ( EFI_STATUS EFIAPI GetCseVariable ( - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VariableGuid, - OUT UINT32 *Attributes OPTIONAL, - IN OUT UINTN *DataSize, - OUT VOID *Data, - OUT VARIABLE_NVM_HEADER *VariableHeader OPTIONAL + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, + OUT UINT32 *Attributes OPTIONAL, + IN OUT UINTN *DataSize, + OUT VOID *Data, + OUT VARIABLE_NVM_HEADER *VariableHeader OPTIONAL ); =20 #endif diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVar= iableStorageSelectorLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private= /Library/CseVariableStorageSelectorLib.h index f1b5cb201..141728083 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableSt= orageSelectorLib.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableSt= orageSelectorLib.h @@ -1,7 +1,7 @@ /** @file CSE Variable Storage Selector Library. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -46,9 +46,9 @@ typedef enum { CSE_VARIABLE_FILE_TYPE EFIAPI GetCseVariableStoreFileType ( - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VendorGuid, - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo ); =20 /** diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c= b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c index 48e037bd9..77aaa85ec 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c @@ -1,7 +1,7 @@ /** @file Base IPC library implementation. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -66,6 +66,7 @@ ReadyForNewIpc ( =20 **/ EFI_STATUS +EFIAPI IpcSendCommandEx ( IN UINT32 Command, IN UINT8 SubCommand, @@ -108,7 +109,7 @@ IpcSendCommandEx ( @param[in, out] BufferSize The size, in bytes, of Buffer. Ig= nored if Buffer is NULL. =20 **/ -RETURN_STATUS +EFI_STATUS EFIAPI IpcSendCommandBar0Ex ( IN UINT32 PciBar0, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariabl= eStorageLib/BaseCseVariableStorageLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/L= ibrary/Private/BaseCseVariableStorageLib/BaseCseVariableStorageLib.c index f60ed52ab..936495394 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariableStorag= eLib/BaseCseVariableStorageLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariableStorag= eLib/BaseCseVariableStorageLib.c @@ -1,7 +1,7 @@ /** @file CSE Variable Storage Library. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016-2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -110,7 +110,7 @@ EstablishAndLoadCseVariableStores ( // // Check if the variable store exists // - Status =3D HeciGetNVMFileSize (CseVariableFileInfo[Type]->FileName= , &VariableHeaderRegionBufferSize); + Status =3D HeciGetNVMFileSize ((UINT8 *)(CseVariableFileInfo[Type]= ->FileName), &VariableHeaderRegionBufferSize); =20 // // If there's an error finding the file, do not establish this sto= re as @@ -354,9 +354,9 @@ ReadCseNvmFile ( } =20 if (HeciProtocolActive =3D=3D CseVariableHeci1Protocol) { - return HeciReadNVMFile (CseFileName, FileOffset, Data, DataSize); + return HeciReadNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataSi= ze); } else if (Heci2Protocol !=3D NULL) { - return Heci2ReadNVMFile (CseFileName, FileOffset, Data, DataSize, Heci= 2Protocol); + return Heci2ReadNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataS= ize, Heci2Protocol); } else { ASSERT (FALSE); } @@ -412,9 +412,9 @@ UpdateCseNvmFile ( } =20 if (HeciProtocolActive =3D=3D CseVariableHeci1Protocol) { - return HeciWriteNVMFile (CseFileName, FileOffset, Data, DataSize, Trun= cate); + return HeciWriteNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataS= ize, Truncate); } else if (Heci2Protocol !=3D NULL) { - Status =3D Heci2WriteNVMFile (CseFileName, FileOffset, Data, DataSize,= Truncate); + Status =3D Heci2WriteNVMFile ((UINT8 *)CseFileName, FileOffset, Data, = DataSize, Truncate); return Status; } else { ASSERT (FALSE); @@ -455,7 +455,7 @@ CreateCseNvmVariableStore ( // // Check if a variable store already exists // - Status =3D HeciGetNVMFileSize (StoreFileName, StoreSize); + Status =3D HeciGetNVMFileSize ((UINT8 *)StoreFileName, StoreSize); if (Status =3D=3D EFI_SUCCESS || (Status !=3D EFI_NOT_FOUND && EFI_ERROR= (Status))) { return Status; } @@ -731,10 +731,10 @@ FindVariableEx ( EFI_STATUS EFIAPI FindVariable ( - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VendorGuid, - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, - OUT VARIABLE_NVM_POINTER_TRACK *VariablePtrTrack + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, + OUT VARIABLE_NVM_POINTER_TRACK *VariablePtrTrack ) { EFI_STATUS Status; @@ -801,9 +801,9 @@ FindVariable ( EFI_STATUS EFIAPI GetNextCseVariableName ( - IN CHAR16 *VariableName, - IN EFI_GUID *VariableGuid, - IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, OUT VARIABLE_NVM_HEADER **VariablePtr, OUT BOOLEAN *IsAuthVariable ) @@ -979,9 +979,9 @@ GetNextCseVariableName ( EFI_STATUS EFIAPI GetCseVariable ( - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VariableGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo, + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, OUT UINT32 *Attributes OPTIONAL, IN OUT UINTN *DataSize, OUT VOID *Data, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVaria= bleStorageSelectorLib/CseVariableStorageSelectorLib.c b/Silicon/BroxtonSoC/= BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/CseVariabl= eStorageSelectorLib.c index 108719615..be65bd8a1 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStor= ageSelectorLib/CseVariableStorageSelectorLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStor= ageSelectorLib/CseVariableStorageSelectorLib.c @@ -31,9 +31,9 @@ EFI_HECI_PROTOCOL *mHeci2Protocol =3D NULL; CSE_VARIABLE_FILE_TYPE EFIAPI GetCseVariableStoreFileType ( - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VendorGuid, - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo ) { CSE_VARIABLE_FILE_TYPE Type; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariable= StorageSelectorLib/PeiCseVariableStorageSelectorLib.c b/Silicon/BroxtonSoC/= BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariabl= eStorageSelectorLib.c index a9d93fe68..f2caaa4f5 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorage= SelectorLib/PeiCseVariableStorageSelectorLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorage= SelectorLib/PeiCseVariableStorageSelectorLib.c @@ -32,9 +32,9 @@ CSE_VARIABLE_FILE_TYPE EFIAPI GetCseVariableStoreFileType ( - IN CONST CHAR16 *VariableName, - IN CONST EFI_GUID *VendorGuid, - IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + IN CSE_VARIABLE_FILE_INFO **CseVariableFileInfo ) { CSE_VARIABLE_FILE_TYPE Type; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbios= MemoryLib/SmbiosMemory.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Lib= rary/DxeSmbiosMemoryLib/SmbiosMemory.h index b62cd67e6..4effcd33b 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryL= ib/SmbiosMemory.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryL= ib/SmbiosMemory.h @@ -3,7 +3,7 @@ This driver will determine memory configuration information from the chi= pset and memory and create SMBIOS memory structures appropriately. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -159,9 +159,9 @@ typedef struct { // // Module-wide global variables // -MEM_INFO_PROTOCOL *mMemInfoHob; +extern MEM_INFO_PROTOCOL *mMemInfoHob; extern EFI_SMBIOS_PROTOCOL *mSmbios; -EFI_SMBIOS_HANDLE mSmbiosType16Handle; +extern EFI_SMBIOS_HANDLE mSmbiosType16Handle; =20 extern CHAR8 *DimmToDevLocator[]; extern CHAR8 *DimmToBankLocator[]; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbios= MemoryLib/SmbiosType16.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Lib= rary/DxeSmbiosMemoryLib/SmbiosType16.c index 2124543b1..194df4494 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryL= ib/SmbiosType16.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryL= ib/SmbiosType16.c @@ -2,7 +2,7 @@ This library will determine memory configuration information from the ch= ipset and memory and create SMBIOS memory structures appropriately. =20 - Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -16,6 +16,9 @@ =20 #include "SmbiosMemory.h" =20 +MEM_INFO_PROTOCOL *mMemInfoHob; +EFI_SMBIOS_HANDLE mSmbiosType16Handle; + // // Physical Memory Array (Type 16) data // diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe= /PciHostBridge.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBrid= ge/Dxe/PciHostBridge.c index 834cace03..3f7a51d27 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHos= tBridge.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHos= tBridge.c @@ -2,7 +2,7 @@ Pci Host Bridge driver: Provides the basic interfaces to abstract a PCI Host Bridge Resource All= ocation. =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -41,24 +41,37 @@ // static UINTN RootBridgeNumber[1] =3D { = 1 }; =20 -static UINT64 RootBridgeAttribute[1][1] =3D { = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM }; +static UINT64 RootBridgeAttribute[1][1] =3D { = {EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM }}; =20 static EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1= ] =3D { - { - ACPI_DEVICE_PATH, - ACPI_DP, - (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8), - EISA_PNP_ID(0x0A03), - 0, - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - END_DEVICE_PATH_LENGTH, - 0 +{=20 + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A03), + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } } + + } }; =20 -static PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] =3D { { 0, 25= 5, 0, 0xffffffff, 0, 1 << 16 } }; +static PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] =3D { {{ 0, 2= 55, 0, 0xffffffff, 0, (1 << 16) } }}; =20 static EFI_HANDLE mDriverImageHandle; =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpR= egion.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegi= on.c index 961c6b2a0..5d147879a 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegion.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegion.c @@ -3,7 +3,7 @@ Software SCI interface between system BIOS, ASL code, and Graphics drive= rs. The code in this file will load the driver and initialize the interface. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -722,7 +722,7 @@ IgdOpRegionInit ( // Status =3D EfiCreateEventReadyToBootEx( TPL_CALLBACK, - SetGOPVersionCallback, + (EFI_EVENT_NOTIFY)SetGOPVersionCallback, NULL, &mReadyToBootEvent ); diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Includ= e/Ppi/SmmControl.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePk= g/Include/Ppi/SmmControl.h index e7b67c5a6..7dd71a530 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Include/Ppi/S= mmControl.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Include/Ppi/S= mmControl.h @@ -9,7 +9,7 @@ event from a platform chipset agent is an optional capability for both I= A-32 and Itanium-based systems. =20 - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -25,7 +25,7 @@ #define _SMM_CONTROL_PPI_H_ =20 #define PEI_SMM_CONTROL_PPI_GUID \ - { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0= xc5 } + { 0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, = 0xc5} } =20 typedef struct _PEI_SMM_CONTROL_PPI PEI_SMM_CONTROL_PPI; =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmm= PchSerialIoLib/PeiDxeSmmPchSerialIoLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/= SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c index 36dcf53d1..209d6493d 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSeri= alIoLib/PeiDxeSmmPchSerialIoLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSeri= alIoLib/PeiDxeSmmPchSerialIoLib.c @@ -3,7 +3,7 @@ All function in this library is available for PEI, DXE, and SMM, But do not support UEFI RUNTIME environment call. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -214,7 +214,7 @@ ConfigureSerialIoController ( Bar =3D MmioRead32 (PciCfgBase + R_LPSS_IO_BAR) & 0xFFFFF000; } =20 - MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar); + MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, (UINT32)Bar); =20 // // Set Memory space Enable @@ -236,7 +236,7 @@ ConfigureSerialIoController ( =20 do { PchPcrRead32(0xC6, SerialIoPsf3Offsets[Controller].Psf3BaseAddre= ss + 0x001C, &Data32); - } while (Data32 & BIT18 !=3D BIT18); + } while ((Data32 & BIT18) !=3D BIT18); =20 // // Assign BAR0 and Set Memory space Enable @@ -254,7 +254,7 @@ ConfigureSerialIoController ( // // Update Address Remap Register with Current BAR // - MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar); + MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, (UINT32)Bar); =20 /// /// Get controller out of reset diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmm= PchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf b/Silicon/BroxtonSoC/BroxtonSiPk= g/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf index 2e8b9b5bf..da4f849a1 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSeri= alIoLib/PeiDxeSmmPchSerialIoLib.inf +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSeri= alIoLib/PeiDxeSmmPchSerialIoLib.inf @@ -35,7 +35,3 @@ MmPciLib ScPlatformLib =20 -[BuildOptions] - *_*_IA32_ASM_FLAGS =3D /w /Od /GL- - *_*_IA32_CC_FLAGS =3D /w /Od /GL- - *_*_X64_CC_FLAGS =3D /w /Od /GL- diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmCore.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatch= er/Smm/ScSmmCore.c index c9a956677..2886a849e 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mCore.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mCore.c @@ -2,7 +2,7 @@ This driver is responsible for the registration of child drivers and the abstraction of the SC SMI sources. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -33,84 +33,102 @@ PRIVATE_DATA mPrivateData =3D { // for the s= tructure NULL, // Handler returned whan calling S= miHandlerRegister NULL, // EFI handle returned when callin= g InstallMultipleProtocolInterfaces { // protocol arrays + + { // // elements within the array // - { - PROTOCOL_SIGNATURE, - UsbType, - &gEfiSmmUsbDispatch2ProtocolGuid, - { - (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, - (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister - } + (UINTN)PROTOCOL_SIGNATURE, + UsbType, + &gEfiSmmUsbDispatch2ProtocolGuid, + { + { + (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, + (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister + } + } + }, { - PROTOCOL_SIGNATURE, - SxType, - &gEfiSmmSxDispatch2ProtocolGuid, - { - (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, - (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister - } + + (UINTN)PROTOCOL_SIGNATURE, + SxType, + &gEfiSmmSxDispatch2ProtocolGuid, + {{ + (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, + (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister + }} + =20 }, { - PROTOCOL_SIGNATURE, - SwType, - &gEfiSmmSwDispatch2ProtocolGuid, - { - (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, - (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister, - (UINTN) MAXIMUM_SWI_VALUE - } + + (UINTN)PROTOCOL_SIGNATURE, + SwType, + &gEfiSmmSwDispatch2ProtocolGuid, + {{ + (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, + (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister, + (UINTN) MAXIMUM_SWI_VALUE + }} + =20 }, { - PROTOCOL_SIGNATURE, - GpiType, - &gEfiSmmGpiDispatch2ProtocolGuid, - { - (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, - (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister, - (UINTN) V_GPIO_NUM_SUPPORTED_GPIS - } + + (UINTN)PROTOCOL_SIGNATURE, + GpiType, + &gEfiSmmGpiDispatch2ProtocolGuid, + {{ + (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, + (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister, + (UINTN) V_GPIO_NUM_SUPPORTED_GPIS + }} + }, { - PROTOCOL_SIGNATURE, - IchnType, - &gEfiSmmIchnDispatchProtocolGuid, - { - (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, - (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister - } + + (UINTN)PROTOCOL_SIGNATURE, + IchnType, + &gEfiSmmIchnDispatchProtocolGuid, + {{ + (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, + (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister + }} + }, - { - PROTOCOL_SIGNATURE, + {=20 + + (UINTN)PROTOCOL_SIGNATURE, IchnExType, &gEfiSmmIchnDispatchExProtocolGuid, - { + {{ (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister - } + }} + }, - { - PROTOCOL_SIGNATURE, + { =20 + + (UINTN)PROTOCOL_SIGNATURE, PowerButtonType, &gEfiSmmPowerButtonDispatch2ProtocolGuid, - { + {{ (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister - } + }} + =20 }, { - PROTOCOL_SIGNATURE, + + (UINTN)PROTOCOL_SIGNATURE, PeriodicTimerType, &gEfiSmmPeriodicTimerDispatch2ProtocolGuid, - { + {{ (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister, (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister, (UINTN) ScSmmPeriodicTimerDispatchGetNextShorterInterval - } - }, + }} + + } } }; =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmGpi.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatche= r/Smm/ScSmmGpi.c index 195288edf..090db445f 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mGpi.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mGpi.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Smm Gpi dispatch= protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -26,7 +26,7 @@ CONST SC_SMM_SOURCE_DESC SC_GPI_SOURCE_DESC_TEMPLATE =3D= { { { { - GPIO_ADDR_TYPE, 0x0 + GPIO_ADDR_TYPE, {0x0} }, S_GPIO_GP_SMI_EN, 0x0, }, @@ -36,7 +36,7 @@ CONST SC_SMM_SOURCE_DESC SC_GPI_SOURCE_DESC_TEMPLATE =3D= { { { { - GPIO_ADDR_TYPE, 0x0 + GPIO_ADDR_TYPE, {0x0} }, S_GPIO_GP_SMI_STS, 0x0, }, diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmIchn.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatch= er/Smm/ScSmmIchn.c index aeb3b1538..b2b58edb8 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mIchn.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mIchn.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Smm Ichn dispatc= h protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -56,7 +56,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] =3D { { { ACPI_ADDR_TYPE, - R_ACPI_PM1_EN + {R_ACPI_PM1_EN} }, S_ACPI_PM1_EN, N_ACPI_PM1_EN_RTC @@ -68,7 +68,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] =3D { { { ACPI_ADDR_TYPE, - R_ACPI_PM1_STS + {R_ACPI_PM1_STS} }, S_ACPI_PM1_STS, N_ACPI_PM1_STS_RTC @@ -122,7 +122,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_SERIRQ @@ -154,7 +154,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_TCO @@ -166,7 +166,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_TCO @@ -198,7 +198,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_TCO @@ -207,7 +207,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { PCR_ADDR_TYPE, - SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS) + {SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS)} }, S_PCR_ITSS_NMICSTS, N_PCR_ITSS_NMI2SMIEN @@ -218,7 +218,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { PCR_ADDR_TYPE, - SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS) + {SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS)} }, S_PCR_ITSS_NMICSTS, N_PCR_ITSS_NMI2SMISTS @@ -251,7 +251,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_SPI_SSMI @@ -276,7 +276,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_SPI_SSMI @@ -474,7 +474,7 @@ SC_SMM_SOURCE_DESC ICHN_EX_SOURCE_DESCS[IchnExTypeMAX -= IchnExPciExpress] =3D { { { ACPI_ADDR_TYPE, - R_ACPI_PM1_EN + {R_ACPI_PM1_EN} }, S_ACPI_PM1_EN, N_ACPI_PM1_EN_TMROF @@ -486,7 +486,7 @@ SC_SMM_SOURCE_DESC ICHN_EX_SOURCE_DESCS[IchnExTypeMAX -= IchnExPciExpress] =3D { { { ACPI_ADDR_TYPE, - R_ACPI_PM1_STS + {R_ACPI_PM1_STS} }, S_ACPI_PM1_STS, N_ACPI_PM1_STS_TMROF diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmPeriodicTimer.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSm= iDispatcher/Smm/ScSmmPeriodicTimer.c index a7d69fa7e..c752e2e4e 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mPeriodicTimer.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mPeriodicTimer.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Periodical Timer= dispatch protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -115,7 +115,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_PERIODIC @@ -127,7 +127,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_PERIODIC @@ -141,7 +141,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_SWSMI_TMR @@ -153,7 +153,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_SWSMI_TMR diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmPowerButton.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiD= ispatcher/Smm/ScSmmPowerButton.c index 497ca74a1..166658fa5 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mPowerButton.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mPowerButton.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Smm Power Button= dispatch protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -21,7 +21,7 @@ CONST SC_SMM_SOURCE_DESC POWER_BUTTON_SOURCE_DESC =3D { { { ACPI_ADDR_TYPE, - R_ACPI_PM1_EN + {R_ACPI_PM1_EN} }, S_ACPI_PM1_EN, N_ACPI_PM1_EN_PWRBTN @@ -33,7 +33,7 @@ CONST SC_SMM_SOURCE_DESC POWER_BUTTON_SOURCE_DESC =3D { { { ACPI_ADDR_TYPE, - R_ACPI_PM1_STS + {R_ACPI_PM1_STS} }, S_ACPI_PM1_STS, N_ACPI_PM1_STS_PWRBTN diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmSw.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher= /Smm/ScSmmSw.c index dab2309fc..8cdaae153 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mSw.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mSw.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Smm Sw dispatch = protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -30,7 +30,7 @@ CONST SC_SMM_SOURCE_DESC SW_SOURCE_DESC =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_APMC @@ -42,7 +42,7 @@ CONST SC_SMM_SOURCE_DESC SW_SOURCE_DESC =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_APM diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmSx.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher= /Smm/ScSmmSx.c index e1aa7fdcd..8baf1c0eb 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mSx.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mSx.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Smm Sx dispatch = protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -25,7 +25,7 @@ const SC_SMM_SOURCE_DESC SX_SOURCE_DESC =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_ON_SLP_EN @@ -37,7 +37,7 @@ const SC_SMM_SOURCE_DESC SX_SOURCE_DESC =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_ON_SLP_EN diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/S= mm/ScSmmUsb.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatche= r/Smm/ScSmmUsb.c index ea512121e..c514f42dc 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mUsb.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSm= mUsb.c @@ -1,7 +1,7 @@ /** @file File to contain all the hardware specific stuff for the Smm USB dispatch= protocol. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -22,7 +22,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB1_LE= GACY =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_LEGACY_USB @@ -34,7 +34,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB1_LE= GACY =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_LEGACY_USB @@ -48,7 +48,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB3_LE= GACY =3D { { { ACPI_ADDR_TYPE, - R_SMI_EN + {R_SMI_EN} }, S_SMI_EN, N_SMI_EN_LEGACY_USB3 @@ -60,7 +60,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB3_LE= GACY =3D { { { ACPI_ADDR_TYPE, - R_SMI_STS + {R_SMI_STS} }, S_SMI_STS, N_SMI_STS_LEGACY_USB3 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcM= ediaDeviceDxe/MMCSDTransfer.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluste= r/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c index d367326c1..13258dec0 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDev= iceDxe/MMCSDTransfer.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDev= iceDxe/MMCSDTransfer.c @@ -2244,6 +2244,7 @@ MmcGetCurrentPartitionNum ( =20 **/ VOID +EFIAPI SetEmmcWpOnEvent( IN EFI_EVENT Event, IN VOID *Context diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdCon= trollerDxe/SdController.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sd= io/Dxe/SD/SdControllerDxe/SdController.c index ff01c85e1..f4811969e 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdController= Dxe/SdController.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdController= Dxe/SdController.c @@ -1,7 +1,7 @@ /** @file The SD host controller driver model and HC protocol routines. =20 - Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -247,6 +247,7 @@ GetErrorReason ( =20 **/ EFI_STATUS +EFIAPI SetHighSpeedMode ( IN EFI_SD_HOST_IO_PROTOCOL *This, IN BOOLEAN Enable diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c b/Silic= on/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c index bb98ae04b..3c114246c 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c @@ -1,7 +1,7 @@ /** @file HECI driver. =20 - Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -76,7 +76,7 @@ FlashDeviceEndOfPostEvent ( Status =3D gBS->LocateProtocol ( &gEfiHeciSmmRuntimeProtocolGuid, NULL, - &mHeci2Protocol + (VOID **)&mHeci2Protocol ); if (GetFirstGuidHob (&gFdoModeEnabledHobGuid) =3D=3D NULL) { ASSERT_EFI_ERROR (Status); diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c b/Silic= on/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c index 0353ba701..c95cf0195 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c @@ -1,7 +1,7 @@ /** @file HECI Smm driver. =20 - Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -1217,15 +1217,15 @@ AtRuntime ( =20 =20 EFI_HECI_PROTOCOL mHeciSmmProtocol =3D { - EfiHeciSendwack, - EfiHeciReadMessage, - EfiHeciSendMessage, - EfiHeciReset, - EfiHeciInit, - EfiHeciResetWait, - EfiHeciReinit, - EfiHeciGetSecStatus, - EfiHeciGetSecMode + (EFI_HECI_SENDWACK)EfiHeciSendwack, + (EFI_HECI_READ_MESSAGE)EfiHeciReadMessage, + (EFI_HECI_SEND_MESSAGE)EfiHeciSendMessage, + (EFI_HECI_RESET)EfiHeciReset, + (EFI_HECI_INIT)EfiHeciInit, + (EFI_HECI_RESET_WAIT)EfiHeciResetWait, + (EFI_HECI_REINIT)EfiHeciReinit, + (EFI_HECI_GET_SEC_STATUS)EfiHeciGetSecStatus, + (EFI_HECI_GET_SEC_MODE)EfiHeciGetSecMode }; =20 EFI_HECI2_PM_PROTOCOL mHeci2PmSmmProtocol =3D { @@ -1342,7 +1342,7 @@ HeciSmmInitialize ( ASSERT_EFI_ERROR (Status); =20 SmmHandle =3D NULL; - Status =3D gSmst->SmiHandlerRegister (SmmPlatformHeci2ProxyHandler, NULL= , &SmmHandle); + Status =3D gSmst->SmiHandlerRegister ((EFI_SMM_HANDLER_ENTRY_POINT2)SmmP= latformHeci2ProxyHandler, NULL, &SmmHandle); =20 // // Register EFI_SMM_END_OF_DXE_PROTOCOL_GUID notify function. diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe= .c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c index a23a1f48a..53184c414 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c @@ -1,7 +1,7 @@ /** @file HECI Smm Runtime Dxe driver. =20 - Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -523,15 +523,15 @@ EfiHeciGetSecMode ( } =20 EFI_HECI_PROTOCOL mHeciProtocol =3D { - EfiHeciSendwack, - EfiHeciReadMessage, - EfiHeciSendMessage, - EfiHeciReset, - EfiHeciInit, - EfiHeciResetWait, - EfiHeciReinit, - EfiHeciGetSecStatus, - EfiHeciGetSecMode + (EFI_HECI_SENDWACK)EfiHeciSendwack, + (EFI_HECI_READ_MESSAGE)EfiHeciReadMessage, + (EFI_HECI_SEND_MESSAGE)EfiHeciSendMessage, + (EFI_HECI_RESET)EfiHeciReset, + (EFI_HECI_INIT)EfiHeciInit, + (EFI_HECI_RESET_WAIT)EfiHeciResetWait, + (EFI_HECI_REINIT)EfiHeciReinit, + (EFI_HECI_GET_SEC_STATUS)EfiHeciGetSecStatus, + (EFI_HECI_GET_SEC_MODE)EfiHeciGetSecMode }; =20 =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmH= eciMsgLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmm= HeciMsgLib.c index f64f50ad5..2fd56f891 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmHeciMsgL= ib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmHeciMsgL= ib.c @@ -236,7 +236,7 @@ Heci2WriteNVMFile ( // // Copy the name of the NVM file to write // - ASSERT (AsciiStrLen (FileName) <=3D sizeof (WriteFileMessage->FileName= )); + ASSERT (AsciiStrLen ((CONST CHAR8*)FileName) <=3D sizeof (WriteFileMes= sage->FileName)); ASSERT (sizeof (Heci2DataBuffer) > sizeof (HECI2_TRUSTED_CHANNEL_BIOS_= WRITE_REQ)); AsciiStrCpyS ((CHAR8 *) WriteFileMessage->FileName, sizeof (WriteFileM= essage->FileName), (CONST CHAR8 *) FileName); =20 @@ -351,7 +351,7 @@ Heci2ReadNVMFile ( // // Copy the name of the NVM file to read // - ASSERT (AsciiStrLen (FileName) <=3D sizeof (ReadFileMessage->FileName)= ); + ASSERT (AsciiStrLen ((CONST CHAR8*)FileName) <=3D sizeof (ReadFileMess= age->FileName)); ASSERT (sizeof (Heci2DataBuffer) > sizeof (HECI2_TRUSTED_CHANNEL_BIOS_= READ_REQ)); AsciiStrCpyS ((CHAR8 *) ReadFileMessage->FileName, sizeof (ReadFileMes= sage->FileName), (CONST CHAR8 *) FileName); =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeci= InitLib/HeciCore.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/Pe= iDxeHeciInitLib/HeciCore.c index 92934090d..50340eaba 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeciInitLib= /HeciCore.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeciInitLib= /HeciCore.c @@ -1,7 +1,7 @@ /** @file Heci driver core. For Dxe Phase, determines the HECI device and initiali= zes it. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -528,7 +528,6 @@ HeciReceive ( ) { UINTN ReadSize; - UINTN Size; UINTN Index; UINTN HeciMBAR; HECI_MESSAGE_HEADER MessageHeader; @@ -543,7 +542,7 @@ HeciReceive ( EFI_STATUS Status; =20 DEBUG ((EFI_D_INFO, "Start HeciReceive\n")); - Size =3D 0; + ReadSize =3D 0; =20 HeciMBAR =3D CheckAndFixHeciForAccess (HeciDev); @@ -700,7 +699,7 @@ HeciSend ( UINTN HeciMBAR; UINTN StallCount; UINTN MaxCount; - UINTN OverAllDelay; + BOOLEAN TimeOut; HECI_MESSAGE_HEADER MessageHeader; EFI_HECI2_PM_PROTOCOL *Heci2PmProtocol; @@ -748,7 +747,7 @@ HeciSend ( MaxBuffer =3D HostControlReg->r.H_CBD; =20 MaxCount =3D 0; - OverAllDelay =3D 0; + TimeOut =3D FALSE; =20 DEBUG_CODE_BEGIN (); @@ -961,11 +960,10 @@ HeciInitialize( HECI_FWS_REGISTER SeCFirmwareStatus; UINTN HeciMBAR; EFI_STATUS Status; - UINT32 SeCMode; + =20 DEBUG ((EFI_D_INFO, "HECI Initialize ++ \n ")); =20 - SeCMode =3D SEC_MODE_NORMAL; =20 // // Make sure that HECI device BAR is correct and device is enabled. diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/= SeCUma.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/Se= CUma.c index 06d1c260a..459ff4373 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/SeCUma.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/SeCUma.c @@ -1,7 +1,7 @@ /** @file Framework PEIM to SeCUma. =20 - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -141,7 +141,6 @@ HandleSecBiosAction ( IN UINT8 BiosAction ) { - EFI_STATUS Status; HECI_FWS_REGISTER SeCFirmwareStatus; =20 // @@ -163,7 +162,7 @@ HandleSecBiosAction ( // Case: Perform Non-Power Cycle Reset // DEBUG ((DEBUG_ERROR, "SEC FW has requested a Non-PCR.\n")); - Status =3D PerformReset (CBM_DIR_NON_PCR); + PerformReset (CBM_DIR_NON_PCR); break; =20 case CBM_DIR_PCR: @@ -171,7 +170,7 @@ HandleSecBiosAction ( // Case: Perform Power Cycle Reset // DEBUG ((DEBUG_ERROR, "SEC FW has requested a PCR.\n")); - Status =3D PerformReset (CBM_DIR_PCR); + PerformReset (CBM_DIR_PCR); break; =20 case 3: @@ -200,7 +199,7 @@ HandleSecBiosAction ( // Case: Perform Global Reset // DEBUG ((DEBUG_ERROR, "SEC FW has requested a Global Reset.\n")); - Status =3D PerformReset (CBM_DIR_GLOBAL_RESET); + PerformReset (CBM_DIR_GLOBAL_RESET); break; =20 case CBM_DIR_CONTINUE_POST: @@ -333,7 +332,6 @@ PerformReset ( UINT8 ResetType ) { - EFI_STATUS Status; UINT32 Data32; UINT32 GpioBase; UINT8 Reset; @@ -342,7 +340,7 @@ PerformReset ( Reset =3D 0; GpioBase =3D 0; =20 - Status =3D ClearDISB (); + ClearDISB (); =20 ETR =3D (UINT32) MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PMC, PCI_FUNCTION= _NUMBER_PMC_IPC1, R_PMC_PMIR); MmioAnd32 ( diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManag= ementLib/SmmHeci2PowerManagementLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe= /Library/SmmHeci2PowerManagementLib/SmmHeci2PowerManagementLib.c index 4bf66dc78..79b5935e4 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManagementLi= b/SmmHeci2PowerManagementLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManagementLi= b/SmmHeci2PowerManagementLib.c @@ -1,7 +1,7 @@ /** @file Implementation file for the HECI2 Power Management library. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016-2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -41,7 +41,7 @@ GetHeci2PmProtocol ( Status =3D gSmst->SmmLocateProtocol ( &gEfiHeci2PmProtocolGuid, NULL, - &mHeci2PmProtocol + (VOID **)&mHeci2PmProtocol ); =20 if (EFI_ERROR (Status)) { --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel