From nobody Fri May 3 14:57:33 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1493964361621961.6905275908413; Thu, 4 May 2017 23:06:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 30D5521A134BC; Thu, 4 May 2017 23:06:00 -0700 (PDT) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A6B9721A134AE for ; Thu, 4 May 2017 23:05:58 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP; 04 May 2017 23:05:58 -0700 Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.197.110]) by orsmga001.jf.intel.com with ESMTP; 04 May 2017 23:05:57 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,291,1491289200"; d="scan'208";a="1126701959" From: zwei4 To: edk2-devel@lists.01.org Date: Fri, 5 May 2017 14:05:49 +0800 Message-Id: <20170505060549.16816-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3] Clean up BOARD_ID identification code. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shifei Lu MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" BOARD_ID bits and GPIO pins mapping: BOARD_ID0 GPIO_224(J45) BOARD_ID1 GPIO_213(M47) BOARD_ID2 GPIO_223(H48) BOARD_ID3 GP_CAMERASB10(R34) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 CC: Mang Guo CC: Shifei Lu --- .../Board/LeafHill/BoardInitPreMem/PlatformId.c | 268 ++++++++---------= ---- .../MinnowBoard3/BoardInitPreMem/PlatformId.c | 265 ++++++++---------= --- .../Common/Include/Guid/PlatformInfo.h | 4 +- .../Common/Include/Guid/PlatformInfo_Aplk.h | 4 +- 4 files changed, 211 insertions(+), 330 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Pla= tformId.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Plat= formId.c index 19c1bb561..d550fd400 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId= .c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId= .c @@ -1,7 +1,7 @@ /** @file Implement Platform ID code. =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -20,59 +20,6 @@ #include #include "PlatformId.h" =20 -/** - Read in GPIO state and return it. - -**/ -BOOLEAN -IsThisMinnow ( - VOID - ) -{ - UINT32 CommAndOffset =3D NW_GPIO_215; - BXT_CONF_PAD0 PadConfg0; - BXT_CONF_PAD1 PadConfg1; - BOOLEAN ReturnValue; - - if (PcdGetBool (PcdMinnowBoardDetectionRun)) { - // - // Already detected this. Return stored value. - // - ReturnValue =3D PcdGetBool (PcdMinnowBoardDetected); - DEBUG ((EFI_D_INFO, "Already detected. Returning stored value =3D %x\n= ", ReturnValue)); - } else { - // - // Enable GPI mode with a pull-up - // - PadConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_= CONF0_OFFSET); - PadConfg1.padCnf1 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_= CONF1_OFFSET); - PadConfg0.r.PMode =3D M0; // Set to GPIO mode - PadConfg0.r.GPIORxTxDis =3D GPI; // Set to GPI - PadConfg1.r.IOSTerm =3D EnPu; // Enable pull-up - PadConfg1.r.Term =3D P_20K_H; // Set to 20K pull-up - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, PadConfg0.pad= Cnf0); - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, PadConfg1.pad= Cnf1); - - // - // Read in GPI state and set return value - // - PadConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - ReturnValue =3D (BOOLEAN) PadConfg0.r.GPIORxState; - - // - // Set detection PCDs - // - PcdSetBoolS (PcdMinnowBoardDetectionRun, TRUE); - PcdSetBoolS (PcdMinnowBoardDetected, ReturnValue); - } - - // - // Return answer - // - return ReturnValue; -} - - EFI_STATUS EFIAPI GetEmbeddedBoardIdFabId( @@ -88,121 +35,114 @@ GetEmbeddedBoardIdFabId( DEBUG ((DEBUG_INFO, "GetEmbeddedBoardIdFabId++\n")); =20 // - // Set BoardId & FabId + // Board_ID0: PMIC_STDBY + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00F0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; // Set to GPIO mode + padConfg0.r.GPIORxTxDis =3D 0x1; // Set to GPI + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + padConfg1.padCnf1 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OF= FSET); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Board_ID1: PMIC_SDWN_B + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Board_ID2: PMIC_RESET_B + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C8); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Board_ID3: PMIC_PWRGOOD + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); // - if (IsThisMinnow ()) { - // - // NW_PMIC_PWRGOOD says this is a Minnow board. Force Minnow defaults. - // - *BoardId =3D BOARD_ID_MINNOW; - *FabId =3D PcdGet8 (PcdDefaultFabId); + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + =20 + *BoardId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C0) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3)); + + DEBUG ((DEBUG_INFO, "BoardId from PMIC strap: %02X\n", *BoardId)); =20 - DEBUG ((EFI_D_INFO, "BoardId forced from NW_GPIO_215 detection: %02X\= n", *BoardId)); - DEBUG ((EFI_D_INFO, " FabId forced from NW_GPIO_215 detection: %02X\= n", *FabId)); - } else { - // - // Board_ID0: PMIC_STDBY - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00F0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; // Set to GPIO mode - padConfg0.r.GPIORxTxDis =3D 0x1; // Set to GPI - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - padConfg1.padCnf1 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_= OFFSET); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Board_ID1: PMIC_SDWN_B - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Board_ID2: PMIC_RESET_B - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C8); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Board_ID3: PMIC_PWRGOOD - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - *BoardId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0)= + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2)); + // + // Fab_ID0: PMIC_I2C_SDA + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0108); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Fab_ID1: PMIC_I2C_SCL + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0100); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + //Set to Pull Up 20K + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Fab_ID2: PMIC_BCUDISW2 + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D8); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Fab_ID3: PMIC_BCUDISCRIT + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00E0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); =20 - DEBUG ((DEBUG_INFO, "BoardId from PMIC strap: %02X\n", *BoardId)); - // - // Fab_ID0: PMIC_I2C_SDA - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0108); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Fab_ID1: PMIC_I2C_SCL - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0100); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Fab_ID2: PMIC_BCUDISW2 - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D8); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Fab_ID3: PMIC_BCUDISCRIT - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00E0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); + *FabId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0108) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0100) + BXT= _GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + BXT= _GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + BXT= _GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3)); =20 - *FabId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0108) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0100) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3)); + DEBUG ((EFI_D_INFO, "FabId from PMIC strap: %02X\n", *FabId)); =20 - DEBUG ((EFI_D_INFO, "FabId from PMIC strap: %02X\n", *FabId)); - } =20 return EFI_SUCCESS; } diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem= /PlatformId.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPre= Mem/PlatformId.c index e7135a9dc..d550fd400 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/Platfo= rmId.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/Platfo= rmId.c @@ -1,7 +1,7 @@ /** @file Implement Platform ID code. =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -20,59 +20,6 @@ #include #include "PlatformId.h" =20 -/** - Read in GPIO state and return it. - -**/ -BOOLEAN -IsThisMinnow ( - VOID - ) -{ - UINT32 CommAndOffset =3D NW_GPIO_215; - BXT_CONF_PAD0 PadConfg0; - BXT_CONF_PAD1 PadConfg1; - BOOLEAN ReturnValue; - - if (PcdGetBool (PcdMinnowBoardDetectionRun)) { - // - // Already detected this. Return stored value. - // - ReturnValue =3D PcdGetBool (PcdMinnowBoardDetected); - DEBUG ((EFI_D_INFO, "Already detected. Returning stored value =3D %x\n= ", ReturnValue)); - } else { - // - // Enable GPI mode with a pull-up - // - PadConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_= CONF0_OFFSET); - PadConfg1.padCnf1 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_= CONF1_OFFSET); - PadConfg0.r.PMode =3D M0; // Set to GPIO mode - PadConfg0.r.GPIORxTxDis =3D GPI; // Set to GPI - PadConfg1.r.IOSTerm =3D EnPu; // Enable pull-up - PadConfg1.r.Term =3D P_20K_H; // Set to 20K pull-up - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, PadConfg0.pad= Cnf0); - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, PadConfg1.pad= Cnf1); - - // - // Read in GPI state and set return value - // - PadConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - ReturnValue =3D (BOOLEAN) PadConfg0.r.GPIORxState; - - // - // Set detection PCDs - // - PcdSetBoolS (PcdMinnowBoardDetectionRun, TRUE); - PcdSetBoolS (PcdMinnowBoardDetected, ReturnValue); - } - - // - // Return answer - // - return ReturnValue; -} - - EFI_STATUS EFIAPI GetEmbeddedBoardIdFabId( @@ -88,120 +35,114 @@ GetEmbeddedBoardIdFabId( DEBUG ((DEBUG_INFO, "GetEmbeddedBoardIdFabId++\n")); =20 // - // Set BoardId & FabId + // Board_ID0: PMIC_STDBY + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00F0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; // Set to GPIO mode + padConfg0.r.GPIORxTxDis =3D 0x1; // Set to GPI + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + padConfg1.padCnf1 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OF= FSET); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Board_ID1: PMIC_SDWN_B + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Board_ID2: PMIC_RESET_B + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C8); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Board_ID3: PMIC_PWRGOOD + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K // - if (IsThisMinnow ()) { - // - // NW_PMIC_PWRGOOD says this is a Minnow board. Force Minnow defaults. - // - *BoardId =3D BOARD_ID_MINNOW; - *FabId =3D PcdGet8 (PcdDefaultFabId); + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + =20 + *BoardId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C0) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3)); =20 - DEBUG ((EFI_D_INFO, "BoardId forced from NW_GPIO_215 detection: %02X\= n", *BoardId)); - DEBUG ((EFI_D_INFO, " FabId forced from NW_GPIO_215 detection: %02X\= n", *FabId)); - } else { - // - // Board_ID0: PMIC_STDBY - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00F0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; // Set to GPIO mode - padConfg0.r.GPIORxTxDis =3D 0x1; // Set to GPI - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - padConfg1.padCnf1 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_= OFFSET); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Board_ID1: PMIC_SDWN_B - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Board_ID2: PMIC_RESET_B - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C8); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Board_ID3: PMIC_PWRGOOD - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00C0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - *BoardId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00F0)= + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D0) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00C8) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2)); + DEBUG ((DEBUG_INFO, "BoardId from PMIC strap: %02X\n", *BoardId)); =20 - DEBUG ((DEBUG_INFO, "BoardId from PMIC strap: %02X\n", *BoardId)); + // + // Fab_ID0: PMIC_I2C_SDA + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0108); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Fab_ID1: PMIC_I2C_SCL + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0100); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + //Set to Pull Up 20K + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Fab_ID2: PMIC_BCUDISW2 + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D8); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); + // + // Fab_ID3: PMIC_BCUDISCRIT + // + CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00E0); + padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OF= FSET); + padConfg0.r.PMode =3D 0; + padConfg0.r.GPIORxTxDis =3D 0x1; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCn= f0); + // + // Set to Pull Up 20K + // + padConfg1.r.Term =3D 0xC; + GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); =20 - // - // Fab_ID0: PMIC_I2C_SDA - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0108); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Fab_ID1: PMIC_I2C_SCL - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x0100); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - //Set to Pull Up 20K - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Fab_ID2: PMIC_BCUDISW2 - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00D8); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); - // - // Fab_ID3: PMIC_BCUDISCRIT - // - CommAndOffset =3D GetCommOffset (NORTHWEST, 0x00E0); - padConfg0.padCnf0 =3D GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_= OFFSET); - padConfg0.r.PMode =3D 0; - padConfg0.r.GPIORxTxDis =3D 0x1; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.pad= Cnf0); - // - // Set to Pull Up 20K - // - padConfg1.r.Term =3D 0xC; - GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.pad= Cnf1); + *FabId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0108) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0100) + BXT= _GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + BXT= _GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \ + (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + BXT= _GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3)); =20 - *FabId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0108) += BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x0100) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 2) | \ - (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + B= XT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 3)); + DEBUG ((EFI_D_INFO, "FabId from PMIC strap: %02X\n", *FabId)); =20 - DEBUG ((EFI_D_INFO, "FabId from PMIC strap: %02X\n", *FabId)); - } =20 return EFI_SUCCESS; } diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h= b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h index aed58998c..5db0cbc33 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h @@ -1,7 +1,7 @@ /** @file GUID used for Platform Info Data entries in the HOB list. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -163,7 +163,7 @@ typedef enum { =20 typedef enum { BOARD_ID_LFH_CRB =3D 0x07, // Leaf Hill - BOARD_ID_MINNOW =3D 0x80, // Minnow Board + BOARD_ID_MINNOW =3D 0x0F, // Minnow Board BOARD_ID_APL_UNKNOWN =3D 0xFF } APL_BOARD_ID_LIST; =20 diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_A= plk.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h index d02afcbd2..e8063de32 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h @@ -1,7 +1,7 @@ /** @file GUID used for Platform Info Data entries in the HOB list. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -149,7 +149,7 @@ typedef struct { =20 typedef enum { BOARD_ID_LFH_CRB =3D 0x07, // Leaf Hill - BOARD_ID_MINNOW =3D 0x80, // Minnow Board + BOARD_ID_MINNOW =3D 0x0F, // Minnow Board BOARD_ID_APL_UNKNOWN =3D 0xFF } APL_BOARD_ID_LIST; =20 --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel